2 * QEMU GT64120 PCI host
4 * Copyright (c) 2006,2007 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "exec-memory.h"
35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
37 #define DPRINTF(fmt, ...)
40 #define GT_REGS (0x1000 >> 2)
42 /* CPU Configuration */
43 #define GT_CPU (0x000 >> 2)
44 #define GT_MULTI (0x120 >> 2)
46 /* CPU Address Decode */
47 #define GT_SCS10LD (0x008 >> 2)
48 #define GT_SCS10HD (0x010 >> 2)
49 #define GT_SCS32LD (0x018 >> 2)
50 #define GT_SCS32HD (0x020 >> 2)
51 #define GT_CS20LD (0x028 >> 2)
52 #define GT_CS20HD (0x030 >> 2)
53 #define GT_CS3BOOTLD (0x038 >> 2)
54 #define GT_CS3BOOTHD (0x040 >> 2)
55 #define GT_PCI0IOLD (0x048 >> 2)
56 #define GT_PCI0IOHD (0x050 >> 2)
57 #define GT_PCI0M0LD (0x058 >> 2)
58 #define GT_PCI0M0HD (0x060 >> 2)
59 #define GT_PCI0M1LD (0x080 >> 2)
60 #define GT_PCI0M1HD (0x088 >> 2)
61 #define GT_PCI1IOLD (0x090 >> 2)
62 #define GT_PCI1IOHD (0x098 >> 2)
63 #define GT_PCI1M0LD (0x0a0 >> 2)
64 #define GT_PCI1M0HD (0x0a8 >> 2)
65 #define GT_PCI1M1LD (0x0b0 >> 2)
66 #define GT_PCI1M1HD (0x0b8 >> 2)
67 #define GT_ISD (0x068 >> 2)
69 #define GT_SCS10AR (0x0d0 >> 2)
70 #define GT_SCS32AR (0x0d8 >> 2)
71 #define GT_CS20R (0x0e0 >> 2)
72 #define GT_CS3BOOTR (0x0e8 >> 2)
74 #define GT_PCI0IOREMAP (0x0f0 >> 2)
75 #define GT_PCI0M0REMAP (0x0f8 >> 2)
76 #define GT_PCI0M1REMAP (0x100 >> 2)
77 #define GT_PCI1IOREMAP (0x108 >> 2)
78 #define GT_PCI1M0REMAP (0x110 >> 2)
79 #define GT_PCI1M1REMAP (0x118 >> 2)
81 /* CPU Error Report */
82 #define GT_CPUERR_ADDRLO (0x070 >> 2)
83 #define GT_CPUERR_ADDRHI (0x078 >> 2)
84 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
85 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
86 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
88 /* CPU Sync Barrier */
89 #define GT_PCI0SYNC (0x0c0 >> 2)
90 #define GT_PCI1SYNC (0x0c8 >> 2)
92 /* SDRAM and Device Address Decode */
93 #define GT_SCS0LD (0x400 >> 2)
94 #define GT_SCS0HD (0x404 >> 2)
95 #define GT_SCS1LD (0x408 >> 2)
96 #define GT_SCS1HD (0x40c >> 2)
97 #define GT_SCS2LD (0x410 >> 2)
98 #define GT_SCS2HD (0x414 >> 2)
99 #define GT_SCS3LD (0x418 >> 2)
100 #define GT_SCS3HD (0x41c >> 2)
101 #define GT_CS0LD (0x420 >> 2)
102 #define GT_CS0HD (0x424 >> 2)
103 #define GT_CS1LD (0x428 >> 2)
104 #define GT_CS1HD (0x42c >> 2)
105 #define GT_CS2LD (0x430 >> 2)
106 #define GT_CS2HD (0x434 >> 2)
107 #define GT_CS3LD (0x438 >> 2)
108 #define GT_CS3HD (0x43c >> 2)
109 #define GT_BOOTLD (0x440 >> 2)
110 #define GT_BOOTHD (0x444 >> 2)
111 #define GT_ADERR (0x470 >> 2)
113 /* SDRAM Configuration */
114 #define GT_SDRAM_CFG (0x448 >> 2)
115 #define GT_SDRAM_OPMODE (0x474 >> 2)
116 #define GT_SDRAM_BM (0x478 >> 2)
117 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
119 /* SDRAM Parameters */
120 #define GT_SDRAM_B0 (0x44c >> 2)
121 #define GT_SDRAM_B1 (0x450 >> 2)
122 #define GT_SDRAM_B2 (0x454 >> 2)
123 #define GT_SDRAM_B3 (0x458 >> 2)
125 /* Device Parameters */
126 #define GT_DEV_B0 (0x45c >> 2)
127 #define GT_DEV_B1 (0x460 >> 2)
128 #define GT_DEV_B2 (0x464 >> 2)
129 #define GT_DEV_B3 (0x468 >> 2)
130 #define GT_DEV_BOOT (0x46c >> 2)
133 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
134 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
135 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
136 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
137 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
140 #define GT_DMA0_CNT (0x800 >> 2)
141 #define GT_DMA1_CNT (0x804 >> 2)
142 #define GT_DMA2_CNT (0x808 >> 2)
143 #define GT_DMA3_CNT (0x80c >> 2)
144 #define GT_DMA0_SA (0x810 >> 2)
145 #define GT_DMA1_SA (0x814 >> 2)
146 #define GT_DMA2_SA (0x818 >> 2)
147 #define GT_DMA3_SA (0x81c >> 2)
148 #define GT_DMA0_DA (0x820 >> 2)
149 #define GT_DMA1_DA (0x824 >> 2)
150 #define GT_DMA2_DA (0x828 >> 2)
151 #define GT_DMA3_DA (0x82c >> 2)
152 #define GT_DMA0_NEXT (0x830 >> 2)
153 #define GT_DMA1_NEXT (0x834 >> 2)
154 #define GT_DMA2_NEXT (0x838 >> 2)
155 #define GT_DMA3_NEXT (0x83c >> 2)
156 #define GT_DMA0_CUR (0x870 >> 2)
157 #define GT_DMA1_CUR (0x874 >> 2)
158 #define GT_DMA2_CUR (0x878 >> 2)
159 #define GT_DMA3_CUR (0x87c >> 2)
161 /* DMA Channel Control */
162 #define GT_DMA0_CTRL (0x840 >> 2)
163 #define GT_DMA1_CTRL (0x844 >> 2)
164 #define GT_DMA2_CTRL (0x848 >> 2)
165 #define GT_DMA3_CTRL (0x84c >> 2)
168 #define GT_DMA_ARB (0x860 >> 2)
171 #define GT_TC0 (0x850 >> 2)
172 #define GT_TC1 (0x854 >> 2)
173 #define GT_TC2 (0x858 >> 2)
174 #define GT_TC3 (0x85c >> 2)
175 #define GT_TC_CONTROL (0x864 >> 2)
178 #define GT_PCI0_CMD (0xc00 >> 2)
179 #define GT_PCI0_TOR (0xc04 >> 2)
180 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
181 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
182 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
183 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
184 #define GT_PCI1_IACK (0xc30 >> 2)
185 #define GT_PCI0_IACK (0xc34 >> 2)
186 #define GT_PCI0_BARE (0xc3c >> 2)
187 #define GT_PCI0_PREFMBR (0xc40 >> 2)
188 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
189 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
190 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
191 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
192 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
193 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
194 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
195 #define GT_PCI1_CMD (0xc80 >> 2)
196 #define GT_PCI1_TOR (0xc84 >> 2)
197 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
198 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
199 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
200 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
201 #define GT_PCI1_BARE (0xcbc >> 2)
202 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
203 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
204 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
205 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
206 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
207 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
208 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
209 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
210 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
211 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
212 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
213 #define GT_PCI0_CFGDATA (0xcfc >> 2)
216 #define GT_INTRCAUSE (0xc18 >> 2)
217 #define GT_INTRMASK (0xc1c >> 2)
218 #define GT_PCI0_ICMASK (0xc24 >> 2)
219 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
220 #define GT_CPU_INTSEL (0xc70 >> 2)
221 #define GT_PCI0_INTSEL (0xc74 >> 2)
222 #define GT_HINTRCAUSE (0xc98 >> 2)
223 #define GT_HINTRMASK (0xc9c >> 2)
224 #define GT_PCI0_HICMASK (0xca4 >> 2)
225 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
227 #define PCI_MAPPING_ENTRY(regname) \
228 target_phys_addr_t regname ##_start; \
229 target_phys_addr_t regname ##_length; \
230 MemoryRegion regname ##_mem
232 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
234 #define GT64120_PCI_HOST_BRIDGE(obj) \
235 OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE)
237 typedef struct GT64120State
{
240 uint32_t regs
[GT_REGS
];
241 PCI_MAPPING_ENTRY(PCI0IO
);
242 PCI_MAPPING_ENTRY(ISD
);
245 /* Adjust range to avoid touching space which isn't mappable via PCI */
246 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
247 0x1fc00000 - 0x1fd00000 */
248 static void check_reserved_space (target_phys_addr_t
*start
,
249 target_phys_addr_t
*length
)
251 target_phys_addr_t begin
= *start
;
252 target_phys_addr_t end
= *start
+ *length
;
254 if (end
>= 0x1e000000LL
&& end
< 0x1f100000LL
)
256 if (begin
>= 0x1e000000LL
&& begin
< 0x1f100000LL
)
257 begin
= 0x1f100000LL
;
258 if (end
>= 0x1fc00000LL
&& end
< 0x1fd00000LL
)
260 if (begin
>= 0x1fc00000LL
&& begin
< 0x1fd00000LL
)
261 begin
= 0x1fd00000LL
;
262 /* XXX: This is broken when a reserved range splits the requested range */
263 if (end
>= 0x1f100000LL
&& begin
< 0x1e000000LL
)
265 if (end
>= 0x1fd00000LL
&& begin
< 0x1fc00000LL
)
269 *length
= end
- begin
;
272 static void gt64120_isd_mapping(GT64120State
*s
)
274 target_phys_addr_t start
= s
->regs
[GT_ISD
] << 21;
275 target_phys_addr_t length
= 0x1000;
278 memory_region_del_subregion(get_system_memory(), &s
->ISD_mem
);
280 check_reserved_space(&start
, &length
);
282 /* Map new address */
283 DPRINTF("ISD: "TARGET_FMT_plx
"@"TARGET_FMT_plx
284 " -> "TARGET_FMT_plx
"@"TARGET_FMT_plx
"\n",
285 s
->ISD_length
, s
->ISD_start
, length
, start
);
286 s
->ISD_start
= start
;
287 s
->ISD_length
= length
;
288 memory_region_add_subregion(get_system_memory(), s
->ISD_start
, &s
->ISD_mem
);
291 static void gt64120_pci_mapping(GT64120State
*s
)
293 /* Update IO mapping */
294 if ((s
->regs
[GT_PCI0IOLD
] & 0x7f) <= s
->regs
[GT_PCI0IOHD
])
296 /* Unmap old IO address */
297 if (s
->PCI0IO_length
)
299 memory_region_del_subregion(get_system_memory(), &s
->PCI0IO_mem
);
300 memory_region_destroy(&s
->PCI0IO_mem
);
302 /* Map new IO address */
303 s
->PCI0IO_start
= s
->regs
[GT_PCI0IOLD
] << 21;
304 s
->PCI0IO_length
= ((s
->regs
[GT_PCI0IOHD
] + 1) - (s
->regs
[GT_PCI0IOLD
] & 0x7f)) << 21;
305 isa_mem_base
= s
->PCI0IO_start
;
306 if (s
->PCI0IO_length
) {
307 isa_mmio_setup(&s
->PCI0IO_mem
, s
->PCI0IO_length
);
308 memory_region_add_subregion(get_system_memory(), s
->PCI0IO_start
,
314 static void gt64120_writel (void *opaque
, target_phys_addr_t addr
,
315 uint64_t val
, unsigned size
)
317 GT64120State
*s
= opaque
;
320 if (!(s
->regs
[GT_CPU
] & 0x00001000))
323 saddr
= (addr
& 0xfff) >> 2;
326 /* CPU Configuration */
328 s
->regs
[GT_CPU
] = val
;
331 /* Read-only register as only one GT64xxx is present on the CPU bus */
334 /* CPU Address Decode */
336 s
->regs
[GT_PCI0IOLD
] = val
& 0x00007fff;
337 s
->regs
[GT_PCI0IOREMAP
] = val
& 0x000007ff;
338 gt64120_pci_mapping(s
);
341 s
->regs
[GT_PCI0M0LD
] = val
& 0x00007fff;
342 s
->regs
[GT_PCI0M0REMAP
] = val
& 0x000007ff;
345 s
->regs
[GT_PCI0M1LD
] = val
& 0x00007fff;
346 s
->regs
[GT_PCI0M1REMAP
] = val
& 0x000007ff;
349 s
->regs
[GT_PCI1IOLD
] = val
& 0x00007fff;
350 s
->regs
[GT_PCI1IOREMAP
] = val
& 0x000007ff;
353 s
->regs
[GT_PCI1M0LD
] = val
& 0x00007fff;
354 s
->regs
[GT_PCI1M0REMAP
] = val
& 0x000007ff;
357 s
->regs
[GT_PCI1M1LD
] = val
& 0x00007fff;
358 s
->regs
[GT_PCI1M1REMAP
] = val
& 0x000007ff;
361 s
->regs
[saddr
] = val
& 0x0000007f;
362 gt64120_pci_mapping(s
);
369 s
->regs
[saddr
] = val
& 0x0000007f;
372 s
->regs
[saddr
] = val
& 0x00007fff;
373 gt64120_isd_mapping(s
);
382 s
->regs
[saddr
] = val
& 0x000007ff;
385 /* CPU Error Report */
386 case GT_CPUERR_ADDRLO
:
387 case GT_CPUERR_ADDRHI
:
388 case GT_CPUERR_DATALO
:
389 case GT_CPUERR_DATAHI
:
390 case GT_CPUERR_PARITY
:
391 /* Read-only registers, do nothing */
394 /* CPU Sync Barrier */
397 /* Read-only registers, do nothing */
400 /* SDRAM and Device Address Decode */
420 /* SDRAM Configuration */
422 case GT_SDRAM_OPMODE
:
424 case GT_SDRAM_ADDRDECODE
:
425 /* Accept and ignore SDRAM interleave configuration */
426 s
->regs
[saddr
] = val
;
429 /* Device Parameters */
435 /* Not implemented */
436 DPRINTF ("Unimplemented device register offset 0x%x\n", saddr
<< 2);
440 case GT_ECC_ERRDATALO
:
441 case GT_ECC_ERRDATAHI
:
445 /* Read-only registers, do nothing */
469 /* Not implemented */
470 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr
<< 2);
473 /* DMA Channel Control */
478 /* Not implemented */
479 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr
<< 2);
484 /* Not implemented */
485 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr
<< 2);
494 /* Not implemented */
495 DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr
<< 2);
501 s
->regs
[saddr
] = val
& 0x0401fc0f;
504 case GT_PCI0_BS_SCS10
:
505 case GT_PCI0_BS_SCS32
:
506 case GT_PCI0_BS_CS20
:
507 case GT_PCI0_BS_CS3BT
:
511 case GT_PCI0_PREFMBR
:
512 case GT_PCI0_SCS10_BAR
:
513 case GT_PCI0_SCS32_BAR
:
514 case GT_PCI0_CS20_BAR
:
515 case GT_PCI0_CS3BT_BAR
:
516 case GT_PCI0_SSCS10_BAR
:
517 case GT_PCI0_SSCS32_BAR
:
518 case GT_PCI0_SCS3BT_BAR
:
520 case GT_PCI1_BS_SCS10
:
521 case GT_PCI1_BS_SCS32
:
522 case GT_PCI1_BS_CS20
:
523 case GT_PCI1_BS_CS3BT
:
525 case GT_PCI1_PREFMBR
:
526 case GT_PCI1_SCS10_BAR
:
527 case GT_PCI1_SCS32_BAR
:
528 case GT_PCI1_CS20_BAR
:
529 case GT_PCI1_CS3BT_BAR
:
530 case GT_PCI1_SSCS10_BAR
:
531 case GT_PCI1_SSCS32_BAR
:
532 case GT_PCI1_SCS3BT_BAR
:
533 case GT_PCI1_CFGADDR
:
534 case GT_PCI1_CFGDATA
:
535 /* not implemented */
537 case GT_PCI0_CFGADDR
:
538 s
->pci
.config_reg
= val
& 0x80fffffc;
540 case GT_PCI0_CFGDATA
:
541 if (!(s
->regs
[GT_PCI0_CMD
] & 1) && (s
->pci
.config_reg
& 0x00fff800))
543 if (s
->pci
.config_reg
& (1u << 31))
544 pci_data_write(s
->pci
.bus
, s
->pci
.config_reg
, val
, 4);
549 /* not really implemented */
550 s
->regs
[saddr
] = ~(~(s
->regs
[saddr
]) | ~(val
& 0xfffffffe));
551 s
->regs
[saddr
] |= !!(s
->regs
[saddr
] & 0xfffffffe);
552 DPRINTF("INTRCAUSE %" PRIx64
"\n", val
);
555 s
->regs
[saddr
] = val
& 0x3c3ffffe;
556 DPRINTF("INTRMASK %" PRIx64
"\n", val
);
559 s
->regs
[saddr
] = val
& 0x03fffffe;
560 DPRINTF("ICMASK %" PRIx64
"\n", val
);
562 case GT_PCI0_SERR0MASK
:
563 s
->regs
[saddr
] = val
& 0x0000003f;
564 DPRINTF("SERR0MASK %" PRIx64
"\n", val
);
567 /* Reserved when only PCI_0 is configured. */
572 case GT_PCI0_HICMASK
:
573 case GT_PCI1_SERR1MASK
:
574 /* not implemented */
577 /* SDRAM Parameters */
582 /* We don't simulate electrical parameters of the SDRAM.
583 Accept, but ignore the values. */
584 s
->regs
[saddr
] = val
;
588 DPRINTF ("Bad register offset 0x%x\n", (int)addr
);
593 static uint64_t gt64120_readl (void *opaque
,
594 target_phys_addr_t addr
, unsigned size
)
596 GT64120State
*s
= opaque
;
600 saddr
= (addr
& 0xfff) >> 2;
603 /* CPU Configuration */
605 /* Only one GT64xxx is present on the CPU bus, return
607 val
= s
->regs
[saddr
];
610 /* CPU Error Report */
611 case GT_CPUERR_ADDRLO
:
612 case GT_CPUERR_ADDRHI
:
613 case GT_CPUERR_DATALO
:
614 case GT_CPUERR_DATAHI
:
615 case GT_CPUERR_PARITY
:
616 /* Emulated memory has no error, always return the initial
618 val
= s
->regs
[saddr
];
621 /* CPU Sync Barrier */
624 /* Reading those register should empty all FIFO on the PCI
625 bus, which are not emulated. The return value should be
626 a random value that should be ignored. */
631 case GT_ECC_ERRDATALO
:
632 case GT_ECC_ERRDATAHI
:
636 /* Emulated memory has no error, always return the initial
638 val
= s
->regs
[saddr
];
673 val
= s
->regs
[saddr
];
676 /* Read the IRQ number */
677 val
= pic_read_irq(isa_pic
);
680 /* SDRAM and Device Address Decode */
700 val
= s
->regs
[saddr
];
703 /* SDRAM Configuration */
705 case GT_SDRAM_OPMODE
:
707 case GT_SDRAM_ADDRDECODE
:
708 val
= s
->regs
[saddr
];
711 /* SDRAM Parameters */
716 /* We don't simulate electrical parameters of the SDRAM.
717 Just return the last written value. */
718 val
= s
->regs
[saddr
];
721 /* Device Parameters */
727 val
= s
->regs
[saddr
];
751 val
= s
->regs
[saddr
];
754 /* DMA Channel Control */
759 val
= s
->regs
[saddr
];
764 val
= s
->regs
[saddr
];
773 val
= s
->regs
[saddr
];
777 case GT_PCI0_CFGADDR
:
778 val
= s
->pci
.config_reg
;
780 case GT_PCI0_CFGDATA
:
781 if (!(s
->pci
.config_reg
& (1 << 31)))
784 val
= pci_data_read(s
->pci
.bus
, s
->pci
.config_reg
, 4);
785 if (!(s
->regs
[GT_PCI0_CMD
] & 1) && (s
->pci
.config_reg
& 0x00fff800))
791 case GT_PCI0_BS_SCS10
:
792 case GT_PCI0_BS_SCS32
:
793 case GT_PCI0_BS_CS20
:
794 case GT_PCI0_BS_CS3BT
:
797 case GT_PCI0_PREFMBR
:
798 case GT_PCI0_SCS10_BAR
:
799 case GT_PCI0_SCS32_BAR
:
800 case GT_PCI0_CS20_BAR
:
801 case GT_PCI0_CS3BT_BAR
:
802 case GT_PCI0_SSCS10_BAR
:
803 case GT_PCI0_SSCS32_BAR
:
804 case GT_PCI0_SCS3BT_BAR
:
807 case GT_PCI1_BS_SCS10
:
808 case GT_PCI1_BS_SCS32
:
809 case GT_PCI1_BS_CS20
:
810 case GT_PCI1_BS_CS3BT
:
812 case GT_PCI1_PREFMBR
:
813 case GT_PCI1_SCS10_BAR
:
814 case GT_PCI1_SCS32_BAR
:
815 case GT_PCI1_CS20_BAR
:
816 case GT_PCI1_CS3BT_BAR
:
817 case GT_PCI1_SSCS10_BAR
:
818 case GT_PCI1_SSCS32_BAR
:
819 case GT_PCI1_SCS3BT_BAR
:
820 case GT_PCI1_CFGADDR
:
821 case GT_PCI1_CFGDATA
:
822 val
= s
->regs
[saddr
];
827 val
= s
->regs
[saddr
];
828 DPRINTF("INTRCAUSE %x\n", val
);
831 val
= s
->regs
[saddr
];
832 DPRINTF("INTRMASK %x\n", val
);
835 val
= s
->regs
[saddr
];
836 DPRINTF("ICMASK %x\n", val
);
838 case GT_PCI0_SERR0MASK
:
839 val
= s
->regs
[saddr
];
840 DPRINTF("SERR0MASK %x\n", val
);
843 /* Reserved when only PCI_0 is configured. */
848 case GT_PCI0_HICMASK
:
849 case GT_PCI1_SERR1MASK
:
850 val
= s
->regs
[saddr
];
854 val
= s
->regs
[saddr
];
855 DPRINTF ("Bad register offset 0x%x\n", (int)addr
);
859 if (!(s
->regs
[GT_CPU
] & 0x00001000))
865 static const MemoryRegionOps isd_mem_ops
= {
866 .read
= gt64120_readl
,
867 .write
= gt64120_writel
,
868 .endianness
= DEVICE_NATIVE_ENDIAN
,
871 static int gt64120_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
875 slot
= (pci_dev
->devfn
>> 3);
881 /* AMD 79C973 Ethernet */
884 /* Crystal 4281 Sound */
887 /* PCI slot 1 to 4 */
889 return ((slot
- 18) + irq_num
) & 0x03;
890 /* Unknown device, don't do any translation */
896 static int pci_irq_levels
[4];
898 static void gt64120_pci_set_irq(void *opaque
, int irq_num
, int level
)
900 int i
, pic_irq
, pic_level
;
901 qemu_irq
*pic
= opaque
;
903 pci_irq_levels
[irq_num
] = level
;
905 /* now we change the pic irq level according to the piix irq mappings */
907 pic_irq
= piix4_dev
->config
[0x60 + irq_num
];
909 /* The pic level is the logical OR of all the PCI irqs mapped
912 for (i
= 0; i
< 4; i
++) {
913 if (pic_irq
== piix4_dev
->config
[0x60 + i
])
914 pic_level
|= pci_irq_levels
[i
];
916 qemu_set_irq(pic
[pic_irq
], pic_level
);
921 static void gt64120_reset(void *opaque
)
923 GT64120State
*s
= opaque
;
925 /* FIXME: Malta specific hw assumptions ahead */
927 /* CPU Configuration */
928 #ifdef TARGET_WORDS_BIGENDIAN
929 s
->regs
[GT_CPU
] = 0x00000000;
931 s
->regs
[GT_CPU
] = 0x00001000;
933 s
->regs
[GT_MULTI
] = 0x00000003;
935 /* CPU Address decode */
936 s
->regs
[GT_SCS10LD
] = 0x00000000;
937 s
->regs
[GT_SCS10HD
] = 0x00000007;
938 s
->regs
[GT_SCS32LD
] = 0x00000008;
939 s
->regs
[GT_SCS32HD
] = 0x0000000f;
940 s
->regs
[GT_CS20LD
] = 0x000000e0;
941 s
->regs
[GT_CS20HD
] = 0x00000070;
942 s
->regs
[GT_CS3BOOTLD
] = 0x000000f8;
943 s
->regs
[GT_CS3BOOTHD
] = 0x0000007f;
945 s
->regs
[GT_PCI0IOLD
] = 0x00000080;
946 s
->regs
[GT_PCI0IOHD
] = 0x0000000f;
947 s
->regs
[GT_PCI0M0LD
] = 0x00000090;
948 s
->regs
[GT_PCI0M0HD
] = 0x0000001f;
949 s
->regs
[GT_ISD
] = 0x000000a0;
950 s
->regs
[GT_PCI0M1LD
] = 0x00000790;
951 s
->regs
[GT_PCI0M1HD
] = 0x0000001f;
952 s
->regs
[GT_PCI1IOLD
] = 0x00000100;
953 s
->regs
[GT_PCI1IOHD
] = 0x0000000f;
954 s
->regs
[GT_PCI1M0LD
] = 0x00000110;
955 s
->regs
[GT_PCI1M0HD
] = 0x0000001f;
956 s
->regs
[GT_PCI1M1LD
] = 0x00000120;
957 s
->regs
[GT_PCI1M1HD
] = 0x0000002f;
959 s
->regs
[GT_SCS10AR
] = 0x00000000;
960 s
->regs
[GT_SCS32AR
] = 0x00000008;
961 s
->regs
[GT_CS20R
] = 0x000000e0;
962 s
->regs
[GT_CS3BOOTR
] = 0x000000f8;
964 s
->regs
[GT_PCI0IOREMAP
] = 0x00000080;
965 s
->regs
[GT_PCI0M0REMAP
] = 0x00000090;
966 s
->regs
[GT_PCI0M1REMAP
] = 0x00000790;
967 s
->regs
[GT_PCI1IOREMAP
] = 0x00000100;
968 s
->regs
[GT_PCI1M0REMAP
] = 0x00000110;
969 s
->regs
[GT_PCI1M1REMAP
] = 0x00000120;
971 /* CPU Error Report */
972 s
->regs
[GT_CPUERR_ADDRLO
] = 0x00000000;
973 s
->regs
[GT_CPUERR_ADDRHI
] = 0x00000000;
974 s
->regs
[GT_CPUERR_DATALO
] = 0xffffffff;
975 s
->regs
[GT_CPUERR_DATAHI
] = 0xffffffff;
976 s
->regs
[GT_CPUERR_PARITY
] = 0x000000ff;
978 /* CPU Sync Barrier */
979 s
->regs
[GT_PCI0SYNC
] = 0x00000000;
980 s
->regs
[GT_PCI1SYNC
] = 0x00000000;
982 /* SDRAM and Device Address Decode */
983 s
->regs
[GT_SCS0LD
] = 0x00000000;
984 s
->regs
[GT_SCS0HD
] = 0x00000007;
985 s
->regs
[GT_SCS1LD
] = 0x00000008;
986 s
->regs
[GT_SCS1HD
] = 0x0000000f;
987 s
->regs
[GT_SCS2LD
] = 0x00000010;
988 s
->regs
[GT_SCS2HD
] = 0x00000017;
989 s
->regs
[GT_SCS3LD
] = 0x00000018;
990 s
->regs
[GT_SCS3HD
] = 0x0000001f;
991 s
->regs
[GT_CS0LD
] = 0x000000c0;
992 s
->regs
[GT_CS0HD
] = 0x000000c7;
993 s
->regs
[GT_CS1LD
] = 0x000000c8;
994 s
->regs
[GT_CS1HD
] = 0x000000cf;
995 s
->regs
[GT_CS2LD
] = 0x000000d0;
996 s
->regs
[GT_CS2HD
] = 0x000000df;
997 s
->regs
[GT_CS3LD
] = 0x000000f0;
998 s
->regs
[GT_CS3HD
] = 0x000000fb;
999 s
->regs
[GT_BOOTLD
] = 0x000000fc;
1000 s
->regs
[GT_BOOTHD
] = 0x000000ff;
1001 s
->regs
[GT_ADERR
] = 0xffffffff;
1003 /* SDRAM Configuration */
1004 s
->regs
[GT_SDRAM_CFG
] = 0x00000200;
1005 s
->regs
[GT_SDRAM_OPMODE
] = 0x00000000;
1006 s
->regs
[GT_SDRAM_BM
] = 0x00000007;
1007 s
->regs
[GT_SDRAM_ADDRDECODE
] = 0x00000002;
1009 /* SDRAM Parameters */
1010 s
->regs
[GT_SDRAM_B0
] = 0x00000005;
1011 s
->regs
[GT_SDRAM_B1
] = 0x00000005;
1012 s
->regs
[GT_SDRAM_B2
] = 0x00000005;
1013 s
->regs
[GT_SDRAM_B3
] = 0x00000005;
1016 s
->regs
[GT_ECC_ERRDATALO
] = 0x00000000;
1017 s
->regs
[GT_ECC_ERRDATAHI
] = 0x00000000;
1018 s
->regs
[GT_ECC_MEM
] = 0x00000000;
1019 s
->regs
[GT_ECC_CALC
] = 0x00000000;
1020 s
->regs
[GT_ECC_ERRADDR
] = 0x00000000;
1022 /* Device Parameters */
1023 s
->regs
[GT_DEV_B0
] = 0x386fffff;
1024 s
->regs
[GT_DEV_B1
] = 0x386fffff;
1025 s
->regs
[GT_DEV_B2
] = 0x386fffff;
1026 s
->regs
[GT_DEV_B3
] = 0x386fffff;
1027 s
->regs
[GT_DEV_BOOT
] = 0x146fffff;
1029 /* DMA registers are all zeroed at reset */
1032 s
->regs
[GT_TC0
] = 0xffffffff;
1033 s
->regs
[GT_TC1
] = 0x00ffffff;
1034 s
->regs
[GT_TC2
] = 0x00ffffff;
1035 s
->regs
[GT_TC3
] = 0x00ffffff;
1036 s
->regs
[GT_TC_CONTROL
] = 0x00000000;
1039 #ifdef TARGET_WORDS_BIGENDIAN
1040 s
->regs
[GT_PCI0_CMD
] = 0x00000000;
1042 s
->regs
[GT_PCI0_CMD
] = 0x00010001;
1044 s
->regs
[GT_PCI0_TOR
] = 0x0000070f;
1045 s
->regs
[GT_PCI0_BS_SCS10
] = 0x00fff000;
1046 s
->regs
[GT_PCI0_BS_SCS32
] = 0x00fff000;
1047 s
->regs
[GT_PCI0_BS_CS20
] = 0x01fff000;
1048 s
->regs
[GT_PCI0_BS_CS3BT
] = 0x00fff000;
1049 s
->regs
[GT_PCI1_IACK
] = 0x00000000;
1050 s
->regs
[GT_PCI0_IACK
] = 0x00000000;
1051 s
->regs
[GT_PCI0_BARE
] = 0x0000000f;
1052 s
->regs
[GT_PCI0_PREFMBR
] = 0x00000040;
1053 s
->regs
[GT_PCI0_SCS10_BAR
] = 0x00000000;
1054 s
->regs
[GT_PCI0_SCS32_BAR
] = 0x01000000;
1055 s
->regs
[GT_PCI0_CS20_BAR
] = 0x1c000000;
1056 s
->regs
[GT_PCI0_CS3BT_BAR
] = 0x1f000000;
1057 s
->regs
[GT_PCI0_SSCS10_BAR
] = 0x00000000;
1058 s
->regs
[GT_PCI0_SSCS32_BAR
] = 0x01000000;
1059 s
->regs
[GT_PCI0_SCS3BT_BAR
] = 0x1f000000;
1060 #ifdef TARGET_WORDS_BIGENDIAN
1061 s
->regs
[GT_PCI1_CMD
] = 0x00000000;
1063 s
->regs
[GT_PCI1_CMD
] = 0x00010001;
1065 s
->regs
[GT_PCI1_TOR
] = 0x0000070f;
1066 s
->regs
[GT_PCI1_BS_SCS10
] = 0x00fff000;
1067 s
->regs
[GT_PCI1_BS_SCS32
] = 0x00fff000;
1068 s
->regs
[GT_PCI1_BS_CS20
] = 0x01fff000;
1069 s
->regs
[GT_PCI1_BS_CS3BT
] = 0x00fff000;
1070 s
->regs
[GT_PCI1_BARE
] = 0x0000000f;
1071 s
->regs
[GT_PCI1_PREFMBR
] = 0x00000040;
1072 s
->regs
[GT_PCI1_SCS10_BAR
] = 0x00000000;
1073 s
->regs
[GT_PCI1_SCS32_BAR
] = 0x01000000;
1074 s
->regs
[GT_PCI1_CS20_BAR
] = 0x1c000000;
1075 s
->regs
[GT_PCI1_CS3BT_BAR
] = 0x1f000000;
1076 s
->regs
[GT_PCI1_SSCS10_BAR
] = 0x00000000;
1077 s
->regs
[GT_PCI1_SSCS32_BAR
] = 0x01000000;
1078 s
->regs
[GT_PCI1_SCS3BT_BAR
] = 0x1f000000;
1079 s
->regs
[GT_PCI1_CFGADDR
] = 0x00000000;
1080 s
->regs
[GT_PCI1_CFGDATA
] = 0x00000000;
1081 s
->regs
[GT_PCI0_CFGADDR
] = 0x00000000;
1083 /* Interrupt registers are all zeroed at reset */
1085 gt64120_isd_mapping(s
);
1086 gt64120_pci_mapping(s
);
1089 PCIBus
*gt64120_register(qemu_irq
*pic
)
1095 dev
= qdev_create(NULL
, TYPE_GT64120_PCI_HOST_BRIDGE
);
1096 qdev_init_nofail(dev
);
1097 d
= GT64120_PCI_HOST_BRIDGE(dev
);
1099 phb
->bus
= pci_register_bus(dev
, "pci",
1100 gt64120_pci_set_irq
, gt64120_pci_map_irq
,
1102 get_system_memory(),
1104 PCI_DEVFN(18, 0), 4);
1105 memory_region_init_io(&d
->ISD_mem
, &isd_mem_ops
, d
, "isd-mem", 0x1000);
1107 pci_create_simple(phb
->bus
, PCI_DEVFN(0, 0), "gt64120_pci");
1111 static int gt64120_init(SysBusDevice
*dev
)
1115 s
= GT64120_PCI_HOST_BRIDGE(dev
);
1117 /* FIXME: This value is computed from registers during reset, but some
1118 devices (e.g. VGA card) need to know it when they are registered.
1119 This also mean that changing the register to change the mapping
1120 does not fully work. */
1121 isa_mem_base
= 0x10000000;
1122 qemu_register_reset(gt64120_reset
, s
);
1126 static int gt64120_pci_init(PCIDevice
*d
)
1128 /* FIXME: Malta specific hw assumptions ahead */
1129 pci_set_word(d
->config
+ PCI_COMMAND
, 0);
1130 pci_set_word(d
->config
+ PCI_STATUS
,
1131 PCI_STATUS_FAST_BACK
| PCI_STATUS_DEVSEL_MEDIUM
);
1132 pci_config_set_prog_interface(d
->config
, 0);
1133 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_0
, 0x00000008);
1134 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_1
, 0x01000008);
1135 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_2
, 0x1c000000);
1136 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_3
, 0x1f000000);
1137 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_4
, 0x14000000);
1138 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_5
, 0x14000001);
1139 pci_set_byte(d
->config
+ 0x3d, 0x01);
1144 static void gt64120_pci_class_init(ObjectClass
*klass
, void *data
)
1146 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1148 k
->init
= gt64120_pci_init
;
1149 k
->vendor_id
= PCI_VENDOR_ID_MARVELL
;
1150 k
->device_id
= PCI_DEVICE_ID_MARVELL_GT6412X
;
1152 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
1155 static const TypeInfo gt64120_pci_info
= {
1156 .name
= "gt64120_pci",
1157 .parent
= TYPE_PCI_DEVICE
,
1158 .instance_size
= sizeof(PCIDevice
),
1159 .class_init
= gt64120_pci_class_init
,
1162 static void gt64120_class_init(ObjectClass
*klass
, void *data
)
1164 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1166 sdc
->init
= gt64120_init
;
1169 static const TypeInfo gt64120_info
= {
1170 .name
= TYPE_GT64120_PCI_HOST_BRIDGE
,
1171 .parent
= TYPE_SYS_BUS_DEVICE
,
1172 .instance_size
= sizeof(GT64120State
),
1173 .class_init
= gt64120_class_init
,
1176 static void gt64120_pci_register_types(void)
1178 type_register_static(>64120_info
);
1179 type_register_static(>64120_pci_info
);
1182 type_init(gt64120_pci_register_types
)