balloon: Separate out stat and balloon handling
[qemu/agraf.git] / hw / ppc_mac.h
blob6fad20a745635f66873b6f9d618fd945ede1cb6a
1 /*
2 * QEMU PowerMac emulation shared definitions and prototypes
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
25 #if !defined(__PPC_MAC_H__)
26 #define __PPC_MAC_H__
28 #include "memory.h"
30 /* SMP is not enabled, for now */
31 #define MAX_CPUS 1
33 #define BIOS_SIZE (1024 * 1024)
34 #define BIOS_FILENAME "ppc_rom.bin"
35 #define NVRAM_SIZE 0x2000
36 #define PROM_FILENAME "openbios-ppc"
37 #define PROM_ADDR 0xfff00000
39 #define KERNEL_LOAD_ADDR 0x01000000
40 #define KERNEL_GAP 0x00100000
42 #define ESCC_CLOCK 3686400
44 /* Cuda */
45 void cuda_init (int *cuda_mem_index, qemu_irq irq);
47 /* MacIO */
48 void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
49 int dbdma_mem_index, int cuda_mem_index, void *nvram,
50 int nb_ide, int *ide_mem_index, int escc_mem_index);
52 /* Heathrow PIC */
53 qemu_irq *heathrow_pic_init(int *pmem_index,
54 int nb_cpus, qemu_irq **irqs);
56 /* Grackle PCI */
57 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
58 MemoryRegion *address_space);
60 /* UniNorth PCI */
61 PCIBus *pci_pmac_init(qemu_irq *pic, MemoryRegion *address_space);
62 PCIBus *pci_pmac_u3_init(qemu_irq *pic, MemoryRegion *address_space);
64 /* Mac NVRAM */
65 typedef struct MacIONVRAMState MacIONVRAMState;
67 MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
68 unsigned int it_shift);
69 void macio_nvram_map (void *opaque, target_phys_addr_t mem_base);
70 void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
71 uint32_t macio_nvram_read (void *opaque, uint32_t addr);
72 void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);
74 /* adb.c */
76 #define MAX_ADB_DEVICES 16
78 #define ADB_MAX_OUT_LEN 16
80 typedef struct ADBDevice ADBDevice;
82 /* buf = NULL means polling */
83 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
84 const uint8_t *buf, int len);
85 typedef int ADBDeviceReset(ADBDevice *d);
87 struct ADBDevice {
88 struct ADBBusState *bus;
89 int devaddr;
90 int handler;
91 ADBDeviceRequest *devreq;
92 ADBDeviceReset *devreset;
93 void *opaque;
96 typedef struct ADBBusState {
97 ADBDevice devices[MAX_ADB_DEVICES];
98 int nb_devices;
99 int poll_index;
100 } ADBBusState;
102 int adb_request(ADBBusState *s, uint8_t *buf_out,
103 const uint8_t *buf, int len);
104 int adb_poll(ADBBusState *s, uint8_t *buf_out);
106 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
107 ADBDeviceRequest *devreq,
108 ADBDeviceReset *devreset,
109 void *opaque);
110 void adb_kbd_init(ADBBusState *bus);
111 void adb_mouse_init(ADBBusState *bus);
113 extern ADBBusState adb_bus;
115 #endif /* !defined(__PPC_MAC_H__) */