target-ppc: Fix invalid SPR read/write warnings
[qemu/agraf.git] / target-moxie / cpu.h
bloba9d9ace3035e44a4de3ebb47e8be3a5947b5b36c
1 /*
2 * Moxie emulation
4 * Copyright (c) 2008, 2010, 2013 Anthony Green
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef _CPU_MOXIE_H
20 #define _CPU_MOXIE_H
22 #include "config.h"
23 #include "qemu-common.h"
25 #define TARGET_LONG_BITS 32
27 #define CPUArchState struct CPUMoxieState
29 #define TARGET_HAS_ICE 1
31 #define ELF_MACHINE 0xFEED /* EM_MOXIE */
33 #define MOXIE_EX_DIV0 0
34 #define MOXIE_EX_BAD 1
35 #define MOXIE_EX_IRQ 2
36 #define MOXIE_EX_SWI 3
37 #define MOXIE_EX_MMU_MISS 4
38 #define MOXIE_EX_BREAK 16
40 #include "exec/cpu-defs.h"
41 #include "fpu/softfloat.h"
43 #define TARGET_PAGE_BITS 12 /* 4k */
45 #define TARGET_PHYS_ADDR_SPACE_BITS 32
46 #define TARGET_VIRT_ADDR_SPACE_BITS 32
48 #define NB_MMU_MODES 1
50 typedef struct CPUMoxieState {
52 uint32_t flags; /* general execution flags */
53 uint32_t gregs[16]; /* general registers */
54 uint32_t sregs[256]; /* special registers */
55 uint32_t pc; /* program counter */
56 /* Instead of saving the cc value, we save the cmp arguments
57 and compute cc on demand. */
58 uint32_t cc_a; /* reg a for condition code calculation */
59 uint32_t cc_b; /* reg b for condition code calculation */
61 void *irq[8];
63 CPU_COMMON
65 } CPUMoxieState;
67 #include "qom/cpu.h"
69 #define TYPE_MOXIE_CPU "moxie-cpu"
71 #define MOXIE_CPU_CLASS(klass) \
72 OBJECT_CLASS_CHECK(MoxieCPUClass, (klass), TYPE_MOXIE_CPU)
73 #define MOXIE_CPU(obj) \
74 OBJECT_CHECK(MoxieCPU, (obj), TYPE_MOXIE_CPU)
75 #define MOXIE_CPU_GET_CLASS(obj) \
76 OBJECT_GET_CLASS(MoxieCPUClass, (obj), TYPE_MOXIE_CPU)
78 /**
79 * MoxieCPUClass:
80 * @parent_reset: The parent class' reset handler.
82 * A Moxie CPU model.
84 typedef struct MoxieCPUClass {
85 /*< private >*/
86 CPUClass parent_class;
87 /*< public >*/
89 DeviceRealize parent_realize;
90 void (*parent_reset)(CPUState *cpu);
91 } MoxieCPUClass;
93 /**
94 * MoxieCPU:
95 * @env: #CPUMoxieState
97 * A Moxie CPU.
99 typedef struct MoxieCPU {
100 /*< private >*/
101 CPUState parent_obj;
102 /*< public >*/
104 CPUMoxieState env;
105 } MoxieCPU;
107 static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env)
109 return MOXIE_CPU(container_of(env, MoxieCPU, env));
112 #define ENV_GET_CPU(e) CPU(moxie_env_get_cpu(e))
114 #define ENV_OFFSET offsetof(MoxieCPU, env)
116 MoxieCPU *cpu_moxie_init(const char *cpu_model);
117 int cpu_moxie_exec(CPUMoxieState *s);
118 void moxie_cpu_do_interrupt(CPUState *cs);
119 void moxie_translate_init(void);
120 int cpu_moxie_signal_handler(int host_signum, void *pinfo,
121 void *puc);
123 static inline CPUMoxieState *cpu_init(const char *cpu_model)
125 MoxieCPU *cpu = cpu_moxie_init(cpu_model);
126 if (cpu == NULL) {
127 return NULL;
129 return &cpu->env;
132 #define cpu_exec cpu_moxie_exec
133 #define cpu_gen_code cpu_moxie_gen_code
134 #define cpu_signal_handler cpu_moxie_signal_handler
136 static inline int cpu_mmu_index(CPUMoxieState *env)
138 return 0;
141 #include "exec/cpu-all.h"
142 #include "exec/exec-all.h"
144 static inline void cpu_pc_from_tb(CPUMoxieState *env, TranslationBlock *tb)
146 env->pc = tb->pc;
149 static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc,
150 target_ulong *cs_base, int *flags)
152 *pc = env->pc;
153 *cs_base = 0;
154 *flags = 0;
157 static inline int cpu_has_work(CPUState *cpu)
159 return cpu->interrupt_request & CPU_INTERRUPT_HARD;
162 int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
163 int rw, int mmu_idx);
165 #endif /* _CPU_MOXIE_H */