target-ppc: Fix invalid SPR read/write warnings
[qemu/agraf.git] / target-lm32 / cpu.c
blob23c05ddbed5a10612fdc6e38c9d3978a67c761cd
1 /*
2 * QEMU LatticeMico32 CPU
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "cpu.h"
22 #include "qemu-common.h"
25 /* CPUClass::reset() */
26 static void lm32_cpu_reset(CPUState *s)
28 LM32CPU *cpu = LM32_CPU(s);
29 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
30 CPULM32State *env = &cpu->env;
32 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
33 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
34 log_cpu_state(env, 0);
37 lcc->parent_reset(s);
39 /* reset cpu state */
40 memset(env, 0, offsetof(CPULM32State, breakpoints));
42 tlb_flush(env, 1);
45 static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
47 LM32CPU *cpu = LM32_CPU(dev);
48 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
50 cpu_reset(CPU(cpu));
52 qemu_init_vcpu(&cpu->env);
54 lcc->parent_realize(dev, errp);
57 static void lm32_cpu_initfn(Object *obj)
59 CPUState *cs = CPU(obj);
60 LM32CPU *cpu = LM32_CPU(obj);
61 CPULM32State *env = &cpu->env;
62 static bool tcg_initialized;
64 cs->env_ptr = env;
65 cpu_exec_init(env);
67 env->flags = 0;
69 if (tcg_enabled() && !tcg_initialized) {
70 tcg_initialized = true;
71 lm32_translate_init();
75 static void lm32_cpu_class_init(ObjectClass *oc, void *data)
77 LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
78 CPUClass *cc = CPU_CLASS(oc);
79 DeviceClass *dc = DEVICE_CLASS(oc);
81 lcc->parent_realize = dc->realize;
82 dc->realize = lm32_cpu_realizefn;
84 lcc->parent_reset = cc->reset;
85 cc->reset = lm32_cpu_reset;
87 cc->do_interrupt = lm32_cpu_do_interrupt;
88 cpu_class_set_vmsd(cc, &vmstate_lm32_cpu);
91 static const TypeInfo lm32_cpu_type_info = {
92 .name = TYPE_LM32_CPU,
93 .parent = TYPE_CPU,
94 .instance_size = sizeof(LM32CPU),
95 .instance_init = lm32_cpu_initfn,
96 .abstract = false,
97 .class_size = sizeof(LM32CPUClass),
98 .class_init = lm32_cpu_class_init,
101 static void lm32_cpu_register_types(void)
103 type_register_static(&lm32_cpu_type_info);
106 type_init(lm32_cpu_register_types)