?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-ppc: Fix invalid SPR read/write warnings
[qemu/agraf.git] / target-i386 / cpu.c
blob9f2adad805e6db6bf645e9b4b86d4a05e56032ad
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hyperv.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
49 #endif
50
51 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
52 uint32_t vendor2, uint32_t vendor3)
53 {
54 int i;
55 for (i = 0; i < 4; i++) {
56 dst[i] = vendor1 >> (8 * i);
57 dst[i + 4] = vendor2 >> (8 * i);
58 dst[i + 8] = vendor3 >> (8 * i);
59 }
60 dst[CPUID_VENDOR_SZ] = '\0';
61 }
62
63 /* feature flags taken from "Intel Processor Identification and the CPUID
64 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
65 * between feature naming conventions, aliases may be added.
66 */
67 static const char *feature_name[] = {
68 "fpu", "vme", "de", "pse",
69 "tsc", "msr", "pae", "mce",
70 "cx8", "apic", NULL, "sep",
71 "mtrr", "pge", "mca", "cmov",
72 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
73 NULL, "ds" /* Intel dts */, "acpi", "mmx",
74 "fxsr", "sse", "sse2", "ss",
75 "ht" /* Intel htt */, "tm", "ia64", "pbe",
76 };
77 static const char *ext_feature_name[] = {
78 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
79 "ds_cpl", "vmx", "smx", "est",
80 "tm2", "ssse3", "cid", NULL,
81 "fma", "cx16", "xtpr", "pdcm",
82 NULL, "pcid", "dca", "sse4.1|sse4_1",
83 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
84 "tsc-deadline", "aes", "xsave", "osxsave",
85 "avx", "f16c", "rdrand", "hypervisor",
86 };
87 /* Feature names that are already defined on feature_name[] but are set on
88 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
89 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
90 * if and only if CPU vendor is AMD.
91 */
92 static const char *ext2_feature_name[] = {
93 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
94 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
95 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
96 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
97 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
98 "nx|xd", NULL, "mmxext", NULL /* mmx */,
99 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
100 NULL, "lm|i64", "3dnowext", "3dnow",
101 };
102 static const char *ext3_feature_name[] = {
103 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
104 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
105 "3dnowprefetch", "osvw", "ibs", "xop",
106 "skinit", "wdt", NULL, "lwp",
107 "fma4", "tce", NULL, "nodeid_msr",
108 NULL, "tbm", "topoext", "perfctr_core",
109 "perfctr_nb", NULL, NULL, NULL,
110 NULL, NULL, NULL, NULL,
111 };
112
113 static const char *ext4_feature_name[] = {
114 NULL, NULL, "xstore", "xstore-en",
115 NULL, NULL, "xcrypt", "xcrypt-en",
116 "ace2", "ace2-en", "phe", "phe-en",
117 "pmm", "pmm-en", NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 NULL, NULL, NULL, NULL,
121 NULL, NULL, NULL, NULL,
122 };
123
124 static const char *kvm_feature_name[] = {
125 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
126 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
132 NULL, NULL, NULL, NULL,
133 };
134
135 static const char *svm_feature_name[] = {
136 "npt", "lbrv", "svm_lock", "nrip_save",
137 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
138 NULL, NULL, "pause_filter", NULL,
139 "pfthreshold", NULL, NULL, NULL,
140 NULL, NULL, NULL, NULL,
141 NULL, NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143 NULL, NULL, NULL, NULL,
144 };
145
146 static const char *cpuid_7_0_ebx_feature_name[] = {
147 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
148 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
149 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
150 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
151 };
152
153 typedef struct FeatureWordInfo {
154 const char **feat_names;
155 uint32_t cpuid_eax; /* Input EAX for CPUID */
156 int cpuid_reg; /* R_* register constant */
157 } FeatureWordInfo;
158
159 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
160 [FEAT_1_EDX] = {
161 .feat_names = feature_name,
162 .cpuid_eax = 1, .cpuid_reg = R_EDX,
163 },
164 [FEAT_1_ECX] = {
165 .feat_names = ext_feature_name,
166 .cpuid_eax = 1, .cpuid_reg = R_ECX,
167 },
168 [FEAT_8000_0001_EDX] = {
169 .feat_names = ext2_feature_name,
170 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
171 },
172 [FEAT_8000_0001_ECX] = {
173 .feat_names = ext3_feature_name,
174 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
175 },
176 [FEAT_C000_0001_EDX] = {
177 .feat_names = ext4_feature_name,
178 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
179 },
180 [FEAT_KVM] = {
181 .feat_names = kvm_feature_name,
182 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
183 },
184 [FEAT_SVM] = {
185 .feat_names = svm_feature_name,
186 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
187 },
188 [FEAT_7_0_EBX] = {
189 .feat_names = cpuid_7_0_ebx_feature_name,
190 .cpuid_eax = 7, .cpuid_reg = R_EBX,
191 },
192 };
193
194 const char *get_register_name_32(unsigned int reg)
195 {
196 static const char *reg_names[CPU_NB_REGS32] = {
197 [R_EAX] = "EAX",
198 [R_ECX] = "ECX",
199 [R_EDX] = "EDX",
200 [R_EBX] = "EBX",
201 [R_ESP] = "ESP",
202 [R_EBP] = "EBP",
203 [R_ESI] = "ESI",
204 [R_EDI] = "EDI",
205 };
206
207 if (reg > CPU_NB_REGS32) {
208 return NULL;
209 }
210 return reg_names[reg];
211 }
212
213 /* collects per-function cpuid data
214 */
215 typedef struct model_features_t {
216 uint32_t *guest_feat;
217 uint32_t *host_feat;
218 FeatureWord feat_word;
219 } model_features_t;
220
221 int check_cpuid = 0;
222 int enforce_cpuid = 0;
223
224 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
225 (1 << KVM_FEATURE_NOP_IO_DELAY) |
226 (1 << KVM_FEATURE_CLOCKSOURCE2) |
227 (1 << KVM_FEATURE_ASYNC_PF) |
228 (1 << KVM_FEATURE_STEAL_TIME) |
229 (1 << KVM_FEATURE_PV_EOI) |
230 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
231
232 void disable_kvm_pv_eoi(void)
233 {
234 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
235 }
236
237 void host_cpuid(uint32_t function, uint32_t count,
238 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
239 {
240 #if defined(CONFIG_KVM)
241 uint32_t vec[4];
242
243 #ifdef __x86_64__
244 asm volatile("cpuid"
245 : "=a"(vec[0]), "=b"(vec[1]),
246 "=c"(vec[2]), "=d"(vec[3])
247 : "0"(function), "c"(count) : "cc");
248 #else
249 asm volatile("pusha \n\t"
250 "cpuid \n\t"
251 "mov %%eax, 0(%2) \n\t"
252 "mov %%ebx, 4(%2) \n\t"
253 "mov %%ecx, 8(%2) \n\t"
254 "mov %%edx, 12(%2) \n\t"
255 "popa"
256 : : "a"(function), "c"(count), "S"(vec)
257 : "memory", "cc");
258 #endif
259
260 if (eax)
261 *eax = vec[0];
262 if (ebx)
263 *ebx = vec[1];
264 if (ecx)
265 *ecx = vec[2];
266 if (edx)
267 *edx = vec[3];
268 #endif
269 }
270
271 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
272
273 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
274 * a substring. ex if !NULL points to the first char after a substring,
275 * otherwise the string is assumed to sized by a terminating nul.
276 * Return lexical ordering of *s1:*s2.
277 */
278 static int sstrcmp(const char *s1, const char *e1, const char *s2,
279 const char *e2)
280 {
281 for (;;) {
282 if (!*s1 || !*s2 || *s1 != *s2)
283 return (*s1 - *s2);
284 ++s1, ++s2;
285 if (s1 == e1 && s2 == e2)
286 return (0);
287 else if (s1 == e1)
288 return (*s2);
289 else if (s2 == e2)
290 return (*s1);
291 }
292 }
293
294 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
295 * '|' delimited (possibly empty) strings in which case search for a match
296 * within the alternatives proceeds left to right. Return 0 for success,
297 * non-zero otherwise.
298 */
299 static int altcmp(const char *s, const char *e, const char *altstr)
300 {
301 const char *p, *q;
302
303 for (q = p = altstr; ; ) {
304 while (*p && *p != '|')
305 ++p;
306 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
307 return (0);
308 if (!*p)
309 return (1);
310 else
311 q = ++p;
312 }
313 }
314
315 /* search featureset for flag *[s..e), if found set corresponding bit in
316 * *pval and return true, otherwise return false
317 */
318 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
319 const char **featureset)
320 {
321 uint32_t mask;
322 const char **ppc;
323 bool found = false;
324
325 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
326 if (*ppc && !altcmp(s, e, *ppc)) {
327 *pval |= mask;
328 found = true;
329 }
330 }
331 return found;
332 }
333
334 static void add_flagname_to_bitmaps(const char *flagname,
335 FeatureWordArray words)
336 {
337 FeatureWord w;
338 for (w = 0; w < FEATURE_WORDS; w++) {
339 FeatureWordInfo *wi = &feature_word_info[w];
340 if (wi->feat_names &&
341 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
342 break;
343 }
344 }
345 if (w == FEATURE_WORDS) {
346 fprintf(stderr, "CPU feature %s not found\n", flagname);
347 }
348 }
349
350 typedef struct x86_def_t {
351 const char *name;
352 uint32_t level;
353 uint32_t xlevel;
354 uint32_t xlevel2;
355 /* vendor is zero-terminated, 12 character ASCII string */
356 char vendor[CPUID_VENDOR_SZ + 1];
357 int family;
358 int model;
359 int stepping;
360 FeatureWordArray features;
361 char model_id[48];
362 } x86_def_t;
363
364 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
365 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
366 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
367 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
368 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
369 CPUID_PSE36 | CPUID_FXSR)
370 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
371 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
372 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
373 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
374 CPUID_PAE | CPUID_SEP | CPUID_APIC)
375
376 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
377 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
378 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
379 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
380 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
381 /* partly implemented:
382 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
383 CPUID_PSE36 (needed for Solaris) */
384 /* missing:
385 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
386 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
387 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
388 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
389 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
390 /* missing:
391 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
392 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
393 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
394 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
395 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
396 CPUID_EXT_RDRAND */
397 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
398 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
399 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
400 /* missing:
401 CPUID_EXT2_PDPE1GB */
402 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
403 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
404 #define TCG_SVM_FEATURES 0
405 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
406 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
407 /* missing:
408 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
409 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
410 CPUID_7_0_EBX_RDSEED */
411
412 /* built-in CPU model definitions
413 */
414 static x86_def_t builtin_x86_defs[] = {
415 {
416 .name = "qemu64",
417 .level = 4,
418 .vendor = CPUID_VENDOR_AMD,
419 .family = 6,
420 .model = 2,
421 .stepping = 3,
422 .features[FEAT_1_EDX] =
423 PPRO_FEATURES |
424 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
425 CPUID_PSE36,
426 .features[FEAT_1_ECX] =
427 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
428 .features[FEAT_8000_0001_EDX] =
429 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
430 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
431 .features[FEAT_8000_0001_ECX] =
432 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
433 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
434 .xlevel = 0x8000000A,
435 },
436 {
437 .name = "phenom",
438 .level = 5,
439 .vendor = CPUID_VENDOR_AMD,
440 .family = 16,
441 .model = 2,
442 .stepping = 3,
443 .features[FEAT_1_EDX] =
444 PPRO_FEATURES |
445 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
446 CPUID_PSE36 | CPUID_VME | CPUID_HT,
447 .features[FEAT_1_ECX] =
448 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
449 CPUID_EXT_POPCNT,
450 .features[FEAT_8000_0001_EDX] =
451 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
452 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
453 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
454 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
455 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
456 CPUID_EXT3_CR8LEG,
457 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
458 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
459 .features[FEAT_8000_0001_ECX] =
460 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
461 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
462 .features[FEAT_SVM] =
463 CPUID_SVM_NPT | CPUID_SVM_LBRV,
464 .xlevel = 0x8000001A,
465 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
466 },
467 {
468 .name = "core2duo",
469 .level = 10,
470 .vendor = CPUID_VENDOR_INTEL,
471 .family = 6,
472 .model = 15,
473 .stepping = 11,
474 .features[FEAT_1_EDX] =
475 PPRO_FEATURES |
476 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
477 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
478 CPUID_HT | CPUID_TM | CPUID_PBE,
479 .features[FEAT_1_ECX] =
480 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
481 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
482 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
483 .features[FEAT_8000_0001_EDX] =
484 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
485 .features[FEAT_8000_0001_ECX] =
486 CPUID_EXT3_LAHF_LM,
487 .xlevel = 0x80000008,
488 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
489 },
490 {
491 .name = "kvm64",
492 .level = 5,
493 .vendor = CPUID_VENDOR_INTEL,
494 .family = 15,
495 .model = 6,
496 .stepping = 1,
497 /* Missing: CPUID_VME, CPUID_HT */
498 .features[FEAT_1_EDX] =
499 PPRO_FEATURES |
500 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
501 CPUID_PSE36,
502 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
503 .features[FEAT_1_ECX] =
504 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
505 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
506 .features[FEAT_8000_0001_EDX] =
507 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
508 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
509 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
510 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
511 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
512 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
513 .features[FEAT_8000_0001_ECX] =
514 0,
515 .xlevel = 0x80000008,
516 .model_id = "Common KVM processor"
517 },
518 {
519 .name = "qemu32",
520 .level = 4,
521 .vendor = CPUID_VENDOR_INTEL,
522 .family = 6,
523 .model = 3,
524 .stepping = 3,
525 .features[FEAT_1_EDX] =
526 PPRO_FEATURES,
527 .features[FEAT_1_ECX] =
528 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
529 .xlevel = 0x80000004,
530 },
531 {
532 .name = "kvm32",
533 .level = 5,
534 .vendor = CPUID_VENDOR_INTEL,
535 .family = 15,
536 .model = 6,
537 .stepping = 1,
538 .features[FEAT_1_EDX] =
539 PPRO_FEATURES |
540 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
541 .features[FEAT_1_ECX] =
542 CPUID_EXT_SSE3,
543 .features[FEAT_8000_0001_EDX] =
544 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
545 .features[FEAT_8000_0001_ECX] =
546 0,
547 .xlevel = 0x80000008,
548 .model_id = "Common 32-bit KVM processor"
549 },
550 {
551 .name = "coreduo",
552 .level = 10,
553 .vendor = CPUID_VENDOR_INTEL,
554 .family = 6,
555 .model = 14,
556 .stepping = 8,
557 .features[FEAT_1_EDX] =
558 PPRO_FEATURES | CPUID_VME |
559 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
560 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
561 .features[FEAT_1_ECX] =
562 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
563 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
564 .features[FEAT_8000_0001_EDX] =
565 CPUID_EXT2_NX,
566 .xlevel = 0x80000008,
567 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
568 },
569 {
570 .name = "486",
571 .level = 1,
572 .vendor = CPUID_VENDOR_INTEL,
573 .family = 4,
574 .model = 0,
575 .stepping = 0,
576 .features[FEAT_1_EDX] =
577 I486_FEATURES,
578 .xlevel = 0,
579 },
580 {
581 .name = "pentium",
582 .level = 1,
583 .vendor = CPUID_VENDOR_INTEL,
584 .family = 5,
585 .model = 4,
586 .stepping = 3,
587 .features[FEAT_1_EDX] =
588 PENTIUM_FEATURES,
589 .xlevel = 0,
590 },
591 {
592 .name = "pentium2",
593 .level = 2,
594 .vendor = CPUID_VENDOR_INTEL,
595 .family = 6,
596 .model = 5,
597 .stepping = 2,
598 .features[FEAT_1_EDX] =
599 PENTIUM2_FEATURES,
600 .xlevel = 0,
601 },
602 {
603 .name = "pentium3",
604 .level = 2,
605 .vendor = CPUID_VENDOR_INTEL,
606 .family = 6,
607 .model = 7,
608 .stepping = 3,
609 .features[FEAT_1_EDX] =
610 PENTIUM3_FEATURES,
611 .xlevel = 0,
612 },
613 {
614 .name = "athlon",
615 .level = 2,
616 .vendor = CPUID_VENDOR_AMD,
617 .family = 6,
618 .model = 2,
619 .stepping = 3,
620 .features[FEAT_1_EDX] =
621 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
622 CPUID_MCA,
623 .features[FEAT_8000_0001_EDX] =
624 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
625 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
626 .xlevel = 0x80000008,
627 },
628 {
629 .name = "n270",
630 /* original is on level 10 */
631 .level = 5,
632 .vendor = CPUID_VENDOR_INTEL,
633 .family = 6,
634 .model = 28,
635 .stepping = 2,
636 .features[FEAT_1_EDX] =
637 PPRO_FEATURES |
638 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
639 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
640 /* Some CPUs got no CPUID_SEP */
641 .features[FEAT_1_ECX] =
642 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
643 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
644 .features[FEAT_8000_0001_EDX] =
645 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
646 CPUID_EXT2_NX,
647 .features[FEAT_8000_0001_ECX] =
648 CPUID_EXT3_LAHF_LM,
649 .xlevel = 0x8000000A,
650 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
651 },
652 {
653 .name = "Conroe",
654 .level = 2,
655 .vendor = CPUID_VENDOR_INTEL,
656 .family = 6,
657 .model = 2,
658 .stepping = 3,
659 .features[FEAT_1_EDX] =
660 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
661 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
662 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
663 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
664 CPUID_DE | CPUID_FP87,
665 .features[FEAT_1_ECX] =
666 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
667 .features[FEAT_8000_0001_EDX] =
668 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
669 .features[FEAT_8000_0001_ECX] =
670 CPUID_EXT3_LAHF_LM,
671 .xlevel = 0x8000000A,
672 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
673 },
674 {
675 .name = "Penryn",
676 .level = 2,
677 .vendor = CPUID_VENDOR_INTEL,
678 .family = 6,
679 .model = 2,
680 .stepping = 3,
681 .features[FEAT_1_EDX] =
682 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
683 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
684 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
685 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
686 CPUID_DE | CPUID_FP87,
687 .features[FEAT_1_ECX] =
688 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
689 CPUID_EXT_SSE3,
690 .features[FEAT_8000_0001_EDX] =
691 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
692 .features[FEAT_8000_0001_ECX] =
693 CPUID_EXT3_LAHF_LM,
694 .xlevel = 0x8000000A,
695 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
696 },
697 {
698 .name = "Nehalem",
699 .level = 2,
700 .vendor = CPUID_VENDOR_INTEL,
701 .family = 6,
702 .model = 2,
703 .stepping = 3,
704 .features[FEAT_1_EDX] =
705 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
706 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
707 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
708 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
709 CPUID_DE | CPUID_FP87,
710 .features[FEAT_1_ECX] =
711 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
712 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
713 .features[FEAT_8000_0001_EDX] =
714 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
715 .features[FEAT_8000_0001_ECX] =
716 CPUID_EXT3_LAHF_LM,
717 .xlevel = 0x8000000A,
718 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
719 },
720 {
721 .name = "Westmere",
722 .level = 11,
723 .vendor = CPUID_VENDOR_INTEL,
724 .family = 6,
725 .model = 44,
726 .stepping = 1,
727 .features[FEAT_1_EDX] =
728 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
729 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
730 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
731 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
732 CPUID_DE | CPUID_FP87,
733 .features[FEAT_1_ECX] =
734 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
735 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
736 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
737 .features[FEAT_8000_0001_EDX] =
738 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
739 .features[FEAT_8000_0001_ECX] =
740 CPUID_EXT3_LAHF_LM,
741 .xlevel = 0x8000000A,
742 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
743 },
744 {
745 .name = "SandyBridge",
746 .level = 0xd,
747 .vendor = CPUID_VENDOR_INTEL,
748 .family = 6,
749 .model = 42,
750 .stepping = 1,
751 .features[FEAT_1_EDX] =
752 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
753 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
754 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
755 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
756 CPUID_DE | CPUID_FP87,
757 .features[FEAT_1_ECX] =
758 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
759 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
760 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
761 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
762 CPUID_EXT_SSE3,
763 .features[FEAT_8000_0001_EDX] =
764 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
765 CPUID_EXT2_SYSCALL,
766 .features[FEAT_8000_0001_ECX] =
767 CPUID_EXT3_LAHF_LM,
768 .xlevel = 0x8000000A,
769 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
770 },
771 {
772 .name = "Haswell",
773 .level = 0xd,
774 .vendor = CPUID_VENDOR_INTEL,
775 .family = 6,
776 .model = 60,
777 .stepping = 1,
778 .features[FEAT_1_EDX] =
779 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
780 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
781 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
782 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
783 CPUID_DE | CPUID_FP87,
784 .features[FEAT_1_ECX] =
785 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
786 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
787 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
788 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
789 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
790 CPUID_EXT_PCID,
791 .features[FEAT_8000_0001_EDX] =
792 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
793 CPUID_EXT2_SYSCALL,
794 .features[FEAT_8000_0001_ECX] =
795 CPUID_EXT3_LAHF_LM,
796 .features[FEAT_7_0_EBX] =
797 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
798 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
799 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
800 CPUID_7_0_EBX_RTM,
801 .xlevel = 0x8000000A,
802 .model_id = "Intel Core Processor (Haswell)",
803 },
804 {
805 .name = "Opteron_G1",
806 .level = 5,
807 .vendor = CPUID_VENDOR_AMD,
808 .family = 15,
809 .model = 6,
810 .stepping = 1,
811 .features[FEAT_1_EDX] =
812 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
813 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
814 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
815 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
816 CPUID_DE | CPUID_FP87,
817 .features[FEAT_1_ECX] =
818 CPUID_EXT_SSE3,
819 .features[FEAT_8000_0001_EDX] =
820 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
821 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
822 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
823 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
824 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
825 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
826 .xlevel = 0x80000008,
827 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
828 },
829 {
830 .name = "Opteron_G2",
831 .level = 5,
832 .vendor = CPUID_VENDOR_AMD,
833 .family = 15,
834 .model = 6,
835 .stepping = 1,
836 .features[FEAT_1_EDX] =
837 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
838 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
839 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
840 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
841 CPUID_DE | CPUID_FP87,
842 .features[FEAT_1_ECX] =
843 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
844 .features[FEAT_8000_0001_EDX] =
845 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
846 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
847 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
848 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
849 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
850 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
851 CPUID_EXT2_DE | CPUID_EXT2_FPU,
852 .features[FEAT_8000_0001_ECX] =
853 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
854 .xlevel = 0x80000008,
855 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
856 },
857 {
858 .name = "Opteron_G3",
859 .level = 5,
860 .vendor = CPUID_VENDOR_AMD,
861 .family = 15,
862 .model = 6,
863 .stepping = 1,
864 .features[FEAT_1_EDX] =
865 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
866 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
867 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
868 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
869 CPUID_DE | CPUID_FP87,
870 .features[FEAT_1_ECX] =
871 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
872 CPUID_EXT_SSE3,
873 .features[FEAT_8000_0001_EDX] =
874 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
875 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
876 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
877 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
878 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
879 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
880 CPUID_EXT2_DE | CPUID_EXT2_FPU,
881 .features[FEAT_8000_0001_ECX] =
882 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
883 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
884 .xlevel = 0x80000008,
885 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
886 },
887 {
888 .name = "Opteron_G4",
889 .level = 0xd,
890 .vendor = CPUID_VENDOR_AMD,
891 .family = 21,
892 .model = 1,
893 .stepping = 2,
894 .features[FEAT_1_EDX] =
895 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
896 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
897 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
898 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
899 CPUID_DE | CPUID_FP87,
900 .features[FEAT_1_ECX] =
901 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
902 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
903 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
904 CPUID_EXT_SSE3,
905 .features[FEAT_8000_0001_EDX] =
906 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
907 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
908 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
909 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
910 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
911 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
912 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
913 .features[FEAT_8000_0001_ECX] =
914 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
915 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
916 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
917 CPUID_EXT3_LAHF_LM,
918 .xlevel = 0x8000001A,
919 .model_id = "AMD Opteron 62xx class CPU",
920 },
921 {
922 .name = "Opteron_G5",
923 .level = 0xd,
924 .vendor = CPUID_VENDOR_AMD,
925 .family = 21,
926 .model = 2,
927 .stepping = 0,
928 .features[FEAT_1_EDX] =
929 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
930 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
931 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
932 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
933 CPUID_DE | CPUID_FP87,
934 .features[FEAT_1_ECX] =
935 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
936 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
937 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
938 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
939 .features[FEAT_8000_0001_EDX] =
940 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
941 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
942 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
943 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
944 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
945 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
946 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
947 .features[FEAT_8000_0001_ECX] =
948 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
949 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
950 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
951 CPUID_EXT3_LAHF_LM,
952 .xlevel = 0x8000001A,
953 .model_id = "AMD Opteron 63xx class CPU",
954 },
955 };
956
957 #ifdef CONFIG_KVM
958 static int cpu_x86_fill_model_id(char *str)
959 {
960 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
961 int i;
962
963 for (i = 0; i < 3; i++) {
964 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
965 memcpy(str + i * 16 + 0, &eax, 4);
966 memcpy(str + i * 16 + 4, &ebx, 4);
967 memcpy(str + i * 16 + 8, &ecx, 4);
968 memcpy(str + i * 16 + 12, &edx, 4);
969 }
970 return 0;
971 }
972 #endif
973
974 /* Fill a x86_def_t struct with information about the host CPU, and
975 * the CPU features supported by the host hardware + host kernel
976 *
977 * This function may be called only if KVM is enabled.
978 */
979 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
980 {
981 #ifdef CONFIG_KVM
982 KVMState *s = kvm_state;
983 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
984
985 assert(kvm_enabled());
986
987 x86_cpu_def->name = "host";
988 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
989 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
990
991 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
992 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
993 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
994 x86_cpu_def->stepping = eax & 0x0F;
995
996 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
997 x86_cpu_def->features[FEAT_1_EDX] =
998 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
999 x86_cpu_def->features[FEAT_1_ECX] =
1000 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
1001
1002 if (x86_cpu_def->level >= 7) {
1003 x86_cpu_def->features[FEAT_7_0_EBX] =
1004 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
1005 } else {
1006 x86_cpu_def->features[FEAT_7_0_EBX] = 0;
1007 }
1008
1009 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1010 x86_cpu_def->features[FEAT_8000_0001_EDX] =
1011 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1012 x86_cpu_def->features[FEAT_8000_0001_ECX] =
1013 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1014
1015 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1016
1017 /* Call Centaur's CPUID instruction. */
1018 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
1019 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
1020 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1021 if (eax >= 0xC0000001) {
1022 /* Support VIA max extended level */
1023 x86_cpu_def->xlevel2 = eax;
1024 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
1025 x86_cpu_def->features[FEAT_C000_0001_EDX] =
1026 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1027 }
1028 }
1029
1030 /* Other KVM-specific feature fields: */
1031 x86_cpu_def->features[FEAT_SVM] =
1032 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1033 x86_cpu_def->features[FEAT_KVM] =
1034 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1035
1036 #endif /* CONFIG_KVM */
1037 }
1038
1039 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1040 {
1041 int i;
1042
1043 for (i = 0; i < 32; ++i)
1044 if (1 << i & mask) {
1045 const char *reg = get_register_name_32(f->cpuid_reg);
1046 assert(reg);
1047 fprintf(stderr, "warning: host doesn't support requested feature: "
1048 "CPUID.%02XH:%s%s%s [bit %d]\n",
1049 f->cpuid_eax, reg,
1050 f->feat_names[i] ? "." : "",
1051 f->feat_names[i] ? f->feat_names[i] : "", i);
1052 break;
1053 }
1054 return 0;
1055 }
1056
1057 /* Check if all requested cpu flags are making their way to the guest
1058 *
1059 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1060 *
1061 * This function may be called only if KVM is enabled.
1062 */
1063 static int kvm_check_features_against_host(X86CPU *cpu)
1064 {
1065 CPUX86State *env = &cpu->env;
1066 x86_def_t host_def;
1067 uint32_t mask;
1068 int rv, i;
1069 struct model_features_t ft[] = {
1070 {&env->features[FEAT_1_EDX],
1071 &host_def.features[FEAT_1_EDX],
1072 FEAT_1_EDX },
1073 {&env->features[FEAT_1_ECX],
1074 &host_def.features[FEAT_1_ECX],
1075 FEAT_1_ECX },
1076 {&env->features[FEAT_8000_0001_EDX],
1077 &host_def.features[FEAT_8000_0001_EDX],
1078 FEAT_8000_0001_EDX },
1079 {&env->features[FEAT_8000_0001_ECX],
1080 &host_def.features[FEAT_8000_0001_ECX],
1081 FEAT_8000_0001_ECX },
1082 {&env->features[FEAT_C000_0001_EDX],
1083 &host_def.features[FEAT_C000_0001_EDX],
1084 FEAT_C000_0001_EDX },
1085 {&env->features[FEAT_7_0_EBX],
1086 &host_def.features[FEAT_7_0_EBX],
1087 FEAT_7_0_EBX },
1088 {&env->features[FEAT_SVM],
1089 &host_def.features[FEAT_SVM],
1090 FEAT_SVM },
1091 {&env->features[FEAT_KVM],
1092 &host_def.features[FEAT_KVM],
1093 FEAT_KVM },
1094 };
1095
1096 assert(kvm_enabled());
1097
1098 kvm_cpu_fill_host(&host_def);
1099 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1100 FeatureWord w = ft[i].feat_word;
1101 FeatureWordInfo *wi = &feature_word_info[w];
1102 for (mask = 1; mask; mask <<= 1) {
1103 if (*ft[i].guest_feat & mask &&
1104 !(*ft[i].host_feat & mask)) {
1105 unavailable_host_feature(wi, mask);
1106 rv = 1;
1107 }
1108 }
1109 }
1110 return rv;
1111 }
1112
1113 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1114 const char *name, Error **errp)
1115 {
1116 X86CPU *cpu = X86_CPU(obj);
1117 CPUX86State *env = &cpu->env;
1118 int64_t value;
1119
1120 value = (env->cpuid_version >> 8) & 0xf;
1121 if (value == 0xf) {
1122 value += (env->cpuid_version >> 20) & 0xff;
1123 }
1124 visit_type_int(v, &value, name, errp);
1125 }
1126
1127 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1128 const char *name, Error **errp)
1129 {
1130 X86CPU *cpu = X86_CPU(obj);
1131 CPUX86State *env = &cpu->env;
1132 const int64_t min = 0;
1133 const int64_t max = 0xff + 0xf;
1134 int64_t value;
1135
1136 visit_type_int(v, &value, name, errp);
1137 if (error_is_set(errp)) {
1138 return;
1139 }
1140 if (value < min || value > max) {
1141 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1142 name ? name : "null", value, min, max);
1143 return;
1144 }
1145
1146 env->cpuid_version &= ~0xff00f00;
1147 if (value > 0x0f) {
1148 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1149 } else {
1150 env->cpuid_version |= value << 8;
1151 }
1152 }
1153
1154 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1155 const char *name, Error **errp)
1156 {
1157 X86CPU *cpu = X86_CPU(obj);
1158 CPUX86State *env = &cpu->env;
1159 int64_t value;
1160
1161 value = (env->cpuid_version >> 4) & 0xf;
1162 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1163 visit_type_int(v, &value, name, errp);
1164 }
1165
1166 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1167 const char *name, Error **errp)
1168 {
1169 X86CPU *cpu = X86_CPU(obj);
1170 CPUX86State *env = &cpu->env;
1171 const int64_t min = 0;
1172 const int64_t max = 0xff;
1173 int64_t value;
1174
1175 visit_type_int(v, &value, name, errp);
1176 if (error_is_set(errp)) {
1177 return;
1178 }
1179 if (value < min || value > max) {
1180 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1181 name ? name : "null", value, min, max);
1182 return;
1183 }
1184
1185 env->cpuid_version &= ~0xf00f0;
1186 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1187 }
1188
1189 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1190 void *opaque, const char *name,
1191 Error **errp)
1192 {
1193 X86CPU *cpu = X86_CPU(obj);
1194 CPUX86State *env = &cpu->env;
1195 int64_t value;
1196
1197 value = env->cpuid_version & 0xf;
1198 visit_type_int(v, &value, name, errp);
1199 }
1200
1201 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1202 void *opaque, const char *name,
1203 Error **errp)
1204 {
1205 X86CPU *cpu = X86_CPU(obj);
1206 CPUX86State *env = &cpu->env;
1207 const int64_t min = 0;
1208 const int64_t max = 0xf;
1209 int64_t value;
1210
1211 visit_type_int(v, &value, name, errp);
1212 if (error_is_set(errp)) {
1213 return;
1214 }
1215 if (value < min || value > max) {
1216 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1217 name ? name : "null", value, min, max);
1218 return;
1219 }
1220
1221 env->cpuid_version &= ~0xf;
1222 env->cpuid_version |= value & 0xf;
1223 }
1224
1225 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1226 const char *name, Error **errp)
1227 {
1228 X86CPU *cpu = X86_CPU(obj);
1229
1230 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1231 }
1232
1233 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1234 const char *name, Error **errp)
1235 {
1236 X86CPU *cpu = X86_CPU(obj);
1237
1238 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1239 }
1240
1241 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1242 const char *name, Error **errp)
1243 {
1244 X86CPU *cpu = X86_CPU(obj);
1245
1246 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1247 }
1248
1249 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1250 const char *name, Error **errp)
1251 {
1252 X86CPU *cpu = X86_CPU(obj);
1253
1254 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1255 }
1256
1257 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1258 {
1259 X86CPU *cpu = X86_CPU(obj);
1260 CPUX86State *env = &cpu->env;
1261 char *value;
1262
1263 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1264 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1265 env->cpuid_vendor3);
1266 return value;
1267 }
1268
1269 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1270 Error **errp)
1271 {
1272 X86CPU *cpu = X86_CPU(obj);
1273 CPUX86State *env = &cpu->env;
1274 int i;
1275
1276 if (strlen(value) != CPUID_VENDOR_SZ) {
1277 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1278 "vendor", value);
1279 return;
1280 }
1281
1282 env->cpuid_vendor1 = 0;
1283 env->cpuid_vendor2 = 0;
1284 env->cpuid_vendor3 = 0;
1285 for (i = 0; i < 4; i++) {
1286 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1287 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1288 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1289 }
1290 }
1291
1292 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1293 {
1294 X86CPU *cpu = X86_CPU(obj);
1295 CPUX86State *env = &cpu->env;
1296 char *value;
1297 int i;
1298
1299 value = g_malloc(48 + 1);
1300 for (i = 0; i < 48; i++) {
1301 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1302 }
1303 value[48] = '\0';
1304 return value;
1305 }
1306
1307 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1308 Error **errp)
1309 {
1310 X86CPU *cpu = X86_CPU(obj);
1311 CPUX86State *env = &cpu->env;
1312 int c, len, i;
1313
1314 if (model_id == NULL) {
1315 model_id = "";
1316 }
1317 len = strlen(model_id);
1318 memset(env->cpuid_model, 0, 48);
1319 for (i = 0; i < 48; i++) {
1320 if (i >= len) {
1321 c = '\0';
1322 } else {
1323 c = (uint8_t)model_id[i];
1324 }
1325 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1326 }
1327 }
1328
1329 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1330 const char *name, Error **errp)
1331 {
1332 X86CPU *cpu = X86_CPU(obj);
1333 int64_t value;
1334
1335 value = cpu->env.tsc_khz * 1000;
1336 visit_type_int(v, &value, name, errp);
1337 }
1338
1339 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1340 const char *name, Error **errp)
1341 {
1342 X86CPU *cpu = X86_CPU(obj);
1343 const int64_t min = 0;
1344 const int64_t max = INT64_MAX;
1345 int64_t value;
1346
1347 visit_type_int(v, &value, name, errp);
1348 if (error_is_set(errp)) {
1349 return;
1350 }
1351 if (value < min || value > max) {
1352 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1353 name ? name : "null", value, min, max);
1354 return;
1355 }
1356
1357 cpu->env.tsc_khz = value / 1000;
1358 }
1359
1360 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1361 const char *name, Error **errp)
1362 {
1363 X86CPU *cpu = X86_CPU(obj);
1364 int64_t value = cpu->env.cpuid_apic_id;
1365
1366 visit_type_int(v, &value, name, errp);
1367 }
1368
1369 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1370 const char *name, Error **errp)
1371 {
1372 X86CPU *cpu = X86_CPU(obj);
1373 DeviceState *dev = DEVICE(obj);
1374 const int64_t min = 0;
1375 const int64_t max = UINT32_MAX;
1376 Error *error = NULL;
1377 int64_t value;
1378
1379 if (dev->realized) {
1380 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1381 "it was realized", name, object_get_typename(obj));
1382 return;
1383 }
1384
1385 visit_type_int(v, &value, name, &error);
1386 if (error) {
1387 error_propagate(errp, error);
1388 return;
1389 }
1390 if (value < min || value > max) {
1391 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1392 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1393 object_get_typename(obj), name, value, min, max);
1394 return;
1395 }
1396
1397 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1398 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1399 return;
1400 }
1401 cpu->env.cpuid_apic_id = value;
1402 }
1403
1404 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1405 {
1406 x86_def_t *def;
1407 int i;
1408
1409 if (name == NULL) {
1410 return -1;
1411 }
1412 if (kvm_enabled() && strcmp(name, "host") == 0) {
1413 kvm_cpu_fill_host(x86_cpu_def);
1414 return 0;
1415 }
1416
1417 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1418 def = &builtin_x86_defs[i];
1419 if (strcmp(name, def->name) == 0) {
1420 memcpy(x86_cpu_def, def, sizeof(*def));
1421 /* sysenter isn't supported in compatibility mode on AMD,
1422 * syscall isn't supported in compatibility mode on Intel.
1423 * Normally we advertise the actual CPU vendor, but you can
1424 * override this using the 'vendor' property if you want to use
1425 * KVM's sysenter/syscall emulation in compatibility mode and
1426 * when doing cross vendor migration
1427 */
1428 if (kvm_enabled()) {
1429 uint32_t ebx = 0, ecx = 0, edx = 0;
1430 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1431 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1432 }
1433 return 0;
1434 }
1435 }
1436
1437 return -1;
1438 }
1439
1440 /* Convert all '_' in a feature string option name to '-', to make feature
1441 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1442 */
1443 static inline void feat2prop(char *s)
1444 {
1445 while ((s = strchr(s, '_'))) {
1446 *s = '-';
1447 }
1448 }
1449
1450 /* Parse "+feature,-feature,feature=foo" CPU feature string
1451 */
1452 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1453 {
1454 char *featurestr; /* Single 'key=value" string being parsed */
1455 /* Features to be added */
1456 FeatureWordArray plus_features = { 0 };
1457 /* Features to be removed */
1458 FeatureWordArray minus_features = { 0 };
1459 uint32_t numvalue;
1460 CPUX86State *env = &cpu->env;
1461
1462 featurestr = features ? strtok(features, ",") : NULL;
1463
1464 while (featurestr) {
1465 char *val;
1466 if (featurestr[0] == '+') {
1467 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1468 } else if (featurestr[0] == '-') {
1469 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1470 } else if ((val = strchr(featurestr, '='))) {
1471 *val = 0; val++;
1472 feat2prop(featurestr);
1473 if (!strcmp(featurestr, "family")) {
1474 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1475 } else if (!strcmp(featurestr, "model")) {
1476 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1477 } else if (!strcmp(featurestr, "stepping")) {
1478 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1479 } else if (!strcmp(featurestr, "level")) {
1480 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1481 } else if (!strcmp(featurestr, "xlevel")) {
1482 char *err;
1483 char num[32];
1484
1485 numvalue = strtoul(val, &err, 0);
1486 if (!*val || *err) {
1487 error_setg(errp, "bad numerical value %s", val);
1488 goto out;
1489 }
1490 if (numvalue < 0x80000000) {
1491 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1492 ", fixup will be removed in future versions\n");
1493 numvalue += 0x80000000;
1494 }
1495 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1496 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1497 } else if (!strcmp(featurestr, "vendor")) {
1498 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1499 } else if (!strcmp(featurestr, "model-id")) {
1500 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1501 } else if (!strcmp(featurestr, "tsc-freq")) {
1502 int64_t tsc_freq;
1503 char *err;
1504 char num[32];
1505
1506 tsc_freq = strtosz_suffix_unit(val, &err,
1507 STRTOSZ_DEFSUFFIX_B, 1000);
1508 if (tsc_freq < 0 || *err) {
1509 error_setg(errp, "bad numerical value %s", val);
1510 goto out;
1511 }
1512 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1513 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1514 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1515 char *err;
1516 numvalue = strtoul(val, &err, 0);
1517 if (!*val || *err) {
1518 error_setg(errp, "bad numerical value %s", val);
1519 goto out;
1520 }
1521 hyperv_set_spinlock_retries(numvalue);
1522 } else {
1523 error_setg(errp, "unrecognized feature %s", featurestr);
1524 goto out;
1525 }
1526 } else if (!strcmp(featurestr, "check")) {
1527 check_cpuid = 1;
1528 } else if (!strcmp(featurestr, "enforce")) {
1529 check_cpuid = enforce_cpuid = 1;
1530 } else if (!strcmp(featurestr, "hv_relaxed")) {
1531 hyperv_enable_relaxed_timing(true);
1532 } else if (!strcmp(featurestr, "hv_vapic")) {
1533 hyperv_enable_vapic_recommended(true);
1534 } else {
1535 error_setg(errp, "feature string `%s' not in format (+feature|"
1536 "-feature|feature=xyz)", featurestr);
1537 goto out;
1538 }
1539 if (error_is_set(errp)) {
1540 goto out;
1541 }
1542 featurestr = strtok(NULL, ",");
1543 }
1544 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1545 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1546 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1547 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1548 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1549 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1550 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1551 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1552 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1553 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1554 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1555 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1556 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1557 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1558 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1559 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1560
1561 out:
1562 return;
1563 }
1564
1565 /* generate a composite string into buf of all cpuid names in featureset
1566 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1567 * if flags, suppress names undefined in featureset.
1568 */
1569 static void listflags(char *buf, int bufsize, uint32_t fbits,
1570 const char **featureset, uint32_t flags)
1571 {
1572 const char **p = &featureset[31];
1573 char *q, *b, bit;
1574 int nc;
1575
1576 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1577 *buf = '\0';
1578 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1579 if (fbits & 1 << bit && (*p || !flags)) {
1580 if (*p)
1581 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1582 else
1583 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1584 if (bufsize <= nc) {
1585 if (b) {
1586 memcpy(b, "...", sizeof("..."));
1587 }
1588 return;
1589 }
1590 q += nc;
1591 bufsize -= nc;
1592 }
1593 }
1594
1595 /* generate CPU information. */
1596 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1597 {
1598 x86_def_t *def;
1599 char buf[256];
1600 int i;
1601
1602 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1603 def = &builtin_x86_defs[i];
1604 snprintf(buf, sizeof(buf), "%s", def->name);
1605 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1606 }
1607 #ifdef CONFIG_KVM
1608 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1609 "KVM processor with all supported host features "
1610 "(only available in KVM mode)");
1611 #endif
1612
1613 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1614 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1615 FeatureWordInfo *fw = &feature_word_info[i];
1616
1617 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1618 (*cpu_fprintf)(f, " %s\n", buf);
1619 }
1620 }
1621
1622 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1623 {
1624 CpuDefinitionInfoList *cpu_list = NULL;
1625 x86_def_t *def;
1626 int i;
1627
1628 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1629 CpuDefinitionInfoList *entry;
1630 CpuDefinitionInfo *info;
1631
1632 def = &builtin_x86_defs[i];
1633 info = g_malloc0(sizeof(*info));
1634 info->name = g_strdup(def->name);
1635
1636 entry = g_malloc0(sizeof(*entry));
1637 entry->value = info;
1638 entry->next = cpu_list;
1639 cpu_list = entry;
1640 }
1641
1642 return cpu_list;
1643 }
1644
1645 #ifdef CONFIG_KVM
1646 static void filter_features_for_kvm(X86CPU *cpu)
1647 {
1648 CPUX86State *env = &cpu->env;
1649 KVMState *s = kvm_state;
1650
1651 env->features[FEAT_1_EDX] &=
1652 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1653 env->features[FEAT_1_ECX] &=
1654 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1655 env->features[FEAT_8000_0001_EDX] &=
1656 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1657 env->features[FEAT_8000_0001_ECX] &=
1658 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1659 env->features[FEAT_SVM] &=
1660 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1661 env->features[FEAT_7_0_EBX] &=
1662 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1663 env->features[FEAT_KVM] &=
1664 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1665 env->features[FEAT_C000_0001_EDX] &=
1666 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1667
1668 }
1669 #endif
1670
1671 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1672 {
1673 CPUX86State *env = &cpu->env;
1674 x86_def_t def1, *def = &def1;
1675
1676 memset(def, 0, sizeof(*def));
1677
1678 if (cpu_x86_find_by_name(def, name) < 0) {
1679 error_setg(errp, "Unable to find CPU definition: %s", name);
1680 return;
1681 }
1682
1683 if (kvm_enabled()) {
1684 def->features[FEAT_KVM] |= kvm_default_features;
1685 }
1686 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1687
1688 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1689 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1690 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1691 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1692 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1693 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1694 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1695 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1696 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1697 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1698 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1699 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1700 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1701 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1702 env->cpuid_xlevel2 = def->xlevel2;
1703
1704 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1705 }
1706
1707 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1708 Error **errp)
1709 {
1710 X86CPU *cpu = NULL;
1711 CPUX86State *env;
1712 gchar **model_pieces;
1713 char *name, *features;
1714 Error *error = NULL;
1715
1716 model_pieces = g_strsplit(cpu_model, ",", 2);
1717 if (!model_pieces[0]) {
1718 error_setg(&error, "Invalid/empty CPU model name");
1719 goto out;
1720 }
1721 name = model_pieces[0];
1722 features = model_pieces[1];
1723
1724 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1725 #ifndef CONFIG_USER_ONLY
1726 if (icc_bridge == NULL) {
1727 error_setg(&error, "Invalid icc-bridge value");
1728 goto out;
1729 }
1730 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1731 object_unref(OBJECT(cpu));
1732 #endif
1733 env = &cpu->env;
1734 env->cpu_model_str = cpu_model;
1735
1736 cpu_x86_register(cpu, name, &error);
1737 if (error) {
1738 goto out;
1739 }
1740
1741 cpu_x86_parse_featurestr(cpu, features, &error);
1742 if (error) {
1743 goto out;
1744 }
1745
1746 out:
1747 error_propagate(errp, error);
1748 g_strfreev(model_pieces);
1749 return cpu;
1750 }
1751
1752 X86CPU *cpu_x86_init(const char *cpu_model)
1753 {
1754 Error *error = NULL;
1755 X86CPU *cpu;
1756
1757 cpu = cpu_x86_create(cpu_model, NULL, &error);
1758 if (error) {
1759 goto out;
1760 }
1761
1762 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1763
1764 out:
1765 if (error) {
1766 fprintf(stderr, "%s\n", error_get_pretty(error));
1767 error_free(error);
1768 if (cpu != NULL) {
1769 object_unref(OBJECT(cpu));
1770 cpu = NULL;
1771 }
1772 }
1773 return cpu;
1774 }
1775
1776 #if !defined(CONFIG_USER_ONLY)
1777
1778 void cpu_clear_apic_feature(CPUX86State *env)
1779 {
1780 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
1781 }
1782
1783 #endif /* !CONFIG_USER_ONLY */
1784
1785 /* Initialize list of CPU models, filling some non-static fields if necessary
1786 */
1787 void x86_cpudef_setup(void)
1788 {
1789 int i, j;
1790 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1791
1792 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1793 x86_def_t *def = &builtin_x86_defs[i];
1794
1795 /* Look for specific "cpudef" models that */
1796 /* have the QEMU version in .model_id */
1797 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1798 if (strcmp(model_with_versions[j], def->name) == 0) {
1799 pstrcpy(def->model_id, sizeof(def->model_id),
1800 "QEMU Virtual CPU version ");
1801 pstrcat(def->model_id, sizeof(def->model_id),
1802 qemu_get_version());
1803 break;
1804 }
1805 }
1806 }
1807 }
1808
1809 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1810 uint32_t *ecx, uint32_t *edx)
1811 {
1812 *ebx = env->cpuid_vendor1;
1813 *edx = env->cpuid_vendor2;
1814 *ecx = env->cpuid_vendor3;
1815 }
1816
1817 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1818 uint32_t *eax, uint32_t *ebx,
1819 uint32_t *ecx, uint32_t *edx)
1820 {
1821 X86CPU *cpu = x86_env_get_cpu(env);
1822 CPUState *cs = CPU(cpu);
1823
1824 /* test if maximum index reached */
1825 if (index & 0x80000000) {
1826 if (index > env->cpuid_xlevel) {
1827 if (env->cpuid_xlevel2 > 0) {
1828 /* Handle the Centaur's CPUID instruction. */
1829 if (index > env->cpuid_xlevel2) {
1830 index = env->cpuid_xlevel2;
1831 } else if (index < 0xC0000000) {
1832 index = env->cpuid_xlevel;
1833 }
1834 } else {
1835 /* Intel documentation states that invalid EAX input will
1836 * return the same information as EAX=cpuid_level
1837 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1838 */
1839 index = env->cpuid_level;
1840 }
1841 }
1842 } else {
1843 if (index > env->cpuid_level)
1844 index = env->cpuid_level;
1845 }
1846
1847 switch(index) {
1848 case 0:
1849 *eax = env->cpuid_level;
1850 get_cpuid_vendor(env, ebx, ecx, edx);
1851 break;
1852 case 1:
1853 *eax = env->cpuid_version;
1854 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1855 *ecx = env->features[FEAT_1_ECX];
1856 *edx = env->features[FEAT_1_EDX];
1857 if (cs->nr_cores * cs->nr_threads > 1) {
1858 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1859 *edx |= 1 << 28; /* HTT bit */
1860 }
1861 break;
1862 case 2:
1863 /* cache info: needed for Pentium Pro compatibility */
1864 *eax = 1;
1865 *ebx = 0;
1866 *ecx = 0;
1867 *edx = 0x2c307d;
1868 break;
1869 case 4:
1870 /* cache info: needed for Core compatibility */
1871 if (cs->nr_cores > 1) {
1872 *eax = (cs->nr_cores - 1) << 26;
1873 } else {
1874 *eax = 0;
1875 }
1876 switch (count) {
1877 case 0: /* L1 dcache info */
1878 *eax |= 0x0000121;
1879 *ebx = 0x1c0003f;
1880 *ecx = 0x000003f;
1881 *edx = 0x0000001;
1882 break;
1883 case 1: /* L1 icache info */
1884 *eax |= 0x0000122;
1885 *ebx = 0x1c0003f;
1886 *ecx = 0x000003f;
1887 *edx = 0x0000001;
1888 break;
1889 case 2: /* L2 cache info */
1890 *eax |= 0x0000143;
1891 if (cs->nr_threads > 1) {
1892 *eax |= (cs->nr_threads - 1) << 14;
1893 }
1894 *ebx = 0x3c0003f;
1895 *ecx = 0x0000fff;
1896 *edx = 0x0000001;
1897 break;
1898 default: /* end of info */
1899 *eax = 0;
1900 *ebx = 0;
1901 *ecx = 0;
1902 *edx = 0;
1903 break;
1904 }
1905 break;
1906 case 5:
1907 /* mwait info: needed for Core compatibility */
1908 *eax = 0; /* Smallest monitor-line size in bytes */
1909 *ebx = 0; /* Largest monitor-line size in bytes */
1910 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1911 *edx = 0;
1912 break;
1913 case 6:
1914 /* Thermal and Power Leaf */
1915 *eax = 0;
1916 *ebx = 0;
1917 *ecx = 0;
1918 *edx = 0;
1919 break;
1920 case 7:
1921 /* Structured Extended Feature Flags Enumeration Leaf */
1922 if (count == 0) {
1923 *eax = 0; /* Maximum ECX value for sub-leaves */
1924 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
1925 *ecx = 0; /* Reserved */
1926 *edx = 0; /* Reserved */
1927 } else {
1928 *eax = 0;
1929 *ebx = 0;
1930 *ecx = 0;
1931 *edx = 0;
1932 }
1933 break;
1934 case 9:
1935 /* Direct Cache Access Information Leaf */
1936 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1937 *ebx = 0;
1938 *ecx = 0;
1939 *edx = 0;
1940 break;
1941 case 0xA:
1942 /* Architectural Performance Monitoring Leaf */
1943 if (kvm_enabled()) {
1944 KVMState *s = cs->kvm_state;
1945
1946 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1947 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1948 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1949 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1950 } else {
1951 *eax = 0;
1952 *ebx = 0;
1953 *ecx = 0;
1954 *edx = 0;
1955 }
1956 break;
1957 case 0xD:
1958 /* Processor Extended State */
1959 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
1960 *eax = 0;
1961 *ebx = 0;
1962 *ecx = 0;
1963 *edx = 0;
1964 break;
1965 }
1966 if (kvm_enabled()) {
1967 KVMState *s = cs->kvm_state;
1968
1969 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1970 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1971 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1972 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1973 } else {
1974 *eax = 0;
1975 *ebx = 0;
1976 *ecx = 0;
1977 *edx = 0;
1978 }
1979 break;
1980 case 0x80000000:
1981 *eax = env->cpuid_xlevel;
1982 *ebx = env->cpuid_vendor1;
1983 *edx = env->cpuid_vendor2;
1984 *ecx = env->cpuid_vendor3;
1985 break;
1986 case 0x80000001:
1987 *eax = env->cpuid_version;
1988 *ebx = 0;
1989 *ecx = env->features[FEAT_8000_0001_ECX];
1990 *edx = env->features[FEAT_8000_0001_EDX];
1991
1992 /* The Linux kernel checks for the CMPLegacy bit and
1993 * discards multiple thread information if it is set.
1994 * So dont set it here for Intel to make Linux guests happy.
1995 */
1996 if (cs->nr_cores * cs->nr_threads > 1) {
1997 uint32_t tebx, tecx, tedx;
1998 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1999 if (tebx != CPUID_VENDOR_INTEL_1 ||
2000 tedx != CPUID_VENDOR_INTEL_2 ||
2001 tecx != CPUID_VENDOR_INTEL_3) {
2002 *ecx |= 1 << 1; /* CmpLegacy bit */
2003 }
2004 }
2005 break;
2006 case 0x80000002:
2007 case 0x80000003:
2008 case 0x80000004:
2009 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2010 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2011 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2012 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2013 break;
2014 case 0x80000005:
2015 /* cache info (L1 cache) */
2016 *eax = 0x01ff01ff;
2017 *ebx = 0x01ff01ff;
2018 *ecx = 0x40020140;
2019 *edx = 0x40020140;
2020 break;
2021 case 0x80000006:
2022 /* cache info (L2 cache) */
2023 *eax = 0;
2024 *ebx = 0x42004200;
2025 *ecx = 0x02008140;
2026 *edx = 0;
2027 break;
2028 case 0x80000008:
2029 /* virtual & phys address size in low 2 bytes. */
2030 /* XXX: This value must match the one used in the MMU code. */
2031 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2032 /* 64 bit processor */
2033 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2034 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2035 } else {
2036 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2037 *eax = 0x00000024; /* 36 bits physical */
2038 } else {
2039 *eax = 0x00000020; /* 32 bits physical */
2040 }
2041 }
2042 *ebx = 0;
2043 *ecx = 0;
2044 *edx = 0;
2045 if (cs->nr_cores * cs->nr_threads > 1) {
2046 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2047 }
2048 break;
2049 case 0x8000000A:
2050 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2051 *eax = 0x00000001; /* SVM Revision */
2052 *ebx = 0x00000010; /* nr of ASIDs */
2053 *ecx = 0;
2054 *edx = env->features[FEAT_SVM]; /* optional features */
2055 } else {
2056 *eax = 0;
2057 *ebx = 0;
2058 *ecx = 0;
2059 *edx = 0;
2060 }
2061 break;
2062 case 0xC0000000:
2063 *eax = env->cpuid_xlevel2;
2064 *ebx = 0;
2065 *ecx = 0;
2066 *edx = 0;
2067 break;
2068 case 0xC0000001:
2069 /* Support for VIA CPU's CPUID instruction */
2070 *eax = env->cpuid_version;
2071 *ebx = 0;
2072 *ecx = 0;
2073 *edx = env->features[FEAT_C000_0001_EDX];
2074 break;
2075 case 0xC0000002:
2076 case 0xC0000003:
2077 case 0xC0000004:
2078 /* Reserved for the future, and now filled with zero */
2079 *eax = 0;
2080 *ebx = 0;
2081 *ecx = 0;
2082 *edx = 0;
2083 break;
2084 default:
2085 /* reserved values: zero */
2086 *eax = 0;
2087 *ebx = 0;
2088 *ecx = 0;
2089 *edx = 0;
2090 break;
2091 }
2092 }
2093
2094 /* CPUClass::reset() */
2095 static void x86_cpu_reset(CPUState *s)
2096 {
2097 X86CPU *cpu = X86_CPU(s);
2098 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2099 CPUX86State *env = &cpu->env;
2100 int i;
2101
2102 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
2103 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
2104 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
2105 }
2106
2107 xcc->parent_reset(s);
2108
2109
2110 memset(env, 0, offsetof(CPUX86State, breakpoints));
2111
2112 tlb_flush(env, 1);
2113
2114 env->old_exception = -1;
2115
2116 /* init to reset state */
2117
2118 #ifdef CONFIG_SOFTMMU
2119 env->hflags |= HF_SOFTMMU_MASK;
2120 #endif
2121 env->hflags2 |= HF2_GIF_MASK;
2122
2123 cpu_x86_update_cr0(env, 0x60000010);
2124 env->a20_mask = ~0x0;
2125 env->smbase = 0x30000;
2126
2127 env->idt.limit = 0xffff;
2128 env->gdt.limit = 0xffff;
2129 env->ldt.limit = 0xffff;
2130 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2131 env->tr.limit = 0xffff;
2132 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2133
2134 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2135 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2136 DESC_R_MASK | DESC_A_MASK);
2137 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2138 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2139 DESC_A_MASK);
2140 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2141 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2142 DESC_A_MASK);
2143 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2144 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2145 DESC_A_MASK);
2146 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2147 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2148 DESC_A_MASK);
2149 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2150 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2151 DESC_A_MASK);
2152
2153 env->eip = 0xfff0;
2154 env->regs[R_EDX] = env->cpuid_version;
2155
2156 env->eflags = 0x2;
2157
2158 /* FPU init */
2159 for (i = 0; i < 8; i++) {
2160 env->fptags[i] = 1;
2161 }
2162 env->fpuc = 0x37f;
2163
2164 env->mxcsr = 0x1f80;
2165
2166 env->pat = 0x0007040600070406ULL;
2167 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2168
2169 memset(env->dr, 0, sizeof(env->dr));
2170 env->dr[6] = DR6_FIXED_1;
2171 env->dr[7] = DR7_FIXED_1;
2172 cpu_breakpoint_remove_all(env, BP_CPU);
2173 cpu_watchpoint_remove_all(env, BP_CPU);
2174
2175 #if !defined(CONFIG_USER_ONLY)
2176 /* We hard-wire the BSP to the first CPU. */
2177 if (s->cpu_index == 0) {
2178 apic_designate_bsp(env->apic_state);
2179 }
2180
2181 s->halted = !cpu_is_bsp(cpu);
2182 #endif
2183 }
2184
2185 #ifndef CONFIG_USER_ONLY
2186 bool cpu_is_bsp(X86CPU *cpu)
2187 {
2188 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2189 }
2190
2191 /* TODO: remove me, when reset over QOM tree is implemented */
2192 static void x86_cpu_machine_reset_cb(void *opaque)
2193 {
2194 X86CPU *cpu = opaque;
2195 cpu_reset(CPU(cpu));
2196 }
2197 #endif
2198
2199 static void mce_init(X86CPU *cpu)
2200 {
2201 CPUX86State *cenv = &cpu->env;
2202 unsigned int bank;
2203
2204 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2205 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2206 (CPUID_MCE | CPUID_MCA)) {
2207 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2208 cenv->mcg_ctl = ~(uint64_t)0;
2209 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2210 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2211 }
2212 }
2213 }
2214
2215 #ifndef CONFIG_USER_ONLY
2216 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2217 {
2218 CPUX86State *env = &cpu->env;
2219 DeviceState *dev = DEVICE(cpu);
2220 APICCommonState *apic;
2221 const char *apic_type = "apic";
2222
2223 if (kvm_irqchip_in_kernel()) {
2224 apic_type = "kvm-apic";
2225 } else if (xen_enabled()) {
2226 apic_type = "xen-apic";
2227 }
2228
2229 env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2230 if (env->apic_state == NULL) {
2231 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2232 return;
2233 }
2234
2235 object_property_add_child(OBJECT(cpu), "apic",
2236 OBJECT(env->apic_state), NULL);
2237 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2238 /* TODO: convert to link<> */
2239 apic = APIC_COMMON(env->apic_state);
2240 apic->cpu = cpu;
2241 }
2242
2243 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2244 {
2245 CPUX86State *env = &cpu->env;
2246
2247 if (env->apic_state == NULL) {
2248 return;
2249 }
2250
2251 if (qdev_init(env->apic_state)) {
2252 error_setg(errp, "APIC device '%s' could not be initialized",
2253 object_get_typename(OBJECT(env->apic_state)));
2254 return;
2255 }
2256 }
2257 #else
2258 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2259 {
2260 }
2261 #endif
2262
2263 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2264 {
2265 X86CPU *cpu = X86_CPU(dev);
2266 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2267 CPUX86State *env = &cpu->env;
2268 Error *local_err = NULL;
2269
2270 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2271 env->cpuid_level = 7;
2272 }
2273
2274 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2275 * CPUID[1].EDX.
2276 */
2277 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2278 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2279 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2280 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2281 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2282 & CPUID_EXT2_AMD_ALIASES);
2283 }
2284
2285 if (!kvm_enabled()) {
2286 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2287 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2288 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2289 #ifdef TARGET_X86_64
2290 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2291 #endif
2292 );
2293 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2294 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2295 } else {
2296 if (check_cpuid && kvm_check_features_against_host(cpu)
2297 && enforce_cpuid) {
2298 error_setg(&local_err,
2299 "Host's CPU doesn't support requested features");
2300 goto out;
2301 }
2302 #ifdef CONFIG_KVM
2303 filter_features_for_kvm(cpu);
2304 #endif
2305 }
2306
2307 #ifndef CONFIG_USER_ONLY
2308 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2309
2310 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2311 x86_cpu_apic_create(cpu, &local_err);
2312 if (local_err != NULL) {
2313 goto out;
2314 }
2315 }
2316 #endif
2317
2318 mce_init(cpu);
2319 qemu_init_vcpu(&cpu->env);
2320
2321 x86_cpu_apic_realize(cpu, &local_err);
2322 if (local_err != NULL) {
2323 goto out;
2324 }
2325 cpu_reset(CPU(cpu));
2326
2327 xcc->parent_realize(dev, &local_err);
2328 out:
2329 if (local_err != NULL) {
2330 error_propagate(errp, local_err);
2331 return;
2332 }
2333 }
2334
2335 /* Enables contiguous-apic-ID mode, for compatibility */
2336 static bool compat_apic_id_mode;
2337
2338 void enable_compat_apic_id_mode(void)
2339 {
2340 compat_apic_id_mode = true;
2341 }
2342
2343 /* Calculates initial APIC ID for a specific CPU index
2344 *
2345 * Currently we need to be able to calculate the APIC ID from the CPU index
2346 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2347 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2348 * all CPUs up to max_cpus.
2349 */
2350 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2351 {
2352 uint32_t correct_id;
2353 static bool warned;
2354
2355 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2356 if (compat_apic_id_mode) {
2357 if (cpu_index != correct_id && !warned) {
2358 error_report("APIC IDs set in compatibility mode, "
2359 "CPU topology won't match the configuration");
2360 warned = true;
2361 }
2362 return cpu_index;
2363 } else {
2364 return correct_id;
2365 }
2366 }
2367
2368 static void x86_cpu_initfn(Object *obj)
2369 {
2370 CPUState *cs = CPU(obj);
2371 X86CPU *cpu = X86_CPU(obj);
2372 CPUX86State *env = &cpu->env;
2373 static int inited;
2374
2375 cs->env_ptr = env;
2376 cpu_exec_init(env);
2377
2378 object_property_add(obj, "family", "int",
2379 x86_cpuid_version_get_family,
2380 x86_cpuid_version_set_family, NULL, NULL, NULL);
2381 object_property_add(obj, "model", "int",
2382 x86_cpuid_version_get_model,
2383 x86_cpuid_version_set_model, NULL, NULL, NULL);
2384 object_property_add(obj, "stepping", "int",
2385 x86_cpuid_version_get_stepping,
2386 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2387 object_property_add(obj, "level", "int",
2388 x86_cpuid_get_level,
2389 x86_cpuid_set_level, NULL, NULL, NULL);
2390 object_property_add(obj, "xlevel", "int",
2391 x86_cpuid_get_xlevel,
2392 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2393 object_property_add_str(obj, "vendor",
2394 x86_cpuid_get_vendor,
2395 x86_cpuid_set_vendor, NULL);
2396 object_property_add_str(obj, "model-id",
2397 x86_cpuid_get_model_id,
2398 x86_cpuid_set_model_id, NULL);
2399 object_property_add(obj, "tsc-frequency", "int",
2400 x86_cpuid_get_tsc_freq,
2401 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2402 object_property_add(obj, "apic-id", "int",
2403 x86_cpuid_get_apic_id,
2404 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2405
2406 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2407
2408 /* init various static tables used in TCG mode */
2409 if (tcg_enabled() && !inited) {
2410 inited = 1;
2411 optimize_flags_init();
2412 #ifndef CONFIG_USER_ONLY
2413 cpu_set_debug_excp_handler(breakpoint_handler);
2414 #endif
2415 }
2416 }
2417
2418 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2419 {
2420 X86CPU *cpu = X86_CPU(cs);
2421 CPUX86State *env = &cpu->env;
2422
2423 return env->cpuid_apic_id;
2424 }
2425
2426 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2427 {
2428 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2429 CPUClass *cc = CPU_CLASS(oc);
2430 DeviceClass *dc = DEVICE_CLASS(oc);
2431
2432 xcc->parent_realize = dc->realize;
2433 dc->realize = x86_cpu_realizefn;
2434 dc->bus_type = TYPE_ICC_BUS;
2435
2436 xcc->parent_reset = cc->reset;
2437 cc->reset = x86_cpu_reset;
2438
2439 cc->do_interrupt = x86_cpu_do_interrupt;
2440 #ifndef CONFIG_USER_ONLY
2441 cc->write_elf64_note = x86_cpu_write_elf64_note;
2442 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2443 cc->write_elf32_note = x86_cpu_write_elf32_note;
2444 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2445 #endif
2446 cpu_class_set_vmsd(cc, &vmstate_x86_cpu);
2447
2448 cc->get_arch_id = x86_cpu_get_arch_id;
2449 }
2450
2451 static const TypeInfo x86_cpu_type_info = {
2452 .name = TYPE_X86_CPU,
2453 .parent = TYPE_CPU,
2454 .instance_size = sizeof(X86CPU),
2455 .instance_init = x86_cpu_initfn,
2456 .abstract = false,
2457 .class_size = sizeof(X86CPUClass),
2458 .class_init = x86_cpu_common_class_init,
2459 };
2460
2461 static void x86_cpu_register_types(void)
2462 {
2463 type_register_static(&x86_cpu_type_info);
2464 }
2465
2466 type_init(x86_cpu_register_types)
Qemu with PowerPC KVM improvements