target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUArchState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "exec/cpu-defs.h"
  31
  32 #include "fpu/softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 /* ARM-specific interrupt pending bits.  */
  59 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  60
  61
  62 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  63                             int srcreg, int operand, uint32_t value);
  64 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  65                                int dstreg, int operand);
  66
  67 struct arm_boot_info;
  68
  69 #define NB_MMU_MODES 2
  70
  71 /* We currently assume float and double are IEEE single and double
  72    precision respectively.
  73    Doing runtime conversions is tricky because VFP registers may contain
  74    integer values (eg. as the result of a FTOSI instruction).
  75    s<2n> maps to the least significant half of d<n>
  76    s<2n+1> maps to the most significant half of d<n>
  77  */
  78
  79 typedef struct CPUARMState {
  80     /* Regs for current mode.  */
  81     uint32_t regs[16];
  82     /* Frequently accessed CPSR bits are stored separately for efficiency.
  83        This contains all the other bits.  Use cpsr_{read,write} to access
  84        the whole CPSR.  */
  85     uint32_t uncached_cpsr;
  86     uint32_t spsr;
  87
  88     /* Banked registers.  */
  89     uint32_t banked_spsr[6];
  90     uint32_t banked_r13[6];
  91     uint32_t banked_r14[6];
  92
  93     /* These hold r8-r12.  */
  94     uint32_t usr_regs[5];
  95     uint32_t fiq_regs[5];
  96
  97     /* cpsr flag cache for faster execution */
  98     uint32_t CF; /* 0 or 1 */
  99     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 100     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 101     uint32_t ZF; /* Z set if zero.  */
 102     uint32_t QF; /* 0 or 1 */
 103     uint32_t GE; /* cpsr[19:16] */
 104     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 105     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 106
 107     /* System control coprocessor (cp15) */
 108     struct {
 109         uint32_t c0_cpuid;
 110         uint32_t c0_cssel; /* Cache size selection.  */
 111         uint32_t c1_sys; /* System control register.  */
 112         uint32_t c1_coproc; /* Coprocessor access register.  */
 113         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 114         uint32_t c1_scr; /* secure config register.  */
 115         uint32_t c2_base0; /* MMU translation table base 0.  */
 116         uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
 117         uint32_t c2_base1; /* MMU translation table base 0.  */
 118         uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
 119         uint32_t c2_control; /* MMU translation table base control.  */
 120         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 121         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 122         uint32_t c2_data; /* MPU data cachable bits.  */
 123         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 124         uint32_t c3; /* MMU domain access control register
 125                         MPU write buffer control.  */
 126         uint32_t c5_insn; /* Fault status registers.  */
 127         uint32_t c5_data;
 128         uint32_t c6_region[8]; /* MPU base/size registers.  */
 129         uint32_t c6_insn; /* Fault address registers.  */
 130         uint32_t c6_data;
 131         uint32_t c7_par;  /* Translation result. */
 132         uint32_t c7_par_hi;  /* Translation result, high 32 bits */
 133         uint32_t c9_insn; /* Cache lockdown registers.  */
 134         uint32_t c9_data;
 135         uint32_t c9_pmcr; /* performance monitor control register */
 136         uint32_t c9_pmcnten; /* perf monitor counter enables */
 137         uint32_t c9_pmovsr; /* perf monitor overflow status */
 138         uint32_t c9_pmxevtyper; /* perf monitor event type */
 139         uint32_t c9_pmuserenr; /* perf monitor user enable */
 140         uint32_t c9_pminten; /* perf monitor interrupt enables */
 141         uint32_t c13_fcse; /* FCSE PID.  */
 142         uint32_t c13_context; /* Context ID.  */
 143         uint32_t c13_tls1; /* User RW Thread register.  */
 144         uint32_t c13_tls2; /* User RO Thread register.  */
 145         uint32_t c13_tls3; /* Privileged Thread register.  */
 146         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 147         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 148         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 149         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 150         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 151         uint32_t c15_config_base_address; /* SCU base address.  */
 152         uint32_t c15_diagnostic; /* diagnostic register */
 153         uint32_t c15_power_diagnostic;
 154         uint32_t c15_power_control; /* power control */
 155     } cp15;
 156
 157     struct {
 158         uint32_t other_sp;
 159         uint32_t vecbase;
 160         uint32_t basepri;
 161         uint32_t control;
 162         int current_sp;
 163         int exception;
 164         int pending_exception;
 165     } v7m;
 166
 167     /* Thumb-2 EE state.  */
 168     uint32_t teecr;
 169     uint32_t teehbr;
 170
 171     /* VFP coprocessor state.  */
 172     struct {
 173         float64 regs[32];
 174
 175         uint32_t xregs[16];
 176         /* We store these fpcsr fields separately for convenience.  */
 177         int vec_len;
 178         int vec_stride;
 179
 180         /* scratch space when Tn are not sufficient.  */
 181         uint32_t scratch[8];
 182
 183         /* fp_status is the "normal" fp status. standard_fp_status retains
 184          * values corresponding to the ARM "Standard FPSCR Value", ie
 185          * default-NaN, flush-to-zero, round-to-nearest and is used by
 186          * any operations (generally Neon) which the architecture defines
 187          * as controlled by the standard FPSCR value rather than the FPSCR.
 188          *
 189          * To avoid having to transfer exception bits around, we simply
 190          * say that the FPSCR cumulative exception flags are the logical
 191          * OR of the flags in the two fp statuses. This relies on the
 192          * only thing which needs to read the exception flags being
 193          * an explicit FPSCR read.
 194          */
 195         float_status fp_status;
 196         float_status standard_fp_status;
 197     } vfp;
 198     uint32_t exclusive_addr;
 199     uint32_t exclusive_val;
 200     uint32_t exclusive_high;
 201 #if defined(CONFIG_USER_ONLY)
 202     uint32_t exclusive_test;
 203     uint32_t exclusive_info;
 204 #endif
 205
 206     /* iwMMXt coprocessor state.  */
 207     struct {
 208         uint64_t regs[16];
 209         uint64_t val;
 210
 211         uint32_t cregs[16];
 212     } iwmmxt;
 213
 214     /* For mixed endian mode.  */
 215     bool bswap_code;
 216
 217 #if defined(CONFIG_USER_ONLY)
 218     /* For usermode syscall translation.  */
 219     int eabi;
 220 #endif
 221
 222     CPU_COMMON
 223
 224     /* These fields after the common ones so they are preserved on reset.  */
 225
 226     /* Internal CPU feature flags.  */
 227     uint64_t features;
 228
 229     void *nvic;
 230     const struct arm_boot_info *boot_info;
 231 } CPUARMState;
 232
 233 #include "cpu-qom.h"
 234
 235 ARMCPU *cpu_arm_init(const char *cpu_model);
 236 void arm_translate_init(void);
 237 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 238 int cpu_arm_exec(CPUARMState *s);
 239 int bank_number(int mode);
 240 void switch_mode(CPUARMState *, int);
 241 uint32_t do_arm_semihosting(CPUARMState *env);
 242
 243 /* you can call this signal handler from your SIGBUS and SIGSEGV
 244    signal handlers to inform the virtual CPU of exceptions. non zero
 245    is returned if the signal was handled by the virtual CPU.  */
 246 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 247                            void *puc);
 248 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 249                               int mmu_idx);
 250 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 251
 252 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 253 {
 254   env->cp15.c13_tls2 = newtls;
 255 }
 256
 257 #define CPSR_M (0x1f)
 258 #define CPSR_T (1 << 5)
 259 #define CPSR_F (1 << 6)
 260 #define CPSR_I (1 << 7)
 261 #define CPSR_A (1 << 8)
 262 #define CPSR_E (1 << 9)
 263 #define CPSR_IT_2_7 (0xfc00)
 264 #define CPSR_GE (0xf << 16)
 265 #define CPSR_RESERVED (0xf << 20)
 266 #define CPSR_J (1 << 24)
 267 #define CPSR_IT_0_1 (3 << 25)
 268 #define CPSR_Q (1 << 27)
 269 #define CPSR_V (1 << 28)
 270 #define CPSR_C (1 << 29)
 271 #define CPSR_Z (1 << 30)
 272 #define CPSR_N (1 << 31)
 273 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 274
 275 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 276 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 277 /* Bits writable in user mode.  */
 278 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 279 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 280 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 281
 282 /* Return the current CPSR value.  */
 283 uint32_t cpsr_read(CPUARMState *env);
 284 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 285 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 286
 287 /* Return the current xPSR value.  */
 288 static inline uint32_t xpsr_read(CPUARMState *env)
 289 {
 290     int ZF;
 291     ZF = (env->ZF == 0);
 292     return (env->NF & 0x80000000) | (ZF << 30)
 293         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 294         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 295         | ((env->condexec_bits & 0xfc) << 8)
 296         | env->v7m.exception;
 297 }
 298
 299 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 300 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 301 {
 302     if (mask & CPSR_NZCV) {
 303         env->ZF = (~val) & CPSR_Z;
 304         env->NF = val;
 305         env->CF = (val >> 29) & 1;
 306         env->VF = (val << 3) & 0x80000000;
 307     }
 308     if (mask & CPSR_Q)
 309         env->QF = ((val & CPSR_Q) != 0);
 310     if (mask & (1 << 24))
 311         env->thumb = ((val & (1 << 24)) != 0);
 312     if (mask & CPSR_IT_0_1) {
 313         env->condexec_bits &= ~3;
 314         env->condexec_bits |= (val >> 25) & 3;
 315     }
 316     if (mask & CPSR_IT_2_7) {
 317         env->condexec_bits &= 3;
 318         env->condexec_bits |= (val >> 8) & 0xfc;
 319     }
 320     if (mask & 0x1ff) {
 321         env->v7m.exception = val & 0x1ff;
 322     }
 323 }
 324
 325 /* Return the current FPSCR value.  */
 326 uint32_t vfp_get_fpscr(CPUARMState *env);
 327 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 328
 329 enum arm_cpu_mode {
 330   ARM_CPU_MODE_USR = 0x10,
 331   ARM_CPU_MODE_FIQ = 0x11,
 332   ARM_CPU_MODE_IRQ = 0x12,
 333   ARM_CPU_MODE_SVC = 0x13,
 334   ARM_CPU_MODE_ABT = 0x17,
 335   ARM_CPU_MODE_UND = 0x1b,
 336   ARM_CPU_MODE_SYS = 0x1f
 337 };
 338
 339 /* VFP system registers.  */
 340 #define ARM_VFP_FPSID   0
 341 #define ARM_VFP_FPSCR   1
 342 #define ARM_VFP_MVFR1   6
 343 #define ARM_VFP_MVFR0   7
 344 #define ARM_VFP_FPEXC   8
 345 #define ARM_VFP_FPINST  9
 346 #define ARM_VFP_FPINST2 10
 347
 348 /* iwMMXt coprocessor control registers.  */
 349 #define ARM_IWMMXT_wCID         0
 350 #define ARM_IWMMXT_wCon         1
 351 #define ARM_IWMMXT_wCSSF        2
 352 #define ARM_IWMMXT_wCASF        3
 353 #define ARM_IWMMXT_wCGR0        8
 354 #define ARM_IWMMXT_wCGR1        9
 355 #define ARM_IWMMXT_wCGR2        10
 356 #define ARM_IWMMXT_wCGR3        11
 357
 358 /* If adding a feature bit which corresponds to a Linux ELF
 359  * HWCAP bit, remember to update the feature-bit-to-hwcap
 360  * mapping in linux-user/elfload.c:get_elf_hwcap().
 361  */
 362 enum arm_features {
 363     ARM_FEATURE_VFP,
 364     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 365     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 366     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 367     ARM_FEATURE_V6,
 368     ARM_FEATURE_V6K,
 369     ARM_FEATURE_V7,
 370     ARM_FEATURE_THUMB2,
 371     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 372     ARM_FEATURE_VFP3,
 373     ARM_FEATURE_VFP_FP16,
 374     ARM_FEATURE_NEON,
 375     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 376     ARM_FEATURE_M, /* Microcontroller profile.  */
 377     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 378     ARM_FEATURE_THUMB2EE,
 379     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 380     ARM_FEATURE_V4T,
 381     ARM_FEATURE_V5,
 382     ARM_FEATURE_STRONGARM,
 383     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 384     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 385     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 386     ARM_FEATURE_GENERIC_TIMER,
 387     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 388     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 389     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 390     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 391     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 392     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 393     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
 394     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
 395 };
 396
 397 static inline int arm_feature(CPUARMState *env, int feature)
 398 {
 399     return (env->features & (1ULL << feature)) != 0;
 400 }
 401
 402 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 403
 404 /* Interface between CPU and Interrupt controller.  */
 405 void armv7m_nvic_set_pending(void *opaque, int irq);
 406 int armv7m_nvic_acknowledge_irq(void *opaque);
 407 void armv7m_nvic_complete_irq(void *opaque, int irq);
 408
 409 /* Interface for defining coprocessor registers.
 410  * Registers are defined in tables of arm_cp_reginfo structs
 411  * which are passed to define_arm_cp_regs().
 412  */
 413
 414 /* When looking up a coprocessor register we look for it
 415  * via an integer which encodes all of:
 416  *  coprocessor number
 417  *  Crn, Crm, opc1, opc2 fields
 418  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 419  *    or via MRRC/MCRR?)
 420  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 421  * (In this case crn and opc2 should be zero.)
 422  */
 423 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 424     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 425      ((crm) << 7) | ((opc1) << 3) | (opc2))
 426
 427 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 428  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 429  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 430  * TCG can assume the value to be constant (ie load at translate time)
 431  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 432  * indicates that the TB should not be ended after a write to this register
 433  * (the default is that the TB ends after cp writes). OVERRIDE permits
 434  * a register definition to override a previous definition for the
 435  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 436  * old must have the OVERRIDE bit set.
 437  */
 438 #define ARM_CP_SPECIAL 1
 439 #define ARM_CP_CONST 2
 440 #define ARM_CP_64BIT 4
 441 #define ARM_CP_SUPPRESS_TB_END 8
 442 #define ARM_CP_OVERRIDE 16
 443 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 444 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 445 #define ARM_LAST_SPECIAL ARM_CP_WFI
 446 /* Used only as a terminator for ARMCPRegInfo lists */
 447 #define ARM_CP_SENTINEL 0xffff
 448 /* Mask of only the flag bits in a type field */
 449 #define ARM_CP_FLAG_MASK 0x1f
 450
 451 /* Return true if cptype is a valid type field. This is used to try to
 452  * catch errors where the sentinel has been accidentally left off the end
 453  * of a list of registers.
 454  */
 455 static inline bool cptype_valid(int cptype)
 456 {
 457     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 458         || ((cptype & ARM_CP_SPECIAL) &&
 459             (cptype <= ARM_LAST_SPECIAL));
 460 }
 461
 462 /* Access rights:
 463  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 464  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 465  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 466  * (ie any of the privileged modes in Secure state, or Monitor mode).
 467  * If a register is accessible in one privilege level it's always accessible
 468  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 469  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 470  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 471  * terminology a little and call this PL3.
 472  *
 473  * If access permissions for a register are more complex than can be
 474  * described with these bits, then use a laxer set of restrictions, and
 475  * do the more restrictive/complex check inside a helper function.
 476  */
 477 #define PL3_R 0x80
 478 #define PL3_W 0x40
 479 #define PL2_R (0x20 | PL3_R)
 480 #define PL2_W (0x10 | PL3_W)
 481 #define PL1_R (0x08 | PL2_R)
 482 #define PL1_W (0x04 | PL2_W)
 483 #define PL0_R (0x02 | PL1_R)
 484 #define PL0_W (0x01 | PL1_W)
 485
 486 #define PL3_RW (PL3_R | PL3_W)
 487 #define PL2_RW (PL2_R | PL2_W)
 488 #define PL1_RW (PL1_R | PL1_W)
 489 #define PL0_RW (PL0_R | PL0_W)
 490
 491 static inline int arm_current_pl(CPUARMState *env)
 492 {
 493     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 494         return 0;
 495     }
 496     /* We don't currently implement the Virtualization or TrustZone
 497      * extensions, so PL2 and PL3 don't exist for us.
 498      */
 499     return 1;
 500 }
 501
 502 typedef struct ARMCPRegInfo ARMCPRegInfo;
 503
 504 /* Access functions for coprocessor registers. These should return
 505  * 0 on success, or one of the EXCP_* constants if access should cause
 506  * an exception (in which case *value is not written).
 507  */
 508 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 509                      uint64_t *value);
 510 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 511                       uint64_t value);
 512 /* Hook function for register reset */
 513 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 514
 515 #define CP_ANY 0xff
 516
 517 /* Definition of an ARM coprocessor register */
 518 struct ARMCPRegInfo {
 519     /* Name of register (useful mainly for debugging, need not be unique) */
 520     const char *name;
 521     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 522      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 523      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 524      * will be decoded to this register. The register read and write
 525      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 526      * used by the program, so it is possible to register a wildcard and
 527      * then behave differently on read/write if necessary.
 528      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 529      * must both be zero.
 530      */
 531     uint8_t cp;
 532     uint8_t crn;
 533     uint8_t crm;
 534     uint8_t opc1;
 535     uint8_t opc2;
 536     /* Register type: ARM_CP_* bits/values */
 537     int type;
 538     /* Access rights: PL*_[RW] */
 539     int access;
 540     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 541      * this register was defined: can be used to hand data through to the
 542      * register read/write functions, since they are passed the ARMCPRegInfo*.
 543      */
 544     void *opaque;
 545     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 546      * fieldoffset is non-zero, the reset value of the register.
 547      */
 548     uint64_t resetvalue;
 549     /* Offset of the field in CPUARMState for this register. This is not
 550      * needed if either:
 551      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 552      *  2. both readfn and writefn are specified
 553      */
 554     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 555     /* Function for handling reads of this register. If NULL, then reads
 556      * will be done by loading from the offset into CPUARMState specified
 557      * by fieldoffset.
 558      */
 559     CPReadFn *readfn;
 560     /* Function for handling writes of this register. If NULL, then writes
 561      * will be done by writing to the offset into CPUARMState specified
 562      * by fieldoffset.
 563      */
 564     CPWriteFn *writefn;
 565     /* Function for resetting the register. If NULL, then reset will be done
 566      * by writing resetvalue to the field specified in fieldoffset. If
 567      * fieldoffset is 0 then no reset will be done.
 568      */
 569     CPResetFn *resetfn;
 570 };
 571
 572 /* Macros which are lvalues for the field in CPUARMState for the
 573  * ARMCPRegInfo *ri.
 574  */
 575 #define CPREG_FIELD32(env, ri) \
 576     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 577 #define CPREG_FIELD64(env, ri) \
 578     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 579
 580 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 581
 582 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 583                                     const ARMCPRegInfo *regs, void *opaque);
 584 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 585                                        const ARMCPRegInfo *regs, void *opaque);
 586 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 587 {
 588     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 589 }
 590 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 591 {
 592     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 593 }
 594 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 595
 596 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 597 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 598                         uint64_t value);
 599 /* CPReadFn that can be used for read-as-zero behaviour */
 600 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 601
 602 static inline bool cp_access_ok(CPUARMState *env,
 603                                 const ARMCPRegInfo *ri, int isread)
 604 {
 605     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 606 }
 607
 608 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 609    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 610    conventional cores (ie. Application or Realtime profile).  */
 611
 612 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 613
 614 #define ARM_CPUID_TI915T      0x54029152
 615 #define ARM_CPUID_TI925T      0x54029252
 616
 617 #if defined(CONFIG_USER_ONLY)
 618 #define TARGET_PAGE_BITS 12
 619 #else
 620 /* The ARM MMU allows 1k pages.  */
 621 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 622    architecture revisions.  Maybe a configure option to disable them.  */
 623 #define TARGET_PAGE_BITS 10
 624 #endif
 625
 626 #define TARGET_PHYS_ADDR_SPACE_BITS 40
 627 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 628
 629 static inline CPUARMState *cpu_init(const char *cpu_model)
 630 {
 631     ARMCPU *cpu = cpu_arm_init(cpu_model);
 632     if (cpu) {
 633         return &cpu->env;
 634     }
 635     return NULL;
 636 }
 637
 638 #define cpu_exec cpu_arm_exec
 639 #define cpu_gen_code cpu_arm_gen_code
 640 #define cpu_signal_handler cpu_arm_signal_handler
 641 #define cpu_list arm_cpu_list
 642
 643 /* MMU modes definitions */
 644 #define MMU_MODE0_SUFFIX _kernel
 645 #define MMU_MODE1_SUFFIX _user
 646 #define MMU_USER_IDX 1
 647 static inline int cpu_mmu_index (CPUARMState *env)
 648 {
 649     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 650 }
 651
 652 #if defined(CONFIG_USER_ONLY)
 653 static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 654 {
 655     if (newsp)
 656         env->regs[13] = newsp;
 657     env->regs[0] = 0;
 658 }
 659 #endif
 660
 661 #include "exec/cpu-all.h"
 662
 663 /* Bit usage in the TB flags field: */
 664 #define ARM_TBFLAG_THUMB_SHIFT      0
 665 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 666 #define ARM_TBFLAG_VECLEN_SHIFT     1
 667 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 668 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 669 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 670 #define ARM_TBFLAG_PRIV_SHIFT       6
 671 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 672 #define ARM_TBFLAG_VFPEN_SHIFT      7
 673 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 674 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 675 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 676 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 677 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 678 /* Bits 31..17 are currently unused. */
 679
 680 /* some convenience accessor macros */
 681 #define ARM_TBFLAG_THUMB(F) \
 682     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 683 #define ARM_TBFLAG_VECLEN(F) \
 684     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 685 #define ARM_TBFLAG_VECSTRIDE(F) \
 686     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 687 #define ARM_TBFLAG_PRIV(F) \
 688     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 689 #define ARM_TBFLAG_VFPEN(F) \
 690     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 691 #define ARM_TBFLAG_CONDEXEC(F) \
 692     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 693 #define ARM_TBFLAG_BSWAP_CODE(F) \
 694     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 695
 696 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 697                                         target_ulong *cs_base, int *flags)
 698 {
 699     int privmode;
 700     *pc = env->regs[15];
 701     *cs_base = 0;
 702     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 703         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 704         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 705         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 706         | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 707     if (arm_feature(env, ARM_FEATURE_M)) {
 708         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 709     } else {
 710         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 711     }
 712     if (privmode) {
 713         *flags |= ARM_TBFLAG_PRIV_MASK;
 714     }
 715     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 716         *flags |= ARM_TBFLAG_VFPEN_MASK;
 717     }
 718 }
 719
 720 static inline bool cpu_has_work(CPUState *cpu)
 721 {
 722     return cpu->interrupt_request &
 723         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 724 }
 725
 726 #include "exec/exec-all.h"
 727
 728 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 729 {
 730     env->regs[15] = tb->pc;
 731 }
 732
 733 /* Load an instruction and return it in the standard little-endian order */
 734 static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
 735                                     bool do_swap)
 736 {
 737     uint32_t insn = cpu_ldl_code(env, addr);
 738     if (do_swap) {
 739         return bswap32(insn);
 740     }
 741     return insn;
 742 }
 743
 744 /* Ditto, for a halfword (Thumb) instruction */
 745 static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
 746                                      bool do_swap)
 747 {
 748     uint16_t insn = cpu_lduw_code(env, addr);
 749     if (do_swap) {
 750         return bswap16(insn);
 751     }
 752     return insn;
 753 }
 754
 755 #endif