hw/gpio/puv3_gpio.c

   1 /*
   2  * GPIO device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11 #include "hw/hw.h"
  12 #include "hw/sysbus.h"
  13
  14 #undef DEBUG_PUV3
  15 #include "hw/unicore32/puv3.h"
  16
  17 typedef struct {
  18     SysBusDevice busdev;
  19     MemoryRegion iomem;
  20     qemu_irq irq[9];
  21
  22     uint32_t reg_GPLR;
  23     uint32_t reg_GPDR;
  24     uint32_t reg_GPIR;
  25 } PUV3GPIOState;
  26
  27 static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
  28         unsigned size)
  29 {
  30     PUV3GPIOState *s = opaque;
  31     uint32_t ret = 0;
  32
  33     switch (offset) {
  34     case 0x00:
  35         ret = s->reg_GPLR;
  36         break;
  37     case 0x04:
  38         ret = s->reg_GPDR;
  39         break;
  40     case 0x20:
  41         ret = s->reg_GPIR;
  42         break;
  43     default:
  44         DPRINTF("Bad offset 0x%x\n", offset);
  45     }
  46     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  47
  48     return ret;
  49 }
  50
  51 static void puv3_gpio_write(void *opaque, hwaddr offset,
  52         uint64_t value, unsigned size)
  53 {
  54     PUV3GPIOState *s = opaque;
  55
  56     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  57     switch (offset) {
  58     case 0x04:
  59         s->reg_GPDR = value;
  60         break;
  61     case 0x08:
  62         if (s->reg_GPDR & value) {
  63             s->reg_GPLR |= value;
  64         } else {
  65             DPRINTF("Write gpio input port error!");
  66         }
  67         break;
  68     case 0x0c:
  69         if (s->reg_GPDR & value) {
  70             s->reg_GPLR &= ~value;
  71         } else {
  72             DPRINTF("Write gpio input port error!");
  73         }
  74         break;
  75     case 0x10: /* GRER */
  76     case 0x14: /* GFER */
  77     case 0x18: /* GEDR */
  78         break;
  79     case 0x20: /* GPIR */
  80         s->reg_GPIR = value;
  81         break;
  82     default:
  83         DPRINTF("Bad offset 0x%x\n", offset);
  84     }
  85 }
  86
  87 static const MemoryRegionOps puv3_gpio_ops = {
  88     .read = puv3_gpio_read,
  89     .write = puv3_gpio_write,
  90     .impl = {
  91         .min_access_size = 4,
  92         .max_access_size = 4,
  93     },
  94     .endianness = DEVICE_NATIVE_ENDIAN,
  95 };
  96
  97 static int puv3_gpio_init(SysBusDevice *dev)
  98 {
  99     PUV3GPIOState *s = FROM_SYSBUS(PUV3GPIOState, dev);
 100
 101     s->reg_GPLR = 0;
 102     s->reg_GPDR = 0;
 103
 104     /* FIXME: these irqs not handled yet */
 105     sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]);
 106     sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]);
 107     sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]);
 108     sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]);
 109     sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]);
 110     sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]);
 111     sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]);
 112     sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]);
 113     sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]);
 114
 115     memory_region_init_io(&s->iomem, &puv3_gpio_ops, s, "puv3_gpio",
 116             PUV3_REGS_OFFSET);
 117     sysbus_init_mmio(dev, &s->iomem);
 118
 119     return 0;
 120 }
 121
 122 static void puv3_gpio_class_init(ObjectClass *klass, void *data)
 123 {
 124     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 125
 126     sdc->init = puv3_gpio_init;
 127 }
 128
 129 static const TypeInfo puv3_gpio_info = {
 130     .name = "puv3_gpio",
 131     .parent = TYPE_SYS_BUS_DEVICE,
 132     .instance_size = sizeof(PUV3GPIOState),
 133     .class_init = puv3_gpio_class_init,
 134 };
 135
 136 static void puv3_gpio_register_type(void)
 137 {
 138     type_register_static(&puv3_gpio_info);
 139 }
 140
 141 type_init(puv3_gpio_register_type)