target-ppc: Fix invalid SPR read/write warnings
[qemu/agraf.git] / exec.c
blob19725dbc05e0a72767c95239337d1ed800bdf82a
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "config.h"
20 #ifdef _WIN32
21 #include <windows.h>
22 #else
23 #include <sys/types.h>
24 #include <sys/mman.h>
25 #endif
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "tcg.h"
30 #include "hw/hw.h"
31 #include "hw/qdev.h"
32 #include "qemu/osdep.h"
33 #include "sysemu/kvm.h"
34 #include "hw/xen/xen.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "exec/memory.h"
38 #include "sysemu/dma.h"
39 #include "exec/address-spaces.h"
40 #if defined(CONFIG_USER_ONLY)
41 #include <qemu.h>
42 #else /* !CONFIG_USER_ONLY */
43 #include "sysemu/xen-mapcache.h"
44 #include "trace.h"
45 #endif
46 #include "exec/cpu-all.h"
48 #include "exec/cputlb.h"
49 #include "translate-all.h"
51 #include "exec/memory-internal.h"
53 //#define DEBUG_UNASSIGNED
54 //#define DEBUG_SUBPAGE
56 #if !defined(CONFIG_USER_ONLY)
57 int phys_ram_fd;
58 static int in_migration;
60 RAMList ram_list = { .blocks = QTAILQ_HEAD_INITIALIZER(ram_list.blocks) };
62 static MemoryRegion *system_memory;
63 static MemoryRegion *system_io;
65 AddressSpace address_space_io;
66 AddressSpace address_space_memory;
67 DMAContext dma_context_memory;
69 MemoryRegion io_mem_ram, io_mem_rom, io_mem_unassigned, io_mem_notdirty;
70 static MemoryRegion io_mem_subpage_ram;
72 #endif
74 CPUArchState *first_cpu;
75 /* current CPU in the current thread. It is only valid inside
76 cpu_exec() */
77 DEFINE_TLS(CPUArchState *,cpu_single_env);
78 /* 0 = Do not count executed instructions.
79 1 = Precise instruction counting.
80 2 = Adaptive rate instruction counting. */
81 int use_icount;
83 #if !defined(CONFIG_USER_ONLY)
85 static MemoryRegionSection *phys_sections;
86 static unsigned phys_sections_nb, phys_sections_nb_alloc;
87 static uint16_t phys_section_unassigned;
88 static uint16_t phys_section_notdirty;
89 static uint16_t phys_section_rom;
90 static uint16_t phys_section_watch;
92 /* Simple allocator for PhysPageEntry nodes */
93 static PhysPageEntry (*phys_map_nodes)[L2_SIZE];
94 static unsigned phys_map_nodes_nb, phys_map_nodes_nb_alloc;
96 #define PHYS_MAP_NODE_NIL (((uint16_t)~0) >> 1)
98 static void io_mem_init(void);
99 static void memory_map_init(void);
100 static void *qemu_safe_ram_ptr(ram_addr_t addr);
102 static MemoryRegion io_mem_watch;
103 #endif
105 #if !defined(CONFIG_USER_ONLY)
107 static void phys_map_node_reserve(unsigned nodes)
109 if (phys_map_nodes_nb + nodes > phys_map_nodes_nb_alloc) {
110 typedef PhysPageEntry Node[L2_SIZE];
111 phys_map_nodes_nb_alloc = MAX(phys_map_nodes_nb_alloc * 2, 16);
112 phys_map_nodes_nb_alloc = MAX(phys_map_nodes_nb_alloc,
113 phys_map_nodes_nb + nodes);
114 phys_map_nodes = g_renew(Node, phys_map_nodes,
115 phys_map_nodes_nb_alloc);
119 static uint16_t phys_map_node_alloc(void)
121 unsigned i;
122 uint16_t ret;
124 ret = phys_map_nodes_nb++;
125 assert(ret != PHYS_MAP_NODE_NIL);
126 assert(ret != phys_map_nodes_nb_alloc);
127 for (i = 0; i < L2_SIZE; ++i) {
128 phys_map_nodes[ret][i].is_leaf = 0;
129 phys_map_nodes[ret][i].ptr = PHYS_MAP_NODE_NIL;
131 return ret;
134 static void phys_map_nodes_reset(void)
136 phys_map_nodes_nb = 0;
140 static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index,
141 hwaddr *nb, uint16_t leaf,
142 int level)
144 PhysPageEntry *p;
145 int i;
146 hwaddr step = (hwaddr)1 << (level * L2_BITS);
148 if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) {
149 lp->ptr = phys_map_node_alloc();
150 p = phys_map_nodes[lp->ptr];
151 if (level == 0) {
152 for (i = 0; i < L2_SIZE; i++) {
153 p[i].is_leaf = 1;
154 p[i].ptr = phys_section_unassigned;
157 } else {
158 p = phys_map_nodes[lp->ptr];
160 lp = &p[(*index >> (level * L2_BITS)) & (L2_SIZE - 1)];
162 while (*nb && lp < &p[L2_SIZE]) {
163 if ((*index & (step - 1)) == 0 && *nb >= step) {
164 lp->is_leaf = true;
165 lp->ptr = leaf;
166 *index += step;
167 *nb -= step;
168 } else {
169 phys_page_set_level(lp, index, nb, leaf, level - 1);
171 ++lp;
175 static void phys_page_set(AddressSpaceDispatch *d,
176 hwaddr index, hwaddr nb,
177 uint16_t leaf)
179 /* Wildly overreserve - it doesn't matter much. */
180 phys_map_node_reserve(3 * P_L2_LEVELS);
182 phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
185 MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
187 PhysPageEntry lp = d->phys_map;
188 PhysPageEntry *p;
189 int i;
190 uint16_t s_index = phys_section_unassigned;
192 for (i = P_L2_LEVELS - 1; i >= 0 && !lp.is_leaf; i--) {
193 if (lp.ptr == PHYS_MAP_NODE_NIL) {
194 goto not_found;
196 p = phys_map_nodes[lp.ptr];
197 lp = p[(index >> (i * L2_BITS)) & (L2_SIZE - 1)];
200 s_index = lp.ptr;
201 not_found:
202 return &phys_sections[s_index];
205 bool memory_region_is_unassigned(MemoryRegion *mr)
207 return mr != &io_mem_ram && mr != &io_mem_rom
208 && mr != &io_mem_notdirty && !mr->rom_device
209 && mr != &io_mem_watch;
211 #endif
213 void cpu_exec_init_all(void)
215 #if !defined(CONFIG_USER_ONLY)
216 qemu_mutex_init(&ram_list.mutex);
217 memory_map_init();
218 io_mem_init();
219 #endif
222 #if !defined(CONFIG_USER_ONLY)
224 static int cpu_common_post_load(void *opaque, int version_id)
226 CPUState *cpu = opaque;
228 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
229 version_id is increased. */
230 cpu->interrupt_request &= ~0x01;
231 tlb_flush(cpu->env_ptr, 1);
233 return 0;
236 static const VMStateDescription vmstate_cpu_common = {
237 .name = "cpu_common",
238 .version_id = 1,
239 .minimum_version_id = 1,
240 .minimum_version_id_old = 1,
241 .post_load = cpu_common_post_load,
242 .fields = (VMStateField []) {
243 VMSTATE_UINT32(halted, CPUState),
244 VMSTATE_UINT32(interrupt_request, CPUState),
245 VMSTATE_END_OF_LIST()
248 #else
249 #define vmstate_cpu_common vmstate_dummy
250 #endif
252 CPUState *qemu_get_cpu(int index)
254 CPUArchState *env = first_cpu;
255 CPUState *cpu = NULL;
257 while (env) {
258 cpu = ENV_GET_CPU(env);
259 if (cpu->cpu_index == index) {
260 break;
262 env = env->next_cpu;
265 return env ? cpu : NULL;
268 void qemu_for_each_cpu(void (*func)(CPUState *cpu, void *data), void *data)
270 CPUArchState *env = first_cpu;
272 while (env) {
273 func(ENV_GET_CPU(env), data);
274 env = env->next_cpu;
278 void cpu_exec_init(CPUArchState *env)
280 CPUState *cpu = ENV_GET_CPU(env);
281 CPUClass *cc = CPU_GET_CLASS(cpu);
282 CPUArchState **penv;
283 int cpu_index;
285 #if defined(CONFIG_USER_ONLY)
286 cpu_list_lock();
287 #endif
288 env->next_cpu = NULL;
289 penv = &first_cpu;
290 cpu_index = 0;
291 while (*penv != NULL) {
292 penv = &(*penv)->next_cpu;
293 cpu_index++;
295 cpu->cpu_index = cpu_index;
296 cpu->numa_node = 0;
297 QTAILQ_INIT(&env->breakpoints);
298 QTAILQ_INIT(&env->watchpoints);
299 #ifndef CONFIG_USER_ONLY
300 cpu->thread_id = qemu_get_thread_id();
301 #endif
302 *penv = env;
303 #if defined(CONFIG_USER_ONLY)
304 cpu_list_unlock();
305 #endif
306 vmstate_register(NULL, cpu_index, &vmstate_cpu_common, cpu);
307 #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
308 register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
309 cpu_save, cpu_load, env);
310 assert(cc->vmsd == NULL);
311 #endif
312 if (cc->vmsd != NULL) {
313 vmstate_register(NULL, cpu_index, cc->vmsd, cpu);
317 #if defined(TARGET_HAS_ICE)
318 #if defined(CONFIG_USER_ONLY)
319 static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
321 tb_invalidate_phys_page_range(pc, pc + 1, 0);
323 #else
324 static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
326 tb_invalidate_phys_addr(cpu_get_phys_page_debug(env, pc) |
327 (pc & ~TARGET_PAGE_MASK));
329 #endif
330 #endif /* TARGET_HAS_ICE */
332 #if defined(CONFIG_USER_ONLY)
333 void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
338 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
339 int flags, CPUWatchpoint **watchpoint)
341 return -ENOSYS;
343 #else
344 /* Add a watchpoint. */
345 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
346 int flags, CPUWatchpoint **watchpoint)
348 target_ulong len_mask = ~(len - 1);
349 CPUWatchpoint *wp;
351 /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
352 if ((len & (len - 1)) || (addr & ~len_mask) ||
353 len == 0 || len > TARGET_PAGE_SIZE) {
354 fprintf(stderr, "qemu: tried to set invalid watchpoint at "
355 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
356 return -EINVAL;
358 wp = g_malloc(sizeof(*wp));
360 wp->vaddr = addr;
361 wp->len_mask = len_mask;
362 wp->flags = flags;
364 /* keep all GDB-injected watchpoints in front */
365 if (flags & BP_GDB)
366 QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
367 else
368 QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
370 tlb_flush_page(env, addr);
372 if (watchpoint)
373 *watchpoint = wp;
374 return 0;
377 /* Remove a specific watchpoint. */
378 int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len,
379 int flags)
381 target_ulong len_mask = ~(len - 1);
382 CPUWatchpoint *wp;
384 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
385 if (addr == wp->vaddr && len_mask == wp->len_mask
386 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
387 cpu_watchpoint_remove_by_ref(env, wp);
388 return 0;
391 return -ENOENT;
394 /* Remove a specific watchpoint by reference. */
395 void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
397 QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
399 tlb_flush_page(env, watchpoint->vaddr);
401 g_free(watchpoint);
404 /* Remove all matching watchpoints. */
405 void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
407 CPUWatchpoint *wp, *next;
409 QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
410 if (wp->flags & mask)
411 cpu_watchpoint_remove_by_ref(env, wp);
414 #endif
416 /* Add a breakpoint. */
417 int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
418 CPUBreakpoint **breakpoint)
420 #if defined(TARGET_HAS_ICE)
421 CPUBreakpoint *bp;
423 bp = g_malloc(sizeof(*bp));
425 bp->pc = pc;
426 bp->flags = flags;
428 /* keep all GDB-injected breakpoints in front */
429 if (flags & BP_GDB)
430 QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
431 else
432 QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
434 breakpoint_invalidate(env, pc);
436 if (breakpoint)
437 *breakpoint = bp;
438 return 0;
439 #else
440 return -ENOSYS;
441 #endif
444 /* Remove a specific breakpoint. */
445 int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
447 #if defined(TARGET_HAS_ICE)
448 CPUBreakpoint *bp;
450 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
451 if (bp->pc == pc && bp->flags == flags) {
452 cpu_breakpoint_remove_by_ref(env, bp);
453 return 0;
456 return -ENOENT;
457 #else
458 return -ENOSYS;
459 #endif
462 /* Remove a specific breakpoint by reference. */
463 void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
465 #if defined(TARGET_HAS_ICE)
466 QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
468 breakpoint_invalidate(env, breakpoint->pc);
470 g_free(breakpoint);
471 #endif
474 /* Remove all matching breakpoints. */
475 void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
477 #if defined(TARGET_HAS_ICE)
478 CPUBreakpoint *bp, *next;
480 QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
481 if (bp->flags & mask)
482 cpu_breakpoint_remove_by_ref(env, bp);
484 #endif
487 /* enable or disable single step mode. EXCP_DEBUG is returned by the
488 CPU loop after each instruction */
489 void cpu_single_step(CPUArchState *env, int enabled)
491 #if defined(TARGET_HAS_ICE)
492 if (env->singlestep_enabled != enabled) {
493 env->singlestep_enabled = enabled;
494 if (kvm_enabled())
495 kvm_update_guest_debug(env, 0);
496 else {
497 /* must flush all the translated code to avoid inconsistencies */
498 /* XXX: only flush what is necessary */
499 tb_flush(env);
502 #endif
505 void cpu_exit(CPUArchState *env)
507 CPUState *cpu = ENV_GET_CPU(env);
509 cpu->exit_request = 1;
510 cpu->tcg_exit_req = 1;
513 void cpu_abort(CPUArchState *env, const char *fmt, ...)
515 va_list ap;
516 va_list ap2;
518 va_start(ap, fmt);
519 va_copy(ap2, ap);
520 fprintf(stderr, "qemu: fatal: ");
521 vfprintf(stderr, fmt, ap);
522 fprintf(stderr, "\n");
523 cpu_dump_state(env, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
524 if (qemu_log_enabled()) {
525 qemu_log("qemu: fatal: ");
526 qemu_log_vprintf(fmt, ap2);
527 qemu_log("\n");
528 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
529 qemu_log_flush();
530 qemu_log_close();
532 va_end(ap2);
533 va_end(ap);
534 #if defined(CONFIG_USER_ONLY)
536 struct sigaction act;
537 sigfillset(&act.sa_mask);
538 act.sa_handler = SIG_DFL;
539 sigaction(SIGABRT, &act, NULL);
541 #endif
542 abort();
545 CPUArchState *cpu_copy(CPUArchState *env)
547 CPUArchState *new_env = cpu_init(env->cpu_model_str);
548 CPUArchState *next_cpu = new_env->next_cpu;
549 #if defined(TARGET_HAS_ICE)
550 CPUBreakpoint *bp;
551 CPUWatchpoint *wp;
552 #endif
554 memcpy(new_env, env, sizeof(CPUArchState));
556 /* Preserve chaining. */
557 new_env->next_cpu = next_cpu;
559 /* Clone all break/watchpoints.
560 Note: Once we support ptrace with hw-debug register access, make sure
561 BP_CPU break/watchpoints are handled correctly on clone. */
562 QTAILQ_INIT(&env->breakpoints);
563 QTAILQ_INIT(&env->watchpoints);
564 #if defined(TARGET_HAS_ICE)
565 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
566 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
568 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
569 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
570 wp->flags, NULL);
572 #endif
574 return new_env;
577 #if !defined(CONFIG_USER_ONLY)
578 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t end,
579 uintptr_t length)
581 uintptr_t start1;
583 /* we modify the TLB cache so that the dirty bit will be set again
584 when accessing the range */
585 start1 = (uintptr_t)qemu_safe_ram_ptr(start);
586 /* Check that we don't span multiple blocks - this breaks the
587 address comparisons below. */
588 if ((uintptr_t)qemu_safe_ram_ptr(end - 1) - start1
589 != (end - 1) - start) {
590 abort();
592 cpu_tlb_reset_dirty_all(start1, length);
596 /* Note: start and end must be within the same ram block. */
597 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
598 int dirty_flags)
600 uintptr_t length;
602 start &= TARGET_PAGE_MASK;
603 end = TARGET_PAGE_ALIGN(end);
605 length = end - start;
606 if (length == 0)
607 return;
608 cpu_physical_memory_mask_dirty_range(start, length, dirty_flags);
610 if (tcg_enabled()) {
611 tlb_reset_dirty_range_all(start, end, length);
615 static int cpu_physical_memory_set_dirty_tracking(int enable)
617 int ret = 0;
618 in_migration = enable;
619 return ret;
622 hwaddr memory_region_section_get_iotlb(CPUArchState *env,
623 MemoryRegionSection *section,
624 target_ulong vaddr,
625 hwaddr paddr,
626 int prot,
627 target_ulong *address)
629 hwaddr iotlb;
630 CPUWatchpoint *wp;
632 if (memory_region_is_ram(section->mr)) {
633 /* Normal RAM. */
634 iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
635 + memory_region_section_addr(section, paddr);
636 if (!section->readonly) {
637 iotlb |= phys_section_notdirty;
638 } else {
639 iotlb |= phys_section_rom;
641 } else {
642 /* IO handlers are currently passed a physical address.
643 It would be nice to pass an offset from the base address
644 of that region. This would avoid having to special case RAM,
645 and avoid full address decoding in every device.
646 We can't use the high bits of pd for this because
647 IO_MEM_ROMD uses these as a ram address. */
648 iotlb = section - phys_sections;
649 iotlb += memory_region_section_addr(section, paddr);
652 /* Make accesses to pages with watchpoints go via the
653 watchpoint trap routines. */
654 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
655 if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
656 /* Avoid trapping reads of pages with a write breakpoint. */
657 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
658 iotlb = phys_section_watch + paddr;
659 *address |= TLB_MMIO;
660 break;
665 return iotlb;
667 #endif /* defined(CONFIG_USER_ONLY) */
669 #if !defined(CONFIG_USER_ONLY)
671 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
672 typedef struct subpage_t {
673 MemoryRegion iomem;
674 hwaddr base;
675 uint16_t sub_section[TARGET_PAGE_SIZE];
676 } subpage_t;
678 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
679 uint16_t section);
680 static subpage_t *subpage_init(hwaddr base);
681 static void destroy_page_desc(uint16_t section_index)
683 MemoryRegionSection *section = &phys_sections[section_index];
684 MemoryRegion *mr = section->mr;
686 if (mr->subpage) {
687 subpage_t *subpage = container_of(mr, subpage_t, iomem);
688 memory_region_destroy(&subpage->iomem);
689 g_free(subpage);
693 static void destroy_l2_mapping(PhysPageEntry *lp, unsigned level)
695 unsigned i;
696 PhysPageEntry *p;
698 if (lp->ptr == PHYS_MAP_NODE_NIL) {
699 return;
702 p = phys_map_nodes[lp->ptr];
703 for (i = 0; i < L2_SIZE; ++i) {
704 if (!p[i].is_leaf) {
705 destroy_l2_mapping(&p[i], level - 1);
706 } else {
707 destroy_page_desc(p[i].ptr);
710 lp->is_leaf = 0;
711 lp->ptr = PHYS_MAP_NODE_NIL;
714 static void destroy_all_mappings(AddressSpaceDispatch *d)
716 destroy_l2_mapping(&d->phys_map, P_L2_LEVELS - 1);
717 phys_map_nodes_reset();
720 static uint16_t phys_section_add(MemoryRegionSection *section)
722 if (phys_sections_nb == phys_sections_nb_alloc) {
723 phys_sections_nb_alloc = MAX(phys_sections_nb_alloc * 2, 16);
724 phys_sections = g_renew(MemoryRegionSection, phys_sections,
725 phys_sections_nb_alloc);
727 phys_sections[phys_sections_nb] = *section;
728 return phys_sections_nb++;
731 static void phys_sections_clear(void)
733 phys_sections_nb = 0;
736 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
738 subpage_t *subpage;
739 hwaddr base = section->offset_within_address_space
740 & TARGET_PAGE_MASK;
741 MemoryRegionSection *existing = phys_page_find(d, base >> TARGET_PAGE_BITS);
742 MemoryRegionSection subsection = {
743 .offset_within_address_space = base,
744 .size = TARGET_PAGE_SIZE,
746 hwaddr start, end;
748 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
750 if (!(existing->mr->subpage)) {
751 subpage = subpage_init(base);
752 subsection.mr = &subpage->iomem;
753 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
754 phys_section_add(&subsection));
755 } else {
756 subpage = container_of(existing->mr, subpage_t, iomem);
758 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
759 end = start + section->size - 1;
760 subpage_register(subpage, start, end, phys_section_add(section));
764 static void register_multipage(AddressSpaceDispatch *d, MemoryRegionSection *section)
766 hwaddr start_addr = section->offset_within_address_space;
767 ram_addr_t size = section->size;
768 hwaddr addr;
769 uint16_t section_index = phys_section_add(section);
771 assert(size);
773 addr = start_addr;
774 phys_page_set(d, addr >> TARGET_PAGE_BITS, size >> TARGET_PAGE_BITS,
775 section_index);
778 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
780 AddressSpaceDispatch *d = container_of(listener, AddressSpaceDispatch, listener);
781 MemoryRegionSection now = *section, remain = *section;
783 if ((now.offset_within_address_space & ~TARGET_PAGE_MASK)
784 || (now.size < TARGET_PAGE_SIZE)) {
785 now.size = MIN(TARGET_PAGE_ALIGN(now.offset_within_address_space)
786 - now.offset_within_address_space,
787 now.size);
788 register_subpage(d, &now);
789 remain.size -= now.size;
790 remain.offset_within_address_space += now.size;
791 remain.offset_within_region += now.size;
793 while (remain.size >= TARGET_PAGE_SIZE) {
794 now = remain;
795 if (remain.offset_within_region & ~TARGET_PAGE_MASK) {
796 now.size = TARGET_PAGE_SIZE;
797 register_subpage(d, &now);
798 } else {
799 now.size &= TARGET_PAGE_MASK;
800 register_multipage(d, &now);
802 remain.size -= now.size;
803 remain.offset_within_address_space += now.size;
804 remain.offset_within_region += now.size;
806 now = remain;
807 if (now.size) {
808 register_subpage(d, &now);
812 void qemu_flush_coalesced_mmio_buffer(void)
814 if (kvm_enabled())
815 kvm_flush_coalesced_mmio_buffer();
818 void qemu_mutex_lock_ramlist(void)
820 qemu_mutex_lock(&ram_list.mutex);
823 void qemu_mutex_unlock_ramlist(void)
825 qemu_mutex_unlock(&ram_list.mutex);
828 #if defined(__linux__) && !defined(TARGET_S390X)
830 #include <sys/vfs.h>
832 #define HUGETLBFS_MAGIC 0x958458f6
834 static long gethugepagesize(const char *path)
836 struct statfs fs;
837 int ret;
839 do {
840 ret = statfs(path, &fs);
841 } while (ret != 0 && errno == EINTR);
843 if (ret != 0) {
844 perror(path);
845 return 0;
848 if (fs.f_type != HUGETLBFS_MAGIC)
849 fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path);
851 return fs.f_bsize;
854 static void *file_ram_alloc(RAMBlock *block,
855 ram_addr_t memory,
856 const char *path)
858 char *filename;
859 char *sanitized_name;
860 char *c;
861 void *area;
862 int fd;
863 #ifdef MAP_POPULATE
864 int flags;
865 #endif
866 unsigned long hpagesize;
868 hpagesize = gethugepagesize(path);
869 if (!hpagesize) {
870 return NULL;
873 if (memory < hpagesize) {
874 return NULL;
877 if (kvm_enabled() && !kvm_has_sync_mmu()) {
878 fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n");
879 return NULL;
882 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
883 sanitized_name = g_strdup(block->mr->name);
884 for (c = sanitized_name; *c != '\0'; c++) {
885 if (*c == '/')
886 *c = '_';
889 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
890 sanitized_name);
891 g_free(sanitized_name);
893 fd = mkstemp(filename);
894 if (fd < 0) {
895 perror("unable to create backing store for hugepages");
896 g_free(filename);
897 return NULL;
899 unlink(filename);
900 g_free(filename);
902 memory = (memory+hpagesize-1) & ~(hpagesize-1);
905 * ftruncate is not supported by hugetlbfs in older
906 * hosts, so don't bother bailing out on errors.
907 * If anything goes wrong with it under other filesystems,
908 * mmap will fail.
910 if (ftruncate(fd, memory))
911 perror("ftruncate");
913 #ifdef MAP_POPULATE
914 /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case
915 * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED
916 * to sidestep this quirk.
918 flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE;
919 area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0);
920 #else
921 area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
922 #endif
923 if (area == MAP_FAILED) {
924 perror("file_ram_alloc: can't mmap RAM pages");
925 close(fd);
926 return (NULL);
928 block->fd = fd;
929 return area;
931 #endif
933 static ram_addr_t find_ram_offset(ram_addr_t size)
935 RAMBlock *block, *next_block;
936 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
938 assert(size != 0); /* it would hand out same offset multiple times */
940 if (QTAILQ_EMPTY(&ram_list.blocks))
941 return 0;
943 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
944 ram_addr_t end, next = RAM_ADDR_MAX;
946 end = block->offset + block->length;
948 QTAILQ_FOREACH(next_block, &ram_list.blocks, next) {
949 if (next_block->offset >= end) {
950 next = MIN(next, next_block->offset);
953 if (next - end >= size && next - end < mingap) {
954 offset = end;
955 mingap = next - end;
959 if (offset == RAM_ADDR_MAX) {
960 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
961 (uint64_t)size);
962 abort();
965 return offset;
968 ram_addr_t last_ram_offset(void)
970 RAMBlock *block;
971 ram_addr_t last = 0;
973 QTAILQ_FOREACH(block, &ram_list.blocks, next)
974 last = MAX(last, block->offset + block->length);
976 return last;
979 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
981 int ret;
982 QemuOpts *machine_opts;
984 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
985 machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
986 if (machine_opts &&
987 !qemu_opt_get_bool(machine_opts, "dump-guest-core", true)) {
988 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
989 if (ret) {
990 perror("qemu_madvise");
991 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
992 "but dump_guest_core=off specified\n");
997 void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev)
999 RAMBlock *new_block, *block;
1001 new_block = NULL;
1002 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1003 if (block->offset == addr) {
1004 new_block = block;
1005 break;
1008 assert(new_block);
1009 assert(!new_block->idstr[0]);
1011 if (dev) {
1012 char *id = qdev_get_dev_path(dev);
1013 if (id) {
1014 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1015 g_free(id);
1018 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1020 /* This assumes the iothread lock is taken here too. */
1021 qemu_mutex_lock_ramlist();
1022 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1023 if (block != new_block && !strcmp(block->idstr, new_block->idstr)) {
1024 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1025 new_block->idstr);
1026 abort();
1029 qemu_mutex_unlock_ramlist();
1032 static int memory_try_enable_merging(void *addr, size_t len)
1034 QemuOpts *opts;
1036 opts = qemu_opts_find(qemu_find_opts("machine"), 0);
1037 if (opts && !qemu_opt_get_bool(opts, "mem-merge", true)) {
1038 /* disabled by the user */
1039 return 0;
1042 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1045 ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
1046 MemoryRegion *mr)
1048 RAMBlock *block, *new_block;
1050 size = TARGET_PAGE_ALIGN(size);
1051 new_block = g_malloc0(sizeof(*new_block));
1053 /* This assumes the iothread lock is taken here too. */
1054 qemu_mutex_lock_ramlist();
1055 new_block->mr = mr;
1056 new_block->offset = find_ram_offset(size);
1057 if (host) {
1058 new_block->host = host;
1059 new_block->flags |= RAM_PREALLOC_MASK;
1060 } else {
1061 if (mem_path) {
1062 #if defined (__linux__) && !defined(TARGET_S390X)
1063 new_block->host = file_ram_alloc(new_block, size, mem_path);
1064 if (!new_block->host) {
1065 new_block->host = qemu_vmalloc(size);
1066 memory_try_enable_merging(new_block->host, size);
1068 #else
1069 fprintf(stderr, "-mem-path option unsupported\n");
1070 exit(1);
1071 #endif
1072 } else {
1073 if (xen_enabled()) {
1074 xen_ram_alloc(new_block->offset, size, mr);
1075 } else if (kvm_enabled()) {
1076 /* some s390/kvm configurations have special constraints */
1077 new_block->host = kvm_vmalloc(size);
1078 } else {
1079 new_block->host = qemu_vmalloc(size);
1081 memory_try_enable_merging(new_block->host, size);
1084 new_block->length = size;
1086 /* Keep the list sorted from biggest to smallest block. */
1087 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1088 if (block->length < new_block->length) {
1089 break;
1092 if (block) {
1093 QTAILQ_INSERT_BEFORE(block, new_block, next);
1094 } else {
1095 QTAILQ_INSERT_TAIL(&ram_list.blocks, new_block, next);
1097 ram_list.mru_block = NULL;
1099 ram_list.version++;
1100 qemu_mutex_unlock_ramlist();
1102 ram_list.phys_dirty = g_realloc(ram_list.phys_dirty,
1103 last_ram_offset() >> TARGET_PAGE_BITS);
1104 memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS),
1105 0, size >> TARGET_PAGE_BITS);
1106 cpu_physical_memory_set_dirty_range(new_block->offset, size, 0xff);
1108 qemu_ram_setup_dump(new_block->host, size);
1109 qemu_madvise(new_block->host, size, QEMU_MADV_HUGEPAGE);
1111 if (kvm_enabled())
1112 kvm_setup_guest_memory(new_block->host, size);
1114 return new_block->offset;
1117 ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr)
1119 return qemu_ram_alloc_from_ptr(size, NULL, mr);
1122 void qemu_ram_free_from_ptr(ram_addr_t addr)
1124 RAMBlock *block;
1126 /* This assumes the iothread lock is taken here too. */
1127 qemu_mutex_lock_ramlist();
1128 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1129 if (addr == block->offset) {
1130 QTAILQ_REMOVE(&ram_list.blocks, block, next);
1131 ram_list.mru_block = NULL;
1132 ram_list.version++;
1133 g_free(block);
1134 break;
1137 qemu_mutex_unlock_ramlist();
1140 void qemu_ram_free(ram_addr_t addr)
1142 RAMBlock *block;
1144 /* This assumes the iothread lock is taken here too. */
1145 qemu_mutex_lock_ramlist();
1146 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1147 if (addr == block->offset) {
1148 QTAILQ_REMOVE(&ram_list.blocks, block, next);
1149 ram_list.mru_block = NULL;
1150 ram_list.version++;
1151 if (block->flags & RAM_PREALLOC_MASK) {
1153 } else if (mem_path) {
1154 #if defined (__linux__) && !defined(TARGET_S390X)
1155 if (block->fd) {
1156 munmap(block->host, block->length);
1157 close(block->fd);
1158 } else {
1159 qemu_vfree(block->host);
1161 #else
1162 abort();
1163 #endif
1164 } else {
1165 #if defined(TARGET_S390X) && defined(CONFIG_KVM)
1166 munmap(block->host, block->length);
1167 #else
1168 if (xen_enabled()) {
1169 xen_invalidate_map_cache_entry(block->host);
1170 } else {
1171 qemu_vfree(block->host);
1173 #endif
1175 g_free(block);
1176 break;
1179 qemu_mutex_unlock_ramlist();
1183 #ifndef _WIN32
1184 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
1186 RAMBlock *block;
1187 ram_addr_t offset;
1188 int flags;
1189 void *area, *vaddr;
1191 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1192 offset = addr - block->offset;
1193 if (offset < block->length) {
1194 vaddr = block->host + offset;
1195 if (block->flags & RAM_PREALLOC_MASK) {
1197 } else {
1198 flags = MAP_FIXED;
1199 munmap(vaddr, length);
1200 if (mem_path) {
1201 #if defined(__linux__) && !defined(TARGET_S390X)
1202 if (block->fd) {
1203 #ifdef MAP_POPULATE
1204 flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED :
1205 MAP_PRIVATE;
1206 #else
1207 flags |= MAP_PRIVATE;
1208 #endif
1209 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1210 flags, block->fd, offset);
1211 } else {
1212 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
1213 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1214 flags, -1, 0);
1216 #else
1217 abort();
1218 #endif
1219 } else {
1220 #if defined(TARGET_S390X) && defined(CONFIG_KVM)
1221 flags |= MAP_SHARED | MAP_ANONYMOUS;
1222 area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE,
1223 flags, -1, 0);
1224 #else
1225 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
1226 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1227 flags, -1, 0);
1228 #endif
1230 if (area != vaddr) {
1231 fprintf(stderr, "Could not remap addr: "
1232 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
1233 length, addr);
1234 exit(1);
1236 memory_try_enable_merging(vaddr, length);
1237 qemu_ram_setup_dump(vaddr, length);
1239 return;
1243 #endif /* !_WIN32 */
1245 /* Return a host pointer to ram allocated with qemu_ram_alloc.
1246 With the exception of the softmmu code in this file, this should
1247 only be used for local memory (e.g. video ram) that the device owns,
1248 and knows it isn't going to access beyond the end of the block.
1250 It should not be used for general purpose DMA.
1251 Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
1253 void *qemu_get_ram_ptr(ram_addr_t addr)
1255 RAMBlock *block;
1257 /* The list is protected by the iothread lock here. */
1258 block = ram_list.mru_block;
1259 if (block && addr - block->offset < block->length) {
1260 goto found;
1262 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1263 if (addr - block->offset < block->length) {
1264 goto found;
1268 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1269 abort();
1271 found:
1272 ram_list.mru_block = block;
1273 if (xen_enabled()) {
1274 /* We need to check if the requested address is in the RAM
1275 * because we don't want to map the entire memory in QEMU.
1276 * In that case just map until the end of the page.
1278 if (block->offset == 0) {
1279 return xen_map_cache(addr, 0, 0);
1280 } else if (block->host == NULL) {
1281 block->host =
1282 xen_map_cache(block->offset, block->length, 1);
1285 return block->host + (addr - block->offset);
1288 /* Return a host pointer to ram allocated with qemu_ram_alloc. Same as
1289 * qemu_get_ram_ptr but do not touch ram_list.mru_block.
1291 * ??? Is this still necessary?
1293 static void *qemu_safe_ram_ptr(ram_addr_t addr)
1295 RAMBlock *block;
1297 /* The list is protected by the iothread lock here. */
1298 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1299 if (addr - block->offset < block->length) {
1300 if (xen_enabled()) {
1301 /* We need to check if the requested address is in the RAM
1302 * because we don't want to map the entire memory in QEMU.
1303 * In that case just map until the end of the page.
1305 if (block->offset == 0) {
1306 return xen_map_cache(addr, 0, 0);
1307 } else if (block->host == NULL) {
1308 block->host =
1309 xen_map_cache(block->offset, block->length, 1);
1312 return block->host + (addr - block->offset);
1316 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1317 abort();
1319 return NULL;
1322 /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr
1323 * but takes a size argument */
1324 static void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size)
1326 if (*size == 0) {
1327 return NULL;
1329 if (xen_enabled()) {
1330 return xen_map_cache(addr, *size, 1);
1331 } else {
1332 RAMBlock *block;
1334 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1335 if (addr - block->offset < block->length) {
1336 if (addr - block->offset + *size > block->length)
1337 *size = block->length - addr + block->offset;
1338 return block->host + (addr - block->offset);
1342 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1343 abort();
1347 void qemu_put_ram_ptr(void *addr)
1349 trace_qemu_put_ram_ptr(addr);
1352 int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr)
1354 RAMBlock *block;
1355 uint8_t *host = ptr;
1357 if (xen_enabled()) {
1358 *ram_addr = xen_ram_addr_from_mapcache(ptr);
1359 return 0;
1362 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1363 /* This case append when the block is not mapped. */
1364 if (block->host == NULL) {
1365 continue;
1367 if (host - block->host < block->length) {
1368 *ram_addr = block->offset + (host - block->host);
1369 return 0;
1373 return -1;
1376 /* Some of the softmmu routines need to translate from a host pointer
1377 (typically a TLB entry) back to a ram offset. */
1378 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
1380 ram_addr_t ram_addr;
1382 if (qemu_ram_addr_from_host(ptr, &ram_addr)) {
1383 fprintf(stderr, "Bad ram pointer %p\n", ptr);
1384 abort();
1386 return ram_addr;
1389 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1390 unsigned size)
1392 #ifdef DEBUG_UNASSIGNED
1393 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1394 #endif
1395 #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
1396 cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
1397 #endif
1398 return 0;
1401 static void unassigned_mem_write(void *opaque, hwaddr addr,
1402 uint64_t val, unsigned size)
1404 #ifdef DEBUG_UNASSIGNED
1405 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1406 #endif
1407 #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
1408 cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
1409 #endif
1412 static const MemoryRegionOps unassigned_mem_ops = {
1413 .read = unassigned_mem_read,
1414 .write = unassigned_mem_write,
1415 .endianness = DEVICE_NATIVE_ENDIAN,
1418 static uint64_t error_mem_read(void *opaque, hwaddr addr,
1419 unsigned size)
1421 abort();
1424 static void error_mem_write(void *opaque, hwaddr addr,
1425 uint64_t value, unsigned size)
1427 abort();
1430 static const MemoryRegionOps error_mem_ops = {
1431 .read = error_mem_read,
1432 .write = error_mem_write,
1433 .endianness = DEVICE_NATIVE_ENDIAN,
1436 static const MemoryRegionOps rom_mem_ops = {
1437 .read = error_mem_read,
1438 .write = unassigned_mem_write,
1439 .endianness = DEVICE_NATIVE_ENDIAN,
1442 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
1443 uint64_t val, unsigned size)
1445 int dirty_flags;
1446 dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
1447 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
1448 #if !defined(CONFIG_USER_ONLY)
1449 tb_invalidate_phys_page_fast(ram_addr, size);
1450 dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
1451 #endif
1453 switch (size) {
1454 case 1:
1455 stb_p(qemu_get_ram_ptr(ram_addr), val);
1456 break;
1457 case 2:
1458 stw_p(qemu_get_ram_ptr(ram_addr), val);
1459 break;
1460 case 4:
1461 stl_p(qemu_get_ram_ptr(ram_addr), val);
1462 break;
1463 default:
1464 abort();
1466 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
1467 cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
1468 /* we remove the notdirty callback only if the code has been
1469 flushed */
1470 if (dirty_flags == 0xff)
1471 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
1474 static const MemoryRegionOps notdirty_mem_ops = {
1475 .read = error_mem_read,
1476 .write = notdirty_mem_write,
1477 .endianness = DEVICE_NATIVE_ENDIAN,
1480 /* Generate a debug exception if a watchpoint has been hit. */
1481 static void check_watchpoint(int offset, int len_mask, int flags)
1483 CPUArchState *env = cpu_single_env;
1484 target_ulong pc, cs_base;
1485 target_ulong vaddr;
1486 CPUWatchpoint *wp;
1487 int cpu_flags;
1489 if (env->watchpoint_hit) {
1490 /* We re-entered the check after replacing the TB. Now raise
1491 * the debug interrupt so that is will trigger after the
1492 * current instruction. */
1493 cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_DEBUG);
1494 return;
1496 vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
1497 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
1498 if ((vaddr == (wp->vaddr & len_mask) ||
1499 (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
1500 wp->flags |= BP_WATCHPOINT_HIT;
1501 if (!env->watchpoint_hit) {
1502 env->watchpoint_hit = wp;
1503 tb_check_watchpoint(env);
1504 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
1505 env->exception_index = EXCP_DEBUG;
1506 cpu_loop_exit(env);
1507 } else {
1508 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
1509 tb_gen_code(env, pc, cs_base, cpu_flags, 1);
1510 cpu_resume_from_signal(env, NULL);
1513 } else {
1514 wp->flags &= ~BP_WATCHPOINT_HIT;
1519 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
1520 so these check for a hit then pass through to the normal out-of-line
1521 phys routines. */
1522 static uint64_t watch_mem_read(void *opaque, hwaddr addr,
1523 unsigned size)
1525 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
1526 switch (size) {
1527 case 1: return ldub_phys(addr);
1528 case 2: return lduw_phys(addr);
1529 case 4: return ldl_phys(addr);
1530 default: abort();
1534 static void watch_mem_write(void *opaque, hwaddr addr,
1535 uint64_t val, unsigned size)
1537 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
1538 switch (size) {
1539 case 1:
1540 stb_phys(addr, val);
1541 break;
1542 case 2:
1543 stw_phys(addr, val);
1544 break;
1545 case 4:
1546 stl_phys(addr, val);
1547 break;
1548 default: abort();
1552 static const MemoryRegionOps watch_mem_ops = {
1553 .read = watch_mem_read,
1554 .write = watch_mem_write,
1555 .endianness = DEVICE_NATIVE_ENDIAN,
1558 static uint64_t subpage_read(void *opaque, hwaddr addr,
1559 unsigned len)
1561 subpage_t *mmio = opaque;
1562 unsigned int idx = SUBPAGE_IDX(addr);
1563 MemoryRegionSection *section;
1564 #if defined(DEBUG_SUBPAGE)
1565 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
1566 mmio, len, addr, idx);
1567 #endif
1569 section = &phys_sections[mmio->sub_section[idx]];
1570 addr += mmio->base;
1571 addr -= section->offset_within_address_space;
1572 addr += section->offset_within_region;
1573 return io_mem_read(section->mr, addr, len);
1576 static void subpage_write(void *opaque, hwaddr addr,
1577 uint64_t value, unsigned len)
1579 subpage_t *mmio = opaque;
1580 unsigned int idx = SUBPAGE_IDX(addr);
1581 MemoryRegionSection *section;
1582 #if defined(DEBUG_SUBPAGE)
1583 printf("%s: subpage %p len %d addr " TARGET_FMT_plx
1584 " idx %d value %"PRIx64"\n",
1585 __func__, mmio, len, addr, idx, value);
1586 #endif
1588 section = &phys_sections[mmio->sub_section[idx]];
1589 addr += mmio->base;
1590 addr -= section->offset_within_address_space;
1591 addr += section->offset_within_region;
1592 io_mem_write(section->mr, addr, value, len);
1595 static const MemoryRegionOps subpage_ops = {
1596 .read = subpage_read,
1597 .write = subpage_write,
1598 .endianness = DEVICE_NATIVE_ENDIAN,
1601 static uint64_t subpage_ram_read(void *opaque, hwaddr addr,
1602 unsigned size)
1604 ram_addr_t raddr = addr;
1605 void *ptr = qemu_get_ram_ptr(raddr);
1606 switch (size) {
1607 case 1: return ldub_p(ptr);
1608 case 2: return lduw_p(ptr);
1609 case 4: return ldl_p(ptr);
1610 default: abort();
1614 static void subpage_ram_write(void *opaque, hwaddr addr,
1615 uint64_t value, unsigned size)
1617 ram_addr_t raddr = addr;
1618 void *ptr = qemu_get_ram_ptr(raddr);
1619 switch (size) {
1620 case 1: return stb_p(ptr, value);
1621 case 2: return stw_p(ptr, value);
1622 case 4: return stl_p(ptr, value);
1623 default: abort();
1627 static const MemoryRegionOps subpage_ram_ops = {
1628 .read = subpage_ram_read,
1629 .write = subpage_ram_write,
1630 .endianness = DEVICE_NATIVE_ENDIAN,
1633 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1634 uint16_t section)
1636 int idx, eidx;
1638 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
1639 return -1;
1640 idx = SUBPAGE_IDX(start);
1641 eidx = SUBPAGE_IDX(end);
1642 #if defined(DEBUG_SUBPAGE)
1643 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__,
1644 mmio, start, end, idx, eidx, memory);
1645 #endif
1646 if (memory_region_is_ram(phys_sections[section].mr)) {
1647 MemoryRegionSection new_section = phys_sections[section];
1648 new_section.mr = &io_mem_subpage_ram;
1649 section = phys_section_add(&new_section);
1651 for (; idx <= eidx; idx++) {
1652 mmio->sub_section[idx] = section;
1655 return 0;
1658 static subpage_t *subpage_init(hwaddr base)
1660 subpage_t *mmio;
1662 mmio = g_malloc0(sizeof(subpage_t));
1664 mmio->base = base;
1665 memory_region_init_io(&mmio->iomem, &subpage_ops, mmio,
1666 "subpage", TARGET_PAGE_SIZE);
1667 mmio->iomem.subpage = true;
1668 #if defined(DEBUG_SUBPAGE)
1669 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
1670 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
1671 #endif
1672 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, phys_section_unassigned);
1674 return mmio;
1677 static uint16_t dummy_section(MemoryRegion *mr)
1679 MemoryRegionSection section = {
1680 .mr = mr,
1681 .offset_within_address_space = 0,
1682 .offset_within_region = 0,
1683 .size = UINT64_MAX,
1686 return phys_section_add(&section);
1689 MemoryRegion *iotlb_to_region(hwaddr index)
1691 return phys_sections[index & ~TARGET_PAGE_MASK].mr;
1694 static void io_mem_init(void)
1696 memory_region_init_io(&io_mem_ram, &error_mem_ops, NULL, "ram", UINT64_MAX);
1697 memory_region_init_io(&io_mem_rom, &rom_mem_ops, NULL, "rom", UINT64_MAX);
1698 memory_region_init_io(&io_mem_unassigned, &unassigned_mem_ops, NULL,
1699 "unassigned", UINT64_MAX);
1700 memory_region_init_io(&io_mem_notdirty, &notdirty_mem_ops, NULL,
1701 "notdirty", UINT64_MAX);
1702 memory_region_init_io(&io_mem_subpage_ram, &subpage_ram_ops, NULL,
1703 "subpage-ram", UINT64_MAX);
1704 memory_region_init_io(&io_mem_watch, &watch_mem_ops, NULL,
1705 "watch", UINT64_MAX);
1708 static void mem_begin(MemoryListener *listener)
1710 AddressSpaceDispatch *d = container_of(listener, AddressSpaceDispatch, listener);
1712 destroy_all_mappings(d);
1713 d->phys_map.ptr = PHYS_MAP_NODE_NIL;
1716 static void core_begin(MemoryListener *listener)
1718 phys_sections_clear();
1719 phys_section_unassigned = dummy_section(&io_mem_unassigned);
1720 phys_section_notdirty = dummy_section(&io_mem_notdirty);
1721 phys_section_rom = dummy_section(&io_mem_rom);
1722 phys_section_watch = dummy_section(&io_mem_watch);
1725 static void tcg_commit(MemoryListener *listener)
1727 CPUArchState *env;
1729 /* since each CPU stores ram addresses in its TLB cache, we must
1730 reset the modified entries */
1731 /* XXX: slow ! */
1732 for(env = first_cpu; env != NULL; env = env->next_cpu) {
1733 tlb_flush(env, 1);
1737 static void core_log_global_start(MemoryListener *listener)
1739 cpu_physical_memory_set_dirty_tracking(1);
1742 static void core_log_global_stop(MemoryListener *listener)
1744 cpu_physical_memory_set_dirty_tracking(0);
1747 static void io_region_add(MemoryListener *listener,
1748 MemoryRegionSection *section)
1750 MemoryRegionIORange *mrio = g_new(MemoryRegionIORange, 1);
1752 mrio->mr = section->mr;
1753 mrio->offset = section->offset_within_region;
1754 iorange_init(&mrio->iorange, &memory_region_iorange_ops,
1755 section->offset_within_address_space, section->size);
1756 ioport_register(&mrio->iorange);
1759 static void io_region_del(MemoryListener *listener,
1760 MemoryRegionSection *section)
1762 isa_unassign_ioport(section->offset_within_address_space, section->size);
1765 static MemoryListener core_memory_listener = {
1766 .begin = core_begin,
1767 .log_global_start = core_log_global_start,
1768 .log_global_stop = core_log_global_stop,
1769 .priority = 1,
1772 static MemoryListener io_memory_listener = {
1773 .region_add = io_region_add,
1774 .region_del = io_region_del,
1775 .priority = 0,
1778 static MemoryListener tcg_memory_listener = {
1779 .commit = tcg_commit,
1782 void address_space_init_dispatch(AddressSpace *as)
1784 AddressSpaceDispatch *d = g_new(AddressSpaceDispatch, 1);
1786 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .is_leaf = 0 };
1787 d->listener = (MemoryListener) {
1788 .begin = mem_begin,
1789 .region_add = mem_add,
1790 .region_nop = mem_add,
1791 .priority = 0,
1793 as->dispatch = d;
1794 memory_listener_register(&d->listener, as);
1797 void address_space_destroy_dispatch(AddressSpace *as)
1799 AddressSpaceDispatch *d = as->dispatch;
1801 memory_listener_unregister(&d->listener);
1802 destroy_l2_mapping(&d->phys_map, P_L2_LEVELS - 1);
1803 g_free(d);
1804 as->dispatch = NULL;
1807 static void memory_map_init(void)
1809 system_memory = g_malloc(sizeof(*system_memory));
1810 memory_region_init(system_memory, "system", INT64_MAX);
1811 address_space_init(&address_space_memory, system_memory);
1812 address_space_memory.name = "memory";
1814 system_io = g_malloc(sizeof(*system_io));
1815 memory_region_init(system_io, "io", 65536);
1816 address_space_init(&address_space_io, system_io);
1817 address_space_io.name = "I/O";
1819 memory_listener_register(&core_memory_listener, &address_space_memory);
1820 memory_listener_register(&io_memory_listener, &address_space_io);
1821 memory_listener_register(&tcg_memory_listener, &address_space_memory);
1823 dma_context_init(&dma_context_memory, &address_space_memory,
1824 NULL, NULL, NULL);
1827 MemoryRegion *get_system_memory(void)
1829 return system_memory;
1832 MemoryRegion *get_system_io(void)
1834 return system_io;
1837 #endif /* !defined(CONFIG_USER_ONLY) */
1839 /* physical memory access (slow version, mainly for debug) */
1840 #if defined(CONFIG_USER_ONLY)
1841 int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
1842 uint8_t *buf, int len, int is_write)
1844 int l, flags;
1845 target_ulong page;
1846 void * p;
1848 while (len > 0) {
1849 page = addr & TARGET_PAGE_MASK;
1850 l = (page + TARGET_PAGE_SIZE) - addr;
1851 if (l > len)
1852 l = len;
1853 flags = page_get_flags(page);
1854 if (!(flags & PAGE_VALID))
1855 return -1;
1856 if (is_write) {
1857 if (!(flags & PAGE_WRITE))
1858 return -1;
1859 /* XXX: this code should not depend on lock_user */
1860 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
1861 return -1;
1862 memcpy(p, buf, l);
1863 unlock_user(p, addr, l);
1864 } else {
1865 if (!(flags & PAGE_READ))
1866 return -1;
1867 /* XXX: this code should not depend on lock_user */
1868 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
1869 return -1;
1870 memcpy(buf, p, l);
1871 unlock_user(p, addr, 0);
1873 len -= l;
1874 buf += l;
1875 addr += l;
1877 return 0;
1880 #else
1882 static void invalidate_and_set_dirty(hwaddr addr,
1883 hwaddr length)
1885 if (!cpu_physical_memory_is_dirty(addr)) {
1886 /* invalidate code */
1887 tb_invalidate_phys_page_range(addr, addr + length, 0);
1888 /* set dirty bit */
1889 cpu_physical_memory_set_dirty_flags(addr, (0xff & ~CODE_DIRTY_FLAG));
1891 xen_modified_memory(addr, length);
1894 void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
1895 int len, bool is_write)
1897 AddressSpaceDispatch *d = as->dispatch;
1898 int l;
1899 uint8_t *ptr;
1900 uint32_t val;
1901 hwaddr page;
1902 MemoryRegionSection *section;
1904 while (len > 0) {
1905 page = addr & TARGET_PAGE_MASK;
1906 l = (page + TARGET_PAGE_SIZE) - addr;
1907 if (l > len)
1908 l = len;
1909 section = phys_page_find(d, page >> TARGET_PAGE_BITS);
1911 if (is_write) {
1912 if (!memory_region_is_ram(section->mr)) {
1913 hwaddr addr1;
1914 addr1 = memory_region_section_addr(section, addr);
1915 /* XXX: could force cpu_single_env to NULL to avoid
1916 potential bugs */
1917 if (l >= 4 && ((addr1 & 3) == 0)) {
1918 /* 32 bit write access */
1919 val = ldl_p(buf);
1920 io_mem_write(section->mr, addr1, val, 4);
1921 l = 4;
1922 } else if (l >= 2 && ((addr1 & 1) == 0)) {
1923 /* 16 bit write access */
1924 val = lduw_p(buf);
1925 io_mem_write(section->mr, addr1, val, 2);
1926 l = 2;
1927 } else {
1928 /* 8 bit write access */
1929 val = ldub_p(buf);
1930 io_mem_write(section->mr, addr1, val, 1);
1931 l = 1;
1933 } else if (!section->readonly) {
1934 ram_addr_t addr1;
1935 addr1 = memory_region_get_ram_addr(section->mr)
1936 + memory_region_section_addr(section, addr);
1937 /* RAM case */
1938 ptr = qemu_get_ram_ptr(addr1);
1939 memcpy(ptr, buf, l);
1940 invalidate_and_set_dirty(addr1, l);
1941 qemu_put_ram_ptr(ptr);
1943 } else {
1944 if (!(memory_region_is_ram(section->mr) ||
1945 memory_region_is_romd(section->mr))) {
1946 hwaddr addr1;
1947 /* I/O case */
1948 addr1 = memory_region_section_addr(section, addr);
1949 if (l >= 4 && ((addr1 & 3) == 0)) {
1950 /* 32 bit read access */
1951 val = io_mem_read(section->mr, addr1, 4);
1952 stl_p(buf, val);
1953 l = 4;
1954 } else if (l >= 2 && ((addr1 & 1) == 0)) {
1955 /* 16 bit read access */
1956 val = io_mem_read(section->mr, addr1, 2);
1957 stw_p(buf, val);
1958 l = 2;
1959 } else {
1960 /* 8 bit read access */
1961 val = io_mem_read(section->mr, addr1, 1);
1962 stb_p(buf, val);
1963 l = 1;
1965 } else {
1966 /* RAM case */
1967 ptr = qemu_get_ram_ptr(section->mr->ram_addr
1968 + memory_region_section_addr(section,
1969 addr));
1970 memcpy(buf, ptr, l);
1971 qemu_put_ram_ptr(ptr);
1974 len -= l;
1975 buf += l;
1976 addr += l;
1980 void address_space_write(AddressSpace *as, hwaddr addr,
1981 const uint8_t *buf, int len)
1983 address_space_rw(as, addr, (uint8_t *)buf, len, true);
1987 * address_space_read: read from an address space.
1989 * @as: #AddressSpace to be accessed
1990 * @addr: address within that address space
1991 * @buf: buffer with the data transferred
1993 void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
1995 address_space_rw(as, addr, buf, len, false);
1999 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
2000 int len, int is_write)
2002 return address_space_rw(&address_space_memory, addr, buf, len, is_write);
2005 /* used for ROM loading : can write in RAM and ROM */
2006 void cpu_physical_memory_write_rom(hwaddr addr,
2007 const uint8_t *buf, int len)
2009 AddressSpaceDispatch *d = address_space_memory.dispatch;
2010 int l;
2011 uint8_t *ptr;
2012 hwaddr page;
2013 MemoryRegionSection *section;
2015 while (len > 0) {
2016 page = addr & TARGET_PAGE_MASK;
2017 l = (page + TARGET_PAGE_SIZE) - addr;
2018 if (l > len)
2019 l = len;
2020 section = phys_page_find(d, page >> TARGET_PAGE_BITS);
2022 if (!(memory_region_is_ram(section->mr) ||
2023 memory_region_is_romd(section->mr))) {
2024 /* do nothing */
2025 } else {
2026 unsigned long addr1;
2027 addr1 = memory_region_get_ram_addr(section->mr)
2028 + memory_region_section_addr(section, addr);
2029 /* ROM/RAM case */
2030 ptr = qemu_get_ram_ptr(addr1);
2031 memcpy(ptr, buf, l);
2032 invalidate_and_set_dirty(addr1, l);
2033 qemu_put_ram_ptr(ptr);
2035 len -= l;
2036 buf += l;
2037 addr += l;
2041 typedef struct {
2042 void *buffer;
2043 hwaddr addr;
2044 hwaddr len;
2045 } BounceBuffer;
2047 static BounceBuffer bounce;
2049 typedef struct MapClient {
2050 void *opaque;
2051 void (*callback)(void *opaque);
2052 QLIST_ENTRY(MapClient) link;
2053 } MapClient;
2055 static QLIST_HEAD(map_client_list, MapClient) map_client_list
2056 = QLIST_HEAD_INITIALIZER(map_client_list);
2058 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
2060 MapClient *client = g_malloc(sizeof(*client));
2062 client->opaque = opaque;
2063 client->callback = callback;
2064 QLIST_INSERT_HEAD(&map_client_list, client, link);
2065 return client;
2068 static void cpu_unregister_map_client(void *_client)
2070 MapClient *client = (MapClient *)_client;
2072 QLIST_REMOVE(client, link);
2073 g_free(client);
2076 static void cpu_notify_map_clients(void)
2078 MapClient *client;
2080 while (!QLIST_EMPTY(&map_client_list)) {
2081 client = QLIST_FIRST(&map_client_list);
2082 client->callback(client->opaque);
2083 cpu_unregister_map_client(client);
2087 /* Map a physical memory region into a host virtual address.
2088 * May map a subset of the requested range, given by and returned in *plen.
2089 * May return NULL if resources needed to perform the mapping are exhausted.
2090 * Use only for reads OR writes - not for read-modify-write operations.
2091 * Use cpu_register_map_client() to know when retrying the map operation is
2092 * likely to succeed.
2094 void *address_space_map(AddressSpace *as,
2095 hwaddr addr,
2096 hwaddr *plen,
2097 bool is_write)
2099 AddressSpaceDispatch *d = as->dispatch;
2100 hwaddr len = *plen;
2101 hwaddr todo = 0;
2102 int l;
2103 hwaddr page;
2104 MemoryRegionSection *section;
2105 ram_addr_t raddr = RAM_ADDR_MAX;
2106 ram_addr_t rlen;
2107 void *ret;
2109 while (len > 0) {
2110 page = addr & TARGET_PAGE_MASK;
2111 l = (page + TARGET_PAGE_SIZE) - addr;
2112 if (l > len)
2113 l = len;
2114 section = phys_page_find(d, page >> TARGET_PAGE_BITS);
2116 if (!(memory_region_is_ram(section->mr) && !section->readonly)) {
2117 if (todo || bounce.buffer) {
2118 break;
2120 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
2121 bounce.addr = addr;
2122 bounce.len = l;
2123 if (!is_write) {
2124 address_space_read(as, addr, bounce.buffer, l);
2127 *plen = l;
2128 return bounce.buffer;
2130 if (!todo) {
2131 raddr = memory_region_get_ram_addr(section->mr)
2132 + memory_region_section_addr(section, addr);
2135 len -= l;
2136 addr += l;
2137 todo += l;
2139 rlen = todo;
2140 ret = qemu_ram_ptr_length(raddr, &rlen);
2141 *plen = rlen;
2142 return ret;
2145 /* Unmaps a memory region previously mapped by address_space_map().
2146 * Will also mark the memory as dirty if is_write == 1. access_len gives
2147 * the amount of memory that was actually read or written by the caller.
2149 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
2150 int is_write, hwaddr access_len)
2152 if (buffer != bounce.buffer) {
2153 if (is_write) {
2154 ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer);
2155 while (access_len) {
2156 unsigned l;
2157 l = TARGET_PAGE_SIZE;
2158 if (l > access_len)
2159 l = access_len;
2160 invalidate_and_set_dirty(addr1, l);
2161 addr1 += l;
2162 access_len -= l;
2165 if (xen_enabled()) {
2166 xen_invalidate_map_cache_entry(buffer);
2168 return;
2170 if (is_write) {
2171 address_space_write(as, bounce.addr, bounce.buffer, access_len);
2173 qemu_vfree(bounce.buffer);
2174 bounce.buffer = NULL;
2175 cpu_notify_map_clients();
2178 void *cpu_physical_memory_map(hwaddr addr,
2179 hwaddr *plen,
2180 int is_write)
2182 return address_space_map(&address_space_memory, addr, plen, is_write);
2185 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
2186 int is_write, hwaddr access_len)
2188 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
2191 /* warning: addr must be aligned */
2192 static inline uint32_t ldl_phys_internal(hwaddr addr,
2193 enum device_endian endian)
2195 uint8_t *ptr;
2196 uint32_t val;
2197 MemoryRegionSection *section;
2199 section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
2201 if (!(memory_region_is_ram(section->mr) ||
2202 memory_region_is_romd(section->mr))) {
2203 /* I/O case */
2204 addr = memory_region_section_addr(section, addr);
2205 val = io_mem_read(section->mr, addr, 4);
2206 #if defined(TARGET_WORDS_BIGENDIAN)
2207 if (endian == DEVICE_LITTLE_ENDIAN) {
2208 val = bswap32(val);
2210 #else
2211 if (endian == DEVICE_BIG_ENDIAN) {
2212 val = bswap32(val);
2214 #endif
2215 } else {
2216 /* RAM case */
2217 ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
2218 & TARGET_PAGE_MASK)
2219 + memory_region_section_addr(section, addr));
2220 switch (endian) {
2221 case DEVICE_LITTLE_ENDIAN:
2222 val = ldl_le_p(ptr);
2223 break;
2224 case DEVICE_BIG_ENDIAN:
2225 val = ldl_be_p(ptr);
2226 break;
2227 default:
2228 val = ldl_p(ptr);
2229 break;
2232 return val;
2235 uint32_t ldl_phys(hwaddr addr)
2237 return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
2240 uint32_t ldl_le_phys(hwaddr addr)
2242 return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
2245 uint32_t ldl_be_phys(hwaddr addr)
2247 return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
2250 /* warning: addr must be aligned */
2251 static inline uint64_t ldq_phys_internal(hwaddr addr,
2252 enum device_endian endian)
2254 uint8_t *ptr;
2255 uint64_t val;
2256 MemoryRegionSection *section;
2258 section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
2260 if (!(memory_region_is_ram(section->mr) ||
2261 memory_region_is_romd(section->mr))) {
2262 /* I/O case */
2263 addr = memory_region_section_addr(section, addr);
2265 /* XXX This is broken when device endian != cpu endian.
2266 Fix and add "endian" variable check */
2267 #ifdef TARGET_WORDS_BIGENDIAN
2268 val = io_mem_read(section->mr, addr, 4) << 32;
2269 val |= io_mem_read(section->mr, addr + 4, 4);
2270 #else
2271 val = io_mem_read(section->mr, addr, 4);
2272 val |= io_mem_read(section->mr, addr + 4, 4) << 32;
2273 #endif
2274 } else {
2275 /* RAM case */
2276 ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
2277 & TARGET_PAGE_MASK)
2278 + memory_region_section_addr(section, addr));
2279 switch (endian) {
2280 case DEVICE_LITTLE_ENDIAN:
2281 val = ldq_le_p(ptr);
2282 break;
2283 case DEVICE_BIG_ENDIAN:
2284 val = ldq_be_p(ptr);
2285 break;
2286 default:
2287 val = ldq_p(ptr);
2288 break;
2291 return val;
2294 uint64_t ldq_phys(hwaddr addr)
2296 return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
2299 uint64_t ldq_le_phys(hwaddr addr)
2301 return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
2304 uint64_t ldq_be_phys(hwaddr addr)
2306 return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
2309 /* XXX: optimize */
2310 uint32_t ldub_phys(hwaddr addr)
2312 uint8_t val;
2313 cpu_physical_memory_read(addr, &val, 1);
2314 return val;
2317 /* warning: addr must be aligned */
2318 static inline uint32_t lduw_phys_internal(hwaddr addr,
2319 enum device_endian endian)
2321 uint8_t *ptr;
2322 uint64_t val;
2323 MemoryRegionSection *section;
2325 section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
2327 if (!(memory_region_is_ram(section->mr) ||
2328 memory_region_is_romd(section->mr))) {
2329 /* I/O case */
2330 addr = memory_region_section_addr(section, addr);
2331 val = io_mem_read(section->mr, addr, 2);
2332 #if defined(TARGET_WORDS_BIGENDIAN)
2333 if (endian == DEVICE_LITTLE_ENDIAN) {
2334 val = bswap16(val);
2336 #else
2337 if (endian == DEVICE_BIG_ENDIAN) {
2338 val = bswap16(val);
2340 #endif
2341 } else {
2342 /* RAM case */
2343 ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
2344 & TARGET_PAGE_MASK)
2345 + memory_region_section_addr(section, addr));
2346 switch (endian) {
2347 case DEVICE_LITTLE_ENDIAN:
2348 val = lduw_le_p(ptr);
2349 break;
2350 case DEVICE_BIG_ENDIAN:
2351 val = lduw_be_p(ptr);
2352 break;
2353 default:
2354 val = lduw_p(ptr);
2355 break;
2358 return val;
2361 uint32_t lduw_phys(hwaddr addr)
2363 return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
2366 uint32_t lduw_le_phys(hwaddr addr)
2368 return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
2371 uint32_t lduw_be_phys(hwaddr addr)
2373 return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
2376 /* warning: addr must be aligned. The ram page is not masked as dirty
2377 and the code inside is not invalidated. It is useful if the dirty
2378 bits are used to track modified PTEs */
2379 void stl_phys_notdirty(hwaddr addr, uint32_t val)
2381 uint8_t *ptr;
2382 MemoryRegionSection *section;
2384 section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
2386 if (!memory_region_is_ram(section->mr) || section->readonly) {
2387 addr = memory_region_section_addr(section, addr);
2388 if (memory_region_is_ram(section->mr)) {
2389 section = &phys_sections[phys_section_rom];
2391 io_mem_write(section->mr, addr, val, 4);
2392 } else {
2393 unsigned long addr1 = (memory_region_get_ram_addr(section->mr)
2394 & TARGET_PAGE_MASK)
2395 + memory_region_section_addr(section, addr);
2396 ptr = qemu_get_ram_ptr(addr1);
2397 stl_p(ptr, val);
2399 if (unlikely(in_migration)) {
2400 if (!cpu_physical_memory_is_dirty(addr1)) {
2401 /* invalidate code */
2402 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
2403 /* set dirty bit */
2404 cpu_physical_memory_set_dirty_flags(
2405 addr1, (0xff & ~CODE_DIRTY_FLAG));
2411 void stq_phys_notdirty(hwaddr addr, uint64_t val)
2413 uint8_t *ptr;
2414 MemoryRegionSection *section;
2416 section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
2418 if (!memory_region_is_ram(section->mr) || section->readonly) {
2419 addr = memory_region_section_addr(section, addr);
2420 if (memory_region_is_ram(section->mr)) {
2421 section = &phys_sections[phys_section_rom];
2423 #ifdef TARGET_WORDS_BIGENDIAN
2424 io_mem_write(section->mr, addr, val >> 32, 4);
2425 io_mem_write(section->mr, addr + 4, (uint32_t)val, 4);
2426 #else
2427 io_mem_write(section->mr, addr, (uint32_t)val, 4);
2428 io_mem_write(section->mr, addr + 4, val >> 32, 4);
2429 #endif
2430 } else {
2431 ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
2432 & TARGET_PAGE_MASK)
2433 + memory_region_section_addr(section, addr));
2434 stq_p(ptr, val);
2438 /* warning: addr must be aligned */
2439 static inline void stl_phys_internal(hwaddr addr, uint32_t val,
2440 enum device_endian endian)
2442 uint8_t *ptr;
2443 MemoryRegionSection *section;
2445 section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
2447 if (!memory_region_is_ram(section->mr) || section->readonly) {
2448 addr = memory_region_section_addr(section, addr);
2449 if (memory_region_is_ram(section->mr)) {
2450 section = &phys_sections[phys_section_rom];
2452 #if defined(TARGET_WORDS_BIGENDIAN)
2453 if (endian == DEVICE_LITTLE_ENDIAN) {
2454 val = bswap32(val);
2456 #else
2457 if (endian == DEVICE_BIG_ENDIAN) {
2458 val = bswap32(val);
2460 #endif
2461 io_mem_write(section->mr, addr, val, 4);
2462 } else {
2463 unsigned long addr1;
2464 addr1 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
2465 + memory_region_section_addr(section, addr);
2466 /* RAM case */
2467 ptr = qemu_get_ram_ptr(addr1);
2468 switch (endian) {
2469 case DEVICE_LITTLE_ENDIAN:
2470 stl_le_p(ptr, val);
2471 break;
2472 case DEVICE_BIG_ENDIAN:
2473 stl_be_p(ptr, val);
2474 break;
2475 default:
2476 stl_p(ptr, val);
2477 break;
2479 invalidate_and_set_dirty(addr1, 4);
2483 void stl_phys(hwaddr addr, uint32_t val)
2485 stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
2488 void stl_le_phys(hwaddr addr, uint32_t val)
2490 stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
2493 void stl_be_phys(hwaddr addr, uint32_t val)
2495 stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
2498 /* XXX: optimize */
2499 void stb_phys(hwaddr addr, uint32_t val)
2501 uint8_t v = val;
2502 cpu_physical_memory_write(addr, &v, 1);
2505 /* warning: addr must be aligned */
2506 static inline void stw_phys_internal(hwaddr addr, uint32_t val,
2507 enum device_endian endian)
2509 uint8_t *ptr;
2510 MemoryRegionSection *section;
2512 section = phys_page_find(address_space_memory.dispatch, addr >> TARGET_PAGE_BITS);
2514 if (!memory_region_is_ram(section->mr) || section->readonly) {
2515 addr = memory_region_section_addr(section, addr);
2516 if (memory_region_is_ram(section->mr)) {
2517 section = &phys_sections[phys_section_rom];
2519 #if defined(TARGET_WORDS_BIGENDIAN)
2520 if (endian == DEVICE_LITTLE_ENDIAN) {
2521 val = bswap16(val);
2523 #else
2524 if (endian == DEVICE_BIG_ENDIAN) {
2525 val = bswap16(val);
2527 #endif
2528 io_mem_write(section->mr, addr, val, 2);
2529 } else {
2530 unsigned long addr1;
2531 addr1 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
2532 + memory_region_section_addr(section, addr);
2533 /* RAM case */
2534 ptr = qemu_get_ram_ptr(addr1);
2535 switch (endian) {
2536 case DEVICE_LITTLE_ENDIAN:
2537 stw_le_p(ptr, val);
2538 break;
2539 case DEVICE_BIG_ENDIAN:
2540 stw_be_p(ptr, val);
2541 break;
2542 default:
2543 stw_p(ptr, val);
2544 break;
2546 invalidate_and_set_dirty(addr1, 2);
2550 void stw_phys(hwaddr addr, uint32_t val)
2552 stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
2555 void stw_le_phys(hwaddr addr, uint32_t val)
2557 stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
2560 void stw_be_phys(hwaddr addr, uint32_t val)
2562 stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
2565 /* XXX: optimize */
2566 void stq_phys(hwaddr addr, uint64_t val)
2568 val = tswap64(val);
2569 cpu_physical_memory_write(addr, &val, 8);
2572 void stq_le_phys(hwaddr addr, uint64_t val)
2574 val = cpu_to_le64(val);
2575 cpu_physical_memory_write(addr, &val, 8);
2578 void stq_be_phys(hwaddr addr, uint64_t val)
2580 val = cpu_to_be64(val);
2581 cpu_physical_memory_write(addr, &val, 8);
2584 /* virtual memory access for debug (includes writing to ROM) */
2585 int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
2586 uint8_t *buf, int len, int is_write)
2588 int l;
2589 hwaddr phys_addr;
2590 target_ulong page;
2592 while (len > 0) {
2593 page = addr & TARGET_PAGE_MASK;
2594 phys_addr = cpu_get_phys_page_debug(env, page);
2595 /* if no physical page mapped, return an error */
2596 if (phys_addr == -1)
2597 return -1;
2598 l = (page + TARGET_PAGE_SIZE) - addr;
2599 if (l > len)
2600 l = len;
2601 phys_addr += (addr & ~TARGET_PAGE_MASK);
2602 if (is_write)
2603 cpu_physical_memory_write_rom(phys_addr, buf, l);
2604 else
2605 cpu_physical_memory_rw(phys_addr, buf, l, is_write);
2606 len -= l;
2607 buf += l;
2608 addr += l;
2610 return 0;
2612 #endif
2614 #if !defined(CONFIG_USER_ONLY)
2617 * A helper function for the _utterly broken_ virtio device model to find out if
2618 * it's running on a big endian machine. Don't do this at home kids!
2620 bool virtio_is_big_endian(void);
2621 bool virtio_is_big_endian(void)
2623 #if defined(TARGET_WORDS_BIGENDIAN)
2624 return true;
2625 #else
2626 return false;
2627 #endif
2630 #endif
2632 #ifndef CONFIG_USER_ONLY
2633 bool cpu_physical_memory_is_io(hwaddr phys_addr)
2635 MemoryRegionSection *section;
2637 section = phys_page_find(address_space_memory.dispatch,
2638 phys_addr >> TARGET_PAGE_BITS);
2640 return !(memory_region_is_ram(section->mr) ||
2641 memory_region_is_romd(section->mr));
2643 #endif