2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
29 #undef SPICE_RING_PROD_ITEM
30 #define SPICE_RING_PROD_ITEM(r, ret) { \
31 typeof(r) start = r; \
32 typeof(r) end = r + 1; \
33 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
34 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
35 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
41 #undef SPICE_RING_CONS_ITEM
42 #define SPICE_RING_CONS_ITEM(r, ret) { \
43 typeof(r) start = r; \
44 typeof(r) end = r + 1; \
45 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
46 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
47 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
54 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
56 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
58 #define QXL_MODE(_x, _y, _b, _o) \
62 .stride = (_x) * (_b) / 8, \
63 .x_mili = PIXEL_SIZE * (_x), \
64 .y_mili = PIXEL_SIZE * (_y), \
68 #define QXL_MODE_16_32(x_res, y_res, orientation) \
69 QXL_MODE(x_res, y_res, 16, orientation), \
70 QXL_MODE(x_res, y_res, 32, orientation)
72 #define QXL_MODE_EX(x_res, y_res) \
73 QXL_MODE_16_32(x_res, y_res, 0), \
74 QXL_MODE_16_32(y_res, x_res, 1), \
75 QXL_MODE_16_32(x_res, y_res, 2), \
76 QXL_MODE_16_32(y_res, x_res, 3)
78 static QXLMode qxl_modes
[] = {
79 QXL_MODE_EX(640, 480),
80 QXL_MODE_EX(800, 480),
81 QXL_MODE_EX(800, 600),
82 QXL_MODE_EX(832, 624),
83 QXL_MODE_EX(960, 640),
84 QXL_MODE_EX(1024, 600),
85 QXL_MODE_EX(1024, 768),
86 QXL_MODE_EX(1152, 864),
87 QXL_MODE_EX(1152, 870),
88 QXL_MODE_EX(1280, 720),
89 QXL_MODE_EX(1280, 760),
90 QXL_MODE_EX(1280, 768),
91 QXL_MODE_EX(1280, 800),
92 QXL_MODE_EX(1280, 960),
93 QXL_MODE_EX(1280, 1024),
94 QXL_MODE_EX(1360, 768),
95 QXL_MODE_EX(1366, 768),
96 QXL_MODE_EX(1400, 1050),
97 QXL_MODE_EX(1440, 900),
98 QXL_MODE_EX(1600, 900),
99 QXL_MODE_EX(1600, 1200),
100 QXL_MODE_EX(1680, 1050),
101 QXL_MODE_EX(1920, 1080),
102 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
103 /* these modes need more than 8 MB video memory */
104 QXL_MODE_EX(1920, 1200),
105 QXL_MODE_EX(1920, 1440),
106 QXL_MODE_EX(2048, 1536),
107 QXL_MODE_EX(2560, 1440),
108 QXL_MODE_EX(2560, 1600),
110 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
111 /* these modes need more than 16 MB video memory */
112 QXL_MODE_EX(2560, 2048),
113 QXL_MODE_EX(2800, 2100),
114 QXL_MODE_EX(3200, 2400),
118 static PCIQXLDevice
*qxl0
;
120 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
121 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
122 static void qxl_reset_memslots(PCIQXLDevice
*d
);
123 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
124 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
126 void qxl_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
128 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
129 if (qxl
->guestdebug
) {
132 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
133 vfprintf(stderr
, msg
, ap
);
134 fprintf(stderr
, "\n");
140 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
141 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
142 uint32_t num_dirty_rects
,
143 uint32_t clear_dirty_region
,
144 qxl_async_io async
, struct QXLCookie
*cookie
)
146 if (async
== QXL_SYNC
) {
147 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
,
148 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
150 assert(cookie
!= NULL
);
151 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
152 clear_dirty_region
, (uint64_t)cookie
);
156 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
159 qemu_mutex_lock(&qxl
->track_lock
);
160 qxl
->guest_surfaces
.cmds
[id
] = 0;
161 qxl
->guest_surfaces
.count
--;
162 qemu_mutex_unlock(&qxl
->track_lock
);
165 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
171 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
172 QXL_IO_DESTROY_SURFACE_ASYNC
);
173 cookie
->u
.surface_id
= id
;
174 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
, (uint64_t)cookie
);
176 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
177 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
181 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
183 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
,
184 (uint64_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
185 QXL_IO_FLUSH_SURFACES_ASYNC
));
188 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
191 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
194 void qxl_spice_oom(PCIQXLDevice
*qxl
)
196 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
199 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
201 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
204 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
206 qemu_mutex_lock(&qxl
->track_lock
);
207 memset(&qxl
->guest_surfaces
.cmds
, 0, sizeof(qxl
->guest_surfaces
.cmds
));
208 qxl
->guest_surfaces
.count
= 0;
209 qemu_mutex_unlock(&qxl
->track_lock
);
212 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
215 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
,
216 (uint64_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
217 QXL_IO_DESTROY_ALL_SURFACES_ASYNC
));
219 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
220 qxl_spice_destroy_surfaces_complete(qxl
);
224 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
226 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
229 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
231 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
232 qemu_mutex_lock(&qxl
->track_lock
);
233 qxl
->guest_cursor
= 0;
234 qemu_mutex_unlock(&qxl
->track_lock
);
238 static inline uint32_t msb_mask(uint32_t val
)
243 mask
= ~(val
- 1) & val
;
245 } while (mask
< val
);
250 static ram_addr_t
qxl_rom_size(void)
252 uint32_t rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) + sizeof(qxl_modes
);
253 rom_size
= MAX(rom_size
, TARGET_PAGE_SIZE
);
254 rom_size
= msb_mask(rom_size
* 2 - 1);
258 static void init_qxl_rom(PCIQXLDevice
*d
)
260 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
261 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
262 uint32_t ram_header_size
;
263 uint32_t surface0_area_size
;
265 uint32_t fb
, maxfb
= 0;
268 memset(rom
, 0, d
->rom_size
);
270 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
271 rom
->id
= cpu_to_le32(d
->id
);
272 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
273 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
275 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
276 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
277 rom
->slots_start
= 1;
278 rom
->slots_end
= NUM_MEMSLOTS
- 1;
279 rom
->n_surfaces
= cpu_to_le32(NUM_SURFACES
);
281 modes
->n_modes
= cpu_to_le32(ARRAY_SIZE(qxl_modes
));
282 for (i
= 0; i
< modes
->n_modes
; i
++) {
283 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
287 modes
->modes
[i
].id
= cpu_to_le32(i
);
288 modes
->modes
[i
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
289 modes
->modes
[i
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
290 modes
->modes
[i
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
291 modes
->modes
[i
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
292 modes
->modes
[i
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
293 modes
->modes
[i
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
294 modes
->modes
[i
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
296 if (maxfb
< VGA_RAM_SIZE
&& d
->id
== 0)
297 maxfb
= VGA_RAM_SIZE
;
299 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
300 surface0_area_size
= ALIGN(maxfb
, 4096);
301 num_pages
= d
->vga
.vram_size
;
302 num_pages
-= ram_header_size
;
303 num_pages
-= surface0_area_size
;
304 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
306 rom
->draw_area_offset
= cpu_to_le32(0);
307 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
308 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
309 rom
->num_pages
= cpu_to_le32(num_pages
);
310 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
312 d
->shadow_rom
= *rom
;
317 static void init_qxl_ram(PCIQXLDevice
*d
)
322 buf
= d
->vga
.vram_ptr
;
323 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
324 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
325 d
->ram
->int_pending
= cpu_to_le32(0);
326 d
->ram
->int_mask
= cpu_to_le32(0);
327 d
->ram
->update_surface
= 0;
328 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
329 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
330 SPICE_RING_INIT(&d
->ram
->release_ring
);
331 SPICE_RING_PROD_ITEM(&d
->ram
->release_ring
, item
);
333 qxl_ring_set_dirty(d
);
336 /* can be called from spice server thread context */
337 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
339 memory_region_set_dirty(mr
, addr
, end
- addr
);
342 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
344 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
347 /* called from spice server thread context only */
348 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
350 void *base
= qxl
->vga
.vram_ptr
;
354 offset
&= ~(TARGET_PAGE_SIZE
-1);
355 assert(offset
< qxl
->vga
.vram_size
);
356 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ TARGET_PAGE_SIZE
);
359 /* can be called from spice server thread context */
360 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
362 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
363 ram_addr_t end
= qxl
->vga
.vram_size
;
364 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
368 * keep track of some command state, for savevm/loadvm.
369 * called from spice server thread context only
371 static void qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
373 switch (le32_to_cpu(ext
->cmd
.type
)) {
374 case QXL_CMD_SURFACE
:
376 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
377 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
378 PANIC_ON(id
>= NUM_SURFACES
);
379 qemu_mutex_lock(&qxl
->track_lock
);
380 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
381 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
382 qxl
->guest_surfaces
.count
++;
383 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
384 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
386 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
387 qxl
->guest_surfaces
.cmds
[id
] = 0;
388 qxl
->guest_surfaces
.count
--;
390 qemu_mutex_unlock(&qxl
->track_lock
);
395 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
396 if (cmd
->type
== QXL_CURSOR_SET
) {
397 qemu_mutex_lock(&qxl
->track_lock
);
398 qxl
->guest_cursor
= ext
->cmd
.data
;
399 qemu_mutex_unlock(&qxl
->track_lock
);
406 /* spice display interface callbacks */
408 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
410 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
412 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
413 qxl
->ssd
.worker
= qxl_worker
;
416 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
418 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
420 dprint(qxl
, 1, "%s: %d\n", __FUNCTION__
, level
);
421 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
422 qxl
->rom
->compression_level
= cpu_to_le32(level
);
423 qxl_rom_set_dirty(qxl
);
426 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
428 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
430 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
431 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
432 qxl_rom_set_dirty(qxl
);
435 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
437 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
439 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
440 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
441 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
442 info
->num_memslots
= NUM_MEMSLOTS
;
443 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
444 info
->internal_groupslot_id
= 0;
445 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
446 info
->n_surfaces
= NUM_SURFACES
;
449 static const char *qxl_mode_to_string(int mode
)
452 case QXL_MODE_COMPAT
:
454 case QXL_MODE_NATIVE
:
456 case QXL_MODE_UNDEFINED
:
464 static const char *io_port_to_string(uint32_t io_port
)
466 if (io_port
>= QXL_IO_RANGE_SIZE
) {
467 return "out of range";
469 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
470 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
471 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
472 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
473 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
474 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
475 [QXL_IO_RESET
] = "QXL_IO_RESET",
476 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
477 [QXL_IO_LOG
] = "QXL_IO_LOG",
478 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
479 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
480 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
481 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
482 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
483 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
484 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
485 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
486 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
487 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
488 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
489 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
490 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
491 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
492 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
493 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
494 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
496 return io_port_to_string
[io_port
];
499 /* called from spice server thread context only */
500 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
502 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
503 SimpleSpiceUpdate
*update
;
504 QXLCommandRing
*ring
;
510 dprint(qxl
, 2, "%s: vga\n", __FUNCTION__
);
512 qemu_mutex_lock(&qxl
->ssd
.lock
);
513 if (qxl
->ssd
.update
!= NULL
) {
514 update
= qxl
->ssd
.update
;
515 qxl
->ssd
.update
= NULL
;
519 qemu_mutex_unlock(&qxl
->ssd
.lock
);
521 dprint(qxl
, 2, "%s %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
522 qxl_log_command(qxl
, "vga", ext
);
525 case QXL_MODE_COMPAT
:
526 case QXL_MODE_NATIVE
:
527 case QXL_MODE_UNDEFINED
:
528 dprint(qxl
, 4, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
529 ring
= &qxl
->ram
->cmd_ring
;
530 if (SPICE_RING_IS_EMPTY(ring
)) {
533 dprint(qxl
, 2, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
534 SPICE_RING_CONS_ITEM(ring
, cmd
);
536 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
537 ext
->flags
= qxl
->cmdflags
;
538 SPICE_RING_POP(ring
, notify
);
539 qxl_ring_set_dirty(qxl
);
541 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
543 qxl
->guest_primary
.commands
++;
544 qxl_track_command(qxl
, ext
);
545 qxl_log_command(qxl
, "cmd", ext
);
552 /* called from spice server thread context only */
553 static int interface_req_cmd_notification(QXLInstance
*sin
)
555 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
559 case QXL_MODE_COMPAT
:
560 case QXL_MODE_NATIVE
:
561 case QXL_MODE_UNDEFINED
:
562 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
563 qxl_ring_set_dirty(qxl
);
572 /* called from spice server thread context only */
573 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
575 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
579 #define QXL_FREE_BUNCH_SIZE 32
581 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
582 /* ring full -- can't push */
585 if (!flush
&& d
->oom_running
) {
586 /* collect everything from oom handler before pushing */
589 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
590 /* collect a bit more before pushing */
594 SPICE_RING_PUSH(ring
, notify
);
595 dprint(d
, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
596 d
->num_free_res
, notify
? "yes" : "no",
597 ring
->prod
- ring
->cons
, ring
->num_items
,
598 ring
->prod
, ring
->cons
);
600 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
602 SPICE_RING_PROD_ITEM(ring
, item
);
605 d
->last_release
= NULL
;
606 qxl_ring_set_dirty(d
);
609 /* called from spice server thread context only */
610 static void interface_release_resource(QXLInstance
*sin
,
611 struct QXLReleaseInfoExt ext
)
613 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
614 QXLReleaseRing
*ring
;
617 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
618 /* host group -> vga mode update request */
619 qemu_spice_destroy_update(&qxl
->ssd
, (void *)(intptr_t)ext
.info
->id
);
624 * ext->info points into guest-visible memory
625 * pci bar 0, $command.release_info
627 ring
= &qxl
->ram
->release_ring
;
628 SPICE_RING_PROD_ITEM(ring
, item
);
630 /* stick head into the ring */
633 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
635 qxl_ring_set_dirty(qxl
);
637 /* append item to the list */
638 qxl
->last_release
->next
= ext
.info
->id
;
639 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
641 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
643 qxl
->last_release
= ext
.info
;
645 dprint(qxl
, 3, "%4d\r", qxl
->num_free_res
);
646 qxl_push_free_res(qxl
, 0);
649 /* called from spice server thread context only */
650 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
652 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
658 case QXL_MODE_COMPAT
:
659 case QXL_MODE_NATIVE
:
660 case QXL_MODE_UNDEFINED
:
661 ring
= &qxl
->ram
->cursor_ring
;
662 if (SPICE_RING_IS_EMPTY(ring
)) {
665 SPICE_RING_CONS_ITEM(ring
, cmd
);
667 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
668 ext
->flags
= qxl
->cmdflags
;
669 SPICE_RING_POP(ring
, notify
);
670 qxl_ring_set_dirty(qxl
);
672 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
674 qxl
->guest_primary
.commands
++;
675 qxl_track_command(qxl
, ext
);
676 qxl_log_command(qxl
, "csr", ext
);
678 qxl_render_cursor(qxl
, ext
);
686 /* called from spice server thread context only */
687 static int interface_req_cursor_notification(QXLInstance
*sin
)
689 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
693 case QXL_MODE_COMPAT
:
694 case QXL_MODE_NATIVE
:
695 case QXL_MODE_UNDEFINED
:
696 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
697 qxl_ring_set_dirty(qxl
);
706 /* called from spice server thread context */
707 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
709 fprintf(stderr
, "%s: abort()\n", __FUNCTION__
);
713 /* called from spice server thread context only */
714 static int interface_flush_resources(QXLInstance
*sin
)
716 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
719 dprint(qxl
, 1, "free: guest flush (have %d)\n", qxl
->num_free_res
);
720 ret
= qxl
->num_free_res
;
722 qxl_push_free_res(qxl
, 1);
727 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
729 /* called from spice server thread context only */
730 static void interface_async_complete_io(PCIQXLDevice
*qxl
, QXLCookie
*cookie
)
732 uint32_t current_async
;
734 qemu_mutex_lock(&qxl
->async_lock
);
735 current_async
= qxl
->current_async
;
736 qxl
->current_async
= QXL_UNDEFINED_IO
;
737 qemu_mutex_unlock(&qxl
->async_lock
);
739 dprint(qxl
, 2, "async_complete: %d (%p) done\n", current_async
, cookie
);
741 fprintf(stderr
, "qxl: %s: error, cookie is NULL\n", __func__
);
744 if (cookie
&& current_async
!= cookie
->io
) {
746 "qxl: %s: error: current_async = %d != %ld = cookie->io\n",
747 __func__
, current_async
, cookie
->io
);
749 switch (current_async
) {
750 case QXL_IO_CREATE_PRIMARY_ASYNC
:
751 qxl_create_guest_primary_complete(qxl
);
753 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
754 qxl_spice_destroy_surfaces_complete(qxl
);
756 case QXL_IO_DESTROY_SURFACE_ASYNC
:
757 qxl_spice_destroy_surface_wait_complete(qxl
, cookie
->u
.surface_id
);
760 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
763 /* called from spice server thread context only */
764 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie_token
)
766 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
767 QXLCookie
*cookie
= (QXLCookie
*)cookie_token
;
769 switch (cookie
->type
) {
770 case QXL_COOKIE_TYPE_IO
:
771 interface_async_complete_io(qxl
, cookie
);
774 fprintf(stderr
, "qxl: %s: unexpected cookie type %d\n",
775 __func__
, cookie
->type
);
780 static const QXLInterface qxl_interface
= {
781 .base
.type
= SPICE_INTERFACE_QXL
,
782 .base
.description
= "qxl gpu",
783 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
784 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
786 .attache_worker
= interface_attach_worker
,
787 .set_compression_level
= interface_set_compression_level
,
788 .set_mm_time
= interface_set_mm_time
,
789 .get_init_info
= interface_get_init_info
,
791 /* the callbacks below are called from spice server thread context */
792 .get_command
= interface_get_command
,
793 .req_cmd_notification
= interface_req_cmd_notification
,
794 .release_resource
= interface_release_resource
,
795 .get_cursor_command
= interface_get_cursor_command
,
796 .req_cursor_notification
= interface_req_cursor_notification
,
797 .notify_update
= interface_notify_update
,
798 .flush_resources
= interface_flush_resources
,
799 .async_complete
= interface_async_complete
,
802 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
804 if (d
->mode
== QXL_MODE_VGA
) {
807 dprint(d
, 1, "%s\n", __FUNCTION__
);
808 qemu_spice_create_host_primary(&d
->ssd
);
809 d
->mode
= QXL_MODE_VGA
;
810 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
813 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
815 if (d
->mode
!= QXL_MODE_VGA
) {
818 dprint(d
, 1, "%s\n", __FUNCTION__
);
819 qxl_destroy_primary(d
, QXL_SYNC
);
822 static void qxl_update_irq(PCIQXLDevice
*d
)
824 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
825 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
826 int level
= !!(pending
& mask
);
827 qemu_set_irq(d
->pci
.irq
[0], level
);
828 qxl_ring_set_dirty(d
);
831 static void qxl_check_state(PCIQXLDevice
*d
)
833 QXLRam
*ram
= d
->ram
;
835 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
836 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
839 static void qxl_reset_state(PCIQXLDevice
*d
)
841 QXLRom
*rom
= d
->rom
;
844 d
->shadow_rom
.update_id
= cpu_to_le32(0);
845 *rom
= d
->shadow_rom
;
846 qxl_rom_set_dirty(d
);
849 d
->last_release
= NULL
;
850 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
853 static void qxl_soft_reset(PCIQXLDevice
*d
)
855 dprint(d
, 1, "%s:\n", __FUNCTION__
);
859 qxl_enter_vga_mode(d
);
861 d
->mode
= QXL_MODE_UNDEFINED
;
865 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
867 dprint(d
, 1, "%s: start%s\n", __FUNCTION__
,
868 loadvm
? " (loadvm)" : "");
870 qxl_spice_reset_cursor(d
);
871 qxl_spice_reset_image_cache(d
);
872 qxl_reset_surfaces(d
);
873 qxl_reset_memslots(d
);
875 /* pre loadvm reset must not touch QXLRam. This lives in
876 * device memory, is migrated together with RAM and thus
877 * already loaded at this point */
881 qemu_spice_create_host_memslot(&d
->ssd
);
884 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
887 static void qxl_reset_handler(DeviceState
*dev
)
889 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
890 qxl_hard_reset(d
, 0);
893 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
895 VGACommonState
*vga
= opaque
;
896 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
898 if (qxl
->mode
!= QXL_MODE_VGA
) {
899 dprint(qxl
, 1, "%s\n", __FUNCTION__
);
900 qxl_destroy_primary(qxl
, QXL_SYNC
);
903 vga_ioport_write(opaque
, addr
, val
);
906 static const MemoryRegionPortio qxl_vga_portio_list
[] = {
907 { 0x04, 2, 1, .read
= vga_ioport_read
,
908 .write
= qxl_vga_ioport_write
}, /* 3b4 */
909 { 0x0a, 1, 1, .read
= vga_ioport_read
,
910 .write
= qxl_vga_ioport_write
}, /* 3ba */
911 { 0x10, 16, 1, .read
= vga_ioport_read
,
912 .write
= qxl_vga_ioport_write
}, /* 3c0 */
913 { 0x24, 2, 1, .read
= vga_ioport_read
,
914 .write
= qxl_vga_ioport_write
}, /* 3d4 */
915 { 0x2a, 1, 1, .read
= vga_ioport_read
,
916 .write
= qxl_vga_ioport_write
}, /* 3da */
917 PORTIO_END_OF_LIST(),
920 static void qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
923 static const int regions
[] = {
925 QXL_VRAM_RANGE_INDEX
,
927 uint64_t guest_start
;
933 QXLDevMemSlot memslot
;
936 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
937 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
939 dprint(d
, 1, "%s: slot %d: guest phys 0x%" PRIx64
" - 0x%" PRIx64
"\n",
940 __FUNCTION__
, slot_id
,
941 guest_start
, guest_end
);
943 PANIC_ON(slot_id
>= NUM_MEMSLOTS
);
944 PANIC_ON(guest_start
> guest_end
);
946 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
947 pci_region
= regions
[i
];
948 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
949 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
951 if (pci_start
== -1) {
954 /* start address in range ? */
955 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
958 /* end address in range ? */
959 if (guest_end
> pci_end
) {
965 PANIC_ON(i
== ARRAY_SIZE(regions
)); /* finished loop without match */
967 switch (pci_region
) {
968 case QXL_RAM_RANGE_INDEX
:
969 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vga
.vram
);
971 case QXL_VRAM_RANGE_INDEX
:
972 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vram_bar
);
975 /* should not happen */
979 memslot
.slot_id
= slot_id
;
980 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
981 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
982 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
983 memslot
.addr_delta
= memslot
.virt_start
- delta
;
984 memslot
.generation
= d
->rom
->slot_generation
= 0;
985 qxl_rom_set_dirty(d
);
987 dprint(d
, 1, "%s: slot %d: host virt 0x%lx - 0x%lx\n",
988 __FUNCTION__
, memslot
.slot_id
,
989 memslot
.virt_start
, memslot
.virt_end
);
991 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
992 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
993 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
994 d
->guest_slots
[slot_id
].delta
= delta
;
995 d
->guest_slots
[slot_id
].active
= 1;
998 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
1000 dprint(d
, 1, "%s: slot %d\n", __FUNCTION__
, slot_id
);
1001 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
1002 d
->guest_slots
[slot_id
].active
= 0;
1005 static void qxl_reset_memslots(PCIQXLDevice
*d
)
1007 dprint(d
, 1, "%s:\n", __FUNCTION__
);
1008 qxl_spice_reset_memslots(d
);
1009 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
1012 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
1014 dprint(d
, 1, "%s:\n", __FUNCTION__
);
1015 d
->mode
= QXL_MODE_UNDEFINED
;
1016 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
1019 /* can be also called from spice server thread context */
1020 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
1022 uint64_t phys
= le64_to_cpu(pqxl
);
1023 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1024 uint64_t offset
= phys
& 0xffffffffffff;
1027 case MEMSLOT_GROUP_HOST
:
1028 return (void *)(intptr_t)offset
;
1029 case MEMSLOT_GROUP_GUEST
:
1030 PANIC_ON(slot
>= NUM_MEMSLOTS
);
1031 PANIC_ON(!qxl
->guest_slots
[slot
].active
);
1032 PANIC_ON(offset
< qxl
->guest_slots
[slot
].delta
);
1033 offset
-= qxl
->guest_slots
[slot
].delta
;
1034 PANIC_ON(offset
> qxl
->guest_slots
[slot
].size
)
1035 return qxl
->guest_slots
[slot
].ptr
+ offset
;
1041 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1043 /* for local rendering */
1044 qxl_render_resize(qxl
);
1047 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1050 QXLDevSurfaceCreate surface
;
1051 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1053 assert(qxl
->mode
!= QXL_MODE_NATIVE
);
1054 qxl_exit_vga_mode(qxl
);
1056 dprint(qxl
, 1, "%s: %dx%d\n", __FUNCTION__
,
1057 le32_to_cpu(sc
->width
), le32_to_cpu(sc
->height
));
1059 surface
.format
= le32_to_cpu(sc
->format
);
1060 surface
.height
= le32_to_cpu(sc
->height
);
1061 surface
.mem
= le64_to_cpu(sc
->mem
);
1062 surface
.position
= le32_to_cpu(sc
->position
);
1063 surface
.stride
= le32_to_cpu(sc
->stride
);
1064 surface
.width
= le32_to_cpu(sc
->width
);
1065 surface
.type
= le32_to_cpu(sc
->type
);
1066 surface
.flags
= le32_to_cpu(sc
->flags
);
1068 surface
.mouse_mode
= true;
1069 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1071 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1074 qxl
->mode
= QXL_MODE_NATIVE
;
1076 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1078 if (async
== QXL_SYNC
) {
1079 qxl_create_guest_primary_complete(qxl
);
1083 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1084 * done (in QXL_SYNC case), 0 otherwise. */
1085 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1087 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1090 dprint(d
, 1, "%s\n", __FUNCTION__
);
1091 d
->mode
= QXL_MODE_UNDEFINED
;
1092 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1093 qxl_spice_reset_cursor(d
);
1097 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
1099 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1100 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1101 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1102 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1107 QXLSurfaceCreate surface
= {
1108 .width
= mode
->x_res
,
1109 .height
= mode
->y_res
,
1110 .stride
= -mode
->x_res
* 4,
1111 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1112 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1114 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1117 dprint(d
, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%" PRIx64
" ]\n",
1118 __func__
, modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
, devmem
);
1120 qxl_hard_reset(d
, 0);
1123 d
->guest_slots
[0].slot
= slot
;
1124 qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
);
1126 d
->guest_primary
.surface
= surface
;
1127 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1129 d
->mode
= QXL_MODE_COMPAT
;
1130 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1131 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1132 if (mode
->bits
== 16) {
1133 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1136 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1137 d
->rom
->mode
= cpu_to_le32(modenr
);
1138 qxl_rom_set_dirty(d
);
1141 static void ioport_write(void *opaque
, target_phys_addr_t addr
,
1142 uint64_t val
, unsigned size
)
1144 PCIQXLDevice
*d
= opaque
;
1145 uint32_t io_port
= addr
;
1146 qxl_async_io async
= QXL_SYNC
;
1147 uint32_t orig_io_port
= io_port
;
1151 case QXL_IO_SET_MODE
:
1152 case QXL_IO_MEMSLOT_ADD
:
1153 case QXL_IO_MEMSLOT_DEL
:
1154 case QXL_IO_CREATE_PRIMARY
:
1155 case QXL_IO_UPDATE_IRQ
:
1157 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1158 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1161 if (d
->mode
!= QXL_MODE_VGA
) {
1164 dprint(d
, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1165 __func__
, io_port
, io_port_to_string(io_port
));
1166 /* be nice to buggy guest drivers */
1167 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1168 io_port
<= QXL_IO_DESTROY_ALL_SURFACES_ASYNC
) {
1169 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1174 /* we change the io_port to avoid ifdeffery in the main switch */
1175 orig_io_port
= io_port
;
1177 case QXL_IO_UPDATE_AREA_ASYNC
:
1178 io_port
= QXL_IO_UPDATE_AREA
;
1180 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1181 io_port
= QXL_IO_MEMSLOT_ADD
;
1183 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1184 io_port
= QXL_IO_CREATE_PRIMARY
;
1186 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1187 io_port
= QXL_IO_DESTROY_PRIMARY
;
1189 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1190 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1192 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1193 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1195 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1198 qemu_mutex_lock(&d
->async_lock
);
1199 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1200 qxl_guest_bug(d
, "%d async started before last (%d) complete",
1201 io_port
, d
->current_async
);
1202 qemu_mutex_unlock(&d
->async_lock
);
1205 d
->current_async
= orig_io_port
;
1206 qemu_mutex_unlock(&d
->async_lock
);
1207 dprint(d
, 2, "start async %d (%"PRId64
")\n", io_port
, val
);
1214 case QXL_IO_UPDATE_AREA
:
1216 QXLRect update
= d
->ram
->update_area
;
1217 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1218 &update
, NULL
, 0, 0, async
,
1219 qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
1220 QXL_IO_UPDATE_AREA_ASYNC
));
1223 case QXL_IO_NOTIFY_CMD
:
1224 qemu_spice_wakeup(&d
->ssd
);
1226 case QXL_IO_NOTIFY_CURSOR
:
1227 qemu_spice_wakeup(&d
->ssd
);
1229 case QXL_IO_UPDATE_IRQ
:
1232 case QXL_IO_NOTIFY_OOM
:
1233 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1240 case QXL_IO_SET_MODE
:
1241 dprint(d
, 1, "QXL_SET_MODE %d\n", (int)val
);
1242 qxl_set_mode(d
, val
, 0);
1245 if (d
->guestdebug
) {
1246 fprintf(stderr
, "qxl/guest-%d: %" PRId64
": %s", d
->id
,
1247 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1251 dprint(d
, 1, "QXL_IO_RESET\n");
1252 qxl_hard_reset(d
, 0);
1254 case QXL_IO_MEMSLOT_ADD
:
1255 if (val
>= NUM_MEMSLOTS
) {
1256 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1259 if (d
->guest_slots
[val
].active
) {
1260 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1263 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1264 qxl_add_memslot(d
, val
, 0, async
);
1266 case QXL_IO_MEMSLOT_DEL
:
1267 if (val
>= NUM_MEMSLOTS
) {
1268 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1271 qxl_del_memslot(d
, val
);
1273 case QXL_IO_CREATE_PRIMARY
:
1275 qxl_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1279 dprint(d
, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async
);
1280 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1281 qxl_create_guest_primary(d
, 0, async
);
1283 case QXL_IO_DESTROY_PRIMARY
:
1285 qxl_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1289 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async
,
1290 qxl_mode_to_string(d
->mode
));
1291 if (!qxl_destroy_primary(d
, async
)) {
1292 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1293 qxl_mode_to_string(d
->mode
));
1297 case QXL_IO_DESTROY_SURFACE_WAIT
:
1298 if (val
>= NUM_SURFACES
) {
1299 qxl_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1300 "%d >= NUM_SURFACES", async
, val
);
1303 qxl_spice_destroy_surface_wait(d
, val
, async
);
1305 case QXL_IO_FLUSH_RELEASE
: {
1306 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1307 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1309 "ERROR: no flush, full release ring [p%d,%dc]\n",
1310 ring
->prod
, ring
->cons
);
1312 qxl_push_free_res(d
, 1 /* flush */);
1313 dprint(d
, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1314 qxl_mode_to_string(d
->mode
), d
->guest_surfaces
.count
,
1315 d
->num_free_res
, d
->last_release
);
1318 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1319 dprint(d
, 1, "QXL_IO_FLUSH_SURFACES_ASYNC"
1320 " (%"PRId64
") (%s, s#=%d, res#=%d)\n",
1321 val
, qxl_mode_to_string(d
->mode
), d
->guest_surfaces
.count
,
1323 qxl_spice_flush_surfaces_async(d
);
1325 case QXL_IO_DESTROY_ALL_SURFACES
:
1326 d
->mode
= QXL_MODE_UNDEFINED
;
1327 qxl_spice_destroy_surfaces(d
, async
);
1330 fprintf(stderr
, "%s: ioport=0x%x, abort()\n", __FUNCTION__
, io_port
);
1336 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1337 qemu_mutex_lock(&d
->async_lock
);
1338 d
->current_async
= QXL_UNDEFINED_IO
;
1339 qemu_mutex_unlock(&d
->async_lock
);
1343 static uint64_t ioport_read(void *opaque
, target_phys_addr_t addr
,
1346 PCIQXLDevice
*d
= opaque
;
1348 dprint(d
, 1, "%s: unexpected\n", __FUNCTION__
);
1352 static const MemoryRegionOps qxl_io_ops
= {
1353 .read
= ioport_read
,
1354 .write
= ioport_write
,
1356 .min_access_size
= 1,
1357 .max_access_size
= 1,
1361 static void pipe_read(void *opaque
)
1363 PCIQXLDevice
*d
= opaque
;
1368 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1369 } while (len
== sizeof(dummy
));
1373 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1375 uint32_t old_pending
;
1376 uint32_t le_events
= cpu_to_le32(events
);
1378 assert(d
->ssd
.running
);
1379 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1380 if ((old_pending
& le_events
) == le_events
) {
1383 if (qemu_thread_is_self(&d
->main
)) {
1386 if (write(d
->pipe
[1], d
, 1) != 1) {
1387 dprint(d
, 1, "%s: write to pipe failed\n", __FUNCTION__
);
1392 static void init_pipe_signaling(PCIQXLDevice
*d
)
1394 if (pipe(d
->pipe
) < 0) {
1395 dprint(d
, 1, "%s: pipe creation failed\n", __FUNCTION__
);
1398 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1399 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1400 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1402 qemu_thread_get_self(&d
->main
);
1403 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1406 /* graphics console */
1408 static void qxl_hw_update(void *opaque
)
1410 PCIQXLDevice
*qxl
= opaque
;
1411 VGACommonState
*vga
= &qxl
->vga
;
1413 switch (qxl
->mode
) {
1417 case QXL_MODE_COMPAT
:
1418 case QXL_MODE_NATIVE
:
1419 qxl_render_update(qxl
);
1426 static void qxl_hw_invalidate(void *opaque
)
1428 PCIQXLDevice
*qxl
= opaque
;
1429 VGACommonState
*vga
= &qxl
->vga
;
1431 vga
->invalidate(vga
);
1434 static void qxl_hw_screen_dump(void *opaque
, const char *filename
, bool cswitch
)
1436 PCIQXLDevice
*qxl
= opaque
;
1437 VGACommonState
*vga
= &qxl
->vga
;
1439 switch (qxl
->mode
) {
1440 case QXL_MODE_COMPAT
:
1441 case QXL_MODE_NATIVE
:
1442 qxl_render_update(qxl
);
1443 ppm_save(filename
, qxl
->ssd
.ds
->surface
);
1446 vga
->screen_dump(vga
, filename
, cswitch
);
1453 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1455 PCIQXLDevice
*qxl
= opaque
;
1456 VGACommonState
*vga
= &qxl
->vga
;
1458 if (qxl
->mode
== QXL_MODE_VGA
) {
1459 vga
->text_update(vga
, chardata
);
1464 static void qxl_dirty_surfaces(PCIQXLDevice
*qxl
)
1466 intptr_t vram_start
;
1469 if (qxl
->mode
!= QXL_MODE_NATIVE
&& qxl
->mode
!= QXL_MODE_COMPAT
) {
1473 /* dirty the primary surface */
1474 qxl_set_dirty(&qxl
->vga
.vram
, qxl
->shadow_rom
.draw_area_offset
,
1475 qxl
->shadow_rom
.surface0_area_size
);
1477 vram_start
= (intptr_t)memory_region_get_ram_ptr(&qxl
->vram_bar
);
1479 /* dirty the off-screen surfaces */
1480 for (i
= 0; i
< NUM_SURFACES
; i
++) {
1482 intptr_t surface_offset
;
1485 if (qxl
->guest_surfaces
.cmds
[i
] == 0) {
1489 cmd
= qxl_phys2virt(qxl
, qxl
->guest_surfaces
.cmds
[i
],
1490 MEMSLOT_GROUP_GUEST
);
1491 assert(cmd
->type
== QXL_SURFACE_CMD_CREATE
);
1492 surface_offset
= (intptr_t)qxl_phys2virt(qxl
,
1493 cmd
->u
.surface_create
.data
,
1494 MEMSLOT_GROUP_GUEST
);
1495 surface_offset
-= vram_start
;
1496 surface_size
= cmd
->u
.surface_create
.height
*
1497 abs(cmd
->u
.surface_create
.stride
);
1498 dprint(qxl
, 3, "%s: dirty surface %d, offset %d, size %d\n", __func__
,
1499 i
, (int)surface_offset
, surface_size
);
1500 qxl_set_dirty(&qxl
->vram_bar
, surface_offset
, surface_size
);
1504 static void qxl_vm_change_state_handler(void *opaque
, int running
,
1507 PCIQXLDevice
*qxl
= opaque
;
1508 qemu_spice_vm_change_state_handler(&qxl
->ssd
, running
, state
);
1512 * if qxl_send_events was called from spice server context before
1513 * migration ended, qxl_update_irq for these events might not have been
1516 qxl_update_irq(qxl
);
1518 /* make sure surfaces are saved before migration */
1519 qxl_dirty_surfaces(qxl
);
1523 /* display change listener */
1525 static void display_update(struct DisplayState
*ds
, int x
, int y
, int w
, int h
)
1527 if (qxl0
->mode
== QXL_MODE_VGA
) {
1528 qemu_spice_display_update(&qxl0
->ssd
, x
, y
, w
, h
);
1532 static void display_resize(struct DisplayState
*ds
)
1534 if (qxl0
->mode
== QXL_MODE_VGA
) {
1535 qemu_spice_display_resize(&qxl0
->ssd
);
1539 static void display_refresh(struct DisplayState
*ds
)
1541 if (qxl0
->mode
== QXL_MODE_VGA
) {
1542 qemu_spice_display_refresh(&qxl0
->ssd
);
1544 qemu_mutex_lock(&qxl0
->ssd
.lock
);
1545 qemu_spice_cursor_refresh_unlocked(&qxl0
->ssd
);
1546 qemu_mutex_unlock(&qxl0
->ssd
.lock
);
1550 static DisplayChangeListener display_listener
= {
1551 .dpy_update
= display_update
,
1552 .dpy_resize
= display_resize
,
1553 .dpy_refresh
= display_refresh
,
1556 static void qxl_init_ramsize(PCIQXLDevice
*qxl
, uint32_t ram_min_mb
)
1558 /* vga ram (bar 0) */
1559 if (qxl
->ram_size_mb
!= -1) {
1560 qxl
->vga
.vram_size
= qxl
->ram_size_mb
* 1024 * 1024;
1562 if (qxl
->vga
.vram_size
< ram_min_mb
* 1024 * 1024) {
1563 qxl
->vga
.vram_size
= ram_min_mb
* 1024 * 1024;
1566 /* vram (surfaces, bar 1) */
1567 if (qxl
->vram_size_mb
!= -1) {
1568 qxl
->vram_size
= qxl
->vram_size_mb
* 1024 * 1024;
1570 if (qxl
->vram_size
< 4096) {
1571 qxl
->vram_size
= 4096;
1573 if (qxl
->revision
== 1) {
1574 qxl
->vram_size
= 4096;
1577 qxl
->vga
.vram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1578 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1581 static int qxl_init_common(PCIQXLDevice
*qxl
)
1583 uint8_t* config
= qxl
->pci
.config
;
1584 uint32_t pci_device_rev
;
1587 qxl
->mode
= QXL_MODE_UNDEFINED
;
1588 qxl
->generation
= 1;
1589 qxl
->num_memslots
= NUM_MEMSLOTS
;
1590 qxl
->num_surfaces
= NUM_SURFACES
;
1591 qemu_mutex_init(&qxl
->track_lock
);
1592 qemu_mutex_init(&qxl
->async_lock
);
1593 qxl
->current_async
= QXL_UNDEFINED_IO
;
1595 switch (qxl
->revision
) {
1596 case 1: /* spice 0.4 -- qxl-1 */
1597 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1599 case 2: /* spice 0.6 -- qxl-2 */
1600 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1604 pci_device_rev
= QXL_DEFAULT_REVISION
;
1608 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1609 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1611 qxl
->rom_size
= qxl_rom_size();
1612 memory_region_init_ram(&qxl
->rom_bar
, "qxl.vrom", qxl
->rom_size
);
1613 vmstate_register_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
);
1617 memory_region_init_ram(&qxl
->vram_bar
, "qxl.vram", qxl
->vram_size
);
1618 vmstate_register_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
);
1620 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1621 if (qxl
->revision
== 1) {
1625 memory_region_init_io(&qxl
->io_bar
, &qxl_io_ops
, qxl
,
1626 "qxl-ioports", io_size
);
1628 vga_dirty_log_start(&qxl
->vga
);
1632 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
1633 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
1635 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
1636 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
1638 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
1639 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
1641 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
1642 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram_bar
);
1644 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
1645 qxl
->ssd
.qxl
.id
= qxl
->id
;
1646 qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
);
1647 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
1649 init_pipe_signaling(qxl
);
1650 qxl_reset_state(qxl
);
1655 static int qxl_init_primary(PCIDevice
*dev
)
1657 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1658 VGACommonState
*vga
= &qxl
->vga
;
1659 PortioList
*qxl_vga_port_list
= g_new(PortioList
, 1);
1662 qxl_init_ramsize(qxl
, 32);
1663 vga_common_init(vga
, qxl
->vga
.vram_size
);
1664 vga_init(vga
, pci_address_space(dev
), pci_address_space_io(dev
), false);
1665 portio_list_init(qxl_vga_port_list
, qxl_vga_portio_list
, vga
, "vga");
1666 portio_list_add(qxl_vga_port_list
, pci_address_space_io(dev
), 0x3b0);
1668 vga
->ds
= graphic_console_init(qxl_hw_update
, qxl_hw_invalidate
,
1669 qxl_hw_screen_dump
, qxl_hw_text_update
, qxl
);
1670 qemu_spice_display_init_common(&qxl
->ssd
, vga
->ds
);
1673 register_displaychangelistener(vga
->ds
, &display_listener
);
1675 return qxl_init_common(qxl
);
1678 static int qxl_init_secondary(PCIDevice
*dev
)
1680 static int device_id
= 1;
1681 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1683 qxl
->id
= device_id
++;
1684 qxl_init_ramsize(qxl
, 16);
1685 memory_region_init_ram(&qxl
->vga
.vram
, "qxl.vgavram", qxl
->vga
.vram_size
);
1686 vmstate_register_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
);
1687 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
1689 return qxl_init_common(qxl
);
1692 static void qxl_pre_save(void *opaque
)
1694 PCIQXLDevice
* d
= opaque
;
1695 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1697 dprint(d
, 1, "%s:\n", __FUNCTION__
);
1698 if (d
->last_release
== NULL
) {
1699 d
->last_release_offset
= 0;
1701 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
1703 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1706 static int qxl_pre_load(void *opaque
)
1708 PCIQXLDevice
* d
= opaque
;
1710 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1711 qxl_hard_reset(d
, 1);
1712 qxl_exit_vga_mode(d
);
1713 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1717 static void qxl_create_memslots(PCIQXLDevice
*d
)
1721 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
1722 if (!d
->guest_slots
[i
].active
) {
1725 dprint(d
, 1, "%s: restoring guest slot %d\n", __func__
, i
);
1726 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
1730 static int qxl_post_load(void *opaque
, int version
)
1732 PCIQXLDevice
* d
= opaque
;
1733 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1734 QXLCommandExt
*cmds
;
1735 int in
, out
, newmode
;
1737 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1739 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1740 if (d
->last_release_offset
== 0) {
1741 d
->last_release
= NULL
;
1743 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
1746 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
1748 dprint(d
, 1, "%s: restore mode (%s)\n", __FUNCTION__
,
1749 qxl_mode_to_string(d
->mode
));
1751 d
->mode
= QXL_MODE_UNDEFINED
;
1754 case QXL_MODE_UNDEFINED
:
1757 qxl_create_memslots(d
);
1758 qxl_enter_vga_mode(d
);
1760 case QXL_MODE_NATIVE
:
1761 qxl_create_memslots(d
);
1762 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
1764 /* replay surface-create and cursor-set commands */
1765 cmds
= g_malloc0(sizeof(QXLCommandExt
) * (NUM_SURFACES
+ 1));
1766 for (in
= 0, out
= 0; in
< NUM_SURFACES
; in
++) {
1767 if (d
->guest_surfaces
.cmds
[in
] == 0) {
1770 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
1771 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
1772 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1775 if (d
->guest_cursor
) {
1776 cmds
[out
].cmd
.data
= d
->guest_cursor
;
1777 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
1778 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1781 qxl_spice_loadvm_commands(d
, cmds
, out
);
1785 case QXL_MODE_COMPAT
:
1786 /* note: no need to call qxl_create_memslots, qxl_set_mode
1787 * creates the mem slot. */
1788 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
1791 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1796 #define QXL_SAVE_VERSION 21
1798 static VMStateDescription qxl_memslot
= {
1799 .name
= "qxl-memslot",
1800 .version_id
= QXL_SAVE_VERSION
,
1801 .minimum_version_id
= QXL_SAVE_VERSION
,
1802 .fields
= (VMStateField
[]) {
1803 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
1804 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
1805 VMSTATE_UINT32(active
, struct guest_slots
),
1806 VMSTATE_END_OF_LIST()
1810 static VMStateDescription qxl_surface
= {
1811 .name
= "qxl-surface",
1812 .version_id
= QXL_SAVE_VERSION
,
1813 .minimum_version_id
= QXL_SAVE_VERSION
,
1814 .fields
= (VMStateField
[]) {
1815 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
1816 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
1817 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
1818 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
1819 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
1820 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
1821 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
1822 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
1823 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
1824 VMSTATE_END_OF_LIST()
1828 static VMStateDescription qxl_vmstate
= {
1830 .version_id
= QXL_SAVE_VERSION
,
1831 .minimum_version_id
= QXL_SAVE_VERSION
,
1832 .pre_save
= qxl_pre_save
,
1833 .pre_load
= qxl_pre_load
,
1834 .post_load
= qxl_post_load
,
1835 .fields
= (VMStateField
[]) {
1836 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
1837 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
1838 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
1839 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
1840 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
1841 VMSTATE_UINT32(mode
, PCIQXLDevice
),
1842 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
1843 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
1844 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
1845 qxl_memslot
, struct guest_slots
),
1846 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
1847 qxl_surface
, QXLSurfaceCreate
),
1848 VMSTATE_INT32_EQUAL(num_surfaces
, PCIQXLDevice
),
1849 VMSTATE_ARRAY(guest_surfaces
.cmds
, PCIQXLDevice
, NUM_SURFACES
, 0,
1850 vmstate_info_uint64
, uint64_t),
1851 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
1852 VMSTATE_END_OF_LIST()
1856 static Property qxl_properties
[] = {
1857 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
1859 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
,
1861 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
1862 QXL_DEFAULT_REVISION
),
1863 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1864 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1865 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1866 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice
, ram_size_mb
, -1),
1867 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice
, vram_size_mb
, -1),
1868 DEFINE_PROP_END_OF_LIST(),
1871 static void qxl_primary_class_init(ObjectClass
*klass
, void *data
)
1873 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1874 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1877 k
->init
= qxl_init_primary
;
1878 k
->romfile
= "vgabios-qxl.bin";
1879 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
1880 k
->device_id
= QXL_DEVICE_ID_STABLE
;
1881 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
1882 dc
->desc
= "Spice QXL GPU (primary, vga compatible)";
1883 dc
->reset
= qxl_reset_handler
;
1884 dc
->vmsd
= &qxl_vmstate
;
1885 dc
->props
= qxl_properties
;
1888 static TypeInfo qxl_primary_info
= {
1890 .parent
= TYPE_PCI_DEVICE
,
1891 .instance_size
= sizeof(PCIQXLDevice
),
1892 .class_init
= qxl_primary_class_init
,
1895 static void qxl_secondary_class_init(ObjectClass
*klass
, void *data
)
1897 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1898 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1900 k
->init
= qxl_init_secondary
;
1901 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
1902 k
->device_id
= QXL_DEVICE_ID_STABLE
;
1903 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
1904 dc
->desc
= "Spice QXL GPU (secondary)";
1905 dc
->reset
= qxl_reset_handler
;
1906 dc
->vmsd
= &qxl_vmstate
;
1907 dc
->props
= qxl_properties
;
1910 static TypeInfo qxl_secondary_info
= {
1912 .parent
= TYPE_PCI_DEVICE
,
1913 .instance_size
= sizeof(PCIQXLDevice
),
1914 .class_init
= qxl_secondary_class_init
,
1917 static void qxl_register_types(void)
1919 type_register_static(&qxl_primary_info
);
1920 type_register_static(&qxl_secondary_info
);
1923 type_init(qxl_register_types
)