2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "host-utils.h"
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
41 # define LOG_DISAS(...) do { } while (0)
43 /*****************************************************************************/
44 /* Code translation helpers */
46 /* global register indexes */
47 static TCGv_ptr cpu_env
;
48 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 static TCGv cpu_gpr
[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh
[32];
59 static TCGv_i64 cpu_fpr
[32];
60 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
61 static TCGv_i32 cpu_crf
[8];
66 #if defined(TARGET_PPC64)
70 static TCGv cpu_reserve
;
71 static TCGv cpu_fpscr
;
72 static TCGv_i32 cpu_access_type
;
74 #include "gen-icount.h"
76 void ppc_translate_init(void)
80 size_t cpu_reg_names_size
;
81 static int done_init
= 0;
86 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
89 cpu_reg_names_size
= sizeof(cpu_reg_names
);
91 for (i
= 0; i
< 8; i
++) {
92 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
93 cpu_crf
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
94 offsetof(CPUPPCState
, crf
[i
]), p
);
96 cpu_reg_names_size
-= 5;
99 for (i
= 0; i
< 32; i
++) {
100 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
101 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
102 offsetof(CPUPPCState
, gpr
[i
]), p
);
103 p
+= (i
< 10) ? 3 : 4;
104 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
107 cpu_gprh
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
108 offsetof(CPUPPCState
, gprh
[i
]), p
);
109 p
+= (i
< 10) ? 4 : 5;
110 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
113 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
114 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUPPCState
, fpr
[i
]), p
);
116 p
+= (i
< 10) ? 4 : 5;
117 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
119 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
122 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
124 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
125 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
127 p
+= (i
< 10) ? 6 : 7;
128 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
130 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
133 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
135 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
136 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
138 p
+= (i
< 10) ? 6 : 7;
139 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
142 cpu_nip
= tcg_global_mem_new(TCG_AREG0
,
143 offsetof(CPUPPCState
, nip
), "nip");
145 cpu_msr
= tcg_global_mem_new(TCG_AREG0
,
146 offsetof(CPUPPCState
, msr
), "msr");
148 cpu_ctr
= tcg_global_mem_new(TCG_AREG0
,
149 offsetof(CPUPPCState
, ctr
), "ctr");
151 cpu_lr
= tcg_global_mem_new(TCG_AREG0
,
152 offsetof(CPUPPCState
, lr
), "lr");
154 #if defined(TARGET_PPC64)
155 cpu_cfar
= tcg_global_mem_new(TCG_AREG0
,
156 offsetof(CPUPPCState
, cfar
), "cfar");
159 cpu_xer
= tcg_global_mem_new(TCG_AREG0
,
160 offsetof(CPUPPCState
, xer
), "xer");
162 cpu_reserve
= tcg_global_mem_new(TCG_AREG0
,
163 offsetof(CPUPPCState
, reserve_addr
),
166 cpu_fpscr
= tcg_global_mem_new(TCG_AREG0
,
167 offsetof(CPUPPCState
, fpscr
), "fpscr");
169 cpu_access_type
= tcg_global_mem_new_i32(TCG_AREG0
,
170 offsetof(CPUPPCState
, access_type
), "access_type");
172 /* register helpers */
179 /* internal defines */
180 typedef struct DisasContext
{
181 struct TranslationBlock
*tb
;
185 /* Routine used to access memory */
188 /* Translation flags */
190 #if defined(TARGET_PPC64)
197 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
198 int singlestep_enabled
;
201 struct opc_handler_t
{
202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
206 /* instruction type */
208 /* extended instruction type */
211 void (*handler
)(DisasContext
*ctx
);
212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
215 #if defined(DO_PPC_STATISTICS)
220 static inline void gen_reset_fpstatus(void)
222 gen_helper_reset_fpstatus(cpu_env
);
225 static inline void gen_compute_fprf(TCGv_i64 arg
, int set_fprf
, int set_rc
)
227 TCGv_i32 t0
= tcg_temp_new_i32();
230 /* This case might be optimized later */
231 tcg_gen_movi_i32(t0
, 1);
232 gen_helper_compute_fprf(t0
, cpu_env
, arg
, t0
);
233 if (unlikely(set_rc
)) {
234 tcg_gen_mov_i32(cpu_crf
[1], t0
);
236 gen_helper_float_check_status(cpu_env
);
237 } else if (unlikely(set_rc
)) {
238 /* We always need to compute fpcc */
239 tcg_gen_movi_i32(t0
, 0);
240 gen_helper_compute_fprf(t0
, cpu_env
, arg
, t0
);
241 tcg_gen_mov_i32(cpu_crf
[1], t0
);
244 tcg_temp_free_i32(t0
);
247 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
249 if (ctx
->access_type
!= access_type
) {
250 tcg_gen_movi_i32(cpu_access_type
, access_type
);
251 ctx
->access_type
= access_type
;
255 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
257 #if defined(TARGET_PPC64)
259 tcg_gen_movi_tl(cpu_nip
, nip
);
262 tcg_gen_movi_tl(cpu_nip
, (uint32_t)nip
);
265 static inline void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
268 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
269 gen_update_nip(ctx
, ctx
->nip
);
271 t0
= tcg_const_i32(excp
);
272 t1
= tcg_const_i32(error
);
273 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
274 tcg_temp_free_i32(t0
);
275 tcg_temp_free_i32(t1
);
276 ctx
->exception
= (excp
);
279 static inline void gen_exception(DisasContext
*ctx
, uint32_t excp
)
282 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
283 gen_update_nip(ctx
, ctx
->nip
);
285 t0
= tcg_const_i32(excp
);
286 gen_helper_raise_exception(cpu_env
, t0
);
287 tcg_temp_free_i32(t0
);
288 ctx
->exception
= (excp
);
291 static inline void gen_debug_exception(DisasContext
*ctx
)
295 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
296 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
297 gen_update_nip(ctx
, ctx
->nip
);
299 t0
= tcg_const_i32(EXCP_DEBUG
);
300 gen_helper_raise_exception(cpu_env
, t0
);
301 tcg_temp_free_i32(t0
);
304 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
306 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
309 /* Stop translation */
310 static inline void gen_stop_exception(DisasContext
*ctx
)
312 gen_update_nip(ctx
, ctx
->nip
);
313 ctx
->exception
= POWERPC_EXCP_STOP
;
316 /* No need to update nip here, as execution flow will change */
317 static inline void gen_sync_exception(DisasContext
*ctx
)
319 ctx
->exception
= POWERPC_EXCP_SYNC
;
322 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
323 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
325 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
326 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
328 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
331 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
334 typedef struct opcode_t
{
335 unsigned char opc1
, opc2
, opc3
;
336 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
337 unsigned char pad
[5];
339 unsigned char pad
[1];
341 opc_handler_t handler
;
345 /*****************************************************************************/
346 /*** Instruction decoding ***/
347 #define EXTRACT_HELPER(name, shift, nb) \
348 static inline uint32_t name(uint32_t opcode) \
350 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
353 #define EXTRACT_SHELPER(name, shift, nb) \
354 static inline int32_t name(uint32_t opcode) \
356 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
360 EXTRACT_HELPER(opc1
, 26, 6);
362 EXTRACT_HELPER(opc2
, 1, 5);
364 EXTRACT_HELPER(opc3
, 6, 5);
365 /* Update Cr0 flags */
366 EXTRACT_HELPER(Rc
, 0, 1);
368 EXTRACT_HELPER(rD
, 21, 5);
370 EXTRACT_HELPER(rS
, 21, 5);
372 EXTRACT_HELPER(rA
, 16, 5);
374 EXTRACT_HELPER(rB
, 11, 5);
376 EXTRACT_HELPER(rC
, 6, 5);
378 EXTRACT_HELPER(crfD
, 23, 3);
379 EXTRACT_HELPER(crfS
, 18, 3);
380 EXTRACT_HELPER(crbD
, 21, 5);
381 EXTRACT_HELPER(crbA
, 16, 5);
382 EXTRACT_HELPER(crbB
, 11, 5);
384 EXTRACT_HELPER(_SPR
, 11, 10);
385 static inline uint32_t SPR(uint32_t opcode
)
387 uint32_t sprn
= _SPR(opcode
);
389 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
391 /*** Get constants ***/
392 EXTRACT_HELPER(IMM
, 12, 8);
393 /* 16 bits signed immediate value */
394 EXTRACT_SHELPER(SIMM
, 0, 16);
395 /* 16 bits unsigned immediate value */
396 EXTRACT_HELPER(UIMM
, 0, 16);
397 /* 5 bits signed immediate value */
398 EXTRACT_HELPER(SIMM5
, 16, 5);
399 /* 5 bits signed immediate value */
400 EXTRACT_HELPER(UIMM5
, 16, 5);
402 EXTRACT_HELPER(NB
, 11, 5);
404 EXTRACT_HELPER(SH
, 11, 5);
405 /* Vector shift count */
406 EXTRACT_HELPER(VSH
, 6, 4);
408 EXTRACT_HELPER(MB
, 6, 5);
410 EXTRACT_HELPER(ME
, 1, 5);
412 EXTRACT_HELPER(TO
, 21, 5);
414 EXTRACT_HELPER(CRM
, 12, 8);
415 EXTRACT_HELPER(FM
, 17, 8);
416 EXTRACT_HELPER(SR
, 16, 4);
417 EXTRACT_HELPER(FPIMM
, 12, 4);
419 /*** Jump target decoding ***/
421 EXTRACT_SHELPER(d
, 0, 16);
422 /* Immediate address */
423 static inline target_ulong
LI(uint32_t opcode
)
425 return (opcode
>> 0) & 0x03FFFFFC;
428 static inline uint32_t BD(uint32_t opcode
)
430 return (opcode
>> 0) & 0xFFFC;
433 EXTRACT_HELPER(BO
, 21, 5);
434 EXTRACT_HELPER(BI
, 16, 5);
435 /* Absolute/relative address */
436 EXTRACT_HELPER(AA
, 1, 1);
438 EXTRACT_HELPER(LK
, 0, 1);
440 /* Create a mask between <start> and <end> bits */
441 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
445 #if defined(TARGET_PPC64)
446 if (likely(start
== 0)) {
447 ret
= UINT64_MAX
<< (63 - end
);
448 } else if (likely(end
== 63)) {
449 ret
= UINT64_MAX
>> start
;
452 if (likely(start
== 0)) {
453 ret
= UINT32_MAX
<< (31 - end
);
454 } else if (likely(end
== 31)) {
455 ret
= UINT32_MAX
>> start
;
459 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
460 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
461 if (unlikely(start
> end
))
468 /*****************************************************************************/
469 /* PowerPC instructions table */
471 #if defined(DO_PPC_STATISTICS)
472 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
482 .handler = &gen_##name, \
483 .oname = stringify(name), \
485 .oname = stringify(name), \
487 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
498 .handler = &gen_##name, \
499 .oname = stringify(name), \
501 .oname = stringify(name), \
503 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
513 .handler = &gen_##name, \
519 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
529 .handler = &gen_##name, \
531 .oname = stringify(name), \
533 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
544 .handler = &gen_##name, \
546 .oname = stringify(name), \
548 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
558 .handler = &gen_##name, \
564 /* SPR load/store helpers */
565 static inline void gen_load_spr(TCGv t
, int reg
)
567 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
570 static inline void gen_store_spr(int reg
, TCGv t
)
572 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
575 /* Invalid instruction */
576 static void gen_invalid(DisasContext
*ctx
)
578 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
581 static opc_handler_t invalid_handler
= {
582 .inval1
= 0xFFFFFFFF,
583 .inval2
= 0xFFFFFFFF,
586 .handler
= gen_invalid
,
589 /*** Integer comparison ***/
591 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
595 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_xer
);
596 tcg_gen_shri_i32(cpu_crf
[crf
], cpu_crf
[crf
], XER_SO
);
597 tcg_gen_andi_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1);
599 l1
= gen_new_label();
600 l2
= gen_new_label();
601 l3
= gen_new_label();
603 tcg_gen_brcond_tl(TCG_COND_LT
, arg0
, arg1
, l1
);
604 tcg_gen_brcond_tl(TCG_COND_GT
, arg0
, arg1
, l2
);
606 tcg_gen_brcond_tl(TCG_COND_LTU
, arg0
, arg1
, l1
);
607 tcg_gen_brcond_tl(TCG_COND_GTU
, arg0
, arg1
, l2
);
609 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_EQ
);
612 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_LT
);
615 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_GT
);
619 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
621 TCGv t0
= tcg_const_local_tl(arg1
);
622 gen_op_cmp(arg0
, t0
, s
, crf
);
626 #if defined(TARGET_PPC64)
627 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
630 t0
= tcg_temp_local_new();
631 t1
= tcg_temp_local_new();
633 tcg_gen_ext32s_tl(t0
, arg0
);
634 tcg_gen_ext32s_tl(t1
, arg1
);
636 tcg_gen_ext32u_tl(t0
, arg0
);
637 tcg_gen_ext32u_tl(t1
, arg1
);
639 gen_op_cmp(t0
, t1
, s
, crf
);
644 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
646 TCGv t0
= tcg_const_local_tl(arg1
);
647 gen_op_cmp32(arg0
, t0
, s
, crf
);
652 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
654 #if defined(TARGET_PPC64)
656 gen_op_cmpi32(reg
, 0, 1, 0);
659 gen_op_cmpi(reg
, 0, 1, 0);
663 static void gen_cmp(DisasContext
*ctx
)
665 #if defined(TARGET_PPC64)
666 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
667 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
668 1, crfD(ctx
->opcode
));
671 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
672 1, crfD(ctx
->opcode
));
676 static void gen_cmpi(DisasContext
*ctx
)
678 #if defined(TARGET_PPC64)
679 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
680 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
681 1, crfD(ctx
->opcode
));
684 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
685 1, crfD(ctx
->opcode
));
689 static void gen_cmpl(DisasContext
*ctx
)
691 #if defined(TARGET_PPC64)
692 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
693 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
694 0, crfD(ctx
->opcode
));
697 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
698 0, crfD(ctx
->opcode
));
702 static void gen_cmpli(DisasContext
*ctx
)
704 #if defined(TARGET_PPC64)
705 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
706 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
707 0, crfD(ctx
->opcode
));
710 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
711 0, crfD(ctx
->opcode
));
714 /* isel (PowerPC 2.03 specification) */
715 static void gen_isel(DisasContext
*ctx
)
718 uint32_t bi
= rC(ctx
->opcode
);
722 l1
= gen_new_label();
723 l2
= gen_new_label();
725 mask
= 1 << (3 - (bi
& 0x03));
726 t0
= tcg_temp_new_i32();
727 tcg_gen_andi_i32(t0
, cpu_crf
[bi
>> 2], mask
);
728 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
729 if (rA(ctx
->opcode
) == 0)
730 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
732 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
735 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
737 tcg_temp_free_i32(t0
);
740 /*** Integer arithmetic ***/
742 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
743 TCGv arg1
, TCGv arg2
, int sub
)
748 l1
= gen_new_label();
749 /* Start with XER OV disabled, the most likely case */
750 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
751 t0
= tcg_temp_local_new();
752 tcg_gen_xor_tl(t0
, arg0
, arg1
);
753 #if defined(TARGET_PPC64)
755 tcg_gen_ext32s_tl(t0
, t0
);
758 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
760 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
761 tcg_gen_xor_tl(t0
, arg1
, arg2
);
762 #if defined(TARGET_PPC64)
764 tcg_gen_ext32s_tl(t0
, t0
);
767 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
769 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
770 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
775 static inline void gen_op_arith_compute_ca(DisasContext
*ctx
, TCGv arg1
,
778 int l1
= gen_new_label();
780 #if defined(TARGET_PPC64)
781 if (!(ctx
->sf_mode
)) {
786 tcg_gen_ext32u_tl(t0
, arg1
);
787 tcg_gen_ext32u_tl(t1
, arg2
);
789 tcg_gen_brcond_tl(TCG_COND_GTU
, t0
, t1
, l1
);
791 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
793 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
801 tcg_gen_brcond_tl(TCG_COND_GTU
, arg1
, arg2
, l1
);
803 tcg_gen_brcond_tl(TCG_COND_GEU
, arg1
, arg2
, l1
);
805 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
812 TCGv arg2
, int add_ca
, int compute_ca
,
817 if ((!compute_ca
&& !compute_ov
) ||
818 (!TCGV_EQUAL(ret
,arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
821 t0
= tcg_temp_local_new();
825 t1
= tcg_temp_local_new();
826 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
827 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
832 if (compute_ca
&& compute_ov
) {
833 /* Start with XER CA and OV disabled, the most likely case */
834 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
835 } else if (compute_ca
) {
836 /* Start with XER CA disabled, the most likely case */
837 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
838 } else if (compute_ov
) {
839 /* Start with XER OV disabled, the most likely case */
840 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
843 tcg_gen_add_tl(t0
, arg1
, arg2
);
846 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
849 tcg_gen_add_tl(t0
, t0
, t1
);
850 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
854 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
857 if (unlikely(Rc(ctx
->opcode
) != 0))
858 gen_set_Rc0(ctx
, t0
);
860 if (!TCGV_EQUAL(t0
, ret
)) {
861 tcg_gen_mov_tl(ret
, t0
);
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov); \
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
878 TCGv t0 = tcg_const_local_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov); \
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
901 static void gen_addi(DisasContext
*ctx
)
903 target_long simm
= SIMM(ctx
->opcode
);
905 if (rA(ctx
->opcode
) == 0) {
907 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
909 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
);
913 static inline void gen_op_addic(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
916 target_long simm
= SIMM(ctx
->opcode
);
918 /* Start with XER CA and OV disabled, the most likely case */
919 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
921 if (likely(simm
!= 0)) {
922 TCGv t0
= tcg_temp_local_new();
923 tcg_gen_addi_tl(t0
, arg1
, simm
);
924 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
925 tcg_gen_mov_tl(ret
, t0
);
928 tcg_gen_mov_tl(ret
, arg1
);
931 gen_set_Rc0(ctx
, ret
);
935 static void gen_addic(DisasContext
*ctx
)
937 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
940 static void gen_addic_(DisasContext
*ctx
)
942 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
946 static void gen_addis(DisasContext
*ctx
)
948 target_long simm
= SIMM(ctx
->opcode
);
950 if (rA(ctx
->opcode
) == 0) {
952 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
954 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
958 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
959 TCGv arg2
, int sign
, int compute_ov
)
961 int l1
= gen_new_label();
962 int l2
= gen_new_label();
963 TCGv_i32 t0
= tcg_temp_local_new_i32();
964 TCGv_i32 t1
= tcg_temp_local_new_i32();
966 tcg_gen_trunc_tl_i32(t0
, arg1
);
967 tcg_gen_trunc_tl_i32(t1
, arg2
);
968 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
970 int l3
= gen_new_label();
971 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
972 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
974 tcg_gen_div_i32(t0
, t0
, t1
);
976 tcg_gen_divu_i32(t0
, t0
, t1
);
979 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
984 tcg_gen_sari_i32(t0
, t0
, 31);
986 tcg_gen_movi_i32(t0
, 0);
989 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
992 tcg_gen_extu_i32_tl(ret
, t0
);
993 tcg_temp_free_i32(t0
);
994 tcg_temp_free_i32(t1
);
995 if (unlikely(Rc(ctx
->opcode
) != 0))
996 gen_set_Rc0(ctx
, ret
);
999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1000 static void glue(gen_, name)(DisasContext *ctx) \
1002 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1004 sign, compute_ov); \
1006 /* divwu divwu. divwuo divwuo. */
1007 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1008 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1009 /* divw divw. divwo divwo. */
1010 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1011 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1012 #if defined(TARGET_PPC64)
1013 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1014 TCGv arg2
, int sign
, int compute_ov
)
1016 int l1
= gen_new_label();
1017 int l2
= gen_new_label();
1019 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1021 int l3
= gen_new_label();
1022 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1023 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1025 tcg_gen_div_i64(ret
, arg1
, arg2
);
1027 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1030 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1035 tcg_gen_sari_i64(ret
, arg1
, 63);
1037 tcg_gen_movi_i64(ret
, 0);
1040 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1043 if (unlikely(Rc(ctx
->opcode
) != 0))
1044 gen_set_Rc0(ctx
, ret
);
1046 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1047 static void glue(gen_, name)(DisasContext *ctx) \
1049 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1050 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1051 sign, compute_ov); \
1053 /* divwu divwu. divwuo divwuo. */
1054 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1055 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1056 /* divw divw. divwo divwo. */
1057 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1058 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1062 static void gen_mulhw(DisasContext
*ctx
)
1066 t0
= tcg_temp_new_i64();
1067 t1
= tcg_temp_new_i64();
1068 #if defined(TARGET_PPC64)
1069 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1070 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1071 tcg_gen_mul_i64(t0
, t0
, t1
);
1072 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1074 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1075 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1076 tcg_gen_mul_i64(t0
, t0
, t1
);
1077 tcg_gen_shri_i64(t0
, t0
, 32);
1078 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1080 tcg_temp_free_i64(t0
);
1081 tcg_temp_free_i64(t1
);
1082 if (unlikely(Rc(ctx
->opcode
) != 0))
1083 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1086 /* mulhwu mulhwu. */
1087 static void gen_mulhwu(DisasContext
*ctx
)
1091 t0
= tcg_temp_new_i64();
1092 t1
= tcg_temp_new_i64();
1093 #if defined(TARGET_PPC64)
1094 tcg_gen_ext32u_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1095 tcg_gen_ext32u_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1096 tcg_gen_mul_i64(t0
, t0
, t1
);
1097 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1099 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1100 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1101 tcg_gen_mul_i64(t0
, t0
, t1
);
1102 tcg_gen_shri_i64(t0
, t0
, 32);
1103 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1105 tcg_temp_free_i64(t0
);
1106 tcg_temp_free_i64(t1
);
1107 if (unlikely(Rc(ctx
->opcode
) != 0))
1108 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1112 static void gen_mullw(DisasContext
*ctx
)
1114 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1115 cpu_gpr
[rB(ctx
->opcode
)]);
1116 tcg_gen_ext32s_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)]);
1117 if (unlikely(Rc(ctx
->opcode
) != 0))
1118 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1121 /* mullwo mullwo. */
1122 static void gen_mullwo(DisasContext
*ctx
)
1127 t0
= tcg_temp_new_i64();
1128 t1
= tcg_temp_new_i64();
1129 l1
= gen_new_label();
1130 /* Start with XER OV disabled, the most likely case */
1131 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1132 #if defined(TARGET_PPC64)
1133 tcg_gen_ext32s_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1134 tcg_gen_ext32s_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1136 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1137 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1139 tcg_gen_mul_i64(t0
, t0
, t1
);
1140 #if defined(TARGET_PPC64)
1141 tcg_gen_ext32s_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1142 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, cpu_gpr
[rD(ctx
->opcode
)], l1
);
1144 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1145 tcg_gen_ext32s_i64(t1
, t0
);
1146 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
1148 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1150 tcg_temp_free_i64(t0
);
1151 tcg_temp_free_i64(t1
);
1152 if (unlikely(Rc(ctx
->opcode
) != 0))
1153 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1157 static void gen_mulli(DisasContext
*ctx
)
1159 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1162 #if defined(TARGET_PPC64)
1163 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1164 static void glue(gen_, name)(DisasContext *ctx) \
1166 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1168 if (unlikely(Rc(ctx->opcode) != 0)) \
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1172 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00);
1173 /* mulhdu mulhdu. */
1174 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02);
1177 static void gen_mulld(DisasContext
*ctx
)
1179 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1180 cpu_gpr
[rB(ctx
->opcode
)]);
1181 if (unlikely(Rc(ctx
->opcode
) != 0))
1182 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1185 /* mulldo mulldo. */
1186 static void gen_mulldo(DisasContext
*ctx
)
1188 gen_helper_mulldo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
1189 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1190 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1191 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1196 /* neg neg. nego nego. */
1197 static inline void gen_op_arith_neg(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1200 int l1
= gen_new_label();
1201 int l2
= gen_new_label();
1202 TCGv t0
= tcg_temp_local_new();
1203 #if defined(TARGET_PPC64)
1205 tcg_gen_mov_tl(t0
, arg1
);
1206 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT64_MIN
, l1
);
1210 tcg_gen_ext32s_tl(t0
, arg1
);
1211 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
1213 tcg_gen_neg_tl(ret
, arg1
);
1215 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1219 tcg_gen_mov_tl(ret
, t0
);
1221 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1225 if (unlikely(Rc(ctx
->opcode
) != 0))
1226 gen_set_Rc0(ctx
, ret
);
1229 static void gen_neg(DisasContext
*ctx
)
1231 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
1234 static void gen_nego(DisasContext
*ctx
)
1236 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
1239 /* Common subf function */
1240 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1241 TCGv arg2
, int add_ca
, int compute_ca
,
1246 if ((!compute_ca
&& !compute_ov
) ||
1247 (!TCGV_EQUAL(ret
, arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
1250 t0
= tcg_temp_local_new();
1254 t1
= tcg_temp_local_new();
1255 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
1256 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
1261 if (compute_ca
&& compute_ov
) {
1262 /* Start with XER CA and OV disabled, the most likely case */
1263 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
1264 } else if (compute_ca
) {
1265 /* Start with XER CA disabled, the most likely case */
1266 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1267 } else if (compute_ov
) {
1268 /* Start with XER OV disabled, the most likely case */
1269 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1273 tcg_gen_not_tl(t0
, arg1
);
1274 tcg_gen_add_tl(t0
, t0
, arg2
);
1275 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 0);
1276 tcg_gen_add_tl(t0
, t0
, t1
);
1277 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
1280 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1282 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 1);
1286 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1289 if (unlikely(Rc(ctx
->opcode
) != 0))
1290 gen_set_Rc0(ctx
, t0
);
1292 if (!TCGV_EQUAL(t0
, ret
)) {
1293 tcg_gen_mov_tl(ret
, t0
);
1297 /* Sub functions with Two operands functions */
1298 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1299 static void glue(gen_, name)(DisasContext *ctx) \
1301 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1302 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1303 add_ca, compute_ca, compute_ov); \
1305 /* Sub functions with one operand and one immediate */
1306 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1307 add_ca, compute_ca, compute_ov) \
1308 static void glue(gen_, name)(DisasContext *ctx) \
1310 TCGv t0 = tcg_const_local_tl(const_val); \
1311 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1312 cpu_gpr[rA(ctx->opcode)], t0, \
1313 add_ca, compute_ca, compute_ov); \
1314 tcg_temp_free(t0); \
1316 /* subf subf. subfo subfo. */
1317 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1318 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1319 /* subfc subfc. subfco subfco. */
1320 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1321 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1322 /* subfe subfe. subfeo subfo. */
1323 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1324 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1325 /* subfme subfme. subfmeo subfmeo. */
1326 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1327 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1328 /* subfze subfze. subfzeo subfzeo.*/
1329 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1330 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1333 static void gen_subfic(DisasContext
*ctx
)
1335 /* Start with XER CA and OV disabled, the most likely case */
1336 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1337 TCGv t0
= tcg_temp_local_new();
1338 TCGv t1
= tcg_const_local_tl(SIMM(ctx
->opcode
));
1339 tcg_gen_sub_tl(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)]);
1340 gen_op_arith_compute_ca(ctx
, t0
, t1
, 1);
1342 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1346 /*** Integer logical ***/
1347 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1348 static void glue(gen_, name)(DisasContext *ctx) \
1350 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1351 cpu_gpr[rB(ctx->opcode)]); \
1352 if (unlikely(Rc(ctx->opcode) != 0)) \
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1356 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1357 static void glue(gen_, name)(DisasContext *ctx) \
1359 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1360 if (unlikely(Rc(ctx->opcode) != 0)) \
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1365 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1367 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1370 static void gen_andi_(DisasContext
*ctx
)
1372 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1373 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1377 static void gen_andis_(DisasContext
*ctx
)
1379 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1380 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1384 static void gen_cntlzw(DisasContext
*ctx
)
1386 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1387 if (unlikely(Rc(ctx
->opcode
) != 0))
1388 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1391 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1392 /* extsb & extsb. */
1393 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1394 /* extsh & extsh. */
1395 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1397 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1399 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1402 static void gen_or(DisasContext
*ctx
)
1406 rs
= rS(ctx
->opcode
);
1407 ra
= rA(ctx
->opcode
);
1408 rb
= rB(ctx
->opcode
);
1409 /* Optimisation for mr. ri case */
1410 if (rs
!= ra
|| rs
!= rb
) {
1412 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1414 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1415 if (unlikely(Rc(ctx
->opcode
) != 0))
1416 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1417 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1418 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1419 #if defined(TARGET_PPC64)
1425 /* Set process priority to low */
1429 /* Set process priority to medium-low */
1433 /* Set process priority to normal */
1436 #if !defined(CONFIG_USER_ONLY)
1438 if (ctx
->mem_idx
> 0) {
1439 /* Set process priority to very low */
1444 if (ctx
->mem_idx
> 0) {
1445 /* Set process priority to medium-hight */
1450 if (ctx
->mem_idx
> 0) {
1451 /* Set process priority to high */
1456 if (ctx
->mem_idx
> 1) {
1457 /* Set process priority to very high */
1467 TCGv t0
= tcg_temp_new();
1468 gen_load_spr(t0
, SPR_PPR
);
1469 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1470 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1471 gen_store_spr(SPR_PPR
, t0
);
1478 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1481 static void gen_xor(DisasContext
*ctx
)
1483 /* Optimisation for "set to zero" case */
1484 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1485 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1487 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1488 if (unlikely(Rc(ctx
->opcode
) != 0))
1489 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1493 static void gen_ori(DisasContext
*ctx
)
1495 target_ulong uimm
= UIMM(ctx
->opcode
);
1497 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1499 /* XXX: should handle special NOPs for POWER series */
1502 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1506 static void gen_oris(DisasContext
*ctx
)
1508 target_ulong uimm
= UIMM(ctx
->opcode
);
1510 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1514 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1518 static void gen_xori(DisasContext
*ctx
)
1520 target_ulong uimm
= UIMM(ctx
->opcode
);
1522 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1526 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1530 static void gen_xoris(DisasContext
*ctx
)
1532 target_ulong uimm
= UIMM(ctx
->opcode
);
1534 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1538 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1541 /* popcntb : PowerPC 2.03 specification */
1542 static void gen_popcntb(DisasContext
*ctx
)
1544 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1547 static void gen_popcntw(DisasContext
*ctx
)
1549 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1552 #if defined(TARGET_PPC64)
1553 /* popcntd: PowerPC 2.06 specification */
1554 static void gen_popcntd(DisasContext
*ctx
)
1556 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1560 #if defined(TARGET_PPC64)
1561 /* extsw & extsw. */
1562 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1565 static void gen_cntlzd(DisasContext
*ctx
)
1567 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1568 if (unlikely(Rc(ctx
->opcode
) != 0))
1569 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1573 /*** Integer rotate ***/
1575 /* rlwimi & rlwimi. */
1576 static void gen_rlwimi(DisasContext
*ctx
)
1578 uint32_t mb
, me
, sh
;
1580 mb
= MB(ctx
->opcode
);
1581 me
= ME(ctx
->opcode
);
1582 sh
= SH(ctx
->opcode
);
1583 if (likely(sh
== 0 && mb
== 0 && me
== 31)) {
1584 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1588 TCGv t0
= tcg_temp_new();
1589 #if defined(TARGET_PPC64)
1590 TCGv_i32 t2
= tcg_temp_new_i32();
1591 tcg_gen_trunc_i64_i32(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
1592 tcg_gen_rotli_i32(t2
, t2
, sh
);
1593 tcg_gen_extu_i32_i64(t0
, t2
);
1594 tcg_temp_free_i32(t2
);
1596 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1598 #if defined(TARGET_PPC64)
1602 mask
= MASK(mb
, me
);
1603 t1
= tcg_temp_new();
1604 tcg_gen_andi_tl(t0
, t0
, mask
);
1605 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1606 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1610 if (unlikely(Rc(ctx
->opcode
) != 0))
1611 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1614 /* rlwinm & rlwinm. */
1615 static void gen_rlwinm(DisasContext
*ctx
)
1617 uint32_t mb
, me
, sh
;
1619 sh
= SH(ctx
->opcode
);
1620 mb
= MB(ctx
->opcode
);
1621 me
= ME(ctx
->opcode
);
1623 if (likely(mb
== 0 && me
== (31 - sh
))) {
1624 if (likely(sh
== 0)) {
1625 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1627 TCGv t0
= tcg_temp_new();
1628 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1629 tcg_gen_shli_tl(t0
, t0
, sh
);
1630 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1633 } else if (likely(sh
!= 0 && me
== 31 && sh
== (32 - mb
))) {
1634 TCGv t0
= tcg_temp_new();
1635 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1636 tcg_gen_shri_tl(t0
, t0
, mb
);
1637 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1640 TCGv t0
= tcg_temp_new();
1641 #if defined(TARGET_PPC64)
1642 TCGv_i32 t1
= tcg_temp_new_i32();
1643 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1644 tcg_gen_rotli_i32(t1
, t1
, sh
);
1645 tcg_gen_extu_i32_i64(t0
, t1
);
1646 tcg_temp_free_i32(t1
);
1648 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1650 #if defined(TARGET_PPC64)
1654 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1657 if (unlikely(Rc(ctx
->opcode
) != 0))
1658 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1661 /* rlwnm & rlwnm. */
1662 static void gen_rlwnm(DisasContext
*ctx
)
1666 #if defined(TARGET_PPC64)
1670 mb
= MB(ctx
->opcode
);
1671 me
= ME(ctx
->opcode
);
1672 t0
= tcg_temp_new();
1673 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1674 #if defined(TARGET_PPC64)
1675 t1
= tcg_temp_new_i32();
1676 t2
= tcg_temp_new_i32();
1677 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1678 tcg_gen_trunc_i64_i32(t2
, t0
);
1679 tcg_gen_rotl_i32(t1
, t1
, t2
);
1680 tcg_gen_extu_i32_i64(t0
, t1
);
1681 tcg_temp_free_i32(t1
);
1682 tcg_temp_free_i32(t2
);
1684 tcg_gen_rotl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1686 if (unlikely(mb
!= 0 || me
!= 31)) {
1687 #if defined(TARGET_PPC64)
1691 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1693 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1696 if (unlikely(Rc(ctx
->opcode
) != 0))
1697 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1700 #if defined(TARGET_PPC64)
1701 #define GEN_PPC64_R2(name, opc1, opc2) \
1702 static void glue(gen_, name##0)(DisasContext *ctx) \
1704 gen_##name(ctx, 0); \
1707 static void glue(gen_, name##1)(DisasContext *ctx) \
1709 gen_##name(ctx, 1); \
1711 #define GEN_PPC64_R4(name, opc1, opc2) \
1712 static void glue(gen_, name##0)(DisasContext *ctx) \
1714 gen_##name(ctx, 0, 0); \
1717 static void glue(gen_, name##1)(DisasContext *ctx) \
1719 gen_##name(ctx, 0, 1); \
1722 static void glue(gen_, name##2)(DisasContext *ctx) \
1724 gen_##name(ctx, 1, 0); \
1727 static void glue(gen_, name##3)(DisasContext *ctx) \
1729 gen_##name(ctx, 1, 1); \
1732 static inline void gen_rldinm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
,
1735 if (likely(sh
!= 0 && mb
== 0 && me
== (63 - sh
))) {
1736 tcg_gen_shli_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1737 } else if (likely(sh
!= 0 && me
== 63 && sh
== (64 - mb
))) {
1738 tcg_gen_shri_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], mb
);
1740 TCGv t0
= tcg_temp_new();
1741 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1742 if (likely(mb
== 0 && me
== 63)) {
1743 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1745 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1749 if (unlikely(Rc(ctx
->opcode
) != 0))
1750 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1752 /* rldicl - rldicl. */
1753 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
1757 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1758 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1759 gen_rldinm(ctx
, mb
, 63, sh
);
1761 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1762 /* rldicr - rldicr. */
1763 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
1767 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1768 me
= MB(ctx
->opcode
) | (men
<< 5);
1769 gen_rldinm(ctx
, 0, me
, sh
);
1771 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1772 /* rldic - rldic. */
1773 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
1777 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1778 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1779 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1781 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1783 static inline void gen_rldnm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
)
1787 mb
= MB(ctx
->opcode
);
1788 me
= ME(ctx
->opcode
);
1789 t0
= tcg_temp_new();
1790 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1791 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1792 if (unlikely(mb
!= 0 || me
!= 63)) {
1793 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1795 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1798 if (unlikely(Rc(ctx
->opcode
) != 0))
1799 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1802 /* rldcl - rldcl. */
1803 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
1807 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1808 gen_rldnm(ctx
, mb
, 63);
1810 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1811 /* rldcr - rldcr. */
1812 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
1816 me
= MB(ctx
->opcode
) | (men
<< 5);
1817 gen_rldnm(ctx
, 0, me
);
1819 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1820 /* rldimi - rldimi. */
1821 static inline void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
1823 uint32_t sh
, mb
, me
;
1825 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1826 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1828 if (unlikely(sh
== 0 && mb
== 0)) {
1829 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1834 t0
= tcg_temp_new();
1835 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1836 t1
= tcg_temp_new();
1837 mask
= MASK(mb
, me
);
1838 tcg_gen_andi_tl(t0
, t0
, mask
);
1839 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1840 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1844 if (unlikely(Rc(ctx
->opcode
) != 0))
1845 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1847 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1850 /*** Integer shift ***/
1853 static void gen_slw(DisasContext
*ctx
)
1857 t0
= tcg_temp_new();
1858 /* AND rS with a mask that is 0 when rB >= 0x20 */
1859 #if defined(TARGET_PPC64)
1860 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1861 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1863 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1864 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1866 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1867 t1
= tcg_temp_new();
1868 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1869 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1872 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1873 if (unlikely(Rc(ctx
->opcode
) != 0))
1874 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1878 static void gen_sraw(DisasContext
*ctx
)
1880 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1881 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1882 if (unlikely(Rc(ctx
->opcode
) != 0))
1883 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1886 /* srawi & srawi. */
1887 static void gen_srawi(DisasContext
*ctx
)
1889 int sh
= SH(ctx
->opcode
);
1893 l1
= gen_new_label();
1894 l2
= gen_new_label();
1895 t0
= tcg_temp_local_new();
1896 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1897 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
1898 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
1899 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1900 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
1903 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1905 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1906 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, sh
);
1909 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1910 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1912 if (unlikely(Rc(ctx
->opcode
) != 0))
1913 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1917 static void gen_srw(DisasContext
*ctx
)
1921 t0
= tcg_temp_new();
1922 /* AND rS with a mask that is 0 when rB >= 0x20 */
1923 #if defined(TARGET_PPC64)
1924 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1925 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1927 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1928 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1930 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1931 tcg_gen_ext32u_tl(t0
, t0
);
1932 t1
= tcg_temp_new();
1933 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1934 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1937 if (unlikely(Rc(ctx
->opcode
) != 0))
1938 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1941 #if defined(TARGET_PPC64)
1943 static void gen_sld(DisasContext
*ctx
)
1947 t0
= tcg_temp_new();
1948 /* AND rS with a mask that is 0 when rB >= 0x40 */
1949 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
1950 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1951 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1952 t1
= tcg_temp_new();
1953 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1954 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1957 if (unlikely(Rc(ctx
->opcode
) != 0))
1958 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1962 static void gen_srad(DisasContext
*ctx
)
1964 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1965 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1966 if (unlikely(Rc(ctx
->opcode
) != 0))
1967 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1969 /* sradi & sradi. */
1970 static inline void gen_sradi(DisasContext
*ctx
, int n
)
1972 int sh
= SH(ctx
->opcode
) + (n
<< 5);
1976 l1
= gen_new_label();
1977 l2
= gen_new_label();
1978 t0
= tcg_temp_local_new();
1979 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
1980 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
1981 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1982 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
1985 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1988 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1990 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1991 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1993 if (unlikely(Rc(ctx
->opcode
) != 0))
1994 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1997 static void gen_sradi0(DisasContext
*ctx
)
2002 static void gen_sradi1(DisasContext
*ctx
)
2008 static void gen_srd(DisasContext
*ctx
)
2012 t0
= tcg_temp_new();
2013 /* AND rS with a mask that is 0 when rB >= 0x40 */
2014 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2015 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2016 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2017 t1
= tcg_temp_new();
2018 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2019 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2022 if (unlikely(Rc(ctx
->opcode
) != 0))
2023 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2027 /*** Floating-Point arithmetic ***/
2028 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2029 static void gen_f##name(DisasContext *ctx) \
2031 if (unlikely(!ctx->fpu_enabled)) { \
2032 gen_exception(ctx, POWERPC_EXCP_FPU); \
2035 /* NIP cannot be restored if the memory exception comes from an helper */ \
2036 gen_update_nip(ctx, ctx->nip - 4); \
2037 gen_reset_fpstatus(); \
2038 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2039 cpu_fpr[rA(ctx->opcode)], \
2040 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2042 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2043 cpu_fpr[rD(ctx->opcode)]); \
2045 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2046 Rc(ctx->opcode) != 0); \
2049 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2050 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2051 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2053 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2054 static void gen_f##name(DisasContext *ctx) \
2056 if (unlikely(!ctx->fpu_enabled)) { \
2057 gen_exception(ctx, POWERPC_EXCP_FPU); \
2060 /* NIP cannot be restored if the memory exception comes from an helper */ \
2061 gen_update_nip(ctx, ctx->nip - 4); \
2062 gen_reset_fpstatus(); \
2063 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2064 cpu_fpr[rA(ctx->opcode)], \
2065 cpu_fpr[rB(ctx->opcode)]); \
2067 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2068 cpu_fpr[rD(ctx->opcode)]); \
2070 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2071 set_fprf, Rc(ctx->opcode) != 0); \
2073 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2074 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2075 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2077 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2078 static void gen_f##name(DisasContext *ctx) \
2080 if (unlikely(!ctx->fpu_enabled)) { \
2081 gen_exception(ctx, POWERPC_EXCP_FPU); \
2084 /* NIP cannot be restored if the memory exception comes from an helper */ \
2085 gen_update_nip(ctx, ctx->nip - 4); \
2086 gen_reset_fpstatus(); \
2087 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2088 cpu_fpr[rA(ctx->opcode)], \
2089 cpu_fpr[rC(ctx->opcode)]); \
2091 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2092 cpu_fpr[rD(ctx->opcode)]); \
2094 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2095 set_fprf, Rc(ctx->opcode) != 0); \
2097 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2098 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2099 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2101 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2102 static void gen_f##name(DisasContext *ctx) \
2104 if (unlikely(!ctx->fpu_enabled)) { \
2105 gen_exception(ctx, POWERPC_EXCP_FPU); \
2108 /* NIP cannot be restored if the memory exception comes from an helper */ \
2109 gen_update_nip(ctx, ctx->nip - 4); \
2110 gen_reset_fpstatus(); \
2111 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2112 cpu_fpr[rB(ctx->opcode)]); \
2113 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2114 set_fprf, Rc(ctx->opcode) != 0); \
2117 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2118 static void gen_f##name(DisasContext *ctx) \
2120 if (unlikely(!ctx->fpu_enabled)) { \
2121 gen_exception(ctx, POWERPC_EXCP_FPU); \
2124 /* NIP cannot be restored if the memory exception comes from an helper */ \
2125 gen_update_nip(ctx, ctx->nip - 4); \
2126 gen_reset_fpstatus(); \
2127 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2128 cpu_fpr[rB(ctx->opcode)]); \
2129 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2130 set_fprf, Rc(ctx->opcode) != 0); \
2134 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2136 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2138 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2141 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2144 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2147 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2150 static void gen_frsqrtes(DisasContext
*ctx
)
2152 if (unlikely(!ctx
->fpu_enabled
)) {
2153 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2156 /* NIP cannot be restored if the memory exception comes from an helper */
2157 gen_update_nip(ctx
, ctx
->nip
- 4);
2158 gen_reset_fpstatus();
2159 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2160 cpu_fpr
[rB(ctx
->opcode
)]);
2161 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2162 cpu_fpr
[rD(ctx
->opcode
)]);
2163 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2167 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2169 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2173 static void gen_fsqrt(DisasContext
*ctx
)
2175 if (unlikely(!ctx
->fpu_enabled
)) {
2176 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2179 /* NIP cannot be restored if the memory exception comes from an helper */
2180 gen_update_nip(ctx
, ctx
->nip
- 4);
2181 gen_reset_fpstatus();
2182 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2183 cpu_fpr
[rB(ctx
->opcode
)]);
2184 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2187 static void gen_fsqrts(DisasContext
*ctx
)
2189 if (unlikely(!ctx
->fpu_enabled
)) {
2190 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2193 /* NIP cannot be restored if the memory exception comes from an helper */
2194 gen_update_nip(ctx
, ctx
->nip
- 4);
2195 gen_reset_fpstatus();
2196 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2197 cpu_fpr
[rB(ctx
->opcode
)]);
2198 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2199 cpu_fpr
[rD(ctx
->opcode
)]);
2200 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2203 /*** Floating-Point multiply-and-add ***/
2204 /* fmadd - fmadds */
2205 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2206 /* fmsub - fmsubs */
2207 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2208 /* fnmadd - fnmadds */
2209 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2210 /* fnmsub - fnmsubs */
2211 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2213 /*** Floating-Point round & convert ***/
2215 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2217 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2219 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2220 #if defined(TARGET_PPC64)
2222 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
2224 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
2226 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
2230 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2232 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2234 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2236 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2238 /*** Floating-Point compare ***/
2241 static void gen_fcmpo(DisasContext
*ctx
)
2244 if (unlikely(!ctx
->fpu_enabled
)) {
2245 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2248 /* NIP cannot be restored if the memory exception comes from an helper */
2249 gen_update_nip(ctx
, ctx
->nip
- 4);
2250 gen_reset_fpstatus();
2251 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2252 gen_helper_fcmpo(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2253 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2254 tcg_temp_free_i32(crf
);
2255 gen_helper_float_check_status(cpu_env
);
2259 static void gen_fcmpu(DisasContext
*ctx
)
2262 if (unlikely(!ctx
->fpu_enabled
)) {
2263 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2266 /* NIP cannot be restored if the memory exception comes from an helper */
2267 gen_update_nip(ctx
, ctx
->nip
- 4);
2268 gen_reset_fpstatus();
2269 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2270 gen_helper_fcmpu(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2271 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2272 tcg_temp_free_i32(crf
);
2273 gen_helper_float_check_status(cpu_env
);
2276 /*** Floating-point move ***/
2278 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2279 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
);
2282 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2283 static void gen_fmr(DisasContext
*ctx
)
2285 if (unlikely(!ctx
->fpu_enabled
)) {
2286 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2289 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2290 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2294 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2295 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
);
2297 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2298 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
);
2300 /*** Floating-Point status & ctrl register ***/
2303 static void gen_mcrfs(DisasContext
*ctx
)
2305 TCGv tmp
= tcg_temp_new();
2308 if (unlikely(!ctx
->fpu_enabled
)) {
2309 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2312 bfa
= 4 * (7 - crfS(ctx
->opcode
));
2313 tcg_gen_shri_tl(tmp
, cpu_fpscr
, bfa
);
2314 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], tmp
);
2316 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2317 tcg_gen_andi_tl(cpu_fpscr
, cpu_fpscr
, ~(0xF << bfa
));
2321 static void gen_mffs(DisasContext
*ctx
)
2323 if (unlikely(!ctx
->fpu_enabled
)) {
2324 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2327 gen_reset_fpstatus();
2328 tcg_gen_extu_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2329 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2333 static void gen_mtfsb0(DisasContext
*ctx
)
2337 if (unlikely(!ctx
->fpu_enabled
)) {
2338 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2341 crb
= 31 - crbD(ctx
->opcode
);
2342 gen_reset_fpstatus();
2343 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2345 /* NIP cannot be restored if the memory exception comes from an helper */
2346 gen_update_nip(ctx
, ctx
->nip
- 4);
2347 t0
= tcg_const_i32(crb
);
2348 gen_helper_fpscr_clrbit(cpu_env
, t0
);
2349 tcg_temp_free_i32(t0
);
2351 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2352 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2353 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2358 static void gen_mtfsb1(DisasContext
*ctx
)
2362 if (unlikely(!ctx
->fpu_enabled
)) {
2363 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2366 crb
= 31 - crbD(ctx
->opcode
);
2367 gen_reset_fpstatus();
2368 /* XXX: we pretend we can only do IEEE floating-point computations */
2369 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2371 /* NIP cannot be restored if the memory exception comes from an helper */
2372 gen_update_nip(ctx
, ctx
->nip
- 4);
2373 t0
= tcg_const_i32(crb
);
2374 gen_helper_fpscr_setbit(cpu_env
, t0
);
2375 tcg_temp_free_i32(t0
);
2377 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2378 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2379 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2381 /* We can raise a differed exception */
2382 gen_helper_float_check_status(cpu_env
);
2386 static void gen_mtfsf(DisasContext
*ctx
)
2389 int L
= ctx
->opcode
& 0x02000000;
2391 if (unlikely(!ctx
->fpu_enabled
)) {
2392 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2395 /* NIP cannot be restored if the memory exception comes from an helper */
2396 gen_update_nip(ctx
, ctx
->nip
- 4);
2397 gen_reset_fpstatus();
2399 t0
= tcg_const_i32(0xff);
2401 t0
= tcg_const_i32(FM(ctx
->opcode
));
2402 gen_helper_store_fpscr(cpu_env
, cpu_fpr
[rB(ctx
->opcode
)], t0
);
2403 tcg_temp_free_i32(t0
);
2404 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2405 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2406 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2408 /* We can raise a differed exception */
2409 gen_helper_float_check_status(cpu_env
);
2413 static void gen_mtfsfi(DisasContext
*ctx
)
2419 if (unlikely(!ctx
->fpu_enabled
)) {
2420 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2423 bf
= crbD(ctx
->opcode
) >> 2;
2425 /* NIP cannot be restored if the memory exception comes from an helper */
2426 gen_update_nip(ctx
, ctx
->nip
- 4);
2427 gen_reset_fpstatus();
2428 t0
= tcg_const_i64(FPIMM(ctx
->opcode
) << (4 * sh
));
2429 t1
= tcg_const_i32(1 << sh
);
2430 gen_helper_store_fpscr(cpu_env
, t0
, t1
);
2431 tcg_temp_free_i64(t0
);
2432 tcg_temp_free_i32(t1
);
2433 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2434 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2435 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2437 /* We can raise a differed exception */
2438 gen_helper_float_check_status(cpu_env
);
2441 /*** Addressing modes ***/
2442 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2443 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2446 target_long simm
= SIMM(ctx
->opcode
);
2449 if (rA(ctx
->opcode
) == 0) {
2450 #if defined(TARGET_PPC64)
2451 if (!ctx
->sf_mode
) {
2452 tcg_gen_movi_tl(EA
, (uint32_t)simm
);
2455 tcg_gen_movi_tl(EA
, simm
);
2456 } else if (likely(simm
!= 0)) {
2457 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2458 #if defined(TARGET_PPC64)
2459 if (!ctx
->sf_mode
) {
2460 tcg_gen_ext32u_tl(EA
, EA
);
2464 #if defined(TARGET_PPC64)
2465 if (!ctx
->sf_mode
) {
2466 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2469 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2473 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2475 if (rA(ctx
->opcode
) == 0) {
2476 #if defined(TARGET_PPC64)
2477 if (!ctx
->sf_mode
) {
2478 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2481 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2483 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2484 #if defined(TARGET_PPC64)
2485 if (!ctx
->sf_mode
) {
2486 tcg_gen_ext32u_tl(EA
, EA
);
2492 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2494 if (rA(ctx
->opcode
) == 0) {
2495 tcg_gen_movi_tl(EA
, 0);
2497 #if defined(TARGET_PPC64)
2498 if (!ctx
->sf_mode
) {
2499 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2502 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2506 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2509 tcg_gen_addi_tl(ret
, arg1
, val
);
2510 #if defined(TARGET_PPC64)
2511 if (!ctx
->sf_mode
) {
2512 tcg_gen_ext32u_tl(ret
, ret
);
2517 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2519 int l1
= gen_new_label();
2520 TCGv t0
= tcg_temp_new();
2522 /* NIP cannot be restored if the memory exception comes from an helper */
2523 gen_update_nip(ctx
, ctx
->nip
- 4);
2524 tcg_gen_andi_tl(t0
, EA
, mask
);
2525 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2526 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2527 t2
= tcg_const_i32(0);
2528 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2529 tcg_temp_free_i32(t1
);
2530 tcg_temp_free_i32(t2
);
2535 /*** Integer load ***/
2536 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2538 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2541 static inline void gen_qemu_ld8s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2543 tcg_gen_qemu_ld8s(arg1
, arg2
, ctx
->mem_idx
);
2546 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2548 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2549 if (unlikely(ctx
->le_mode
)) {
2550 tcg_gen_bswap16_tl(arg1
, arg1
);
2554 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2556 if (unlikely(ctx
->le_mode
)) {
2557 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2558 tcg_gen_bswap16_tl(arg1
, arg1
);
2559 tcg_gen_ext16s_tl(arg1
, arg1
);
2561 tcg_gen_qemu_ld16s(arg1
, arg2
, ctx
->mem_idx
);
2565 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2567 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2568 if (unlikely(ctx
->le_mode
)) {
2569 tcg_gen_bswap32_tl(arg1
, arg1
);
2573 #if defined(TARGET_PPC64)
2574 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2576 if (unlikely(ctx
->le_mode
)) {
2577 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2578 tcg_gen_bswap32_tl(arg1
, arg1
);
2579 tcg_gen_ext32s_tl(arg1
, arg1
);
2581 tcg_gen_qemu_ld32s(arg1
, arg2
, ctx
->mem_idx
);
2585 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2587 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2588 if (unlikely(ctx
->le_mode
)) {
2589 tcg_gen_bswap64_i64(arg1
, arg1
);
2593 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2595 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2598 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2600 if (unlikely(ctx
->le_mode
)) {
2601 TCGv t0
= tcg_temp_new();
2602 tcg_gen_ext16u_tl(t0
, arg1
);
2603 tcg_gen_bswap16_tl(t0
, t0
);
2604 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2607 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2611 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2613 if (unlikely(ctx
->le_mode
)) {
2614 TCGv t0
= tcg_temp_new();
2615 tcg_gen_ext32u_tl(t0
, arg1
);
2616 tcg_gen_bswap32_tl(t0
, t0
);
2617 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2620 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2624 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2626 if (unlikely(ctx
->le_mode
)) {
2627 TCGv_i64 t0
= tcg_temp_new_i64();
2628 tcg_gen_bswap64_i64(t0
, arg1
);
2629 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2630 tcg_temp_free_i64(t0
);
2632 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2635 #define GEN_LD(name, ldop, opc, type) \
2636 static void glue(gen_, name)(DisasContext *ctx) \
2639 gen_set_access_type(ctx, ACCESS_INT); \
2640 EA = tcg_temp_new(); \
2641 gen_addr_imm_index(ctx, EA, 0); \
2642 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2643 tcg_temp_free(EA); \
2646 #define GEN_LDU(name, ldop, opc, type) \
2647 static void glue(gen_, name##u)(DisasContext *ctx) \
2650 if (unlikely(rA(ctx->opcode) == 0 || \
2651 rA(ctx->opcode) == rD(ctx->opcode))) { \
2652 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2655 gen_set_access_type(ctx, ACCESS_INT); \
2656 EA = tcg_temp_new(); \
2657 if (type == PPC_64B) \
2658 gen_addr_imm_index(ctx, EA, 0x03); \
2660 gen_addr_imm_index(ctx, EA, 0); \
2661 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2662 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2663 tcg_temp_free(EA); \
2666 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2667 static void glue(gen_, name##ux)(DisasContext *ctx) \
2670 if (unlikely(rA(ctx->opcode) == 0 || \
2671 rA(ctx->opcode) == rD(ctx->opcode))) { \
2672 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2675 gen_set_access_type(ctx, ACCESS_INT); \
2676 EA = tcg_temp_new(); \
2677 gen_addr_reg_index(ctx, EA); \
2678 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2679 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2680 tcg_temp_free(EA); \
2683 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2684 static void glue(gen_, name##x)(DisasContext *ctx) \
2687 gen_set_access_type(ctx, ACCESS_INT); \
2688 EA = tcg_temp_new(); \
2689 gen_addr_reg_index(ctx, EA); \
2690 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2691 tcg_temp_free(EA); \
2693 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2694 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2696 #define GEN_LDS(name, ldop, op, type) \
2697 GEN_LD(name, ldop, op | 0x20, type); \
2698 GEN_LDU(name, ldop, op | 0x21, type); \
2699 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2700 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2702 /* lbz lbzu lbzux lbzx */
2703 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2704 /* lha lhau lhaux lhax */
2705 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2706 /* lhz lhzu lhzux lhzx */
2707 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2708 /* lwz lwzu lwzux lwzx */
2709 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2710 #if defined(TARGET_PPC64)
2712 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2714 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2716 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2718 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2720 static void gen_ld(DisasContext
*ctx
)
2723 if (Rc(ctx
->opcode
)) {
2724 if (unlikely(rA(ctx
->opcode
) == 0 ||
2725 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2726 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2730 gen_set_access_type(ctx
, ACCESS_INT
);
2731 EA
= tcg_temp_new();
2732 gen_addr_imm_index(ctx
, EA
, 0x03);
2733 if (ctx
->opcode
& 0x02) {
2734 /* lwa (lwau is undefined) */
2735 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2738 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2740 if (Rc(ctx
->opcode
))
2741 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2746 static void gen_lq(DisasContext
*ctx
)
2748 #if defined(CONFIG_USER_ONLY)
2749 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2754 /* Restore CPU state */
2755 if (unlikely(ctx
->mem_idx
== 0)) {
2756 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2759 ra
= rA(ctx
->opcode
);
2760 rd
= rD(ctx
->opcode
);
2761 if (unlikely((rd
& 1) || rd
== ra
)) {
2762 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2765 if (unlikely(ctx
->le_mode
)) {
2766 /* Little-endian mode is not handled */
2767 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2770 gen_set_access_type(ctx
, ACCESS_INT
);
2771 EA
= tcg_temp_new();
2772 gen_addr_imm_index(ctx
, EA
, 0x0F);
2773 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2774 gen_addr_add(ctx
, EA
, EA
, 8);
2775 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2781 /*** Integer store ***/
2782 #define GEN_ST(name, stop, opc, type) \
2783 static void glue(gen_, name)(DisasContext *ctx) \
2786 gen_set_access_type(ctx, ACCESS_INT); \
2787 EA = tcg_temp_new(); \
2788 gen_addr_imm_index(ctx, EA, 0); \
2789 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2790 tcg_temp_free(EA); \
2793 #define GEN_STU(name, stop, opc, type) \
2794 static void glue(gen_, stop##u)(DisasContext *ctx) \
2797 if (unlikely(rA(ctx->opcode) == 0)) { \
2798 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2801 gen_set_access_type(ctx, ACCESS_INT); \
2802 EA = tcg_temp_new(); \
2803 if (type == PPC_64B) \
2804 gen_addr_imm_index(ctx, EA, 0x03); \
2806 gen_addr_imm_index(ctx, EA, 0); \
2807 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2808 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2809 tcg_temp_free(EA); \
2812 #define GEN_STUX(name, stop, opc2, opc3, type) \
2813 static void glue(gen_, name##ux)(DisasContext *ctx) \
2816 if (unlikely(rA(ctx->opcode) == 0)) { \
2817 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2820 gen_set_access_type(ctx, ACCESS_INT); \
2821 EA = tcg_temp_new(); \
2822 gen_addr_reg_index(ctx, EA); \
2823 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2824 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2825 tcg_temp_free(EA); \
2828 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2829 static void glue(gen_, name##x)(DisasContext *ctx) \
2832 gen_set_access_type(ctx, ACCESS_INT); \
2833 EA = tcg_temp_new(); \
2834 gen_addr_reg_index(ctx, EA); \
2835 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2836 tcg_temp_free(EA); \
2838 #define GEN_STX(name, stop, opc2, opc3, type) \
2839 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2841 #define GEN_STS(name, stop, op, type) \
2842 GEN_ST(name, stop, op | 0x20, type); \
2843 GEN_STU(name, stop, op | 0x21, type); \
2844 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2845 GEN_STX(name, stop, 0x17, op | 0x00, type)
2847 /* stb stbu stbux stbx */
2848 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2849 /* sth sthu sthux sthx */
2850 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2851 /* stw stwu stwux stwx */
2852 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2853 #if defined(TARGET_PPC64)
2854 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
2855 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
2857 static void gen_std(DisasContext
*ctx
)
2862 rs
= rS(ctx
->opcode
);
2863 if ((ctx
->opcode
& 0x3) == 0x2) {
2864 #if defined(CONFIG_USER_ONLY)
2865 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2868 if (unlikely(ctx
->mem_idx
== 0)) {
2869 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2872 if (unlikely(rs
& 1)) {
2873 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2876 if (unlikely(ctx
->le_mode
)) {
2877 /* Little-endian mode is not handled */
2878 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2881 gen_set_access_type(ctx
, ACCESS_INT
);
2882 EA
= tcg_temp_new();
2883 gen_addr_imm_index(ctx
, EA
, 0x03);
2884 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2885 gen_addr_add(ctx
, EA
, EA
, 8);
2886 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2891 if (Rc(ctx
->opcode
)) {
2892 if (unlikely(rA(ctx
->opcode
) == 0)) {
2893 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2897 gen_set_access_type(ctx
, ACCESS_INT
);
2898 EA
= tcg_temp_new();
2899 gen_addr_imm_index(ctx
, EA
, 0x03);
2900 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2901 if (Rc(ctx
->opcode
))
2902 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2907 /*** Integer load and store with byte reverse ***/
2909 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2911 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2912 if (likely(!ctx
->le_mode
)) {
2913 tcg_gen_bswap16_tl(arg1
, arg1
);
2916 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2919 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2921 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2922 if (likely(!ctx
->le_mode
)) {
2923 tcg_gen_bswap32_tl(arg1
, arg1
);
2926 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2928 #if defined(TARGET_PPC64)
2930 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2932 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2933 if (likely(!ctx
->le_mode
)) {
2934 tcg_gen_bswap64_tl(arg1
, arg1
);
2937 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
);
2938 #endif /* TARGET_PPC64 */
2941 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2943 if (likely(!ctx
->le_mode
)) {
2944 TCGv t0
= tcg_temp_new();
2945 tcg_gen_ext16u_tl(t0
, arg1
);
2946 tcg_gen_bswap16_tl(t0
, t0
);
2947 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2950 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2953 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2956 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2958 if (likely(!ctx
->le_mode
)) {
2959 TCGv t0
= tcg_temp_new();
2960 tcg_gen_ext32u_tl(t0
, arg1
);
2961 tcg_gen_bswap32_tl(t0
, t0
);
2962 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2965 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2968 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2970 #if defined(TARGET_PPC64)
2972 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2974 if (likely(!ctx
->le_mode
)) {
2975 TCGv t0
= tcg_temp_new();
2976 tcg_gen_bswap64_tl(t0
, arg1
);
2977 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2980 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2983 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
);
2984 #endif /* TARGET_PPC64 */
2986 /*** Integer load and store multiple ***/
2989 static void gen_lmw(DisasContext
*ctx
)
2993 gen_set_access_type(ctx
, ACCESS_INT
);
2994 /* NIP cannot be restored if the memory exception comes from an helper */
2995 gen_update_nip(ctx
, ctx
->nip
- 4);
2996 t0
= tcg_temp_new();
2997 t1
= tcg_const_i32(rD(ctx
->opcode
));
2998 gen_addr_imm_index(ctx
, t0
, 0);
2999 gen_helper_lmw(cpu_env
, t0
, t1
);
3001 tcg_temp_free_i32(t1
);
3005 static void gen_stmw(DisasContext
*ctx
)
3009 gen_set_access_type(ctx
, ACCESS_INT
);
3010 /* NIP cannot be restored if the memory exception comes from an helper */
3011 gen_update_nip(ctx
, ctx
->nip
- 4);
3012 t0
= tcg_temp_new();
3013 t1
= tcg_const_i32(rS(ctx
->opcode
));
3014 gen_addr_imm_index(ctx
, t0
, 0);
3015 gen_helper_stmw(cpu_env
, t0
, t1
);
3017 tcg_temp_free_i32(t1
);
3020 /*** Integer load and store strings ***/
3023 /* PowerPC32 specification says we must generate an exception if
3024 * rA is in the range of registers to be loaded.
3025 * In an other hand, IBM says this is valid, but rA won't be loaded.
3026 * For now, I'll follow the spec...
3028 static void gen_lswi(DisasContext
*ctx
)
3032 int nb
= NB(ctx
->opcode
);
3033 int start
= rD(ctx
->opcode
);
3034 int ra
= rA(ctx
->opcode
);
3040 if (unlikely(((start
+ nr
) > 32 &&
3041 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
3042 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
3043 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3046 gen_set_access_type(ctx
, ACCESS_INT
);
3047 /* NIP cannot be restored if the memory exception comes from an helper */
3048 gen_update_nip(ctx
, ctx
->nip
- 4);
3049 t0
= tcg_temp_new();
3050 gen_addr_register(ctx
, t0
);
3051 t1
= tcg_const_i32(nb
);
3052 t2
= tcg_const_i32(start
);
3053 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
3055 tcg_temp_free_i32(t1
);
3056 tcg_temp_free_i32(t2
);
3060 static void gen_lswx(DisasContext
*ctx
)
3063 TCGv_i32 t1
, t2
, t3
;
3064 gen_set_access_type(ctx
, ACCESS_INT
);
3065 /* NIP cannot be restored if the memory exception comes from an helper */
3066 gen_update_nip(ctx
, ctx
->nip
- 4);
3067 t0
= tcg_temp_new();
3068 gen_addr_reg_index(ctx
, t0
);
3069 t1
= tcg_const_i32(rD(ctx
->opcode
));
3070 t2
= tcg_const_i32(rA(ctx
->opcode
));
3071 t3
= tcg_const_i32(rB(ctx
->opcode
));
3072 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
3074 tcg_temp_free_i32(t1
);
3075 tcg_temp_free_i32(t2
);
3076 tcg_temp_free_i32(t3
);
3080 static void gen_stswi(DisasContext
*ctx
)
3084 int nb
= NB(ctx
->opcode
);
3085 gen_set_access_type(ctx
, ACCESS_INT
);
3086 /* NIP cannot be restored if the memory exception comes from an helper */
3087 gen_update_nip(ctx
, ctx
->nip
- 4);
3088 t0
= tcg_temp_new();
3089 gen_addr_register(ctx
, t0
);
3092 t1
= tcg_const_i32(nb
);
3093 t2
= tcg_const_i32(rS(ctx
->opcode
));
3094 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3096 tcg_temp_free_i32(t1
);
3097 tcg_temp_free_i32(t2
);
3101 static void gen_stswx(DisasContext
*ctx
)
3105 gen_set_access_type(ctx
, ACCESS_INT
);
3106 /* NIP cannot be restored if the memory exception comes from an helper */
3107 gen_update_nip(ctx
, ctx
->nip
- 4);
3108 t0
= tcg_temp_new();
3109 gen_addr_reg_index(ctx
, t0
);
3110 t1
= tcg_temp_new_i32();
3111 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3112 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3113 t2
= tcg_const_i32(rS(ctx
->opcode
));
3114 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3116 tcg_temp_free_i32(t1
);
3117 tcg_temp_free_i32(t2
);
3120 /*** Memory synchronisation ***/
3122 static void gen_eieio(DisasContext
*ctx
)
3127 static void gen_isync(DisasContext
*ctx
)
3129 gen_stop_exception(ctx
);
3133 static void gen_lwarx(DisasContext
*ctx
)
3136 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3137 gen_set_access_type(ctx
, ACCESS_RES
);
3138 t0
= tcg_temp_local_new();
3139 gen_addr_reg_index(ctx
, t0
);
3140 gen_check_align(ctx
, t0
, 0x03);
3141 gen_qemu_ld32u(ctx
, gpr
, t0
);
3142 tcg_gen_mov_tl(cpu_reserve
, t0
);
3143 tcg_gen_st_tl(gpr
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3147 #if defined(CONFIG_USER_ONLY)
3148 static void gen_conditional_store (DisasContext
*ctx
, TCGv EA
,
3151 TCGv t0
= tcg_temp_new();
3152 uint32_t save_exception
= ctx
->exception
;
3154 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3155 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3156 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3158 gen_update_nip(ctx
, ctx
->nip
-4);
3159 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3160 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3161 ctx
->exception
= save_exception
;
3166 static void gen_stwcx_(DisasContext
*ctx
)
3169 gen_set_access_type(ctx
, ACCESS_RES
);
3170 t0
= tcg_temp_local_new();
3171 gen_addr_reg_index(ctx
, t0
);
3172 gen_check_align(ctx
, t0
, 0x03);
3173 #if defined(CONFIG_USER_ONLY)
3174 gen_conditional_store(ctx
, t0
, rS(ctx
->opcode
), 4);
3179 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3180 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3181 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3182 l1
= gen_new_label();
3183 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3184 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3185 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3187 tcg_gen_movi_tl(cpu_reserve
, -1);
3193 #if defined(TARGET_PPC64)
3195 static void gen_ldarx(DisasContext
*ctx
)
3198 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3199 gen_set_access_type(ctx
, ACCESS_RES
);
3200 t0
= tcg_temp_local_new();
3201 gen_addr_reg_index(ctx
, t0
);
3202 gen_check_align(ctx
, t0
, 0x07);
3203 gen_qemu_ld64(ctx
, gpr
, t0
);
3204 tcg_gen_mov_tl(cpu_reserve
, t0
);
3205 tcg_gen_st_tl(gpr
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3210 static void gen_stdcx_(DisasContext
*ctx
)
3213 gen_set_access_type(ctx
, ACCESS_RES
);
3214 t0
= tcg_temp_local_new();
3215 gen_addr_reg_index(ctx
, t0
);
3216 gen_check_align(ctx
, t0
, 0x07);
3217 #if defined(CONFIG_USER_ONLY)
3218 gen_conditional_store(ctx
, t0
, rS(ctx
->opcode
), 8);
3222 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3223 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3224 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3225 l1
= gen_new_label();
3226 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3227 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3228 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3230 tcg_gen_movi_tl(cpu_reserve
, -1);
3235 #endif /* defined(TARGET_PPC64) */
3238 static void gen_sync(DisasContext
*ctx
)
3243 static void gen_wait(DisasContext
*ctx
)
3245 TCGv_i32 t0
= tcg_temp_new_i32();
3246 tcg_gen_st_i32(t0
, cpu_env
, offsetof(CPUPPCState
, halted
));
3247 tcg_temp_free_i32(t0
);
3248 /* Stop translation, as the CPU is supposed to sleep from now */
3249 gen_exception_err(ctx
, EXCP_HLT
, 1);
3252 /*** Floating-point load ***/
3253 #define GEN_LDF(name, ldop, opc, type) \
3254 static void glue(gen_, name)(DisasContext *ctx) \
3257 if (unlikely(!ctx->fpu_enabled)) { \
3258 gen_exception(ctx, POWERPC_EXCP_FPU); \
3261 gen_set_access_type(ctx, ACCESS_FLOAT); \
3262 EA = tcg_temp_new(); \
3263 gen_addr_imm_index(ctx, EA, 0); \
3264 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3265 tcg_temp_free(EA); \
3268 #define GEN_LDUF(name, ldop, opc, type) \
3269 static void glue(gen_, name##u)(DisasContext *ctx) \
3272 if (unlikely(!ctx->fpu_enabled)) { \
3273 gen_exception(ctx, POWERPC_EXCP_FPU); \
3276 if (unlikely(rA(ctx->opcode) == 0)) { \
3277 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3280 gen_set_access_type(ctx, ACCESS_FLOAT); \
3281 EA = tcg_temp_new(); \
3282 gen_addr_imm_index(ctx, EA, 0); \
3283 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3284 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3285 tcg_temp_free(EA); \
3288 #define GEN_LDUXF(name, ldop, opc, type) \
3289 static void glue(gen_, name##ux)(DisasContext *ctx) \
3292 if (unlikely(!ctx->fpu_enabled)) { \
3293 gen_exception(ctx, POWERPC_EXCP_FPU); \
3296 if (unlikely(rA(ctx->opcode) == 0)) { \
3297 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3300 gen_set_access_type(ctx, ACCESS_FLOAT); \
3301 EA = tcg_temp_new(); \
3302 gen_addr_reg_index(ctx, EA); \
3303 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3304 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3305 tcg_temp_free(EA); \
3308 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3309 static void glue(gen_, name##x)(DisasContext *ctx) \
3312 if (unlikely(!ctx->fpu_enabled)) { \
3313 gen_exception(ctx, POWERPC_EXCP_FPU); \
3316 gen_set_access_type(ctx, ACCESS_FLOAT); \
3317 EA = tcg_temp_new(); \
3318 gen_addr_reg_index(ctx, EA); \
3319 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3320 tcg_temp_free(EA); \
3323 #define GEN_LDFS(name, ldop, op, type) \
3324 GEN_LDF(name, ldop, op | 0x20, type); \
3325 GEN_LDUF(name, ldop, op | 0x21, type); \
3326 GEN_LDUXF(name, ldop, op | 0x01, type); \
3327 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3329 static inline void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3331 TCGv t0
= tcg_temp_new();
3332 TCGv_i32 t1
= tcg_temp_new_i32();
3333 gen_qemu_ld32u(ctx
, t0
, arg2
);
3334 tcg_gen_trunc_tl_i32(t1
, t0
);
3336 gen_helper_float32_to_float64(arg1
, cpu_env
, t1
);
3337 tcg_temp_free_i32(t1
);
3340 /* lfd lfdu lfdux lfdx */
3341 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3342 /* lfs lfsu lfsux lfsx */
3343 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3345 /*** Floating-point store ***/
3346 #define GEN_STF(name, stop, opc, type) \
3347 static void glue(gen_, name)(DisasContext *ctx) \
3350 if (unlikely(!ctx->fpu_enabled)) { \
3351 gen_exception(ctx, POWERPC_EXCP_FPU); \
3354 gen_set_access_type(ctx, ACCESS_FLOAT); \
3355 EA = tcg_temp_new(); \
3356 gen_addr_imm_index(ctx, EA, 0); \
3357 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3358 tcg_temp_free(EA); \
3361 #define GEN_STUF(name, stop, opc, type) \
3362 static void glue(gen_, name##u)(DisasContext *ctx) \
3365 if (unlikely(!ctx->fpu_enabled)) { \
3366 gen_exception(ctx, POWERPC_EXCP_FPU); \
3369 if (unlikely(rA(ctx->opcode) == 0)) { \
3370 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3373 gen_set_access_type(ctx, ACCESS_FLOAT); \
3374 EA = tcg_temp_new(); \
3375 gen_addr_imm_index(ctx, EA, 0); \
3376 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3377 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3378 tcg_temp_free(EA); \
3381 #define GEN_STUXF(name, stop, opc, type) \
3382 static void glue(gen_, name##ux)(DisasContext *ctx) \
3385 if (unlikely(!ctx->fpu_enabled)) { \
3386 gen_exception(ctx, POWERPC_EXCP_FPU); \
3389 if (unlikely(rA(ctx->opcode) == 0)) { \
3390 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3393 gen_set_access_type(ctx, ACCESS_FLOAT); \
3394 EA = tcg_temp_new(); \
3395 gen_addr_reg_index(ctx, EA); \
3396 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3397 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3398 tcg_temp_free(EA); \
3401 #define GEN_STXF(name, stop, opc2, opc3, type) \
3402 static void glue(gen_, name##x)(DisasContext *ctx) \
3405 if (unlikely(!ctx->fpu_enabled)) { \
3406 gen_exception(ctx, POWERPC_EXCP_FPU); \
3409 gen_set_access_type(ctx, ACCESS_FLOAT); \
3410 EA = tcg_temp_new(); \
3411 gen_addr_reg_index(ctx, EA); \
3412 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3413 tcg_temp_free(EA); \
3416 #define GEN_STFS(name, stop, op, type) \
3417 GEN_STF(name, stop, op | 0x20, type); \
3418 GEN_STUF(name, stop, op | 0x21, type); \
3419 GEN_STUXF(name, stop, op | 0x01, type); \
3420 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3422 static inline void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3424 TCGv_i32 t0
= tcg_temp_new_i32();
3425 TCGv t1
= tcg_temp_new();
3426 gen_helper_float64_to_float32(t0
, cpu_env
, arg1
);
3427 tcg_gen_extu_i32_tl(t1
, t0
);
3428 tcg_temp_free_i32(t0
);
3429 gen_qemu_st32(ctx
, t1
, arg2
);
3433 /* stfd stfdu stfdux stfdx */
3434 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3435 /* stfs stfsu stfsux stfsx */
3436 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3439 static inline void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3441 TCGv t0
= tcg_temp_new();
3442 tcg_gen_trunc_i64_tl(t0
, arg1
),
3443 gen_qemu_st32(ctx
, t0
, arg2
);
3447 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3449 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3451 #if defined(TARGET_PPC64)
3453 tcg_gen_movi_tl(cpu_cfar
, nip
);
3458 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3460 TranslationBlock
*tb
;
3462 #if defined(TARGET_PPC64)
3464 dest
= (uint32_t) dest
;
3466 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
3467 likely(!ctx
->singlestep_enabled
)) {
3469 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3470 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
3472 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3473 if (unlikely(ctx
->singlestep_enabled
)) {
3474 if ((ctx
->singlestep_enabled
&
3475 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3476 ctx
->exception
== POWERPC_EXCP_BRANCH
) {
3477 target_ulong tmp
= ctx
->nip
;
3479 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3482 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3483 gen_debug_exception(ctx
);
3490 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3492 #if defined(TARGET_PPC64)
3493 if (ctx
->sf_mode
== 0)
3494 tcg_gen_movi_tl(cpu_lr
, (uint32_t)nip
);
3497 tcg_gen_movi_tl(cpu_lr
, nip
);
3501 static void gen_b(DisasContext
*ctx
)
3503 target_ulong li
, target
;
3505 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3506 /* sign extend LI */
3507 #if defined(TARGET_PPC64)
3509 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
3512 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
3513 if (likely(AA(ctx
->opcode
) == 0))
3514 target
= ctx
->nip
+ li
- 4;
3517 if (LK(ctx
->opcode
))
3518 gen_setlr(ctx
, ctx
->nip
);
3519 gen_update_cfar(ctx
, ctx
->nip
);
3520 gen_goto_tb(ctx
, 0, target
);
3527 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3529 uint32_t bo
= BO(ctx
->opcode
);
3533 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3534 if (type
== BCOND_LR
|| type
== BCOND_CTR
) {
3535 target
= tcg_temp_local_new();
3536 if (type
== BCOND_CTR
)
3537 tcg_gen_mov_tl(target
, cpu_ctr
);
3539 tcg_gen_mov_tl(target
, cpu_lr
);
3541 TCGV_UNUSED(target
);
3543 if (LK(ctx
->opcode
))
3544 gen_setlr(ctx
, ctx
->nip
);
3545 l1
= gen_new_label();
3546 if ((bo
& 0x4) == 0) {
3547 /* Decrement and test CTR */
3548 TCGv temp
= tcg_temp_new();
3549 if (unlikely(type
== BCOND_CTR
)) {
3550 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3553 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3554 #if defined(TARGET_PPC64)
3556 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3559 tcg_gen_mov_tl(temp
, cpu_ctr
);
3561 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3563 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3565 tcg_temp_free(temp
);
3567 if ((bo
& 0x10) == 0) {
3569 uint32_t bi
= BI(ctx
->opcode
);
3570 uint32_t mask
= 1 << (3 - (bi
& 0x03));
3571 TCGv_i32 temp
= tcg_temp_new_i32();
3574 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3575 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3577 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3578 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3580 tcg_temp_free_i32(temp
);
3582 gen_update_cfar(ctx
, ctx
->nip
);
3583 if (type
== BCOND_IM
) {
3584 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3585 if (likely(AA(ctx
->opcode
) == 0)) {
3586 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3588 gen_goto_tb(ctx
, 0, li
);
3591 gen_goto_tb(ctx
, 1, ctx
->nip
);
3593 #if defined(TARGET_PPC64)
3594 if (!(ctx
->sf_mode
))
3595 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3598 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3601 #if defined(TARGET_PPC64)
3602 if (!(ctx
->sf_mode
))
3603 tcg_gen_movi_tl(cpu_nip
, (uint32_t)ctx
->nip
);
3606 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
3611 static void gen_bc(DisasContext
*ctx
)
3613 gen_bcond(ctx
, BCOND_IM
);
3616 static void gen_bcctr(DisasContext
*ctx
)
3618 gen_bcond(ctx
, BCOND_CTR
);
3621 static void gen_bclr(DisasContext
*ctx
)
3623 gen_bcond(ctx
, BCOND_LR
);
3626 /*** Condition register logical ***/
3627 #define GEN_CRLOGIC(name, tcg_op, opc) \
3628 static void glue(gen_, name)(DisasContext *ctx) \
3633 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3634 t0 = tcg_temp_new_i32(); \
3636 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3638 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3640 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3641 t1 = tcg_temp_new_i32(); \
3642 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3644 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3646 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3648 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3649 tcg_op(t0, t0, t1); \
3650 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3651 tcg_gen_andi_i32(t0, t0, bitmask); \
3652 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3653 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3654 tcg_temp_free_i32(t0); \
3655 tcg_temp_free_i32(t1); \
3659 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3661 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3663 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3665 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3667 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3669 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3671 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3673 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3676 static void gen_mcrf(DisasContext
*ctx
)
3678 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3681 /*** System linkage ***/
3683 /* rfi (mem_idx only) */
3684 static void gen_rfi(DisasContext
*ctx
)
3686 #if defined(CONFIG_USER_ONLY)
3687 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3689 /* Restore CPU state */
3690 if (unlikely(!ctx
->mem_idx
)) {
3691 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3694 gen_update_cfar(ctx
, ctx
->nip
);
3695 gen_helper_rfi(cpu_env
);
3696 gen_sync_exception(ctx
);
3700 #if defined(TARGET_PPC64)
3701 static void gen_rfid(DisasContext
*ctx
)
3703 #if defined(CONFIG_USER_ONLY)
3704 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3706 /* Restore CPU state */
3707 if (unlikely(!ctx
->mem_idx
)) {
3708 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3711 gen_update_cfar(ctx
, ctx
->nip
);
3712 gen_helper_rfid(cpu_env
);
3713 gen_sync_exception(ctx
);
3717 static void gen_hrfid(DisasContext
*ctx
)
3719 #if defined(CONFIG_USER_ONLY)
3720 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3722 /* Restore CPU state */
3723 if (unlikely(ctx
->mem_idx
<= 1)) {
3724 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3727 gen_helper_hrfid(cpu_env
);
3728 gen_sync_exception(ctx
);
3734 #if defined(CONFIG_USER_ONLY)
3735 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3737 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3739 static void gen_sc(DisasContext
*ctx
)
3743 lev
= (ctx
->opcode
>> 5) & 0x7F;
3744 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3750 static void gen_tw(DisasContext
*ctx
)
3752 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3753 /* Update the nip since this might generate a trap exception */
3754 gen_update_nip(ctx
, ctx
->nip
);
3755 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3757 tcg_temp_free_i32(t0
);
3761 static void gen_twi(DisasContext
*ctx
)
3763 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3764 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3765 /* Update the nip since this might generate a trap exception */
3766 gen_update_nip(ctx
, ctx
->nip
);
3767 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3769 tcg_temp_free_i32(t1
);
3772 #if defined(TARGET_PPC64)
3774 static void gen_td(DisasContext
*ctx
)
3776 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3777 /* Update the nip since this might generate a trap exception */
3778 gen_update_nip(ctx
, ctx
->nip
);
3779 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3781 tcg_temp_free_i32(t0
);
3785 static void gen_tdi(DisasContext
*ctx
)
3787 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3788 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3789 /* Update the nip since this might generate a trap exception */
3790 gen_update_nip(ctx
, ctx
->nip
);
3791 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3793 tcg_temp_free_i32(t1
);
3797 /*** Processor control ***/
3800 static void gen_mcrxr(DisasContext
*ctx
)
3802 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_xer
);
3803 tcg_gen_shri_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], XER_CA
);
3804 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_SO
| 1 << XER_OV
| 1 << XER_CA
));
3808 static void gen_mfcr(DisasContext
*ctx
)
3812 if (likely(ctx
->opcode
& 0x00100000)) {
3813 crm
= CRM(ctx
->opcode
);
3814 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3816 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3817 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3818 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3821 TCGv_i32 t0
= tcg_temp_new_i32();
3822 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3823 tcg_gen_shli_i32(t0
, t0
, 4);
3824 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3825 tcg_gen_shli_i32(t0
, t0
, 4);
3826 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3827 tcg_gen_shli_i32(t0
, t0
, 4);
3828 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3829 tcg_gen_shli_i32(t0
, t0
, 4);
3830 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3831 tcg_gen_shli_i32(t0
, t0
, 4);
3832 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3833 tcg_gen_shli_i32(t0
, t0
, 4);
3834 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3835 tcg_gen_shli_i32(t0
, t0
, 4);
3836 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3837 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3838 tcg_temp_free_i32(t0
);
3843 static void gen_mfmsr(DisasContext
*ctx
)
3845 #if defined(CONFIG_USER_ONLY)
3846 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3848 if (unlikely(!ctx
->mem_idx
)) {
3849 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3852 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3856 static void spr_noaccess(void *opaque
, int gprn
, int sprn
)
3859 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3860 printf("ERROR: try to access SPR %d !\n", sprn
);
3863 #define SPR_NOACCESS (&spr_noaccess)
3866 static inline void gen_op_mfspr(DisasContext
*ctx
)
3868 void (*read_cb
)(void *opaque
, int gprn
, int sprn
);
3869 uint32_t sprn
= SPR(ctx
->opcode
);
3871 #if !defined(CONFIG_USER_ONLY)
3872 if (ctx
->mem_idx
== 2)
3873 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3874 else if (ctx
->mem_idx
)
3875 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3878 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3879 if (likely(read_cb
!= NULL
)) {
3880 if (likely(read_cb
!= SPR_NOACCESS
)) {
3881 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3883 /* Privilege exception */
3884 /* This is a hack to avoid warnings when running Linux:
3885 * this OS breaks the PowerPC virtualisation model,
3886 * allowing userland application to read the PVR
3888 if (sprn
!= SPR_PVR
) {
3889 qemu_log("Trying to read privileged spr %d %03x at "
3890 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3891 printf("Trying to read privileged spr %d %03x at "
3892 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3894 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3898 qemu_log("Trying to read invalid spr %d %03x at "
3899 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3900 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx
"\n",
3901 sprn
, sprn
, ctx
->nip
);
3902 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3906 static void gen_mfspr(DisasContext
*ctx
)
3912 static void gen_mftb(DisasContext
*ctx
)
3918 static void gen_mtcrf(DisasContext
*ctx
)
3922 crm
= CRM(ctx
->opcode
);
3923 if (likely((ctx
->opcode
& 0x00100000))) {
3924 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
3925 TCGv_i32 temp
= tcg_temp_new_i32();
3927 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3928 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
3929 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
3930 tcg_temp_free_i32(temp
);
3933 TCGv_i32 temp
= tcg_temp_new_i32();
3934 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3935 for (crn
= 0 ; crn
< 8 ; crn
++) {
3936 if (crm
& (1 << crn
)) {
3937 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
3938 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
3941 tcg_temp_free_i32(temp
);
3946 #if defined(TARGET_PPC64)
3947 static void gen_mtmsrd(DisasContext
*ctx
)
3949 #if defined(CONFIG_USER_ONLY)
3950 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3952 if (unlikely(!ctx
->mem_idx
)) {
3953 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3956 if (ctx
->opcode
& 0x00010000) {
3957 /* Special form that does not need any synchronisation */
3958 TCGv t0
= tcg_temp_new();
3959 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3960 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3961 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3964 /* XXX: we need to update nip before the store
3965 * if we enter power saving mode, we will exit the loop
3966 * directly from ppc_store_msr
3968 gen_update_nip(ctx
, ctx
->nip
);
3969 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
3970 /* Must stop the translation as machine state (may have) changed */
3971 /* Note that mtmsr is not always defined as context-synchronizing */
3972 gen_stop_exception(ctx
);
3978 static void gen_mtmsr(DisasContext
*ctx
)
3980 #if defined(CONFIG_USER_ONLY)
3981 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3983 if (unlikely(!ctx
->mem_idx
)) {
3984 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3987 if (ctx
->opcode
& 0x00010000) {
3988 /* Special form that does not need any synchronisation */
3989 TCGv t0
= tcg_temp_new();
3990 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3991 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3992 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3995 TCGv msr
= tcg_temp_new();
3997 /* XXX: we need to update nip before the store
3998 * if we enter power saving mode, we will exit the loop
3999 * directly from ppc_store_msr
4001 gen_update_nip(ctx
, ctx
->nip
);
4002 #if defined(TARGET_PPC64)
4003 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4005 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4007 gen_helper_store_msr(cpu_env
, msr
);
4008 /* Must stop the translation as machine state (may have) changed */
4009 /* Note that mtmsr is not always defined as context-synchronizing */
4010 gen_stop_exception(ctx
);
4016 static void gen_mtspr(DisasContext
*ctx
)
4018 void (*write_cb
)(void *opaque
, int sprn
, int gprn
);
4019 uint32_t sprn
= SPR(ctx
->opcode
);
4021 #if !defined(CONFIG_USER_ONLY)
4022 if (ctx
->mem_idx
== 2)
4023 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4024 else if (ctx
->mem_idx
)
4025 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4028 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4029 if (likely(write_cb
!= NULL
)) {
4030 if (likely(write_cb
!= SPR_NOACCESS
)) {
4031 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4033 /* Privilege exception */
4034 qemu_log("Trying to write privileged spr %d %03x at "
4035 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
4036 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4037 "\n", sprn
, sprn
, ctx
->nip
);
4038 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4042 qemu_log("Trying to write invalid spr %d %03x at "
4043 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
4044 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx
"\n",
4045 sprn
, sprn
, ctx
->nip
);
4046 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4050 /*** Cache management ***/
4053 static void gen_dcbf(DisasContext
*ctx
)
4055 /* XXX: specification says this is treated as a load by the MMU */
4057 gen_set_access_type(ctx
, ACCESS_CACHE
);
4058 t0
= tcg_temp_new();
4059 gen_addr_reg_index(ctx
, t0
);
4060 gen_qemu_ld8u(ctx
, t0
, t0
);
4064 /* dcbi (Supervisor only) */
4065 static void gen_dcbi(DisasContext
*ctx
)
4067 #if defined(CONFIG_USER_ONLY)
4068 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4071 if (unlikely(!ctx
->mem_idx
)) {
4072 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4075 EA
= tcg_temp_new();
4076 gen_set_access_type(ctx
, ACCESS_CACHE
);
4077 gen_addr_reg_index(ctx
, EA
);
4078 val
= tcg_temp_new();
4079 /* XXX: specification says this should be treated as a store by the MMU */
4080 gen_qemu_ld8u(ctx
, val
, EA
);
4081 gen_qemu_st8(ctx
, val
, EA
);
4088 static void gen_dcbst(DisasContext
*ctx
)
4090 /* XXX: specification say this is treated as a load by the MMU */
4092 gen_set_access_type(ctx
, ACCESS_CACHE
);
4093 t0
= tcg_temp_new();
4094 gen_addr_reg_index(ctx
, t0
);
4095 gen_qemu_ld8u(ctx
, t0
, t0
);
4100 static void gen_dcbt(DisasContext
*ctx
)
4102 /* interpreted as no-op */
4103 /* XXX: specification say this is treated as a load by the MMU
4104 * but does not generate any exception
4109 static void gen_dcbtst(DisasContext
*ctx
)
4111 /* interpreted as no-op */
4112 /* XXX: specification say this is treated as a load by the MMU
4113 * but does not generate any exception
4118 static void gen_dcbz(DisasContext
*ctx
)
4121 gen_set_access_type(ctx
, ACCESS_CACHE
);
4122 /* NIP cannot be restored if the memory exception comes from an helper */
4123 gen_update_nip(ctx
, ctx
->nip
- 4);
4124 t0
= tcg_temp_new();
4125 gen_addr_reg_index(ctx
, t0
);
4126 gen_helper_dcbz(cpu_env
, t0
);
4130 static void gen_dcbz_970(DisasContext
*ctx
)
4133 gen_set_access_type(ctx
, ACCESS_CACHE
);
4134 /* NIP cannot be restored if the memory exception comes from an helper */
4135 gen_update_nip(ctx
, ctx
->nip
- 4);
4136 t0
= tcg_temp_new();
4137 gen_addr_reg_index(ctx
, t0
);
4138 if (ctx
->opcode
& 0x00200000)
4139 gen_helper_dcbz(cpu_env
, t0
);
4141 gen_helper_dcbz_970(cpu_env
, t0
);
4146 static void gen_dst(DisasContext
*ctx
)
4148 if (rA(ctx
->opcode
) == 0) {
4149 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4151 /* interpreted as no-op */
4156 static void gen_dstst(DisasContext
*ctx
)
4158 if (rA(ctx
->opcode
) == 0) {
4159 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4161 /* interpreted as no-op */
4167 static void gen_dss(DisasContext
*ctx
)
4169 /* interpreted as no-op */
4173 static void gen_icbi(DisasContext
*ctx
)
4176 gen_set_access_type(ctx
, ACCESS_CACHE
);
4177 /* NIP cannot be restored if the memory exception comes from an helper */
4178 gen_update_nip(ctx
, ctx
->nip
- 4);
4179 t0
= tcg_temp_new();
4180 gen_addr_reg_index(ctx
, t0
);
4181 gen_helper_icbi(cpu_env
, t0
);
4187 static void gen_dcba(DisasContext
*ctx
)
4189 /* interpreted as no-op */
4190 /* XXX: specification say this is treated as a store by the MMU
4191 * but does not generate any exception
4195 /*** Segment register manipulation ***/
4196 /* Supervisor only: */
4199 static void gen_mfsr(DisasContext
*ctx
)
4201 #if defined(CONFIG_USER_ONLY)
4202 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4205 if (unlikely(!ctx
->mem_idx
)) {
4206 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4209 t0
= tcg_const_tl(SR(ctx
->opcode
));
4210 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4216 static void gen_mfsrin(DisasContext
*ctx
)
4218 #if defined(CONFIG_USER_ONLY)
4219 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4222 if (unlikely(!ctx
->mem_idx
)) {
4223 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4226 t0
= tcg_temp_new();
4227 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4228 tcg_gen_andi_tl(t0
, t0
, 0xF);
4229 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4235 static void gen_mtsr(DisasContext
*ctx
)
4237 #if defined(CONFIG_USER_ONLY)
4238 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4241 if (unlikely(!ctx
->mem_idx
)) {
4242 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4245 t0
= tcg_const_tl(SR(ctx
->opcode
));
4246 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4252 static void gen_mtsrin(DisasContext
*ctx
)
4254 #if defined(CONFIG_USER_ONLY)
4255 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4258 if (unlikely(!ctx
->mem_idx
)) {
4259 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4262 t0
= tcg_temp_new();
4263 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4264 tcg_gen_andi_tl(t0
, t0
, 0xF);
4265 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4270 #if defined(TARGET_PPC64)
4271 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4274 static void gen_mfsr_64b(DisasContext
*ctx
)
4276 #if defined(CONFIG_USER_ONLY)
4277 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4280 if (unlikely(!ctx
->mem_idx
)) {
4281 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4284 t0
= tcg_const_tl(SR(ctx
->opcode
));
4285 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4291 static void gen_mfsrin_64b(DisasContext
*ctx
)
4293 #if defined(CONFIG_USER_ONLY)
4294 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4297 if (unlikely(!ctx
->mem_idx
)) {
4298 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4301 t0
= tcg_temp_new();
4302 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4303 tcg_gen_andi_tl(t0
, t0
, 0xF);
4304 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4310 static void gen_mtsr_64b(DisasContext
*ctx
)
4312 #if defined(CONFIG_USER_ONLY)
4313 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4316 if (unlikely(!ctx
->mem_idx
)) {
4317 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4320 t0
= tcg_const_tl(SR(ctx
->opcode
));
4321 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4327 static void gen_mtsrin_64b(DisasContext
*ctx
)
4329 #if defined(CONFIG_USER_ONLY)
4330 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4333 if (unlikely(!ctx
->mem_idx
)) {
4334 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4337 t0
= tcg_temp_new();
4338 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4339 tcg_gen_andi_tl(t0
, t0
, 0xF);
4340 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4346 static void gen_slbmte(DisasContext
*ctx
)
4348 #if defined(CONFIG_USER_ONLY)
4349 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4351 if (unlikely(!ctx
->mem_idx
)) {
4352 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4355 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4356 cpu_gpr
[rS(ctx
->opcode
)]);
4360 static void gen_slbmfee(DisasContext
*ctx
)
4362 #if defined(CONFIG_USER_ONLY)
4363 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4365 if (unlikely(!ctx
->mem_idx
)) {
4366 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4369 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4370 cpu_gpr
[rB(ctx
->opcode
)]);
4374 static void gen_slbmfev(DisasContext
*ctx
)
4376 #if defined(CONFIG_USER_ONLY)
4377 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4379 if (unlikely(!ctx
->mem_idx
)) {
4380 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4383 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4384 cpu_gpr
[rB(ctx
->opcode
)]);
4387 #endif /* defined(TARGET_PPC64) */
4389 /*** Lookaside buffer management ***/
4390 /* Optional & mem_idx only: */
4393 static void gen_tlbia(DisasContext
*ctx
)
4395 #if defined(CONFIG_USER_ONLY)
4396 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4398 if (unlikely(!ctx
->mem_idx
)) {
4399 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4402 gen_helper_tlbia(cpu_env
);
4407 static void gen_tlbiel(DisasContext
*ctx
)
4409 #if defined(CONFIG_USER_ONLY)
4410 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4412 if (unlikely(!ctx
->mem_idx
)) {
4413 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4416 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4421 static void gen_tlbie(DisasContext
*ctx
)
4423 #if defined(CONFIG_USER_ONLY)
4424 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4426 if (unlikely(!ctx
->mem_idx
)) {
4427 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4430 #if defined(TARGET_PPC64)
4431 if (!ctx
->sf_mode
) {
4432 TCGv t0
= tcg_temp_new();
4433 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4434 gen_helper_tlbie(cpu_env
, t0
);
4438 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4443 static void gen_tlbsync(DisasContext
*ctx
)
4445 #if defined(CONFIG_USER_ONLY)
4446 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4448 if (unlikely(!ctx
->mem_idx
)) {
4449 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4452 /* This has no effect: it should ensure that all previous
4453 * tlbie have completed
4455 gen_stop_exception(ctx
);
4459 #if defined(TARGET_PPC64)
4461 static void gen_slbia(DisasContext
*ctx
)
4463 #if defined(CONFIG_USER_ONLY)
4464 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4466 if (unlikely(!ctx
->mem_idx
)) {
4467 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4470 gen_helper_slbia(cpu_env
);
4475 static void gen_slbie(DisasContext
*ctx
)
4477 #if defined(CONFIG_USER_ONLY)
4478 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4480 if (unlikely(!ctx
->mem_idx
)) {
4481 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4484 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4489 /*** External control ***/
4493 static void gen_eciwx(DisasContext
*ctx
)
4496 /* Should check EAR[E] ! */
4497 gen_set_access_type(ctx
, ACCESS_EXT
);
4498 t0
= tcg_temp_new();
4499 gen_addr_reg_index(ctx
, t0
);
4500 gen_check_align(ctx
, t0
, 0x03);
4501 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4506 static void gen_ecowx(DisasContext
*ctx
)
4509 /* Should check EAR[E] ! */
4510 gen_set_access_type(ctx
, ACCESS_EXT
);
4511 t0
= tcg_temp_new();
4512 gen_addr_reg_index(ctx
, t0
);
4513 gen_check_align(ctx
, t0
, 0x03);
4514 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4518 /* PowerPC 601 specific instructions */
4521 static void gen_abs(DisasContext
*ctx
)
4523 int l1
= gen_new_label();
4524 int l2
= gen_new_label();
4525 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4526 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4529 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4531 if (unlikely(Rc(ctx
->opcode
) != 0))
4532 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4536 static void gen_abso(DisasContext
*ctx
)
4538 int l1
= gen_new_label();
4539 int l2
= gen_new_label();
4540 int l3
= gen_new_label();
4541 /* Start with XER OV disabled, the most likely case */
4542 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4543 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4544 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4545 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4548 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4551 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4553 if (unlikely(Rc(ctx
->opcode
) != 0))
4554 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4558 static void gen_clcs(DisasContext
*ctx
)
4560 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4561 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4562 tcg_temp_free_i32(t0
);
4563 /* Rc=1 sets CR0 to an undefined state */
4567 static void gen_div(DisasContext
*ctx
)
4569 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4570 cpu_gpr
[rB(ctx
->opcode
)]);
4571 if (unlikely(Rc(ctx
->opcode
) != 0))
4572 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4576 static void gen_divo(DisasContext
*ctx
)
4578 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4579 cpu_gpr
[rB(ctx
->opcode
)]);
4580 if (unlikely(Rc(ctx
->opcode
) != 0))
4581 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4585 static void gen_divs(DisasContext
*ctx
)
4587 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4588 cpu_gpr
[rB(ctx
->opcode
)]);
4589 if (unlikely(Rc(ctx
->opcode
) != 0))
4590 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4593 /* divso - divso. */
4594 static void gen_divso(DisasContext
*ctx
)
4596 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
4597 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4598 if (unlikely(Rc(ctx
->opcode
) != 0))
4599 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4603 static void gen_doz(DisasContext
*ctx
)
4605 int l1
= gen_new_label();
4606 int l2
= gen_new_label();
4607 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4608 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4611 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4613 if (unlikely(Rc(ctx
->opcode
) != 0))
4614 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4618 static void gen_dozo(DisasContext
*ctx
)
4620 int l1
= gen_new_label();
4621 int l2
= gen_new_label();
4622 TCGv t0
= tcg_temp_new();
4623 TCGv t1
= tcg_temp_new();
4624 TCGv t2
= tcg_temp_new();
4625 /* Start with XER OV disabled, the most likely case */
4626 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4627 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4628 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4629 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4630 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4631 tcg_gen_andc_tl(t1
, t1
, t2
);
4632 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4633 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4634 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4637 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4642 if (unlikely(Rc(ctx
->opcode
) != 0))
4643 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4647 static void gen_dozi(DisasContext
*ctx
)
4649 target_long simm
= SIMM(ctx
->opcode
);
4650 int l1
= gen_new_label();
4651 int l2
= gen_new_label();
4652 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4653 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4656 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4658 if (unlikely(Rc(ctx
->opcode
) != 0))
4659 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4662 /* lscbx - lscbx. */
4663 static void gen_lscbx(DisasContext
*ctx
)
4665 TCGv t0
= tcg_temp_new();
4666 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4667 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4668 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4670 gen_addr_reg_index(ctx
, t0
);
4671 /* NIP cannot be restored if the memory exception comes from an helper */
4672 gen_update_nip(ctx
, ctx
->nip
- 4);
4673 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
4674 tcg_temp_free_i32(t1
);
4675 tcg_temp_free_i32(t2
);
4676 tcg_temp_free_i32(t3
);
4677 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4678 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4679 if (unlikely(Rc(ctx
->opcode
) != 0))
4680 gen_set_Rc0(ctx
, t0
);
4684 /* maskg - maskg. */
4685 static void gen_maskg(DisasContext
*ctx
)
4687 int l1
= gen_new_label();
4688 TCGv t0
= tcg_temp_new();
4689 TCGv t1
= tcg_temp_new();
4690 TCGv t2
= tcg_temp_new();
4691 TCGv t3
= tcg_temp_new();
4692 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4693 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4694 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4695 tcg_gen_addi_tl(t2
, t0
, 1);
4696 tcg_gen_shr_tl(t2
, t3
, t2
);
4697 tcg_gen_shr_tl(t3
, t3
, t1
);
4698 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4699 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4700 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4706 if (unlikely(Rc(ctx
->opcode
) != 0))
4707 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4710 /* maskir - maskir. */
4711 static void gen_maskir(DisasContext
*ctx
)
4713 TCGv t0
= tcg_temp_new();
4714 TCGv t1
= tcg_temp_new();
4715 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4716 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4717 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4720 if (unlikely(Rc(ctx
->opcode
) != 0))
4721 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4725 static void gen_mul(DisasContext
*ctx
)
4727 TCGv_i64 t0
= tcg_temp_new_i64();
4728 TCGv_i64 t1
= tcg_temp_new_i64();
4729 TCGv t2
= tcg_temp_new();
4730 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4731 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4732 tcg_gen_mul_i64(t0
, t0
, t1
);
4733 tcg_gen_trunc_i64_tl(t2
, t0
);
4734 gen_store_spr(SPR_MQ
, t2
);
4735 tcg_gen_shri_i64(t1
, t0
, 32);
4736 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4737 tcg_temp_free_i64(t0
);
4738 tcg_temp_free_i64(t1
);
4740 if (unlikely(Rc(ctx
->opcode
) != 0))
4741 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4745 static void gen_mulo(DisasContext
*ctx
)
4747 int l1
= gen_new_label();
4748 TCGv_i64 t0
= tcg_temp_new_i64();
4749 TCGv_i64 t1
= tcg_temp_new_i64();
4750 TCGv t2
= tcg_temp_new();
4751 /* Start with XER OV disabled, the most likely case */
4752 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4753 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4754 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4755 tcg_gen_mul_i64(t0
, t0
, t1
);
4756 tcg_gen_trunc_i64_tl(t2
, t0
);
4757 gen_store_spr(SPR_MQ
, t2
);
4758 tcg_gen_shri_i64(t1
, t0
, 32);
4759 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4760 tcg_gen_ext32s_i64(t1
, t0
);
4761 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4762 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4764 tcg_temp_free_i64(t0
);
4765 tcg_temp_free_i64(t1
);
4767 if (unlikely(Rc(ctx
->opcode
) != 0))
4768 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4772 static void gen_nabs(DisasContext
*ctx
)
4774 int l1
= gen_new_label();
4775 int l2
= gen_new_label();
4776 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4777 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4780 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4782 if (unlikely(Rc(ctx
->opcode
) != 0))
4783 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4786 /* nabso - nabso. */
4787 static void gen_nabso(DisasContext
*ctx
)
4789 int l1
= gen_new_label();
4790 int l2
= gen_new_label();
4791 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4792 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4795 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4797 /* nabs never overflows */
4798 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4799 if (unlikely(Rc(ctx
->opcode
) != 0))
4800 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4804 static void gen_rlmi(DisasContext
*ctx
)
4806 uint32_t mb
= MB(ctx
->opcode
);
4807 uint32_t me
= ME(ctx
->opcode
);
4808 TCGv t0
= tcg_temp_new();
4809 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4810 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4811 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4812 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4813 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4815 if (unlikely(Rc(ctx
->opcode
) != 0))
4816 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4820 static void gen_rrib(DisasContext
*ctx
)
4822 TCGv t0
= tcg_temp_new();
4823 TCGv t1
= tcg_temp_new();
4824 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4825 tcg_gen_movi_tl(t1
, 0x80000000);
4826 tcg_gen_shr_tl(t1
, t1
, t0
);
4827 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4828 tcg_gen_and_tl(t0
, t0
, t1
);
4829 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4830 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4833 if (unlikely(Rc(ctx
->opcode
) != 0))
4834 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4838 static void gen_sle(DisasContext
*ctx
)
4840 TCGv t0
= tcg_temp_new();
4841 TCGv t1
= tcg_temp_new();
4842 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4843 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4844 tcg_gen_subfi_tl(t1
, 32, t1
);
4845 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4846 tcg_gen_or_tl(t1
, t0
, t1
);
4847 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4848 gen_store_spr(SPR_MQ
, t1
);
4851 if (unlikely(Rc(ctx
->opcode
) != 0))
4852 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4856 static void gen_sleq(DisasContext
*ctx
)
4858 TCGv t0
= tcg_temp_new();
4859 TCGv t1
= tcg_temp_new();
4860 TCGv t2
= tcg_temp_new();
4861 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4862 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
4863 tcg_gen_shl_tl(t2
, t2
, t0
);
4864 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4865 gen_load_spr(t1
, SPR_MQ
);
4866 gen_store_spr(SPR_MQ
, t0
);
4867 tcg_gen_and_tl(t0
, t0
, t2
);
4868 tcg_gen_andc_tl(t1
, t1
, t2
);
4869 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4873 if (unlikely(Rc(ctx
->opcode
) != 0))
4874 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4878 static void gen_sliq(DisasContext
*ctx
)
4880 int sh
= SH(ctx
->opcode
);
4881 TCGv t0
= tcg_temp_new();
4882 TCGv t1
= tcg_temp_new();
4883 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4884 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4885 tcg_gen_or_tl(t1
, t0
, t1
);
4886 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4887 gen_store_spr(SPR_MQ
, t1
);
4890 if (unlikely(Rc(ctx
->opcode
) != 0))
4891 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4894 /* slliq - slliq. */
4895 static void gen_slliq(DisasContext
*ctx
)
4897 int sh
= SH(ctx
->opcode
);
4898 TCGv t0
= tcg_temp_new();
4899 TCGv t1
= tcg_temp_new();
4900 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4901 gen_load_spr(t1
, SPR_MQ
);
4902 gen_store_spr(SPR_MQ
, t0
);
4903 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
4904 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
4905 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4908 if (unlikely(Rc(ctx
->opcode
) != 0))
4909 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4913 static void gen_sllq(DisasContext
*ctx
)
4915 int l1
= gen_new_label();
4916 int l2
= gen_new_label();
4917 TCGv t0
= tcg_temp_local_new();
4918 TCGv t1
= tcg_temp_local_new();
4919 TCGv t2
= tcg_temp_local_new();
4920 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4921 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4922 tcg_gen_shl_tl(t1
, t1
, t2
);
4923 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4924 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
4925 gen_load_spr(t0
, SPR_MQ
);
4926 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4929 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4930 gen_load_spr(t2
, SPR_MQ
);
4931 tcg_gen_andc_tl(t1
, t2
, t1
);
4932 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4937 if (unlikely(Rc(ctx
->opcode
) != 0))
4938 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4942 static void gen_slq(DisasContext
*ctx
)
4944 int l1
= gen_new_label();
4945 TCGv t0
= tcg_temp_new();
4946 TCGv t1
= tcg_temp_new();
4947 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4948 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4949 tcg_gen_subfi_tl(t1
, 32, t1
);
4950 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4951 tcg_gen_or_tl(t1
, t0
, t1
);
4952 gen_store_spr(SPR_MQ
, t1
);
4953 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4954 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4955 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4956 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
4960 if (unlikely(Rc(ctx
->opcode
) != 0))
4961 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4964 /* sraiq - sraiq. */
4965 static void gen_sraiq(DisasContext
*ctx
)
4967 int sh
= SH(ctx
->opcode
);
4968 int l1
= gen_new_label();
4969 TCGv t0
= tcg_temp_new();
4970 TCGv t1
= tcg_temp_new();
4971 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4972 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4973 tcg_gen_or_tl(t0
, t0
, t1
);
4974 gen_store_spr(SPR_MQ
, t0
);
4975 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
4976 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4977 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
4978 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
4980 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
4983 if (unlikely(Rc(ctx
->opcode
) != 0))
4984 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4988 static void gen_sraq(DisasContext
*ctx
)
4990 int l1
= gen_new_label();
4991 int l2
= gen_new_label();
4992 TCGv t0
= tcg_temp_new();
4993 TCGv t1
= tcg_temp_local_new();
4994 TCGv t2
= tcg_temp_local_new();
4995 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4996 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4997 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4998 tcg_gen_subfi_tl(t2
, 32, t2
);
4999 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5000 tcg_gen_or_tl(t0
, t0
, t2
);
5001 gen_store_spr(SPR_MQ
, t0
);
5002 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5003 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5004 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5005 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5008 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5009 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
5010 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5011 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5012 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
5016 if (unlikely(Rc(ctx
->opcode
) != 0))
5017 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5021 static void gen_sre(DisasContext
*ctx
)
5023 TCGv t0
= tcg_temp_new();
5024 TCGv t1
= tcg_temp_new();
5025 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5026 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5027 tcg_gen_subfi_tl(t1
, 32, t1
);
5028 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5029 tcg_gen_or_tl(t1
, t0
, t1
);
5030 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5031 gen_store_spr(SPR_MQ
, t1
);
5034 if (unlikely(Rc(ctx
->opcode
) != 0))
5035 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5039 static void gen_srea(DisasContext
*ctx
)
5041 TCGv t0
= tcg_temp_new();
5042 TCGv t1
= tcg_temp_new();
5043 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5044 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5045 gen_store_spr(SPR_MQ
, t0
);
5046 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5049 if (unlikely(Rc(ctx
->opcode
) != 0))
5050 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5054 static void gen_sreq(DisasContext
*ctx
)
5056 TCGv t0
= tcg_temp_new();
5057 TCGv t1
= tcg_temp_new();
5058 TCGv t2
= tcg_temp_new();
5059 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5060 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5061 tcg_gen_shr_tl(t1
, t1
, t0
);
5062 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5063 gen_load_spr(t2
, SPR_MQ
);
5064 gen_store_spr(SPR_MQ
, t0
);
5065 tcg_gen_and_tl(t0
, t0
, t1
);
5066 tcg_gen_andc_tl(t2
, t2
, t1
);
5067 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5071 if (unlikely(Rc(ctx
->opcode
) != 0))
5072 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5076 static void gen_sriq(DisasContext
*ctx
)
5078 int sh
= SH(ctx
->opcode
);
5079 TCGv t0
= tcg_temp_new();
5080 TCGv t1
= tcg_temp_new();
5081 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5082 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5083 tcg_gen_or_tl(t1
, t0
, t1
);
5084 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5085 gen_store_spr(SPR_MQ
, t1
);
5088 if (unlikely(Rc(ctx
->opcode
) != 0))
5089 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5093 static void gen_srliq(DisasContext
*ctx
)
5095 int sh
= SH(ctx
->opcode
);
5096 TCGv t0
= tcg_temp_new();
5097 TCGv t1
= tcg_temp_new();
5098 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5099 gen_load_spr(t1
, SPR_MQ
);
5100 gen_store_spr(SPR_MQ
, t0
);
5101 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5102 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5103 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5106 if (unlikely(Rc(ctx
->opcode
) != 0))
5107 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5111 static void gen_srlq(DisasContext
*ctx
)
5113 int l1
= gen_new_label();
5114 int l2
= gen_new_label();
5115 TCGv t0
= tcg_temp_local_new();
5116 TCGv t1
= tcg_temp_local_new();
5117 TCGv t2
= tcg_temp_local_new();
5118 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5119 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5120 tcg_gen_shr_tl(t2
, t1
, t2
);
5121 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5122 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5123 gen_load_spr(t0
, SPR_MQ
);
5124 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5127 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5128 tcg_gen_and_tl(t0
, t0
, t2
);
5129 gen_load_spr(t1
, SPR_MQ
);
5130 tcg_gen_andc_tl(t1
, t1
, t2
);
5131 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5136 if (unlikely(Rc(ctx
->opcode
) != 0))
5137 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5141 static void gen_srq(DisasContext
*ctx
)
5143 int l1
= gen_new_label();
5144 TCGv t0
= tcg_temp_new();
5145 TCGv t1
= tcg_temp_new();
5146 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5147 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5148 tcg_gen_subfi_tl(t1
, 32, t1
);
5149 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5150 tcg_gen_or_tl(t1
, t0
, t1
);
5151 gen_store_spr(SPR_MQ
, t1
);
5152 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5153 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5154 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5155 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5159 if (unlikely(Rc(ctx
->opcode
) != 0))
5160 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5163 /* PowerPC 602 specific instructions */
5166 static void gen_dsa(DisasContext
*ctx
)
5169 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5173 static void gen_esa(DisasContext
*ctx
)
5176 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5180 static void gen_mfrom(DisasContext
*ctx
)
5182 #if defined(CONFIG_USER_ONLY)
5183 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5185 if (unlikely(!ctx
->mem_idx
)) {
5186 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5189 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5193 /* 602 - 603 - G2 TLB management */
5196 static void gen_tlbld_6xx(DisasContext
*ctx
)
5198 #if defined(CONFIG_USER_ONLY)
5199 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5201 if (unlikely(!ctx
->mem_idx
)) {
5202 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5205 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5210 static void gen_tlbli_6xx(DisasContext
*ctx
)
5212 #if defined(CONFIG_USER_ONLY)
5213 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5215 if (unlikely(!ctx
->mem_idx
)) {
5216 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5219 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5223 /* 74xx TLB management */
5226 static void gen_tlbld_74xx(DisasContext
*ctx
)
5228 #if defined(CONFIG_USER_ONLY)
5229 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5231 if (unlikely(!ctx
->mem_idx
)) {
5232 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5235 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5240 static void gen_tlbli_74xx(DisasContext
*ctx
)
5242 #if defined(CONFIG_USER_ONLY)
5243 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5245 if (unlikely(!ctx
->mem_idx
)) {
5246 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5249 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5253 /* POWER instructions not in PowerPC 601 */
5256 static void gen_clf(DisasContext
*ctx
)
5258 /* Cache line flush: implemented as no-op */
5262 static void gen_cli(DisasContext
*ctx
)
5264 /* Cache line invalidate: privileged and treated as no-op */
5265 #if defined(CONFIG_USER_ONLY)
5266 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5268 if (unlikely(!ctx
->mem_idx
)) {
5269 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5276 static void gen_dclst(DisasContext
*ctx
)
5278 /* Data cache line store: treated as no-op */
5281 static void gen_mfsri(DisasContext
*ctx
)
5283 #if defined(CONFIG_USER_ONLY)
5284 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5286 int ra
= rA(ctx
->opcode
);
5287 int rd
= rD(ctx
->opcode
);
5289 if (unlikely(!ctx
->mem_idx
)) {
5290 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5293 t0
= tcg_temp_new();
5294 gen_addr_reg_index(ctx
, t0
);
5295 tcg_gen_shri_tl(t0
, t0
, 28);
5296 tcg_gen_andi_tl(t0
, t0
, 0xF);
5297 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5299 if (ra
!= 0 && ra
!= rd
)
5300 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5304 static void gen_rac(DisasContext
*ctx
)
5306 #if defined(CONFIG_USER_ONLY)
5307 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5310 if (unlikely(!ctx
->mem_idx
)) {
5311 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5314 t0
= tcg_temp_new();
5315 gen_addr_reg_index(ctx
, t0
);
5316 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5321 static void gen_rfsvc(DisasContext
*ctx
)
5323 #if defined(CONFIG_USER_ONLY)
5324 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5326 if (unlikely(!ctx
->mem_idx
)) {
5327 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5330 gen_helper_rfsvc(cpu_env
);
5331 gen_sync_exception(ctx
);
5335 /* svc is not implemented for now */
5337 /* POWER2 specific instructions */
5338 /* Quad manipulation (load/store two floats at a time) */
5341 static void gen_lfq(DisasContext
*ctx
)
5343 int rd
= rD(ctx
->opcode
);
5345 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5346 t0
= tcg_temp_new();
5347 gen_addr_imm_index(ctx
, t0
, 0);
5348 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5349 gen_addr_add(ctx
, t0
, t0
, 8);
5350 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5355 static void gen_lfqu(DisasContext
*ctx
)
5357 int ra
= rA(ctx
->opcode
);
5358 int rd
= rD(ctx
->opcode
);
5360 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5361 t0
= tcg_temp_new();
5362 t1
= tcg_temp_new();
5363 gen_addr_imm_index(ctx
, t0
, 0);
5364 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5365 gen_addr_add(ctx
, t1
, t0
, 8);
5366 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5368 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5374 static void gen_lfqux(DisasContext
*ctx
)
5376 int ra
= rA(ctx
->opcode
);
5377 int rd
= rD(ctx
->opcode
);
5378 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5380 t0
= tcg_temp_new();
5381 gen_addr_reg_index(ctx
, t0
);
5382 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5383 t1
= tcg_temp_new();
5384 gen_addr_add(ctx
, t1
, t0
, 8);
5385 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5388 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5393 static void gen_lfqx(DisasContext
*ctx
)
5395 int rd
= rD(ctx
->opcode
);
5397 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5398 t0
= tcg_temp_new();
5399 gen_addr_reg_index(ctx
, t0
);
5400 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5401 gen_addr_add(ctx
, t0
, t0
, 8);
5402 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5407 static void gen_stfq(DisasContext
*ctx
)
5409 int rd
= rD(ctx
->opcode
);
5411 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5412 t0
= tcg_temp_new();
5413 gen_addr_imm_index(ctx
, t0
, 0);
5414 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5415 gen_addr_add(ctx
, t0
, t0
, 8);
5416 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5421 static void gen_stfqu(DisasContext
*ctx
)
5423 int ra
= rA(ctx
->opcode
);
5424 int rd
= rD(ctx
->opcode
);
5426 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5427 t0
= tcg_temp_new();
5428 gen_addr_imm_index(ctx
, t0
, 0);
5429 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5430 t1
= tcg_temp_new();
5431 gen_addr_add(ctx
, t1
, t0
, 8);
5432 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5435 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5440 static void gen_stfqux(DisasContext
*ctx
)
5442 int ra
= rA(ctx
->opcode
);
5443 int rd
= rD(ctx
->opcode
);
5445 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5446 t0
= tcg_temp_new();
5447 gen_addr_reg_index(ctx
, t0
);
5448 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5449 t1
= tcg_temp_new();
5450 gen_addr_add(ctx
, t1
, t0
, 8);
5451 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5454 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5459 static void gen_stfqx(DisasContext
*ctx
)
5461 int rd
= rD(ctx
->opcode
);
5463 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5464 t0
= tcg_temp_new();
5465 gen_addr_reg_index(ctx
, t0
);
5466 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5467 gen_addr_add(ctx
, t0
, t0
, 8);
5468 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5472 /* BookE specific instructions */
5474 /* XXX: not implemented on 440 ? */
5475 static void gen_mfapidi(DisasContext
*ctx
)
5478 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5481 /* XXX: not implemented on 440 ? */
5482 static void gen_tlbiva(DisasContext
*ctx
)
5484 #if defined(CONFIG_USER_ONLY)
5485 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5488 if (unlikely(!ctx
->mem_idx
)) {
5489 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5492 t0
= tcg_temp_new();
5493 gen_addr_reg_index(ctx
, t0
);
5494 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5499 /* All 405 MAC instructions are translated here */
5500 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5501 int ra
, int rb
, int rt
, int Rc
)
5505 t0
= tcg_temp_local_new();
5506 t1
= tcg_temp_local_new();
5508 switch (opc3
& 0x0D) {
5510 /* macchw - macchw. - macchwo - macchwo. */
5511 /* macchws - macchws. - macchwso - macchwso. */
5512 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5513 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5514 /* mulchw - mulchw. */
5515 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5516 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5517 tcg_gen_ext16s_tl(t1
, t1
);
5520 /* macchwu - macchwu. - macchwuo - macchwuo. */
5521 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5522 /* mulchwu - mulchwu. */
5523 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5524 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5525 tcg_gen_ext16u_tl(t1
, t1
);
5528 /* machhw - machhw. - machhwo - machhwo. */
5529 /* machhws - machhws. - machhwso - machhwso. */
5530 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5531 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5532 /* mulhhw - mulhhw. */
5533 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5534 tcg_gen_ext16s_tl(t0
, t0
);
5535 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5536 tcg_gen_ext16s_tl(t1
, t1
);
5539 /* machhwu - machhwu. - machhwuo - machhwuo. */
5540 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5541 /* mulhhwu - mulhhwu. */
5542 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5543 tcg_gen_ext16u_tl(t0
, t0
);
5544 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5545 tcg_gen_ext16u_tl(t1
, t1
);
5548 /* maclhw - maclhw. - maclhwo - maclhwo. */
5549 /* maclhws - maclhws. - maclhwso - maclhwso. */
5550 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5551 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5552 /* mullhw - mullhw. */
5553 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5554 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5557 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5558 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5559 /* mullhwu - mullhwu. */
5560 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5561 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5565 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5566 tcg_gen_mul_tl(t1
, t0
, t1
);
5568 /* nmultiply-and-accumulate (0x0E) */
5569 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5571 /* multiply-and-accumulate (0x0C) */
5572 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5576 /* Check overflow and/or saturate */
5577 int l1
= gen_new_label();
5580 /* Start with XER OV disabled, the most likely case */
5581 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
5585 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5586 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5587 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5588 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5591 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5592 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5596 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5599 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5603 /* Check overflow */
5604 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
5607 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5610 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5614 if (unlikely(Rc
) != 0) {
5616 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5620 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5621 static void glue(gen_, name)(DisasContext *ctx) \
5623 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5624 rD(ctx->opcode), Rc(ctx->opcode)); \
5627 /* macchw - macchw. */
5628 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5629 /* macchwo - macchwo. */
5630 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5631 /* macchws - macchws. */
5632 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5633 /* macchwso - macchwso. */
5634 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5635 /* macchwsu - macchwsu. */
5636 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5637 /* macchwsuo - macchwsuo. */
5638 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5639 /* macchwu - macchwu. */
5640 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5641 /* macchwuo - macchwuo. */
5642 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5643 /* machhw - machhw. */
5644 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5645 /* machhwo - machhwo. */
5646 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5647 /* machhws - machhws. */
5648 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5649 /* machhwso - machhwso. */
5650 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5651 /* machhwsu - machhwsu. */
5652 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5653 /* machhwsuo - machhwsuo. */
5654 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5655 /* machhwu - machhwu. */
5656 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5657 /* machhwuo - machhwuo. */
5658 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5659 /* maclhw - maclhw. */
5660 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5661 /* maclhwo - maclhwo. */
5662 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5663 /* maclhws - maclhws. */
5664 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5665 /* maclhwso - maclhwso. */
5666 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5667 /* maclhwu - maclhwu. */
5668 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5669 /* maclhwuo - maclhwuo. */
5670 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5671 /* maclhwsu - maclhwsu. */
5672 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5673 /* maclhwsuo - maclhwsuo. */
5674 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5675 /* nmacchw - nmacchw. */
5676 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5677 /* nmacchwo - nmacchwo. */
5678 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5679 /* nmacchws - nmacchws. */
5680 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5681 /* nmacchwso - nmacchwso. */
5682 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5683 /* nmachhw - nmachhw. */
5684 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5685 /* nmachhwo - nmachhwo. */
5686 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5687 /* nmachhws - nmachhws. */
5688 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5689 /* nmachhwso - nmachhwso. */
5690 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5691 /* nmaclhw - nmaclhw. */
5692 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5693 /* nmaclhwo - nmaclhwo. */
5694 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5695 /* nmaclhws - nmaclhws. */
5696 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5697 /* nmaclhwso - nmaclhwso. */
5698 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5700 /* mulchw - mulchw. */
5701 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5702 /* mulchwu - mulchwu. */
5703 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5704 /* mulhhw - mulhhw. */
5705 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5706 /* mulhhwu - mulhhwu. */
5707 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5708 /* mullhw - mullhw. */
5709 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5710 /* mullhwu - mullhwu. */
5711 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5714 static void gen_mfdcr(DisasContext
*ctx
)
5716 #if defined(CONFIG_USER_ONLY)
5717 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5720 if (unlikely(!ctx
->mem_idx
)) {
5721 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5724 /* NIP cannot be restored if the memory exception comes from an helper */
5725 gen_update_nip(ctx
, ctx
->nip
- 4);
5726 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5727 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
5728 tcg_temp_free(dcrn
);
5733 static void gen_mtdcr(DisasContext
*ctx
)
5735 #if defined(CONFIG_USER_ONLY)
5736 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5739 if (unlikely(!ctx
->mem_idx
)) {
5740 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5743 /* NIP cannot be restored if the memory exception comes from an helper */
5744 gen_update_nip(ctx
, ctx
->nip
- 4);
5745 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5746 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5747 tcg_temp_free(dcrn
);
5752 /* XXX: not implemented on 440 ? */
5753 static void gen_mfdcrx(DisasContext
*ctx
)
5755 #if defined(CONFIG_USER_ONLY)
5756 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5758 if (unlikely(!ctx
->mem_idx
)) {
5759 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5762 /* NIP cannot be restored if the memory exception comes from an helper */
5763 gen_update_nip(ctx
, ctx
->nip
- 4);
5764 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5765 cpu_gpr
[rA(ctx
->opcode
)]);
5766 /* Note: Rc update flag set leads to undefined state of Rc0 */
5771 /* XXX: not implemented on 440 ? */
5772 static void gen_mtdcrx(DisasContext
*ctx
)
5774 #if defined(CONFIG_USER_ONLY)
5775 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5777 if (unlikely(!ctx
->mem_idx
)) {
5778 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5781 /* NIP cannot be restored if the memory exception comes from an helper */
5782 gen_update_nip(ctx
, ctx
->nip
- 4);
5783 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5784 cpu_gpr
[rS(ctx
->opcode
)]);
5785 /* Note: Rc update flag set leads to undefined state of Rc0 */
5789 /* mfdcrux (PPC 460) : user-mode access to DCR */
5790 static void gen_mfdcrux(DisasContext
*ctx
)
5792 /* NIP cannot be restored if the memory exception comes from an helper */
5793 gen_update_nip(ctx
, ctx
->nip
- 4);
5794 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5795 cpu_gpr
[rA(ctx
->opcode
)]);
5796 /* Note: Rc update flag set leads to undefined state of Rc0 */
5799 /* mtdcrux (PPC 460) : user-mode access to DCR */
5800 static void gen_mtdcrux(DisasContext
*ctx
)
5802 /* NIP cannot be restored if the memory exception comes from an helper */
5803 gen_update_nip(ctx
, ctx
->nip
- 4);
5804 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5805 cpu_gpr
[rS(ctx
->opcode
)]);
5806 /* Note: Rc update flag set leads to undefined state of Rc0 */
5810 static void gen_dccci(DisasContext
*ctx
)
5812 #if defined(CONFIG_USER_ONLY)
5813 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5815 if (unlikely(!ctx
->mem_idx
)) {
5816 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5819 /* interpreted as no-op */
5824 static void gen_dcread(DisasContext
*ctx
)
5826 #if defined(CONFIG_USER_ONLY)
5827 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5830 if (unlikely(!ctx
->mem_idx
)) {
5831 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5834 gen_set_access_type(ctx
, ACCESS_CACHE
);
5835 EA
= tcg_temp_new();
5836 gen_addr_reg_index(ctx
, EA
);
5837 val
= tcg_temp_new();
5838 gen_qemu_ld32u(ctx
, val
, EA
);
5840 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5846 static void gen_icbt_40x(DisasContext
*ctx
)
5848 /* interpreted as no-op */
5849 /* XXX: specification say this is treated as a load by the MMU
5850 * but does not generate any exception
5855 static void gen_iccci(DisasContext
*ctx
)
5857 #if defined(CONFIG_USER_ONLY)
5858 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5860 if (unlikely(!ctx
->mem_idx
)) {
5861 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5864 /* interpreted as no-op */
5869 static void gen_icread(DisasContext
*ctx
)
5871 #if defined(CONFIG_USER_ONLY)
5872 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5874 if (unlikely(!ctx
->mem_idx
)) {
5875 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5878 /* interpreted as no-op */
5882 /* rfci (mem_idx only) */
5883 static void gen_rfci_40x(DisasContext
*ctx
)
5885 #if defined(CONFIG_USER_ONLY)
5886 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5888 if (unlikely(!ctx
->mem_idx
)) {
5889 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5892 /* Restore CPU state */
5893 gen_helper_40x_rfci(cpu_env
);
5894 gen_sync_exception(ctx
);
5898 static void gen_rfci(DisasContext
*ctx
)
5900 #if defined(CONFIG_USER_ONLY)
5901 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5903 if (unlikely(!ctx
->mem_idx
)) {
5904 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5907 /* Restore CPU state */
5908 gen_helper_rfci(cpu_env
);
5909 gen_sync_exception(ctx
);
5913 /* BookE specific */
5915 /* XXX: not implemented on 440 ? */
5916 static void gen_rfdi(DisasContext
*ctx
)
5918 #if defined(CONFIG_USER_ONLY)
5919 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5921 if (unlikely(!ctx
->mem_idx
)) {
5922 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5925 /* Restore CPU state */
5926 gen_helper_rfdi(cpu_env
);
5927 gen_sync_exception(ctx
);
5931 /* XXX: not implemented on 440 ? */
5932 static void gen_rfmci(DisasContext
*ctx
)
5934 #if defined(CONFIG_USER_ONLY)
5935 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5937 if (unlikely(!ctx
->mem_idx
)) {
5938 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5941 /* Restore CPU state */
5942 gen_helper_rfmci(cpu_env
);
5943 gen_sync_exception(ctx
);
5947 /* TLB management - PowerPC 405 implementation */
5950 static void gen_tlbre_40x(DisasContext
*ctx
)
5952 #if defined(CONFIG_USER_ONLY)
5953 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5955 if (unlikely(!ctx
->mem_idx
)) {
5956 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5959 switch (rB(ctx
->opcode
)) {
5961 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5962 cpu_gpr
[rA(ctx
->opcode
)]);
5965 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5966 cpu_gpr
[rA(ctx
->opcode
)]);
5969 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5975 /* tlbsx - tlbsx. */
5976 static void gen_tlbsx_40x(DisasContext
*ctx
)
5978 #if defined(CONFIG_USER_ONLY)
5979 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5982 if (unlikely(!ctx
->mem_idx
)) {
5983 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5986 t0
= tcg_temp_new();
5987 gen_addr_reg_index(ctx
, t0
);
5988 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5990 if (Rc(ctx
->opcode
)) {
5991 int l1
= gen_new_label();
5992 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
5993 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
5994 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
5995 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5996 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6003 static void gen_tlbwe_40x(DisasContext
*ctx
)
6005 #if defined(CONFIG_USER_ONLY)
6006 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6008 if (unlikely(!ctx
->mem_idx
)) {
6009 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6012 switch (rB(ctx
->opcode
)) {
6014 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6015 cpu_gpr
[rS(ctx
->opcode
)]);
6018 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6019 cpu_gpr
[rS(ctx
->opcode
)]);
6022 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6028 /* TLB management - PowerPC 440 implementation */
6031 static void gen_tlbre_440(DisasContext
*ctx
)
6033 #if defined(CONFIG_USER_ONLY)
6034 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6036 if (unlikely(!ctx
->mem_idx
)) {
6037 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6040 switch (rB(ctx
->opcode
)) {
6045 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6046 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6047 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6048 tcg_temp_free_i32(t0
);
6052 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6058 /* tlbsx - tlbsx. */
6059 static void gen_tlbsx_440(DisasContext
*ctx
)
6061 #if defined(CONFIG_USER_ONLY)
6062 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6065 if (unlikely(!ctx
->mem_idx
)) {
6066 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6069 t0
= tcg_temp_new();
6070 gen_addr_reg_index(ctx
, t0
);
6071 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6073 if (Rc(ctx
->opcode
)) {
6074 int l1
= gen_new_label();
6075 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
6076 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
6077 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
6078 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6079 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6086 static void gen_tlbwe_440(DisasContext
*ctx
)
6088 #if defined(CONFIG_USER_ONLY)
6089 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6091 if (unlikely(!ctx
->mem_idx
)) {
6092 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6095 switch (rB(ctx
->opcode
)) {
6100 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6101 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6102 cpu_gpr
[rS(ctx
->opcode
)]);
6103 tcg_temp_free_i32(t0
);
6107 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6113 /* TLB management - PowerPC BookE 2.06 implementation */
6116 static void gen_tlbre_booke206(DisasContext
*ctx
)
6118 #if defined(CONFIG_USER_ONLY)
6119 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6121 if (unlikely(!ctx
->mem_idx
)) {
6122 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6126 gen_helper_booke206_tlbre(cpu_env
);
6130 /* tlbsx - tlbsx. */
6131 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6133 #if defined(CONFIG_USER_ONLY)
6134 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6137 if (unlikely(!ctx
->mem_idx
)) {
6138 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6142 if (rA(ctx
->opcode
)) {
6143 t0
= tcg_temp_new();
6144 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6146 t0
= tcg_const_tl(0);
6149 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6150 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6155 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6157 #if defined(CONFIG_USER_ONLY)
6158 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6160 if (unlikely(!ctx
->mem_idx
)) {
6161 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6164 gen_update_nip(ctx
, ctx
->nip
- 4);
6165 gen_helper_booke206_tlbwe(cpu_env
);
6169 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6171 #if defined(CONFIG_USER_ONLY)
6172 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6175 if (unlikely(!ctx
->mem_idx
)) {
6176 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6180 t0
= tcg_temp_new();
6181 gen_addr_reg_index(ctx
, t0
);
6183 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6187 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6189 #if defined(CONFIG_USER_ONLY)
6190 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6193 if (unlikely(!ctx
->mem_idx
)) {
6194 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6198 t0
= tcg_temp_new();
6199 gen_addr_reg_index(ctx
, t0
);
6201 switch((ctx
->opcode
>> 21) & 0x3) {
6203 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6206 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6209 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6212 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6222 static void gen_wrtee(DisasContext
*ctx
)
6224 #if defined(CONFIG_USER_ONLY)
6225 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6228 if (unlikely(!ctx
->mem_idx
)) {
6229 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6232 t0
= tcg_temp_new();
6233 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6234 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6235 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6237 /* Stop translation to have a chance to raise an exception
6238 * if we just set msr_ee to 1
6240 gen_stop_exception(ctx
);
6245 static void gen_wrteei(DisasContext
*ctx
)
6247 #if defined(CONFIG_USER_ONLY)
6248 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6250 if (unlikely(!ctx
->mem_idx
)) {
6251 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6254 if (ctx
->opcode
& 0x00008000) {
6255 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6256 /* Stop translation to have a chance to raise an exception */
6257 gen_stop_exception(ctx
);
6259 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6264 /* PowerPC 440 specific instructions */
6267 static void gen_dlmzb(DisasContext
*ctx
)
6269 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6270 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6271 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6272 tcg_temp_free_i32(t0
);
6275 /* mbar replaces eieio on 440 */
6276 static void gen_mbar(DisasContext
*ctx
)
6278 /* interpreted as no-op */
6281 /* msync replaces sync on 440 */
6282 static void gen_msync_4xx(DisasContext
*ctx
)
6284 /* interpreted as no-op */
6288 static void gen_icbt_440(DisasContext
*ctx
)
6290 /* interpreted as no-op */
6291 /* XXX: specification say this is treated as a load by the MMU
6292 * but does not generate any exception
6296 /* Embedded.Processor Control */
6298 static void gen_msgclr(DisasContext
*ctx
)
6300 #if defined(CONFIG_USER_ONLY)
6301 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6303 if (unlikely(ctx
->mem_idx
== 0)) {
6304 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6308 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6312 static void gen_msgsnd(DisasContext
*ctx
)
6314 #if defined(CONFIG_USER_ONLY)
6315 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6317 if (unlikely(ctx
->mem_idx
== 0)) {
6318 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6322 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6326 /*** Altivec vector extension ***/
6327 /* Altivec registers moves */
6329 static inline TCGv_ptr
gen_avr_ptr(int reg
)
6331 TCGv_ptr r
= tcg_temp_new_ptr();
6332 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6336 #define GEN_VR_LDX(name, opc2, opc3) \
6337 static void glue(gen_, name)(DisasContext *ctx) \
6340 if (unlikely(!ctx->altivec_enabled)) { \
6341 gen_exception(ctx, POWERPC_EXCP_VPU); \
6344 gen_set_access_type(ctx, ACCESS_INT); \
6345 EA = tcg_temp_new(); \
6346 gen_addr_reg_index(ctx, EA); \
6347 tcg_gen_andi_tl(EA, EA, ~0xf); \
6348 if (ctx->le_mode) { \
6349 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6350 tcg_gen_addi_tl(EA, EA, 8); \
6351 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6353 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6354 tcg_gen_addi_tl(EA, EA, 8); \
6355 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6357 tcg_temp_free(EA); \
6360 #define GEN_VR_STX(name, opc2, opc3) \
6361 static void gen_st##name(DisasContext *ctx) \
6364 if (unlikely(!ctx->altivec_enabled)) { \
6365 gen_exception(ctx, POWERPC_EXCP_VPU); \
6368 gen_set_access_type(ctx, ACCESS_INT); \
6369 EA = tcg_temp_new(); \
6370 gen_addr_reg_index(ctx, EA); \
6371 tcg_gen_andi_tl(EA, EA, ~0xf); \
6372 if (ctx->le_mode) { \
6373 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6374 tcg_gen_addi_tl(EA, EA, 8); \
6375 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6377 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6378 tcg_gen_addi_tl(EA, EA, 8); \
6379 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6381 tcg_temp_free(EA); \
6384 #define GEN_VR_LVE(name, opc2, opc3) \
6385 static void gen_lve##name(DisasContext *ctx) \
6389 if (unlikely(!ctx->altivec_enabled)) { \
6390 gen_exception(ctx, POWERPC_EXCP_VPU); \
6393 gen_set_access_type(ctx, ACCESS_INT); \
6394 EA = tcg_temp_new(); \
6395 gen_addr_reg_index(ctx, EA); \
6396 rs = gen_avr_ptr(rS(ctx->opcode)); \
6397 gen_helper_lve##name(cpu_env, rs, EA); \
6398 tcg_temp_free(EA); \
6399 tcg_temp_free_ptr(rs); \
6402 #define GEN_VR_STVE(name, opc2, opc3) \
6403 static void gen_stve##name(DisasContext *ctx) \
6407 if (unlikely(!ctx->altivec_enabled)) { \
6408 gen_exception(ctx, POWERPC_EXCP_VPU); \
6411 gen_set_access_type(ctx, ACCESS_INT); \
6412 EA = tcg_temp_new(); \
6413 gen_addr_reg_index(ctx, EA); \
6414 rs = gen_avr_ptr(rS(ctx->opcode)); \
6415 gen_helper_stve##name(cpu_env, rs, EA); \
6416 tcg_temp_free(EA); \
6417 tcg_temp_free_ptr(rs); \
6420 GEN_VR_LDX(lvx
, 0x07, 0x03);
6421 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6422 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6424 GEN_VR_LVE(bx
, 0x07, 0x00);
6425 GEN_VR_LVE(hx
, 0x07, 0x01);
6426 GEN_VR_LVE(wx
, 0x07, 0x02);
6428 GEN_VR_STX(svx
, 0x07, 0x07);
6429 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6430 GEN_VR_STX(svxl
, 0x07, 0x0F);
6432 GEN_VR_STVE(bx
, 0x07, 0x04);
6433 GEN_VR_STVE(hx
, 0x07, 0x05);
6434 GEN_VR_STVE(wx
, 0x07, 0x06);
6436 static void gen_lvsl(DisasContext
*ctx
)
6440 if (unlikely(!ctx
->altivec_enabled
)) {
6441 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6444 EA
= tcg_temp_new();
6445 gen_addr_reg_index(ctx
, EA
);
6446 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6447 gen_helper_lvsl(rd
, EA
);
6449 tcg_temp_free_ptr(rd
);
6452 static void gen_lvsr(DisasContext
*ctx
)
6456 if (unlikely(!ctx
->altivec_enabled
)) {
6457 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6460 EA
= tcg_temp_new();
6461 gen_addr_reg_index(ctx
, EA
);
6462 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6463 gen_helper_lvsr(rd
, EA
);
6465 tcg_temp_free_ptr(rd
);
6468 static void gen_mfvscr(DisasContext
*ctx
)
6471 if (unlikely(!ctx
->altivec_enabled
)) {
6472 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6475 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6476 t
= tcg_temp_new_i32();
6477 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
6478 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6479 tcg_temp_free_i32(t
);
6482 static void gen_mtvscr(DisasContext
*ctx
)
6485 if (unlikely(!ctx
->altivec_enabled
)) {
6486 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6489 p
= gen_avr_ptr(rD(ctx
->opcode
));
6490 gen_helper_mtvscr(cpu_env
, p
);
6491 tcg_temp_free_ptr(p
);
6494 /* Logical operations */
6495 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6496 static void glue(gen_, name)(DisasContext *ctx) \
6498 if (unlikely(!ctx->altivec_enabled)) { \
6499 gen_exception(ctx, POWERPC_EXCP_VPU); \
6502 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6503 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6506 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6507 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6508 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6509 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6510 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6512 #define GEN_VXFORM(name, opc2, opc3) \
6513 static void glue(gen_, name)(DisasContext *ctx) \
6515 TCGv_ptr ra, rb, rd; \
6516 if (unlikely(!ctx->altivec_enabled)) { \
6517 gen_exception(ctx, POWERPC_EXCP_VPU); \
6520 ra = gen_avr_ptr(rA(ctx->opcode)); \
6521 rb = gen_avr_ptr(rB(ctx->opcode)); \
6522 rd = gen_avr_ptr(rD(ctx->opcode)); \
6523 gen_helper_##name (rd, ra, rb); \
6524 tcg_temp_free_ptr(ra); \
6525 tcg_temp_free_ptr(rb); \
6526 tcg_temp_free_ptr(rd); \
6529 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6530 static void glue(gen_, name)(DisasContext *ctx) \
6532 TCGv_ptr ra, rb, rd; \
6533 if (unlikely(!ctx->altivec_enabled)) { \
6534 gen_exception(ctx, POWERPC_EXCP_VPU); \
6537 ra = gen_avr_ptr(rA(ctx->opcode)); \
6538 rb = gen_avr_ptr(rB(ctx->opcode)); \
6539 rd = gen_avr_ptr(rD(ctx->opcode)); \
6540 gen_helper_##name(cpu_env, rd, ra, rb); \
6541 tcg_temp_free_ptr(ra); \
6542 tcg_temp_free_ptr(rb); \
6543 tcg_temp_free_ptr(rd); \
6546 GEN_VXFORM(vaddubm
, 0, 0);
6547 GEN_VXFORM(vadduhm
, 0, 1);
6548 GEN_VXFORM(vadduwm
, 0, 2);
6549 GEN_VXFORM(vsububm
, 0, 16);
6550 GEN_VXFORM(vsubuhm
, 0, 17);
6551 GEN_VXFORM(vsubuwm
, 0, 18);
6552 GEN_VXFORM(vmaxub
, 1, 0);
6553 GEN_VXFORM(vmaxuh
, 1, 1);
6554 GEN_VXFORM(vmaxuw
, 1, 2);
6555 GEN_VXFORM(vmaxsb
, 1, 4);
6556 GEN_VXFORM(vmaxsh
, 1, 5);
6557 GEN_VXFORM(vmaxsw
, 1, 6);
6558 GEN_VXFORM(vminub
, 1, 8);
6559 GEN_VXFORM(vminuh
, 1, 9);
6560 GEN_VXFORM(vminuw
, 1, 10);
6561 GEN_VXFORM(vminsb
, 1, 12);
6562 GEN_VXFORM(vminsh
, 1, 13);
6563 GEN_VXFORM(vminsw
, 1, 14);
6564 GEN_VXFORM(vavgub
, 1, 16);
6565 GEN_VXFORM(vavguh
, 1, 17);
6566 GEN_VXFORM(vavguw
, 1, 18);
6567 GEN_VXFORM(vavgsb
, 1, 20);
6568 GEN_VXFORM(vavgsh
, 1, 21);
6569 GEN_VXFORM(vavgsw
, 1, 22);
6570 GEN_VXFORM(vmrghb
, 6, 0);
6571 GEN_VXFORM(vmrghh
, 6, 1);
6572 GEN_VXFORM(vmrghw
, 6, 2);
6573 GEN_VXFORM(vmrglb
, 6, 4);
6574 GEN_VXFORM(vmrglh
, 6, 5);
6575 GEN_VXFORM(vmrglw
, 6, 6);
6576 GEN_VXFORM(vmuloub
, 4, 0);
6577 GEN_VXFORM(vmulouh
, 4, 1);
6578 GEN_VXFORM(vmulosb
, 4, 4);
6579 GEN_VXFORM(vmulosh
, 4, 5);
6580 GEN_VXFORM(vmuleub
, 4, 8);
6581 GEN_VXFORM(vmuleuh
, 4, 9);
6582 GEN_VXFORM(vmulesb
, 4, 12);
6583 GEN_VXFORM(vmulesh
, 4, 13);
6584 GEN_VXFORM(vslb
, 2, 4);
6585 GEN_VXFORM(vslh
, 2, 5);
6586 GEN_VXFORM(vslw
, 2, 6);
6587 GEN_VXFORM(vsrb
, 2, 8);
6588 GEN_VXFORM(vsrh
, 2, 9);
6589 GEN_VXFORM(vsrw
, 2, 10);
6590 GEN_VXFORM(vsrab
, 2, 12);
6591 GEN_VXFORM(vsrah
, 2, 13);
6592 GEN_VXFORM(vsraw
, 2, 14);
6593 GEN_VXFORM(vslo
, 6, 16);
6594 GEN_VXFORM(vsro
, 6, 17);
6595 GEN_VXFORM(vaddcuw
, 0, 6);
6596 GEN_VXFORM(vsubcuw
, 0, 22);
6597 GEN_VXFORM_ENV(vaddubs
, 0, 8);
6598 GEN_VXFORM_ENV(vadduhs
, 0, 9);
6599 GEN_VXFORM_ENV(vadduws
, 0, 10);
6600 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
6601 GEN_VXFORM_ENV(vaddshs
, 0, 13);
6602 GEN_VXFORM_ENV(vaddsws
, 0, 14);
6603 GEN_VXFORM_ENV(vsububs
, 0, 24);
6604 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
6605 GEN_VXFORM_ENV(vsubuws
, 0, 26);
6606 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
6607 GEN_VXFORM_ENV(vsubshs
, 0, 29);
6608 GEN_VXFORM_ENV(vsubsws
, 0, 30);
6609 GEN_VXFORM(vrlb
, 2, 0);
6610 GEN_VXFORM(vrlh
, 2, 1);
6611 GEN_VXFORM(vrlw
, 2, 2);
6612 GEN_VXFORM(vsl
, 2, 7);
6613 GEN_VXFORM(vsr
, 2, 11);
6614 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
6615 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
6616 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
6617 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
6618 GEN_VXFORM_ENV(vpkshus
, 7, 4);
6619 GEN_VXFORM_ENV(vpkswus
, 7, 5);
6620 GEN_VXFORM_ENV(vpkshss
, 7, 6);
6621 GEN_VXFORM_ENV(vpkswss
, 7, 7);
6622 GEN_VXFORM(vpkpx
, 7, 12);
6623 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
6624 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
6625 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
6626 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
6627 GEN_VXFORM_ENV(vsumsws
, 4, 30);
6628 GEN_VXFORM_ENV(vaddfp
, 5, 0);
6629 GEN_VXFORM_ENV(vsubfp
, 5, 1);
6630 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
6631 GEN_VXFORM_ENV(vminfp
, 5, 17);
6633 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6634 static void glue(gen_, name)(DisasContext *ctx) \
6636 TCGv_ptr ra, rb, rd; \
6637 if (unlikely(!ctx->altivec_enabled)) { \
6638 gen_exception(ctx, POWERPC_EXCP_VPU); \
6641 ra = gen_avr_ptr(rA(ctx->opcode)); \
6642 rb = gen_avr_ptr(rB(ctx->opcode)); \
6643 rd = gen_avr_ptr(rD(ctx->opcode)); \
6644 gen_helper_##opname(cpu_env, rd, ra, rb); \
6645 tcg_temp_free_ptr(ra); \
6646 tcg_temp_free_ptr(rb); \
6647 tcg_temp_free_ptr(rd); \
6650 #define GEN_VXRFORM(name, opc2, opc3) \
6651 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6652 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6654 GEN_VXRFORM(vcmpequb
, 3, 0)
6655 GEN_VXRFORM(vcmpequh
, 3, 1)
6656 GEN_VXRFORM(vcmpequw
, 3, 2)
6657 GEN_VXRFORM(vcmpgtsb
, 3, 12)
6658 GEN_VXRFORM(vcmpgtsh
, 3, 13)
6659 GEN_VXRFORM(vcmpgtsw
, 3, 14)
6660 GEN_VXRFORM(vcmpgtub
, 3, 8)
6661 GEN_VXRFORM(vcmpgtuh
, 3, 9)
6662 GEN_VXRFORM(vcmpgtuw
, 3, 10)
6663 GEN_VXRFORM(vcmpeqfp
, 3, 3)
6664 GEN_VXRFORM(vcmpgefp
, 3, 7)
6665 GEN_VXRFORM(vcmpgtfp
, 3, 11)
6666 GEN_VXRFORM(vcmpbfp
, 3, 15)
6668 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6669 static void glue(gen_, name)(DisasContext *ctx) \
6673 if (unlikely(!ctx->altivec_enabled)) { \
6674 gen_exception(ctx, POWERPC_EXCP_VPU); \
6677 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6678 rd = gen_avr_ptr(rD(ctx->opcode)); \
6679 gen_helper_##name (rd, simm); \
6680 tcg_temp_free_i32(simm); \
6681 tcg_temp_free_ptr(rd); \
6684 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
6685 GEN_VXFORM_SIMM(vspltish
, 6, 13);
6686 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
6688 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6689 static void glue(gen_, name)(DisasContext *ctx) \
6692 if (unlikely(!ctx->altivec_enabled)) { \
6693 gen_exception(ctx, POWERPC_EXCP_VPU); \
6696 rb = gen_avr_ptr(rB(ctx->opcode)); \
6697 rd = gen_avr_ptr(rD(ctx->opcode)); \
6698 gen_helper_##name (rd, rb); \
6699 tcg_temp_free_ptr(rb); \
6700 tcg_temp_free_ptr(rd); \
6703 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6704 static void glue(gen_, name)(DisasContext *ctx) \
6708 if (unlikely(!ctx->altivec_enabled)) { \
6709 gen_exception(ctx, POWERPC_EXCP_VPU); \
6712 rb = gen_avr_ptr(rB(ctx->opcode)); \
6713 rd = gen_avr_ptr(rD(ctx->opcode)); \
6714 gen_helper_##name(cpu_env, rd, rb); \
6715 tcg_temp_free_ptr(rb); \
6716 tcg_temp_free_ptr(rd); \
6719 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
6720 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
6721 GEN_VXFORM_NOA(vupklsb
, 7, 10);
6722 GEN_VXFORM_NOA(vupklsh
, 7, 11);
6723 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
6724 GEN_VXFORM_NOA(vupklpx
, 7, 15);
6725 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
6726 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
6727 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
6728 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
6729 GEN_VXFORM_NOA_ENV(vrfim
, 5, 8);
6730 GEN_VXFORM_NOA_ENV(vrfin
, 5, 9);
6731 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
6732 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 11);
6734 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6735 static void glue(gen_, name)(DisasContext *ctx) \
6739 if (unlikely(!ctx->altivec_enabled)) { \
6740 gen_exception(ctx, POWERPC_EXCP_VPU); \
6743 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6744 rd = gen_avr_ptr(rD(ctx->opcode)); \
6745 gen_helper_##name (rd, simm); \
6746 tcg_temp_free_i32(simm); \
6747 tcg_temp_free_ptr(rd); \
6750 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6751 static void glue(gen_, name)(DisasContext *ctx) \
6755 if (unlikely(!ctx->altivec_enabled)) { \
6756 gen_exception(ctx, POWERPC_EXCP_VPU); \
6759 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6760 rb = gen_avr_ptr(rB(ctx->opcode)); \
6761 rd = gen_avr_ptr(rD(ctx->opcode)); \
6762 gen_helper_##name (rd, rb, uimm); \
6763 tcg_temp_free_i32(uimm); \
6764 tcg_temp_free_ptr(rb); \
6765 tcg_temp_free_ptr(rd); \
6768 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6769 static void glue(gen_, name)(DisasContext *ctx) \
6774 if (unlikely(!ctx->altivec_enabled)) { \
6775 gen_exception(ctx, POWERPC_EXCP_VPU); \
6778 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6779 rb = gen_avr_ptr(rB(ctx->opcode)); \
6780 rd = gen_avr_ptr(rD(ctx->opcode)); \
6781 gen_helper_##name(cpu_env, rd, rb, uimm); \
6782 tcg_temp_free_i32(uimm); \
6783 tcg_temp_free_ptr(rb); \
6784 tcg_temp_free_ptr(rd); \
6787 GEN_VXFORM_UIMM(vspltb
, 6, 8);
6788 GEN_VXFORM_UIMM(vsplth
, 6, 9);
6789 GEN_VXFORM_UIMM(vspltw
, 6, 10);
6790 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
6791 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
6792 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
6793 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
6795 static void gen_vsldoi(DisasContext
*ctx
)
6797 TCGv_ptr ra
, rb
, rd
;
6799 if (unlikely(!ctx
->altivec_enabled
)) {
6800 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6803 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6804 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6805 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6806 sh
= tcg_const_i32(VSH(ctx
->opcode
));
6807 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
6808 tcg_temp_free_ptr(ra
);
6809 tcg_temp_free_ptr(rb
);
6810 tcg_temp_free_ptr(rd
);
6811 tcg_temp_free_i32(sh
);
6814 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6815 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6817 TCGv_ptr ra, rb, rc, rd; \
6818 if (unlikely(!ctx->altivec_enabled)) { \
6819 gen_exception(ctx, POWERPC_EXCP_VPU); \
6822 ra = gen_avr_ptr(rA(ctx->opcode)); \
6823 rb = gen_avr_ptr(rB(ctx->opcode)); \
6824 rc = gen_avr_ptr(rC(ctx->opcode)); \
6825 rd = gen_avr_ptr(rD(ctx->opcode)); \
6826 if (Rc(ctx->opcode)) { \
6827 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6829 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6831 tcg_temp_free_ptr(ra); \
6832 tcg_temp_free_ptr(rb); \
6833 tcg_temp_free_ptr(rc); \
6834 tcg_temp_free_ptr(rd); \
6837 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
6839 static void gen_vmladduhm(DisasContext
*ctx
)
6841 TCGv_ptr ra
, rb
, rc
, rd
;
6842 if (unlikely(!ctx
->altivec_enabled
)) {
6843 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6846 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6847 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6848 rc
= gen_avr_ptr(rC(ctx
->opcode
));
6849 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6850 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
6851 tcg_temp_free_ptr(ra
);
6852 tcg_temp_free_ptr(rb
);
6853 tcg_temp_free_ptr(rc
);
6854 tcg_temp_free_ptr(rd
);
6857 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
6858 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
6859 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
6860 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
6861 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
6863 /*** SPE extension ***/
6864 /* Register moves */
6867 static inline void gen_evmra(DisasContext
*ctx
)
6870 if (unlikely(!ctx
->spe_enabled
)) {
6871 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
6875 #if defined(TARGET_PPC64)
6877 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6880 tcg_gen_st_i64(cpu_gpr
[rA(ctx
->opcode
)],
6882 offsetof(CPUPPCState
, spe_acc
));
6884 TCGv_i64 tmp
= tcg_temp_new_i64();
6886 /* tmp := rA_lo + rA_hi << 32 */
6887 tcg_gen_concat_i32_i64(tmp
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6889 /* spe_acc := tmp */
6890 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
6891 tcg_temp_free_i64(tmp
);
6894 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6895 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6899 static inline void gen_load_gpr64(TCGv_i64 t
, int reg
)
6901 #if defined(TARGET_PPC64)
6902 tcg_gen_mov_i64(t
, cpu_gpr
[reg
]);
6904 tcg_gen_concat_i32_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
6908 static inline void gen_store_gpr64(int reg
, TCGv_i64 t
)
6910 #if defined(TARGET_PPC64)
6911 tcg_gen_mov_i64(cpu_gpr
[reg
], t
);
6913 TCGv_i64 tmp
= tcg_temp_new_i64();
6914 tcg_gen_trunc_i64_i32(cpu_gpr
[reg
], t
);
6915 tcg_gen_shri_i64(tmp
, t
, 32);
6916 tcg_gen_trunc_i64_i32(cpu_gprh
[reg
], tmp
);
6917 tcg_temp_free_i64(tmp
);
6921 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6922 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6924 if (Rc(ctx->opcode)) \
6930 /* Handler for undefined SPE opcodes */
6931 static inline void gen_speundef(DisasContext
*ctx
)
6933 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6937 #if defined(TARGET_PPC64)
6938 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6939 static inline void gen_##name(DisasContext *ctx) \
6941 if (unlikely(!ctx->spe_enabled)) { \
6942 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6945 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6946 cpu_gpr[rB(ctx->opcode)]); \
6949 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6950 static inline void gen_##name(DisasContext *ctx) \
6952 if (unlikely(!ctx->spe_enabled)) { \
6953 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6956 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6957 cpu_gpr[rB(ctx->opcode)]); \
6958 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6959 cpu_gprh[rB(ctx->opcode)]); \
6963 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
6964 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
6965 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
6966 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
6967 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
6968 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
6969 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
6970 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
6972 /* SPE logic immediate */
6973 #if defined(TARGET_PPC64)
6974 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6975 static inline void gen_##name(DisasContext *ctx) \
6977 if (unlikely(!ctx->spe_enabled)) { \
6978 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6981 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6982 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6983 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6984 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6985 tcg_opi(t0, t0, rB(ctx->opcode)); \
6986 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6987 tcg_gen_trunc_i64_i32(t1, t2); \
6988 tcg_temp_free_i64(t2); \
6989 tcg_opi(t1, t1, rB(ctx->opcode)); \
6990 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6991 tcg_temp_free_i32(t0); \
6992 tcg_temp_free_i32(t1); \
6995 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6996 static inline void gen_##name(DisasContext *ctx) \
6998 if (unlikely(!ctx->spe_enabled)) { \
6999 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7002 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7004 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7008 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
7009 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
7010 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
7011 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
7013 /* SPE arithmetic */
7014 #if defined(TARGET_PPC64)
7015 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7016 static inline void gen_##name(DisasContext *ctx) \
7018 if (unlikely(!ctx->spe_enabled)) { \
7019 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7022 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7023 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7024 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7025 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7027 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7028 tcg_gen_trunc_i64_i32(t1, t2); \
7029 tcg_temp_free_i64(t2); \
7031 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7032 tcg_temp_free_i32(t0); \
7033 tcg_temp_free_i32(t1); \
7036 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7037 static inline void gen_##name(DisasContext *ctx) \
7039 if (unlikely(!ctx->spe_enabled)) { \
7040 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7043 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7044 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7048 static inline void gen_op_evabs(TCGv_i32 ret
, TCGv_i32 arg1
)
7050 int l1
= gen_new_label();
7051 int l2
= gen_new_label();
7053 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
7054 tcg_gen_neg_i32(ret
, arg1
);
7057 tcg_gen_mov_i32(ret
, arg1
);
7060 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
7061 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
7062 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
7063 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
7064 static inline void gen_op_evrndw(TCGv_i32 ret
, TCGv_i32 arg1
)
7066 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
7067 tcg_gen_ext16u_i32(ret
, ret
);
7069 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
7070 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
7071 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
7073 #if defined(TARGET_PPC64)
7074 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7075 static inline void gen_##name(DisasContext *ctx) \
7077 if (unlikely(!ctx->spe_enabled)) { \
7078 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7081 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7082 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7083 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7084 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7085 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7086 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7087 tcg_op(t0, t0, t2); \
7088 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7089 tcg_gen_trunc_i64_i32(t1, t3); \
7090 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7091 tcg_gen_trunc_i64_i32(t2, t3); \
7092 tcg_temp_free_i64(t3); \
7093 tcg_op(t1, t1, t2); \
7094 tcg_temp_free_i32(t2); \
7095 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7096 tcg_temp_free_i32(t0); \
7097 tcg_temp_free_i32(t1); \
7100 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7101 static inline void gen_##name(DisasContext *ctx) \
7103 if (unlikely(!ctx->spe_enabled)) { \
7104 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7107 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7108 cpu_gpr[rB(ctx->opcode)]); \
7109 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7110 cpu_gprh[rB(ctx->opcode)]); \
7114 static inline void gen_op_evsrwu(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7119 l1
= gen_new_label();
7120 l2
= gen_new_label();
7121 t0
= tcg_temp_local_new_i32();
7122 /* No error here: 6 bits are used */
7123 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7124 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7125 tcg_gen_shr_i32(ret
, arg1
, t0
);
7128 tcg_gen_movi_i32(ret
, 0);
7130 tcg_temp_free_i32(t0
);
7132 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
7133 static inline void gen_op_evsrws(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7138 l1
= gen_new_label();
7139 l2
= gen_new_label();
7140 t0
= tcg_temp_local_new_i32();
7141 /* No error here: 6 bits are used */
7142 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7143 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7144 tcg_gen_sar_i32(ret
, arg1
, t0
);
7147 tcg_gen_movi_i32(ret
, 0);
7149 tcg_temp_free_i32(t0
);
7151 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
7152 static inline void gen_op_evslw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7157 l1
= gen_new_label();
7158 l2
= gen_new_label();
7159 t0
= tcg_temp_local_new_i32();
7160 /* No error here: 6 bits are used */
7161 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7162 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7163 tcg_gen_shl_i32(ret
, arg1
, t0
);
7166 tcg_gen_movi_i32(ret
, 0);
7168 tcg_temp_free_i32(t0
);
7170 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
7171 static inline void gen_op_evrlw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7173 TCGv_i32 t0
= tcg_temp_new_i32();
7174 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
7175 tcg_gen_rotl_i32(ret
, arg1
, t0
);
7176 tcg_temp_free_i32(t0
);
7178 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
7179 static inline void gen_evmergehi(DisasContext
*ctx
)
7181 if (unlikely(!ctx
->spe_enabled
)) {
7182 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7185 #if defined(TARGET_PPC64)
7186 TCGv t0
= tcg_temp_new();
7187 TCGv t1
= tcg_temp_new();
7188 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7189 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7190 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7194 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7195 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7198 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
7199 static inline void gen_op_evsubf(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7201 tcg_gen_sub_i32(ret
, arg2
, arg1
);
7203 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
7205 /* SPE arithmetic immediate */
7206 #if defined(TARGET_PPC64)
7207 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7208 static inline void gen_##name(DisasContext *ctx) \
7210 if (unlikely(!ctx->spe_enabled)) { \
7211 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7214 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7215 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7216 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7217 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7218 tcg_op(t0, t0, rA(ctx->opcode)); \
7219 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7220 tcg_gen_trunc_i64_i32(t1, t2); \
7221 tcg_temp_free_i64(t2); \
7222 tcg_op(t1, t1, rA(ctx->opcode)); \
7223 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7224 tcg_temp_free_i32(t0); \
7225 tcg_temp_free_i32(t1); \
7228 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7229 static inline void gen_##name(DisasContext *ctx) \
7231 if (unlikely(!ctx->spe_enabled)) { \
7232 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7235 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7237 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7241 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
7242 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
7244 /* SPE comparison */
7245 #if defined(TARGET_PPC64)
7246 #define GEN_SPEOP_COMP(name, tcg_cond) \
7247 static inline void gen_##name(DisasContext *ctx) \
7249 if (unlikely(!ctx->spe_enabled)) { \
7250 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7253 int l1 = gen_new_label(); \
7254 int l2 = gen_new_label(); \
7255 int l3 = gen_new_label(); \
7256 int l4 = gen_new_label(); \
7257 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7258 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7259 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7260 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7261 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7262 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7263 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7265 gen_set_label(l1); \
7266 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7267 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7268 gen_set_label(l2); \
7269 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7270 tcg_gen_trunc_i64_i32(t0, t2); \
7271 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7272 tcg_gen_trunc_i64_i32(t1, t2); \
7273 tcg_temp_free_i64(t2); \
7274 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7275 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7276 ~(CRF_CH | CRF_CH_AND_CL)); \
7278 gen_set_label(l3); \
7279 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7280 CRF_CH | CRF_CH_OR_CL); \
7281 gen_set_label(l4); \
7282 tcg_temp_free_i32(t0); \
7283 tcg_temp_free_i32(t1); \
7286 #define GEN_SPEOP_COMP(name, tcg_cond) \
7287 static inline void gen_##name(DisasContext *ctx) \
7289 if (unlikely(!ctx->spe_enabled)) { \
7290 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7293 int l1 = gen_new_label(); \
7294 int l2 = gen_new_label(); \
7295 int l3 = gen_new_label(); \
7296 int l4 = gen_new_label(); \
7298 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7299 cpu_gpr[rB(ctx->opcode)], l1); \
7300 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7302 gen_set_label(l1); \
7303 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7304 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7305 gen_set_label(l2); \
7306 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7307 cpu_gprh[rB(ctx->opcode)], l3); \
7308 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7309 ~(CRF_CH | CRF_CH_AND_CL)); \
7311 gen_set_label(l3); \
7312 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7313 CRF_CH | CRF_CH_OR_CL); \
7314 gen_set_label(l4); \
7317 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
7318 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
7319 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
7320 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
7321 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
7324 static inline void gen_brinc(DisasContext
*ctx
)
7326 /* Note: brinc is usable even if SPE is disabled */
7327 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
7328 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7330 static inline void gen_evmergelo(DisasContext
*ctx
)
7332 if (unlikely(!ctx
->spe_enabled
)) {
7333 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7336 #if defined(TARGET_PPC64)
7337 TCGv t0
= tcg_temp_new();
7338 TCGv t1
= tcg_temp_new();
7339 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
7340 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7341 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7345 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7346 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7349 static inline void gen_evmergehilo(DisasContext
*ctx
)
7351 if (unlikely(!ctx
->spe_enabled
)) {
7352 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7355 #if defined(TARGET_PPC64)
7356 TCGv t0
= tcg_temp_new();
7357 TCGv t1
= tcg_temp_new();
7358 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
7359 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7360 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7364 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7365 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7368 static inline void gen_evmergelohi(DisasContext
*ctx
)
7370 if (unlikely(!ctx
->spe_enabled
)) {
7371 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7374 #if defined(TARGET_PPC64)
7375 TCGv t0
= tcg_temp_new();
7376 TCGv t1
= tcg_temp_new();
7377 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7378 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7379 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7383 if (rD(ctx
->opcode
) == rA(ctx
->opcode
)) {
7384 TCGv_i32 tmp
= tcg_temp_new_i32();
7385 tcg_gen_mov_i32(tmp
, cpu_gpr
[rA(ctx
->opcode
)]);
7386 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7387 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], tmp
);
7388 tcg_temp_free_i32(tmp
);
7390 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7391 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7395 static inline void gen_evsplati(DisasContext
*ctx
)
7397 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 27)) >> 27;
7399 #if defined(TARGET_PPC64)
7400 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7402 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7403 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7406 static inline void gen_evsplatfi(DisasContext
*ctx
)
7408 uint64_t imm
= rA(ctx
->opcode
) << 27;
7410 #if defined(TARGET_PPC64)
7411 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7413 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7414 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7418 static inline void gen_evsel(DisasContext
*ctx
)
7420 int l1
= gen_new_label();
7421 int l2
= gen_new_label();
7422 int l3
= gen_new_label();
7423 int l4
= gen_new_label();
7424 TCGv_i32 t0
= tcg_temp_local_new_i32();
7425 #if defined(TARGET_PPC64)
7426 TCGv t1
= tcg_temp_local_new();
7427 TCGv t2
= tcg_temp_local_new();
7429 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
7430 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
7431 #if defined(TARGET_PPC64)
7432 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7434 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7438 #if defined(TARGET_PPC64)
7439 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7441 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7444 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
7445 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
7446 #if defined(TARGET_PPC64)
7447 tcg_gen_ext32u_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)]);
7449 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7453 #if defined(TARGET_PPC64)
7454 tcg_gen_ext32u_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)]);
7456 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7459 tcg_temp_free_i32(t0
);
7460 #if defined(TARGET_PPC64)
7461 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
, t2
);
7467 static void gen_evsel0(DisasContext
*ctx
)
7472 static void gen_evsel1(DisasContext
*ctx
)
7477 static void gen_evsel2(DisasContext
*ctx
)
7482 static void gen_evsel3(DisasContext
*ctx
)
7489 static inline void gen_evmwumi(DisasContext
*ctx
)
7493 if (unlikely(!ctx
->spe_enabled
)) {
7494 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7498 t0
= tcg_temp_new_i64();
7499 t1
= tcg_temp_new_i64();
7501 /* t0 := rA; t1 := rB */
7502 #if defined(TARGET_PPC64)
7503 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7504 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7506 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7507 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7510 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
7512 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
7514 tcg_temp_free_i64(t0
);
7515 tcg_temp_free_i64(t1
);
7518 static inline void gen_evmwumia(DisasContext
*ctx
)
7522 if (unlikely(!ctx
->spe_enabled
)) {
7523 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7527 gen_evmwumi(ctx
); /* rD := rA * rB */
7529 tmp
= tcg_temp_new_i64();
7532 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7533 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7534 tcg_temp_free_i64(tmp
);
7537 static inline void gen_evmwumiaa(DisasContext
*ctx
)
7542 if (unlikely(!ctx
->spe_enabled
)) {
7543 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7547 gen_evmwumi(ctx
); /* rD := rA * rB */
7549 acc
= tcg_temp_new_i64();
7550 tmp
= tcg_temp_new_i64();
7553 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7556 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7558 /* acc := tmp + acc */
7559 tcg_gen_add_i64(acc
, acc
, tmp
);
7562 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7565 gen_store_gpr64(rD(ctx
->opcode
), acc
);
7567 tcg_temp_free_i64(acc
);
7568 tcg_temp_free_i64(tmp
);
7571 static inline void gen_evmwsmi(DisasContext
*ctx
)
7575 if (unlikely(!ctx
->spe_enabled
)) {
7576 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7580 t0
= tcg_temp_new_i64();
7581 t1
= tcg_temp_new_i64();
7583 /* t0 := rA; t1 := rB */
7584 #if defined(TARGET_PPC64)
7585 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7586 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7588 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7589 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7592 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
7594 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
7596 tcg_temp_free_i64(t0
);
7597 tcg_temp_free_i64(t1
);
7600 static inline void gen_evmwsmia(DisasContext
*ctx
)
7604 gen_evmwsmi(ctx
); /* rD := rA * rB */
7606 tmp
= tcg_temp_new_i64();
7609 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7610 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7612 tcg_temp_free_i64(tmp
);
7615 static inline void gen_evmwsmiaa(DisasContext
*ctx
)
7617 TCGv_i64 acc
= tcg_temp_new_i64();
7618 TCGv_i64 tmp
= tcg_temp_new_i64();
7620 gen_evmwsmi(ctx
); /* rD := rA * rB */
7622 acc
= tcg_temp_new_i64();
7623 tmp
= tcg_temp_new_i64();
7626 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7629 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7631 /* acc := tmp + acc */
7632 tcg_gen_add_i64(acc
, acc
, tmp
);
7635 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7638 gen_store_gpr64(rD(ctx
->opcode
), acc
);
7640 tcg_temp_free_i64(acc
);
7641 tcg_temp_free_i64(tmp
);
7644 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7645 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7646 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7647 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7648 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7649 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7650 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7651 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
); //
7652 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
);
7653 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
7654 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7655 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7656 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7657 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7658 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7659 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
7660 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
7661 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7662 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7663 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
);
7664 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7665 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7666 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
); //
7667 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
);
7668 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7669 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7670 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
7671 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
7672 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
); ////
7674 /* SPE load and stores */
7675 static inline void gen_addr_spe_imm_index(DisasContext
*ctx
, TCGv EA
, int sh
)
7677 target_ulong uimm
= rB(ctx
->opcode
);
7679 if (rA(ctx
->opcode
) == 0) {
7680 tcg_gen_movi_tl(EA
, uimm
<< sh
);
7682 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
7683 #if defined(TARGET_PPC64)
7684 if (!ctx
->sf_mode
) {
7685 tcg_gen_ext32u_tl(EA
, EA
);
7691 static inline void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
7693 #if defined(TARGET_PPC64)
7694 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7696 TCGv_i64 t0
= tcg_temp_new_i64();
7697 gen_qemu_ld64(ctx
, t0
, addr
);
7698 tcg_gen_trunc_i64_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7699 tcg_gen_shri_i64(t0
, t0
, 32);
7700 tcg_gen_trunc_i64_i32(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7701 tcg_temp_free_i64(t0
);
7705 static inline void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
7707 #if defined(TARGET_PPC64)
7708 TCGv t0
= tcg_temp_new();
7709 gen_qemu_ld32u(ctx
, t0
, addr
);
7710 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7711 gen_addr_add(ctx
, addr
, addr
, 4);
7712 gen_qemu_ld32u(ctx
, t0
, addr
);
7713 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7716 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7717 gen_addr_add(ctx
, addr
, addr
, 4);
7718 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7722 static inline void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
7724 TCGv t0
= tcg_temp_new();
7725 #if defined(TARGET_PPC64)
7726 gen_qemu_ld16u(ctx
, t0
, addr
);
7727 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7728 gen_addr_add(ctx
, addr
, addr
, 2);
7729 gen_qemu_ld16u(ctx
, t0
, addr
);
7730 tcg_gen_shli_tl(t0
, t0
, 32);
7731 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7732 gen_addr_add(ctx
, addr
, addr
, 2);
7733 gen_qemu_ld16u(ctx
, t0
, addr
);
7734 tcg_gen_shli_tl(t0
, t0
, 16);
7735 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7736 gen_addr_add(ctx
, addr
, addr
, 2);
7737 gen_qemu_ld16u(ctx
, t0
, addr
);
7738 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7740 gen_qemu_ld16u(ctx
, t0
, addr
);
7741 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7742 gen_addr_add(ctx
, addr
, addr
, 2);
7743 gen_qemu_ld16u(ctx
, t0
, addr
);
7744 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7745 gen_addr_add(ctx
, addr
, addr
, 2);
7746 gen_qemu_ld16u(ctx
, t0
, addr
);
7747 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7748 gen_addr_add(ctx
, addr
, addr
, 2);
7749 gen_qemu_ld16u(ctx
, t0
, addr
);
7750 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7755 static inline void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
7757 TCGv t0
= tcg_temp_new();
7758 gen_qemu_ld16u(ctx
, t0
, addr
);
7759 #if defined(TARGET_PPC64)
7760 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7761 tcg_gen_shli_tl(t0
, t0
, 16);
7762 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7764 tcg_gen_shli_tl(t0
, t0
, 16);
7765 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7766 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7771 static inline void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
7773 TCGv t0
= tcg_temp_new();
7774 gen_qemu_ld16u(ctx
, t0
, addr
);
7775 #if defined(TARGET_PPC64)
7776 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7777 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7779 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7780 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7785 static inline void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
7787 TCGv t0
= tcg_temp_new();
7788 gen_qemu_ld16s(ctx
, t0
, addr
);
7789 #if defined(TARGET_PPC64)
7790 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7791 tcg_gen_ext32u_tl(t0
, t0
);
7792 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7794 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7795 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7800 static inline void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
7802 TCGv t0
= tcg_temp_new();
7803 #if defined(TARGET_PPC64)
7804 gen_qemu_ld16u(ctx
, t0
, addr
);
7805 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7806 gen_addr_add(ctx
, addr
, addr
, 2);
7807 gen_qemu_ld16u(ctx
, t0
, addr
);
7808 tcg_gen_shli_tl(t0
, t0
, 16);
7809 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7811 gen_qemu_ld16u(ctx
, t0
, addr
);
7812 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7813 gen_addr_add(ctx
, addr
, addr
, 2);
7814 gen_qemu_ld16u(ctx
, t0
, addr
);
7815 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7820 static inline void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
7822 #if defined(TARGET_PPC64)
7823 TCGv t0
= tcg_temp_new();
7824 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7825 gen_addr_add(ctx
, addr
, addr
, 2);
7826 gen_qemu_ld16u(ctx
, t0
, addr
);
7827 tcg_gen_shli_tl(t0
, t0
, 32);
7828 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7831 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7832 gen_addr_add(ctx
, addr
, addr
, 2);
7833 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7837 static inline void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
7839 #if defined(TARGET_PPC64)
7840 TCGv t0
= tcg_temp_new();
7841 gen_qemu_ld16s(ctx
, t0
, addr
);
7842 tcg_gen_ext32u_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7843 gen_addr_add(ctx
, addr
, addr
, 2);
7844 gen_qemu_ld16s(ctx
, t0
, addr
);
7845 tcg_gen_shli_tl(t0
, t0
, 32);
7846 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7849 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7850 gen_addr_add(ctx
, addr
, addr
, 2);
7851 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7855 static inline void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
7857 TCGv t0
= tcg_temp_new();
7858 gen_qemu_ld32u(ctx
, t0
, addr
);
7859 #if defined(TARGET_PPC64)
7860 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7861 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7863 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7864 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7869 static inline void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
7871 TCGv t0
= tcg_temp_new();
7872 #if defined(TARGET_PPC64)
7873 gen_qemu_ld16u(ctx
, t0
, addr
);
7874 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7875 tcg_gen_shli_tl(t0
, t0
, 32);
7876 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7877 gen_addr_add(ctx
, addr
, addr
, 2);
7878 gen_qemu_ld16u(ctx
, t0
, addr
);
7879 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7880 tcg_gen_shli_tl(t0
, t0
, 16);
7881 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7883 gen_qemu_ld16u(ctx
, t0
, addr
);
7884 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7885 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7886 gen_addr_add(ctx
, addr
, addr
, 2);
7887 gen_qemu_ld16u(ctx
, t0
, addr
);
7888 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7889 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7894 static inline void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
7896 #if defined(TARGET_PPC64)
7897 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7899 TCGv_i64 t0
= tcg_temp_new_i64();
7900 tcg_gen_concat_i32_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gprh
[rS(ctx
->opcode
)]);
7901 gen_qemu_st64(ctx
, t0
, addr
);
7902 tcg_temp_free_i64(t0
);
7906 static inline void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
7908 #if defined(TARGET_PPC64)
7909 TCGv t0
= tcg_temp_new();
7910 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7911 gen_qemu_st32(ctx
, t0
, addr
);
7914 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7916 gen_addr_add(ctx
, addr
, addr
, 4);
7917 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7920 static inline void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
7922 TCGv t0
= tcg_temp_new();
7923 #if defined(TARGET_PPC64)
7924 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7926 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7928 gen_qemu_st16(ctx
, t0
, addr
);
7929 gen_addr_add(ctx
, addr
, addr
, 2);
7930 #if defined(TARGET_PPC64)
7931 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7932 gen_qemu_st16(ctx
, t0
, addr
);
7934 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7936 gen_addr_add(ctx
, addr
, addr
, 2);
7937 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7938 gen_qemu_st16(ctx
, t0
, addr
);
7940 gen_addr_add(ctx
, addr
, addr
, 2);
7941 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7944 static inline void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
7946 TCGv t0
= tcg_temp_new();
7947 #if defined(TARGET_PPC64)
7948 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7950 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7952 gen_qemu_st16(ctx
, t0
, addr
);
7953 gen_addr_add(ctx
, addr
, addr
, 2);
7954 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7955 gen_qemu_st16(ctx
, t0
, addr
);
7959 static inline void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
7961 #if defined(TARGET_PPC64)
7962 TCGv t0
= tcg_temp_new();
7963 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7964 gen_qemu_st16(ctx
, t0
, addr
);
7967 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7969 gen_addr_add(ctx
, addr
, addr
, 2);
7970 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7973 static inline void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
7975 #if defined(TARGET_PPC64)
7976 TCGv t0
= tcg_temp_new();
7977 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7978 gen_qemu_st32(ctx
, t0
, addr
);
7981 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7985 static inline void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
7987 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7990 #define GEN_SPEOP_LDST(name, opc2, sh) \
7991 static void glue(gen_, name)(DisasContext *ctx) \
7994 if (unlikely(!ctx->spe_enabled)) { \
7995 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7998 gen_set_access_type(ctx, ACCESS_INT); \
7999 t0 = tcg_temp_new(); \
8000 if (Rc(ctx->opcode)) { \
8001 gen_addr_spe_imm_index(ctx, t0, sh); \
8003 gen_addr_reg_index(ctx, t0); \
8005 gen_op_##name(ctx, t0); \
8006 tcg_temp_free(t0); \
8009 GEN_SPEOP_LDST(evldd
, 0x00, 3);
8010 GEN_SPEOP_LDST(evldw
, 0x01, 3);
8011 GEN_SPEOP_LDST(evldh
, 0x02, 3);
8012 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
8013 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
8014 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
8015 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
8016 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
8017 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
8018 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
8019 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
8021 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
8022 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
8023 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
8024 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
8025 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
8026 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
8027 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
8029 /* Multiply and add - TODO */
8031 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);//
8032 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8033 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8034 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8035 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8036 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8037 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8038 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8039 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8040 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8041 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8042 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8044 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8045 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8046 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8047 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8048 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8049 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8050 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8051 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8052 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8053 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8054 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8055 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8057 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8058 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8059 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8060 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8061 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE
);
8063 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8064 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8065 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8066 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8067 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8068 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8069 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8070 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8071 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8072 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8073 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8074 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8076 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
8077 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
8078 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8079 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8081 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8082 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8083 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8084 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8085 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8086 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8087 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8088 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8089 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8090 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8091 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8092 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8094 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8095 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8096 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8097 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8098 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8101 /*** SPE floating-point extension ***/
8102 #if defined(TARGET_PPC64)
8103 #define GEN_SPEFPUOP_CONV_32_32(name) \
8104 static inline void gen_##name(DisasContext *ctx) \
8108 t0 = tcg_temp_new_i32(); \
8109 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8110 gen_helper_##name(t0, cpu_env, t0); \
8111 t1 = tcg_temp_new(); \
8112 tcg_gen_extu_i32_tl(t1, t0); \
8113 tcg_temp_free_i32(t0); \
8114 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8115 0xFFFFFFFF00000000ULL); \
8116 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8117 tcg_temp_free(t1); \
8119 #define GEN_SPEFPUOP_CONV_32_64(name) \
8120 static inline void gen_##name(DisasContext *ctx) \
8124 t0 = tcg_temp_new_i32(); \
8125 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8126 t1 = tcg_temp_new(); \
8127 tcg_gen_extu_i32_tl(t1, t0); \
8128 tcg_temp_free_i32(t0); \
8129 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8130 0xFFFFFFFF00000000ULL); \
8131 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8132 tcg_temp_free(t1); \
8134 #define GEN_SPEFPUOP_CONV_64_32(name) \
8135 static inline void gen_##name(DisasContext *ctx) \
8137 TCGv_i32 t0 = tcg_temp_new_i32(); \
8138 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8139 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8140 tcg_temp_free_i32(t0); \
8142 #define GEN_SPEFPUOP_CONV_64_64(name) \
8143 static inline void gen_##name(DisasContext *ctx) \
8145 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8146 cpu_gpr[rB(ctx->opcode)]); \
8148 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8149 static inline void gen_##name(DisasContext *ctx) \
8153 if (unlikely(!ctx->spe_enabled)) { \
8154 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8157 t0 = tcg_temp_new_i32(); \
8158 t1 = tcg_temp_new_i32(); \
8159 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8160 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8161 gen_helper_##name(t0, cpu_env, t0, t1); \
8162 tcg_temp_free_i32(t1); \
8163 t2 = tcg_temp_new(); \
8164 tcg_gen_extu_i32_tl(t2, t0); \
8165 tcg_temp_free_i32(t0); \
8166 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8167 0xFFFFFFFF00000000ULL); \
8168 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8169 tcg_temp_free(t2); \
8171 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8172 static inline void gen_##name(DisasContext *ctx) \
8174 if (unlikely(!ctx->spe_enabled)) { \
8175 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8178 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8179 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8181 #define GEN_SPEFPUOP_COMP_32(name) \
8182 static inline void gen_##name(DisasContext *ctx) \
8185 if (unlikely(!ctx->spe_enabled)) { \
8186 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8189 t0 = tcg_temp_new_i32(); \
8190 t1 = tcg_temp_new_i32(); \
8191 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8192 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8193 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8194 tcg_temp_free_i32(t0); \
8195 tcg_temp_free_i32(t1); \
8197 #define GEN_SPEFPUOP_COMP_64(name) \
8198 static inline void gen_##name(DisasContext *ctx) \
8200 if (unlikely(!ctx->spe_enabled)) { \
8201 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8204 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8205 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8208 #define GEN_SPEFPUOP_CONV_32_32(name) \
8209 static inline void gen_##name(DisasContext *ctx) \
8211 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8212 cpu_gpr[rB(ctx->opcode)]); \
8214 #define GEN_SPEFPUOP_CONV_32_64(name) \
8215 static inline void gen_##name(DisasContext *ctx) \
8217 TCGv_i64 t0 = tcg_temp_new_i64(); \
8218 gen_load_gpr64(t0, rB(ctx->opcode)); \
8219 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8220 tcg_temp_free_i64(t0); \
8222 #define GEN_SPEFPUOP_CONV_64_32(name) \
8223 static inline void gen_##name(DisasContext *ctx) \
8225 TCGv_i64 t0 = tcg_temp_new_i64(); \
8226 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8227 gen_store_gpr64(rD(ctx->opcode), t0); \
8228 tcg_temp_free_i64(t0); \
8230 #define GEN_SPEFPUOP_CONV_64_64(name) \
8231 static inline void gen_##name(DisasContext *ctx) \
8233 TCGv_i64 t0 = tcg_temp_new_i64(); \
8234 gen_load_gpr64(t0, rB(ctx->opcode)); \
8235 gen_helper_##name(t0, cpu_env, t0); \
8236 gen_store_gpr64(rD(ctx->opcode), t0); \
8237 tcg_temp_free_i64(t0); \
8239 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8240 static inline void gen_##name(DisasContext *ctx) \
8242 if (unlikely(!ctx->spe_enabled)) { \
8243 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8246 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8247 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8249 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8250 static inline void gen_##name(DisasContext *ctx) \
8253 if (unlikely(!ctx->spe_enabled)) { \
8254 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8257 t0 = tcg_temp_new_i64(); \
8258 t1 = tcg_temp_new_i64(); \
8259 gen_load_gpr64(t0, rA(ctx->opcode)); \
8260 gen_load_gpr64(t1, rB(ctx->opcode)); \
8261 gen_helper_##name(t0, cpu_env, t0, t1); \
8262 gen_store_gpr64(rD(ctx->opcode), t0); \
8263 tcg_temp_free_i64(t0); \
8264 tcg_temp_free_i64(t1); \
8266 #define GEN_SPEFPUOP_COMP_32(name) \
8267 static inline void gen_##name(DisasContext *ctx) \
8269 if (unlikely(!ctx->spe_enabled)) { \
8270 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8273 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8274 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8276 #define GEN_SPEFPUOP_COMP_64(name) \
8277 static inline void gen_##name(DisasContext *ctx) \
8280 if (unlikely(!ctx->spe_enabled)) { \
8281 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8284 t0 = tcg_temp_new_i64(); \
8285 t1 = tcg_temp_new_i64(); \
8286 gen_load_gpr64(t0, rA(ctx->opcode)); \
8287 gen_load_gpr64(t1, rB(ctx->opcode)); \
8288 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8289 tcg_temp_free_i64(t0); \
8290 tcg_temp_free_i64(t1); \
8294 /* Single precision floating-point vectors operations */
8296 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
8297 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
8298 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
8299 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
8300 static inline void gen_evfsabs(DisasContext
*ctx
)
8302 if (unlikely(!ctx
->spe_enabled
)) {
8303 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8306 #if defined(TARGET_PPC64)
8307 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000080000000LL
);
8309 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x80000000);
8310 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8313 static inline void gen_evfsnabs(DisasContext
*ctx
)
8315 if (unlikely(!ctx
->spe_enabled
)) {
8316 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8319 #if defined(TARGET_PPC64)
8320 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8322 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8323 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8326 static inline void gen_evfsneg(DisasContext
*ctx
)
8328 if (unlikely(!ctx
->spe_enabled
)) {
8329 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8332 #if defined(TARGET_PPC64)
8333 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8335 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8336 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8341 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
8342 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
8343 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
8344 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
8345 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
8346 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
8347 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
8348 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
8349 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
8350 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
8353 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
8354 GEN_SPEFPUOP_COMP_64(evfscmplt
);
8355 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
8356 GEN_SPEFPUOP_COMP_64(evfststgt
);
8357 GEN_SPEFPUOP_COMP_64(evfststlt
);
8358 GEN_SPEFPUOP_COMP_64(evfststeq
);
8360 /* Opcodes definitions */
8361 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8362 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8363 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8364 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8365 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8366 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8367 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8368 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8369 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8370 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8371 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8372 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8373 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8374 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8376 /* Single precision floating-point operations */
8378 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
8379 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
8380 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
8381 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
8382 static inline void gen_efsabs(DisasContext
*ctx
)
8384 if (unlikely(!ctx
->spe_enabled
)) {
8385 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8388 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
8390 static inline void gen_efsnabs(DisasContext
*ctx
)
8392 if (unlikely(!ctx
->spe_enabled
)) {
8393 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8396 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8398 static inline void gen_efsneg(DisasContext
*ctx
)
8400 if (unlikely(!ctx
->spe_enabled
)) {
8401 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8404 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8408 GEN_SPEFPUOP_CONV_32_32(efscfui
);
8409 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
8410 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
8411 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
8412 GEN_SPEFPUOP_CONV_32_32(efsctui
);
8413 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
8414 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
8415 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
8416 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
8417 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
8418 GEN_SPEFPUOP_CONV_32_64(efscfd
);
8421 GEN_SPEFPUOP_COMP_32(efscmpgt
);
8422 GEN_SPEFPUOP_COMP_32(efscmplt
);
8423 GEN_SPEFPUOP_COMP_32(efscmpeq
);
8424 GEN_SPEFPUOP_COMP_32(efststgt
);
8425 GEN_SPEFPUOP_COMP_32(efststlt
);
8426 GEN_SPEFPUOP_COMP_32(efststeq
);
8428 /* Opcodes definitions */
8429 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8430 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8431 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8432 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8433 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8434 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
); //
8435 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8436 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8437 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8438 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8439 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8440 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8441 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8442 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8444 /* Double precision floating-point operations */
8446 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
8447 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
8448 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
8449 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
8450 static inline void gen_efdabs(DisasContext
*ctx
)
8452 if (unlikely(!ctx
->spe_enabled
)) {
8453 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8456 #if defined(TARGET_PPC64)
8457 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000000000000LL
);
8459 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8460 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8463 static inline void gen_efdnabs(DisasContext
*ctx
)
8465 if (unlikely(!ctx
->spe_enabled
)) {
8466 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8469 #if defined(TARGET_PPC64)
8470 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8472 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8473 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8476 static inline void gen_efdneg(DisasContext
*ctx
)
8478 if (unlikely(!ctx
->spe_enabled
)) {
8479 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8482 #if defined(TARGET_PPC64)
8483 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8485 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8486 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8491 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
8492 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
8493 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
8494 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
8495 GEN_SPEFPUOP_CONV_32_64(efdctui
);
8496 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
8497 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
8498 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
8499 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
8500 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
8501 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
8502 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
8503 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
8504 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
8505 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
8508 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
8509 GEN_SPEFPUOP_COMP_64(efdcmplt
);
8510 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
8511 GEN_SPEFPUOP_COMP_64(efdtstgt
);
8512 GEN_SPEFPUOP_COMP_64(efdtstlt
);
8513 GEN_SPEFPUOP_COMP_64(efdtsteq
);
8515 /* Opcodes definitions */
8516 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8517 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8518 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
); //
8519 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8520 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8521 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8522 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8523 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
); //
8524 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8525 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8526 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8527 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8528 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8529 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8530 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8531 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8533 static opcode_t opcodes
[] = {
8534 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
8535 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
8536 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
8537 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
8538 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
8539 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
8540 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8541 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8542 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8543 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8544 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
8545 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
8546 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
8547 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
8548 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8549 #if defined(TARGET_PPC64)
8550 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
8552 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
8553 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
8554 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8555 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8556 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8557 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
8558 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
8559 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
8560 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8561 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8562 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8563 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8564 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB
),
8565 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
8566 #if defined(TARGET_PPC64)
8567 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
8568 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
8570 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8571 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8572 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8573 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
8574 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
8575 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
8576 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
8577 #if defined(TARGET_PPC64)
8578 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
8579 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
8580 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
8581 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
8582 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
8584 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
),
8585 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
8586 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
8587 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
),
8588 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
),
8589 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
),
8590 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
),
8591 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
),
8592 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
),
8593 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
),
8594 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT
),
8595 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
),
8596 #if defined(TARGET_PPC64)
8597 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8598 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
8599 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8601 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8602 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8603 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
8604 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
8605 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
8606 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
8607 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
8608 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
8609 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
8610 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
8611 #if defined(TARGET_PPC64)
8612 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
8613 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
8615 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
8616 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
8617 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8618 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8619 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
8620 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
8621 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
8622 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
8623 #if defined(TARGET_PPC64)
8624 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
8625 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
8627 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
8628 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
8629 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8630 #if defined(TARGET_PPC64)
8631 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
8632 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8634 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
8635 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
8636 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
8637 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
8638 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
8639 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
8640 #if defined(TARGET_PPC64)
8641 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
8643 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
),
8644 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
),
8645 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
8646 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
8647 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
8648 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
),
8649 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
),
8650 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ
),
8651 GEN_HANDLER2(dcbz_970
, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT
),
8652 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
8653 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
8654 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
8655 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
8656 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
8657 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
8658 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
8659 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
8660 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
8661 #if defined(TARGET_PPC64)
8662 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
8663 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8665 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
8666 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8668 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
8669 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
8670 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
8672 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
8673 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE
),
8674 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
),
8675 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
8676 #if defined(TARGET_PPC64)
8677 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
),
8678 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
8680 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
8681 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
8682 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
8683 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
8684 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
8685 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
8686 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
8687 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
8688 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
8689 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
8690 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
8691 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
8692 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
8693 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
8694 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
8695 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
8696 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
8697 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
8698 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
8699 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
8700 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
8701 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
8702 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
8703 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
8704 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
8705 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
8706 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
8707 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
8708 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
8709 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
8710 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
8711 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
8712 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
8713 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
8714 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
8715 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
8716 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
8717 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
8718 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
8719 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
8720 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
8721 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
8722 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
8723 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
8724 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
8725 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
8726 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
8727 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
8728 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
8729 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8730 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8731 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
8732 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
8733 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8734 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8735 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
8736 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
8737 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
8738 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
8739 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
8740 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
8741 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
8742 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
8743 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
8744 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
8745 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
8746 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
8747 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
8748 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
8749 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
8750 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
8751 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
8752 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
8753 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
8754 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
8755 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
8756 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
8757 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
8758 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
8759 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
8760 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8761 PPC_NONE
, PPC2_BOOKE206
),
8762 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8763 PPC_NONE
, PPC2_BOOKE206
),
8764 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8765 PPC_NONE
, PPC2_BOOKE206
),
8766 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8767 PPC_NONE
, PPC2_BOOKE206
),
8768 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8769 PPC_NONE
, PPC2_BOOKE206
),
8770 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8771 PPC_NONE
, PPC2_PRCNTL
),
8772 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8773 PPC_NONE
, PPC2_PRCNTL
),
8774 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
8775 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
8776 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
8777 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
8778 PPC_BOOKE
, PPC2_BOOKE206
),
8779 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
8780 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8781 PPC_BOOKE
, PPC2_BOOKE206
),
8782 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
8783 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
8784 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
8785 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
8786 GEN_HANDLER(vsldoi
, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC
),
8787 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
8788 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
),
8789 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
),
8790 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
),
8791 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
),
8793 #undef GEN_INT_ARITH_ADD
8794 #undef GEN_INT_ARITH_ADD_CONST
8795 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8796 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8797 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8798 add_ca, compute_ca, compute_ov) \
8799 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8800 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
8801 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
8802 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
8803 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
8804 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
8805 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
8806 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
8807 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
8808 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
8809 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
8811 #undef GEN_INT_ARITH_DIVW
8812 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8813 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8814 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
8815 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
8816 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
8817 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
8819 #if defined(TARGET_PPC64)
8820 #undef GEN_INT_ARITH_DIVD
8821 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8822 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8823 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
8824 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
8825 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
8826 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
8828 #undef GEN_INT_ARITH_MUL_HELPER
8829 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8830 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8831 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
8832 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
8833 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
8836 #undef GEN_INT_ARITH_SUBF
8837 #undef GEN_INT_ARITH_SUBF_CONST
8838 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8839 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8840 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8841 add_ca, compute_ca, compute_ov) \
8842 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8843 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
8844 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
8845 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
8846 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
8847 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
8848 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
8849 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
8850 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
8851 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
8852 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
8856 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8857 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8858 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8859 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8860 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
8861 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
8862 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
8863 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
8864 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
8865 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
8866 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
8867 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
8868 #if defined(TARGET_PPC64)
8869 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
8872 #if defined(TARGET_PPC64)
8875 #define GEN_PPC64_R2(name, opc1, opc2) \
8876 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8877 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8879 #define GEN_PPC64_R4(name, opc1, opc2) \
8880 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8881 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8883 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8885 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8887 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
8888 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
8889 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
8890 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
8891 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
8892 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
8895 #undef _GEN_FLOAT_ACB
8896 #undef GEN_FLOAT_ACB
8897 #undef _GEN_FLOAT_AB
8899 #undef _GEN_FLOAT_AC
8903 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8904 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8905 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8906 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8907 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8908 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8909 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8910 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8911 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8912 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8913 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8914 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8915 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8916 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8917 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8918 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8919 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8920 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8921 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8923 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
),
8924 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
),
8925 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
),
8926 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
),
8927 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
),
8928 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
),
8929 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
),
8930 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
),
8931 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
),
8932 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
),
8933 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
),
8934 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
),
8935 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
),
8936 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
),
8937 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
),
8938 #if defined(TARGET_PPC64)
8939 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
),
8940 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
),
8941 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
),
8943 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
),
8944 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
),
8945 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
),
8946 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
),
8947 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
),
8948 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
),
8949 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
),
8956 #define GEN_LD(name, ldop, opc, type) \
8957 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8958 #define GEN_LDU(name, ldop, opc, type) \
8959 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8960 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8961 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8962 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8963 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8964 #define GEN_LDS(name, ldop, op, type) \
8965 GEN_LD(name, ldop, op | 0x20, type) \
8966 GEN_LDU(name, ldop, op | 0x21, type) \
8967 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8968 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8970 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
8971 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
8972 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
8973 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
8974 #if defined(TARGET_PPC64)
8975 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
8976 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
8977 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
8978 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
8979 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
)
8981 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
8982 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
8989 #define GEN_ST(name, stop, opc, type) \
8990 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8991 #define GEN_STU(name, stop, opc, type) \
8992 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8993 #define GEN_STUX(name, stop, opc2, opc3, type) \
8994 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8995 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8996 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8997 #define GEN_STS(name, stop, op, type) \
8998 GEN_ST(name, stop, op | 0x20, type) \
8999 GEN_STU(name, stop, op | 0x21, type) \
9000 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9001 GEN_STX(name, stop, 0x17, op | 0x00, type)
9003 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
9004 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
9005 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
9006 #if defined(TARGET_PPC64)
9007 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
9008 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
9009 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
)
9011 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
9012 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
9019 #define GEN_LDF(name, ldop, opc, type) \
9020 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9021 #define GEN_LDUF(name, ldop, opc, type) \
9022 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9023 #define GEN_LDUXF(name, ldop, opc, type) \
9024 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9025 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9026 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9027 #define GEN_LDFS(name, ldop, op, type) \
9028 GEN_LDF(name, ldop, op | 0x20, type) \
9029 GEN_LDUF(name, ldop, op | 0x21, type) \
9030 GEN_LDUXF(name, ldop, op | 0x01, type) \
9031 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9033 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
)
9034 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
)
9041 #define GEN_STF(name, stop, opc, type) \
9042 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9043 #define GEN_STUF(name, stop, opc, type) \
9044 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9045 #define GEN_STUXF(name, stop, opc, type) \
9046 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9047 #define GEN_STXF(name, stop, opc2, opc3, type) \
9048 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9049 #define GEN_STFS(name, stop, op, type) \
9050 GEN_STF(name, stop, op | 0x20, type) \
9051 GEN_STUF(name, stop, op | 0x21, type) \
9052 GEN_STUXF(name, stop, op | 0x01, type) \
9053 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9055 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
)
9056 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
)
9057 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
)
9060 #define GEN_CRLOGIC(name, tcg_op, opc) \
9061 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9062 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
9063 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
9064 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
9065 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
9066 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
9067 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
9068 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
9069 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
9071 #undef GEN_MAC_HANDLER
9072 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9073 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9074 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
9075 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
9076 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
9077 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
9078 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
9079 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
9080 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
9081 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
9082 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
9083 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
9084 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
9085 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
9086 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
9087 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
9088 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
9089 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
9090 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
9091 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
9092 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
9093 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
9094 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
9095 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
9096 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
9097 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
9098 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
9099 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
9100 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
9101 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
9102 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
9103 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
9104 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
9105 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
9106 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
9107 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
9108 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
9109 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
9110 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
9111 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
9112 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
9113 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
9114 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
9115 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
9121 #define GEN_VR_LDX(name, opc2, opc3) \
9122 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9123 #define GEN_VR_STX(name, opc2, opc3) \
9124 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9125 #define GEN_VR_LVE(name, opc2, opc3) \
9126 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9127 #define GEN_VR_STVE(name, opc2, opc3) \
9128 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9129 GEN_VR_LDX(lvx
, 0x07, 0x03),
9130 GEN_VR_LDX(lvxl
, 0x07, 0x0B),
9131 GEN_VR_LVE(bx
, 0x07, 0x00),
9132 GEN_VR_LVE(hx
, 0x07, 0x01),
9133 GEN_VR_LVE(wx
, 0x07, 0x02),
9134 GEN_VR_STX(svx
, 0x07, 0x07),
9135 GEN_VR_STX(svxl
, 0x07, 0x0F),
9136 GEN_VR_STVE(bx
, 0x07, 0x04),
9137 GEN_VR_STVE(hx
, 0x07, 0x05),
9138 GEN_VR_STVE(wx
, 0x07, 0x06),
9140 #undef GEN_VX_LOGICAL
9141 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9142 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9143 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16),
9144 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17),
9145 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18),
9146 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19),
9147 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20),
9150 #define GEN_VXFORM(name, opc2, opc3) \
9151 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9152 GEN_VXFORM(vaddubm
, 0, 0),
9153 GEN_VXFORM(vadduhm
, 0, 1),
9154 GEN_VXFORM(vadduwm
, 0, 2),
9155 GEN_VXFORM(vsububm
, 0, 16),
9156 GEN_VXFORM(vsubuhm
, 0, 17),
9157 GEN_VXFORM(vsubuwm
, 0, 18),
9158 GEN_VXFORM(vmaxub
, 1, 0),
9159 GEN_VXFORM(vmaxuh
, 1, 1),
9160 GEN_VXFORM(vmaxuw
, 1, 2),
9161 GEN_VXFORM(vmaxsb
, 1, 4),
9162 GEN_VXFORM(vmaxsh
, 1, 5),
9163 GEN_VXFORM(vmaxsw
, 1, 6),
9164 GEN_VXFORM(vminub
, 1, 8),
9165 GEN_VXFORM(vminuh
, 1, 9),
9166 GEN_VXFORM(vminuw
, 1, 10),
9167 GEN_VXFORM(vminsb
, 1, 12),
9168 GEN_VXFORM(vminsh
, 1, 13),
9169 GEN_VXFORM(vminsw
, 1, 14),
9170 GEN_VXFORM(vavgub
, 1, 16),
9171 GEN_VXFORM(vavguh
, 1, 17),
9172 GEN_VXFORM(vavguw
, 1, 18),
9173 GEN_VXFORM(vavgsb
, 1, 20),
9174 GEN_VXFORM(vavgsh
, 1, 21),
9175 GEN_VXFORM(vavgsw
, 1, 22),
9176 GEN_VXFORM(vmrghb
, 6, 0),
9177 GEN_VXFORM(vmrghh
, 6, 1),
9178 GEN_VXFORM(vmrghw
, 6, 2),
9179 GEN_VXFORM(vmrglb
, 6, 4),
9180 GEN_VXFORM(vmrglh
, 6, 5),
9181 GEN_VXFORM(vmrglw
, 6, 6),
9182 GEN_VXFORM(vmuloub
, 4, 0),
9183 GEN_VXFORM(vmulouh
, 4, 1),
9184 GEN_VXFORM(vmulosb
, 4, 4),
9185 GEN_VXFORM(vmulosh
, 4, 5),
9186 GEN_VXFORM(vmuleub
, 4, 8),
9187 GEN_VXFORM(vmuleuh
, 4, 9),
9188 GEN_VXFORM(vmulesb
, 4, 12),
9189 GEN_VXFORM(vmulesh
, 4, 13),
9190 GEN_VXFORM(vslb
, 2, 4),
9191 GEN_VXFORM(vslh
, 2, 5),
9192 GEN_VXFORM(vslw
, 2, 6),
9193 GEN_VXFORM(vsrb
, 2, 8),
9194 GEN_VXFORM(vsrh
, 2, 9),
9195 GEN_VXFORM(vsrw
, 2, 10),
9196 GEN_VXFORM(vsrab
, 2, 12),
9197 GEN_VXFORM(vsrah
, 2, 13),
9198 GEN_VXFORM(vsraw
, 2, 14),
9199 GEN_VXFORM(vslo
, 6, 16),
9200 GEN_VXFORM(vsro
, 6, 17),
9201 GEN_VXFORM(vaddcuw
, 0, 6),
9202 GEN_VXFORM(vsubcuw
, 0, 22),
9203 GEN_VXFORM(vaddubs
, 0, 8),
9204 GEN_VXFORM(vadduhs
, 0, 9),
9205 GEN_VXFORM(vadduws
, 0, 10),
9206 GEN_VXFORM(vaddsbs
, 0, 12),
9207 GEN_VXFORM(vaddshs
, 0, 13),
9208 GEN_VXFORM(vaddsws
, 0, 14),
9209 GEN_VXFORM(vsububs
, 0, 24),
9210 GEN_VXFORM(vsubuhs
, 0, 25),
9211 GEN_VXFORM(vsubuws
, 0, 26),
9212 GEN_VXFORM(vsubsbs
, 0, 28),
9213 GEN_VXFORM(vsubshs
, 0, 29),
9214 GEN_VXFORM(vsubsws
, 0, 30),
9215 GEN_VXFORM(vrlb
, 2, 0),
9216 GEN_VXFORM(vrlh
, 2, 1),
9217 GEN_VXFORM(vrlw
, 2, 2),
9218 GEN_VXFORM(vsl
, 2, 7),
9219 GEN_VXFORM(vsr
, 2, 11),
9220 GEN_VXFORM(vpkuhum
, 7, 0),
9221 GEN_VXFORM(vpkuwum
, 7, 1),
9222 GEN_VXFORM(vpkuhus
, 7, 2),
9223 GEN_VXFORM(vpkuwus
, 7, 3),
9224 GEN_VXFORM(vpkshus
, 7, 4),
9225 GEN_VXFORM(vpkswus
, 7, 5),
9226 GEN_VXFORM(vpkshss
, 7, 6),
9227 GEN_VXFORM(vpkswss
, 7, 7),
9228 GEN_VXFORM(vpkpx
, 7, 12),
9229 GEN_VXFORM(vsum4ubs
, 4, 24),
9230 GEN_VXFORM(vsum4sbs
, 4, 28),
9231 GEN_VXFORM(vsum4shs
, 4, 25),
9232 GEN_VXFORM(vsum2sws
, 4, 26),
9233 GEN_VXFORM(vsumsws
, 4, 30),
9234 GEN_VXFORM(vaddfp
, 5, 0),
9235 GEN_VXFORM(vsubfp
, 5, 1),
9236 GEN_VXFORM(vmaxfp
, 5, 16),
9237 GEN_VXFORM(vminfp
, 5, 17),
9241 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9242 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9243 #define GEN_VXRFORM(name, opc2, opc3) \
9244 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9245 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9246 GEN_VXRFORM(vcmpequb
, 3, 0)
9247 GEN_VXRFORM(vcmpequh
, 3, 1)
9248 GEN_VXRFORM(vcmpequw
, 3, 2)
9249 GEN_VXRFORM(vcmpgtsb
, 3, 12)
9250 GEN_VXRFORM(vcmpgtsh
, 3, 13)
9251 GEN_VXRFORM(vcmpgtsw
, 3, 14)
9252 GEN_VXRFORM(vcmpgtub
, 3, 8)
9253 GEN_VXRFORM(vcmpgtuh
, 3, 9)
9254 GEN_VXRFORM(vcmpgtuw
, 3, 10)
9255 GEN_VXRFORM(vcmpeqfp
, 3, 3)
9256 GEN_VXRFORM(vcmpgefp
, 3, 7)
9257 GEN_VXRFORM(vcmpgtfp
, 3, 11)
9258 GEN_VXRFORM(vcmpbfp
, 3, 15)
9260 #undef GEN_VXFORM_SIMM
9261 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9262 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9263 GEN_VXFORM_SIMM(vspltisb
, 6, 12),
9264 GEN_VXFORM_SIMM(vspltish
, 6, 13),
9265 GEN_VXFORM_SIMM(vspltisw
, 6, 14),
9267 #undef GEN_VXFORM_NOA
9268 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9269 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9270 GEN_VXFORM_NOA(vupkhsb
, 7, 8),
9271 GEN_VXFORM_NOA(vupkhsh
, 7, 9),
9272 GEN_VXFORM_NOA(vupklsb
, 7, 10),
9273 GEN_VXFORM_NOA(vupklsh
, 7, 11),
9274 GEN_VXFORM_NOA(vupkhpx
, 7, 13),
9275 GEN_VXFORM_NOA(vupklpx
, 7, 15),
9276 GEN_VXFORM_NOA(vrefp
, 5, 4),
9277 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5),
9278 GEN_VXFORM_NOA(vexptefp
, 5, 6),
9279 GEN_VXFORM_NOA(vlogefp
, 5, 7),
9280 GEN_VXFORM_NOA(vrfim
, 5, 8),
9281 GEN_VXFORM_NOA(vrfin
, 5, 9),
9282 GEN_VXFORM_NOA(vrfip
, 5, 10),
9283 GEN_VXFORM_NOA(vrfiz
, 5, 11),
9285 #undef GEN_VXFORM_UIMM
9286 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9287 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9288 GEN_VXFORM_UIMM(vspltb
, 6, 8),
9289 GEN_VXFORM_UIMM(vsplth
, 6, 9),
9290 GEN_VXFORM_UIMM(vspltw
, 6, 10),
9291 GEN_VXFORM_UIMM(vcfux
, 5, 12),
9292 GEN_VXFORM_UIMM(vcfsx
, 5, 13),
9293 GEN_VXFORM_UIMM(vctuxs
, 5, 14),
9294 GEN_VXFORM_UIMM(vctsxs
, 5, 15),
9296 #undef GEN_VAFORM_PAIRED
9297 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9298 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9299 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16),
9300 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18),
9301 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19),
9302 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20),
9303 GEN_VAFORM_PAIRED(vsel
, vperm
, 21),
9304 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23),
9307 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9308 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9309 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9310 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9311 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9312 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9313 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9314 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9315 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9316 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
),
9317 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
),
9318 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
9319 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9320 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9321 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9322 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
9323 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
9324 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
),
9325 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
9326 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9327 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9328 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9329 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9330 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9331 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
9332 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
9333 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9334 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9335 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
9336 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
9337 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
),
9339 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9340 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
9341 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9342 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9343 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9344 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9345 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9346 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9347 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9348 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9349 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9350 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9351 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9352 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9354 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9355 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
9356 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9357 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9358 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9359 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
),
9360 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9361 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9362 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9363 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9364 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9365 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9366 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9367 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9369 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
9370 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9371 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
),
9372 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9373 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
9374 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9375 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
9376 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
),
9377 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9378 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9379 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9380 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9381 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9382 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9383 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
9384 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9386 #undef GEN_SPEOP_LDST
9387 #define GEN_SPEOP_LDST(name, opc2, sh) \
9388 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9389 GEN_SPEOP_LDST(evldd
, 0x00, 3),
9390 GEN_SPEOP_LDST(evldw
, 0x01, 3),
9391 GEN_SPEOP_LDST(evldh
, 0x02, 3),
9392 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1),
9393 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1),
9394 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1),
9395 GEN_SPEOP_LDST(evlwhe
, 0x08, 2),
9396 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2),
9397 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2),
9398 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2),
9399 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2),
9401 GEN_SPEOP_LDST(evstdd
, 0x10, 3),
9402 GEN_SPEOP_LDST(evstdw
, 0x11, 3),
9403 GEN_SPEOP_LDST(evstdh
, 0x12, 3),
9404 GEN_SPEOP_LDST(evstwhe
, 0x18, 2),
9405 GEN_SPEOP_LDST(evstwho
, 0x1A, 2),
9406 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2),
9407 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2),
9410 #include "helper_regs.h"
9411 #include "translate_init.c"
9413 /*****************************************************************************/
9414 /* Misc PowerPC helpers */
9415 void cpu_dump_state (CPUPPCState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
9423 cpu_synchronize_state(env
);
9425 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
9426 TARGET_FMT_lx
" XER " TARGET_FMT_lx
"\n",
9427 env
->nip
, env
->lr
, env
->ctr
, env
->xer
);
9428 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
9429 TARGET_FMT_lx
" idx %d\n", env
->msr
, env
->spr
[SPR_HID0
],
9430 env
->hflags
, env
->mmu_idx
);
9431 #if !defined(NO_TIMER_DUMP)
9432 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
9433 #if !defined(CONFIG_USER_ONLY)
9437 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
9438 #if !defined(CONFIG_USER_ONLY)
9439 , cpu_ppc_load_decr(env
)
9443 for (i
= 0; i
< 32; i
++) {
9444 if ((i
& (RGPL
- 1)) == 0)
9445 cpu_fprintf(f
, "GPR%02d", i
);
9446 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
9447 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
9448 cpu_fprintf(f
, "\n");
9450 cpu_fprintf(f
, "CR ");
9451 for (i
= 0; i
< 8; i
++)
9452 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
9453 cpu_fprintf(f
, " [");
9454 for (i
= 0; i
< 8; i
++) {
9456 if (env
->crf
[i
] & 0x08)
9458 else if (env
->crf
[i
] & 0x04)
9460 else if (env
->crf
[i
] & 0x02)
9462 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
9464 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
9466 for (i
= 0; i
< 32; i
++) {
9467 if ((i
& (RFPL
- 1)) == 0)
9468 cpu_fprintf(f
, "FPR%02d", i
);
9469 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
9470 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
9471 cpu_fprintf(f
, "\n");
9473 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
9474 #if !defined(CONFIG_USER_ONLY)
9475 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
9476 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
9477 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
9478 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
9480 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
9481 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
9482 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
9483 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
9485 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
9486 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
9487 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
9488 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
9490 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
9491 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
9492 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
9493 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
9494 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
9496 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
9497 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
9498 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
9499 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
9501 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
9502 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
9503 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
9504 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
9506 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
9507 " EPR " TARGET_FMT_lx
"\n",
9508 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
9509 env
->spr
[SPR_BOOKE_EPR
]);
9512 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
9513 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
9514 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
9515 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
9518 * IVORs are left out as they are large and do not change often --
9519 * they can be read with "p $ivor0", "p $ivor1", etc.
9523 #if defined(TARGET_PPC64)
9524 if (env
->flags
& POWERPC_FLAG_CFAR
) {
9525 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
9529 switch (env
->mmu_model
) {
9530 case POWERPC_MMU_32B
:
9531 case POWERPC_MMU_601
:
9532 case POWERPC_MMU_SOFT_6xx
:
9533 case POWERPC_MMU_SOFT_74xx
:
9534 #if defined(TARGET_PPC64)
9535 case POWERPC_MMU_620
:
9536 case POWERPC_MMU_64B
:
9538 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
]);
9540 case POWERPC_MMU_BOOKE206
:
9541 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
9542 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
9543 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
9544 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
9546 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
9547 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
9548 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
9549 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
9551 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
9552 " TLB1CFG " TARGET_FMT_lx
"\n",
9553 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
9554 env
->spr
[SPR_BOOKE_TLB1CFG
]);
9565 void cpu_dump_statistics (CPUPPCState
*env
, FILE*f
, fprintf_function cpu_fprintf
,
9568 #if defined(DO_PPC_STATISTICS)
9569 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
9573 for (op1
= 0; op1
< 64; op1
++) {
9575 if (is_indirect_opcode(handler
)) {
9576 t2
= ind_table(handler
);
9577 for (op2
= 0; op2
< 32; op2
++) {
9579 if (is_indirect_opcode(handler
)) {
9580 t3
= ind_table(handler
);
9581 for (op3
= 0; op3
< 32; op3
++) {
9583 if (handler
->count
== 0)
9585 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
9586 "%016" PRIx64
" %" PRId64
"\n",
9587 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
9589 handler
->count
, handler
->count
);
9592 if (handler
->count
== 0)
9594 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
9595 "%016" PRIx64
" %" PRId64
"\n",
9596 op1
, op2
, op1
, op2
, handler
->oname
,
9597 handler
->count
, handler
->count
);
9601 if (handler
->count
== 0)
9603 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
9605 op1
, op1
, handler
->oname
,
9606 handler
->count
, handler
->count
);
9612 /*****************************************************************************/
9613 static inline void gen_intermediate_code_internal(CPUPPCState
*env
,
9614 TranslationBlock
*tb
,
9617 DisasContext ctx
, *ctxp
= &ctx
;
9618 opc_handler_t
**table
, *handler
;
9619 target_ulong pc_start
;
9620 uint16_t *gen_opc_end
;
9627 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
9630 ctx
.exception
= POWERPC_EXCP_NONE
;
9631 ctx
.spr_cb
= env
->spr_cb
;
9632 ctx
.mem_idx
= env
->mmu_idx
;
9633 ctx
.access_type
= -1;
9634 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
9635 #if defined(TARGET_PPC64)
9636 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
9637 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
9639 ctx
.fpu_enabled
= msr_fp
;
9640 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
9641 ctx
.spe_enabled
= msr_spe
;
9643 ctx
.spe_enabled
= 0;
9644 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
9645 ctx
.altivec_enabled
= msr_vr
;
9647 ctx
.altivec_enabled
= 0;
9648 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
9649 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
9651 ctx
.singlestep_enabled
= 0;
9652 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
9653 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
9654 if (unlikely(env
->singlestep_enabled
))
9655 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
9656 #if defined (DO_SINGLE_STEP) && 0
9657 /* Single step trace mode */
9661 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9663 max_insns
= CF_COUNT_MASK
;
9666 /* Set env in case of segfault during code fetch */
9667 while (ctx
.exception
== POWERPC_EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
9668 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
9669 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
9670 if (bp
->pc
== ctx
.nip
) {
9671 gen_debug_exception(ctxp
);
9676 if (unlikely(search_pc
)) {
9677 j
= gen_opc_ptr
- gen_opc_buf
;
9681 gen_opc_instr_start
[lj
++] = 0;
9683 gen_opc_pc
[lj
] = ctx
.nip
;
9684 gen_opc_instr_start
[lj
] = 1;
9685 gen_opc_icount
[lj
] = num_insns
;
9687 LOG_DISAS("----------------\n");
9688 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
9689 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
9690 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
9692 if (unlikely(ctx
.le_mode
)) {
9693 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
9695 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
9697 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9698 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
9699 opc3(ctx
.opcode
), little_endian
? "little" : "big");
9700 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
9701 tcg_gen_debug_insn_start(ctx
.nip
);
9704 table
= env
->opcodes
;
9706 handler
= table
[opc1(ctx
.opcode
)];
9707 if (is_indirect_opcode(handler
)) {
9708 table
= ind_table(handler
);
9709 handler
= table
[opc2(ctx
.opcode
)];
9710 if (is_indirect_opcode(handler
)) {
9711 table
= ind_table(handler
);
9712 handler
= table
[opc3(ctx
.opcode
)];
9715 /* Is opcode *REALLY* valid ? */
9716 if (unlikely(handler
->handler
== &gen_invalid
)) {
9717 if (qemu_log_enabled()) {
9718 qemu_log("invalid/unsupported opcode: "
9719 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
" %d\n",
9720 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
9721 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
9726 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
9727 inval
= handler
->inval2
;
9729 inval
= handler
->inval1
;
9732 if (unlikely((ctx
.opcode
& inval
) != 0)) {
9733 if (qemu_log_enabled()) {
9734 qemu_log("invalid bits: %08x for opcode: "
9735 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
"\n",
9736 ctx
.opcode
& inval
, opc1(ctx
.opcode
),
9737 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
9738 ctx
.opcode
, ctx
.nip
- 4);
9740 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
9744 (*(handler
->handler
))(&ctx
);
9745 #if defined(DO_PPC_STATISTICS)
9748 /* Check trace mode exceptions */
9749 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
9750 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
9751 ctx
.exception
!= POWERPC_SYSCALL
&&
9752 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
9753 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
9754 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
9755 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
9756 (env
->singlestep_enabled
) ||
9758 num_insns
>= max_insns
)) {
9759 /* if we reach a page boundary or are single stepping, stop
9765 if (tb
->cflags
& CF_LAST_IO
)
9767 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
9768 gen_goto_tb(&ctx
, 0, ctx
.nip
);
9769 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
9770 if (unlikely(env
->singlestep_enabled
)) {
9771 gen_debug_exception(ctxp
);
9773 /* Generate the return instruction */
9776 gen_icount_end(tb
, num_insns
);
9777 *gen_opc_ptr
= INDEX_op_end
;
9778 if (unlikely(search_pc
)) {
9779 j
= gen_opc_ptr
- gen_opc_buf
;
9782 gen_opc_instr_start
[lj
++] = 0;
9784 tb
->size
= ctx
.nip
- pc_start
;
9785 tb
->icount
= num_insns
;
9787 #if defined(DEBUG_DISAS)
9788 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9790 flags
= env
->bfd_mach
;
9791 flags
|= ctx
.le_mode
<< 16;
9792 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9793 log_target_disas(pc_start
, ctx
.nip
- pc_start
, flags
);
9799 void gen_intermediate_code (CPUPPCState
*env
, struct TranslationBlock
*tb
)
9801 gen_intermediate_code_internal(env
, tb
, 0);
9804 void gen_intermediate_code_pc (CPUPPCState
*env
, struct TranslationBlock
*tb
)
9806 gen_intermediate_code_internal(env
, tb
, 1);
9809 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
, int pc_pos
)
9811 env
->nip
= gen_opc_pc
[pc_pos
];