| 2022-04-22 | Weiwei Li | target/riscv: fix start byte for vmv<nf>r.v when vstart... Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220330021316.18223-1-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-04-22 | Weiwei Li | target/riscv: optimize helper for vmv<nr>r.v Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220325085902.29500-2-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-04-22 | Weiwei Li | target/riscv: optimize condition assign for scale < 0 Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220325085902.29500-1-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-03-03 | Weiwei Li | target/riscv: expose zfinx, zdinx, zhinx{min} properties Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220211043920.28981-7-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-03-03 | Weiwei Li | target/riscv: add support for zhinx/zhinxmin Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220211043920.28981-6-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-03-03 | Weiwei Li | target/riscv: add support for zdinx Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220211043920.28981-5-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-03-03 | Weiwei Li | target/riscv: add support for zfinx Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220211043920.28981-4-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-03-03 | Weiwei Li | target/riscv: hardwire mstatus.FS to zero when enable... Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220211043920.28981-3-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-03-03 | Weiwei Li | target/riscv: add cfg properties for zfinx, zdinx and... Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-02-16 | Weiwei Li | target/riscv: add support for svpbmt extension Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-02-16 | Weiwei Li | target/riscv: add support for svinval extension Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-02-16 | Weiwei Li | target/riscv: add support for svnapot extension Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn> |
commitcommitdifftree |
| 2022-02-16 | Weiwei Li | target/riscv: add PTE_A/PTE_D/PTE_U bits check for... Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn> |
commitcommitdifftree |