| commit | bbce8ba8e6bddcd77abef4810a9426bad9939f3b | |
| author | Weiwei Li <liweiwei@iscas.ac.cn> | |
| Fri, 4 Feb 2022 02:26:58 +0000 (4 10:26 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 16 Feb 2022 02:25:52 +0000 (16 12:25 +1000) | ||
| tree | 0436417581285293b5853ef57ede836fb1f7931e | treesnapshot (tar.gz zip) |
| parent | c5d77ddd8ebcd33da9561982e29c8f4b2dec0978 | commitdiff |
target/riscv: add support for svpbmt extension
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/cpu_bits.h | diffblobblamehistory | |
| target/riscv/cpu_helper.c | diffblobblamehistory |