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target-arm: implement IRQ/FIQ routing to Monitor mode
2014-12-11 Fabian Aggelertarget-arm: implement IRQ/FIQ routing to Monitor mode
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-12-11 Fabian Aggelertarget-arm: move AArch32 SCR into security reglist
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-12-11 Fabian Aggelertarget-arm: insert AArch32 cpregs twice into hashtable
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-12-11 Fabian Aggelertarget-arm: add CPREG secure state support
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-12-11 Fabian Aggelertarget-arm: add banked register accessors
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-10-24 Fabian Aggelertarget-arm: A32: Emulate the SMC instruction
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-10-24 Fabian Aggelertarget-arm: make arm_current_el() return EL3
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-10-24 Fabian Aggelertarget-arm: add arm_is_secure() function
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-10-24 Fabian Aggelertarget-arm: increase arrays of registers R13 & R14
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-06-19 Fabian Aggelertarget-arm: implement PD0/PD1 bits for TTBCR
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-06-09 Fabian Aggelertarget-arm: Prepare cpreg writefns/readfns for EL3...
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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2014-05-27 Fabian Aggelertarget-arm: implement CPACR register logic for ARMv7
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
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QEmu