| commit | de38d23b542efca54108ef28bcc0efe96f378d2e | |
| author | Fabian Aggeler <aggelerf@ethz.ch> | |
| Thu, 11 Dec 2014 12:07:49 +0000 (11 12:07 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 11 Dec 2014 12:07:49 +0000 (11 12:07 +0000) | ||
| tree | 0200b535c25b5684cc7a8cddccfdaff1cc574f99 | treesnapshot (tar.gz zip) |
| parent | 0f1a3b2470d798ad5335eb9d6236f02ff64e31a8 | commitdiff |
target-arm: implement IRQ/FIQ routing to Monitor mode
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-10-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-10-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target-arm/helper.c | diffblobblamehistory |