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RISC-V: Implement existential predicates for CSRs
2019-01-09
Michael
C
lark
RISC-V: Imple
m
ent existenti
a
l
predicates for CS
R
s
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2019-01-09
Michael Clark
RISC-V:
Implemen
t
atom
i
c
mip/sip C
S
R
updates
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2019-01-08
Michael
Clark
RISC-V: Implement modular CS
R
helper
i
nterfa
c
e
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-12-20
Mic
h
ael Clark
RISC-V: Enab
l
e
second UART on
sifive_e and sifive_u
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-12-20
M
ichael Cla
r
k
R
ISC-V: Fix PL
I
C pending bitfield reads
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-12-20
Michael Clark
RISC-
V
: Fix CLINT t
i
mecmp low 32-bit writes
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-12-20
M
ichael
C
l
a
rk
RISC-V:
Add
hartid and \n to in
t
e
r
rup
t
logging
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-10-17
Michael Clark
RISC-V: Don't add
N
ULL bootargs to device-t
r
ee
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-10-17
Michael Clark
RISC-
V
: Add
m
i
s
sing free for plic_hart_
c
o
nfig
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-10-17
Michael Clark
RI
S
C-
V
:
Upd
a
t
e
C
S
R
and i
n
t
errupt d
e
f
i
nitions
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-10-17
Micha
e
l Clark
RISC-V: Move non-ops
from op_
h
el
p
e
r to cpu_helpe
r
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-10-17
Michael Clark
RISC-V:
A
l
lo
w
setting and clearing
m
ultiple irqs
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-09-04
Micha
e
l Clark
R
ISC-V: Simplify riscv_cpu_
l
ocal_irqs_pending
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-09-04
Michael
C
lark
RISC-V: Use
atomic
_
cmpxchg to upd
a
t
e
PLIC bitmaps
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-09-04
Mic
h
ael Cl
a
rk
RISC-V
:
I
mprove page
table
w
alker
sp
e
c compliance
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-09-04
Mich
a
el
Cla
r
k
RI
S
C
-V: Update addr
e
ss b
i
ts to support sv39
and s
v
48
commit
|
commitdiff
|
tree
2018-05-05
Mic
h
ae
l
Clark
RISC-
V
: Mark
R
OM read-only after copyi
n
g in code
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael Clark
R
I
S
C
-V: No
t
raps on wri
t
e
s to misa,
m
i
nstret
,
m
cycle
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael Clark
RIS
C
-V: M
a
ke mtvec/
s
tve
c
ignor
e
ve
c
tore
d
tr
a
ps
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael Clark
RISC-V: Add mcycle/minstret
support for -icou
n
t auto
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Mich
a
e
l
Clark
RI
S
C-V: Use [ms]coun
t
e
r
en CSRs
w
h
e
n
p
riv
ISA
>=
v1
.
10
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
M
i
chael Clark
RISC-V: Allow S
-
mod
e
mxr
a
c
cess
when pri
v
ISA >= v1
.
10
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
M
i
chael Clark
RISC-V
:
Cl
e
ar mt
v
al/stv
a
l on exceptions
w
ithout
i
nfo
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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2018-05-05
Mich
a
el Clark
RISC-V: Har
d
wire sat
p
to
0 for no-mmu case
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Mich
a
e
l
Clar
k
RISC-V: Up
d
ate E and I exte
n
sio
n
orde
r
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Mi
c
hae
l
Clark
RI
S
C-V: Rem
o
ve erron
e
ou
s
c
omment from
translate
.
c
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Michae
l
Cl
a
rk
RISC-V: Remove
EM
_
RISCV ELF_MACHINE indirec
t
ion
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
M
ic
h
ael Clark
RISC
-
V: Ma
k
e
v
i
r
t header comment title consistent
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael C
l
ark
R
I
SC-V: Make some
h
eader guard
s
more specific
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael C
l
ark
RISC-V: Fix
m
issing break stateme
n
t
in di
s
ass
e
m
bler
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael
Clark
R
ISC-V: Inc
l
ude instru
c
tion hex in dis
a
ssembly
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael Cla
r
k
R
ISC-V: R
e
move
u
n
u
sed class defin
i
tions
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Mi
c
hael Clark
R
I
SC
-
V: Remove id
e
ntity_tran
s
late from load_elf
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael Clark
RISC-
V
: Use ROM base address and size fr
o
m memm
a
p
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
M
i
ch
a
e
l
C
lark
RI
S
C-V: Mak
e
virt
board descrip
t
ion match
s
p
ike
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Micha
e
l Clark
R
I
SC-V: Rep
l
ace
h
ar
d
coded
c
onstants with e
n
u
m
value
s
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-29
M
ichael
C
lark
R
ISC-V:
W
orkaroun
d
f
o
r critical mstat
u
s
.
FS bug
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-28
Mi
c
hael
C
lark
RISC-V: Fix incor
r
ect disa
s
sembl
y
for addiw
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-28
Micha
e
l C
l
ark
RIS
C
-V: C
o
nvert cpu d
e
finit
i
o
n to future model
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-20
Mi
c
hael Clar
k
RI
S
C
-V: Fix riscv_isa_string memo
r
y
size bug
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
h
a
el Clark
R
I
SC-V Bui
l
d Inf
r
astructure
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ael Clark
SiFive Freed
o
m U Series RISC-V Machine
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
M
i
chae
l
C
lark
SiF
i
ve Fre
e
dom E S
e
ri
e
s
RISC-V
M
a
c
h
ine
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael
Clar
k
S
iFi
v
e RISC-V PRCI Block
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-03-06
Michael Clark
SiFive RISC
-
V
UART
D
evice
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Cla
r
k
RISC-V VirtIO Machine
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l
Clark
S
i
Five
R
ISC-V Tes
t
Finis
h
e
r
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ael Clark
R
I
SC-V
Spike
Machines
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
Si
F
ive R
I
SC-V PLIC
Block
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ael Cla
r
k
SiFi
v
e RISC-
V
C
L
INT Block
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
M
i
chael Clark
RISC
-
V
HART
A
rray
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Cla
r
k
RIS
C
-
V HTIF Console
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
l
a
rk
Ad
d
sy
m
bol table callback in
t
e
r
face
to load_e
l
f
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
M
i
chael Cla
r
k
RISC-V L
i
nux User Emulation
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michae
l
Clark
RI
S
C-V Physical Memory P
r
otection
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-03-06
Michael Clark
RIS
C
-V TCG Cod
e
Generation
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
hael Clark
RISC-V GDB St
u
b
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael
Clark
RISC-V FPU Support
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mich
a
el Clark
RISC-V CPU Helpers
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
a
e
l Clark
RISC-V Disassemble
r
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michae
l
C
l
a
rk
RISC-V CPU Core Definition
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
R
ISC-V ELF
Mach
i
ne Defi
n
ition
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael C
l
ark
RIS
C
-V
M
aintai
n
e
rs
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree