| commit | 85ba724fd6ad51360d61045476fd96d25dc15b9a | |
| author | Michael Clark <mjc@sifive.com> | |
| Sun, 8 Apr 2018 21:25:25 +0000 (9 09:25 +1200) | ||
| committer | Palmer Dabbelt <palmer@sifive.com> | |
| Wed, 17 Oct 2018 20:02:09 +0000 (17 13:02 -0700) | ||
| tree | 5be393f199a93feefd3a5aa2d35bc9e22cf41d45 | treesnapshot (tar.gz zip) |
| parent | 09558375a634e17cea6cfbfec883ac2376d2dc7f | commitdiff |
RISC-V: Allow setting and clearing multiple irqs
Change the API of riscv_set_local_interrupt to take a
write mask and value to allow setting and clearing of
multiple local interrupts atomically in a single call.
Rename the new function to riscv_cpu_update_mip.
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Change the API of riscv_set_local_interrupt to take a
write mask and value to allow setting and clearing of
multiple local interrupts atomically in a single call.
Rename the new function to riscv_cpu_update_mip.
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| hw/riscv/sifive_clint.c | diffblobblamehistory | |
| hw/riscv/sifive_plic.c | diffblobblamehistory | |
| target/riscv/cpu.h | diffblobblamehistory | |
| target/riscv/op_helper.c | diffblobblamehistory |