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2022-07-27	Palmer Dabbelt	RISC-V: Allow both Zmmul and M Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2022-03-31	Palmer Dabbelt	target/riscv: Avoid leaking "no translation" TLB entries Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2020-03-05	Palmer Dabbelt	RISC-V: Add a missing "," in riscv_excp_names Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2019-11-25	Palmer Dabbelt	RISC-V: virt: This is a "sifive,test1" test finisher Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2019-11-01	Palmer Dabbelt	MAINTAINERS: Change to my personal email address Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>	commit \| commitdiff \| tree
2019-10-28	Palmer Dabbelt	RISC-V: Implement cpu_do_transaction_failed Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Palmer Dabbelt	RISC-V: Handle bus errors in the page table walker Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Palmer Dabbelt	RISC-V: Add support for the Zicsr extension Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Palmer Dabbelt	RISC-V: Add support for the Zifencei extension Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Palmer Dabbelt	RISC-V: Fix a memory leak when realizing a sifive_e Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-22	Palmer Dabbelt	target/riscv: Zero extend the inputs of divuw and remuw Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Palmer Dabbelt	MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-12-21	Palmer Dabbelt	MAINTAINERS: Mark RISC-V as Supported Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-11-13	Palmer Dabbelt	RISC-V: Respect fences for user-only emulators Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-30	Palmer Dabbelt	Add qemu-riscv@nongnu.org as the RISC-V list Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-30	Palmer Dabbelt	Add Alistair as a RISC-V Maintainer Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree

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