| commit | 766a9814749e35b1e4537f8a6ba71ab202ce5709 | |
| author | Zhenzhong Duan <zhenzhong.duan@intel.com> | |
| Wed, 15 Jun 2022 03:45:01 +0000 (15 11:45 +0800) | ||
| committer | Paolo Bonzini <pbonzini@redhat.com> | |
| Wed, 15 Jun 2022 09:11:37 +0000 (15 11:11 +0200) | ||
| tree | fa602bb7f87d2cc43dddada597de63f0b9074cb6 | treesnapshot (tar.gz zip) |
| parent | aa4f3a3b880e9b2109e4b0baeb36cce3e1732159 | commitdiff |
q35：Enable TSEG only when G_SMRAME and TSEG_EN both enabled
According to spec:
"TSEG Enable (T_EN): Enabling of SMRAM memory for Extended SMRAM space
only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG is enabled to appear
in the appropriate physical address space. Note that once D_LCK is set,
this bit becomes read only."
Changed to match the spec description.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Message-Id: <20220615034501.2733802-1-zhenzhong.duan@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
According to spec:
"TSEG Enable (T_EN): Enabling of SMRAM memory for Extended SMRAM space
only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG is enabled to appear
in the appropriate physical address space. Note that once D_LCK is set,
this bit becomes read only."
Changed to match the spec description.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Message-Id: <20220615034501.2733802-1-zhenzhong.duan@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| hw/pci-host/q35.c | diffblobblamehistory |