From 766a9814749e35b1e4537f8a6ba71ab202ce5709 Mon Sep 17 00:00:00 2001 From: Zhenzhong Duan Date: Wed, 15 Jun 2022 11:45:01 +0800 Subject: [PATCH] =?utf8?q?q35=EF=BC=9AEnable=20TSEG=20only=20when=20G=5FSM?= =?utf8?q?RAME=20and=20TSEG=5FEN=20both=20enabled?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit According to spec: "TSEG Enable (T_EN): Enabling of SMRAM memory for Extended SMRAM space only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Note that once D_LCK is set, this bit becomes read only." Changed to match the spec description. Signed-off-by: Zhenzhong Duan Message-Id: <20220615034501.2733802-1-zhenzhong.duan@intel.com> Signed-off-by: Paolo Bonzini --- hw/pci-host/q35.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index ab5a47aff5..20da121374 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -379,7 +379,8 @@ static void mch_update_smram(MCHPCIState *mch) memory_region_set_enabled(&mch->high_smram, false); } - if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { + if ((pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) && + (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME)) { switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: -- 2.11.4.GIT