| commit | 7035b8420fa52e8c94cf4317c0f88c1b73ced28d | |
| author | Yu Li <liyu.yukiteru@bytedance.com> | |
| Tue, 8 Feb 2022 13:07:23 +0000 (8 21:07 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 16 Feb 2022 02:25:52 +0000 (16 12:25 +1000) | ||
| tree | d62e9417d9ceae0f0827094bcaa38d46b834021b | treesnapshot (tar.gz zip) |
| parent | bbce8ba8e6bddcd77abef4810a9426bad9939f3b | commitdiff |
docs/system: riscv: Update description of CPU
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| docs/system/riscv/virt.rst | diffblobblamehistory |