| commit | 1611956bce06b0721ea949e24c089ef22967672a | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Sat, 22 Jan 2022 18:24:39 +0000 (22 18:24 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 28 Jan 2022 14:29:47 +0000 (28 14:29 +0000) | ||
| tree | f46ff64a87548e4e64a71eaddc6e4d6c0092ad57 | treesnapshot (tar.gz zip) |
| parent | d7d19c0aeb7d657c76c88913744ff53fc7e24c23 | commitdiff |
hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported
The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate
that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable
LPIs (as opposed to allowing LPIs to be enabled but not subsequently
disabled). Our implementation permits this, so advertise it
by setting CES to 1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-10-peter.maydell@linaro.org
The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate
that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable
LPIs (as opposed to allowing LPIs to be enabled but not subsequently
disabled). Our implementation permits this, so advertise it
by setting CES to 1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-10-peter.maydell@linaro.org
| hw/intc/arm_gicv3_common.c | diffblobblamehistory | |
| hw/intc/gicv3_internal.h | diffblobblamehistory |