From 1611956bce06b0721ea949e24c089ef22967672a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sat, 22 Jan 2022 18:24:39 +0000 Subject: [PATCH] hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable LPIs (as opposed to allowing LPIs to be enabled but not subsequently disabled). Our implementation permits this, so advertise it by setting CES to 1. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220122182444.724087-10-peter.maydell@linaro.org --- hw/intc/arm_gicv3_common.c | 4 ++++ hw/intc/gicv3_internal.h | 1 + 2 files changed, 5 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 579aa0cb9e..4ca5ae9bc5 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -429,6 +429,10 @@ static void arm_gicv3_common_reset(DeviceState *dev) cs->level = 0; cs->gicr_ctlr = 0; + if (s->lpi_enable) { + /* Our implementation supports clearing GICR_CTLR.EnableLPIs */ + cs->gicr_ctlr |= GICR_CTLR_CES; + } cs->gicr_statusr[GICV3_S] = 0; cs->gicr_statusr[GICV3_NS] = 0; cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep; diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 5394266aaf..a316f6c58a 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -110,6 +110,7 @@ #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) #define GICR_CTLR_ENABLE_LPIS (1U << 0) +#define GICR_CTLR_CES (1U << 1) #define GICR_CTLR_RWP (1U << 3) #define GICR_CTLR_DPG0 (1U << 24) #define GICR_CTLR_DPG1NS (1U << 25) -- 2.11.4.GIT