target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "exec/exec-all.h"
  26 #include "qapi/error.h"
  27 #include "qemu/error-report.h"
  28 #include "hw/qdev-properties.h"
  29 #include "migration/vmstate.h"
  30 #include "fpu/softfloat-helpers.h"
  31
  32 /* RISC-V CPU definitions */
  33
  34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  35
  36 const char * const riscv_int_regnames[] = {
  37   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  38   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  39   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  40   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  41   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  42 };
  43
  44 const char * const riscv_fpr_regnames[] = {
  45   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  46   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  47   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  48   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  49   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  50   "f30/ft10", "f31/ft11"
  51 };
  52
  53 const char * const riscv_excp_names[] = {
  54     "misaligned_fetch",
  55     "fault_fetch",
  56     "illegal_instruction",
  57     "breakpoint",
  58     "misaligned_load",
  59     "fault_load",
  60     "misaligned_store",
  61     "fault_store",
  62     "user_ecall",
  63     "supervisor_ecall",
  64     "hypervisor_ecall",
  65     "machine_ecall",
  66     "exec_page_fault",
  67     "load_page_fault",
  68     "reserved",
  69     "store_page_fault",
  70     "reserved",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "guest_exec_page_fault",
  75     "guest_load_page_fault",
  76     "reserved",
  77     "guest_store_page_fault",
  78 };
  79
  80 const char * const riscv_intr_names[] = {
  81     "u_software",
  82     "s_software",
  83     "vs_software",
  84     "m_software",
  85     "u_timer",
  86     "s_timer",
  87     "vs_timer",
  88     "m_timer",
  89     "u_external",
  90     "vs_external",
  91     "h_external",
  92     "m_external",
  93     "reserved",
  94     "reserved",
  95     "reserved",
  96     "reserved"
  97 };
  98
  99 static void set_misa(CPURISCVState *env, target_ulong misa)
 100 {
 101     env->misa_mask = env->misa = misa;
 102 }
 103
 104 static void set_priv_version(CPURISCVState *env, int priv_ver)
 105 {
 106     env->priv_ver = priv_ver;
 107 }
 108
 109 static void set_vext_version(CPURISCVState *env, int vext_ver)
 110 {
 111     env->vext_ver = vext_ver;
 112 }
 113
 114 static void set_feature(CPURISCVState *env, int feature)
 115 {
 116     env->features |= (1ULL << feature);
 117 }
 118
 119 static void set_resetvec(CPURISCVState *env, int resetvec)
 120 {
 121 #ifndef CONFIG_USER_ONLY
 122     env->resetvec = resetvec;
 123 #endif
 124 }
 125
 126 static void riscv_any_cpu_init(Object *obj)
 127 {
 128     CPURISCVState *env = &RISCV_CPU(obj)->env;
 129     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 130     set_priv_version(env, PRIV_VERSION_1_11_0);
 131     set_resetvec(env, DEFAULT_RSTVEC);
 132 }
 133
 134 static void riscv_base_cpu_init(Object *obj)
 135 {
 136     CPURISCVState *env = &RISCV_CPU(obj)->env;
 137     /* We set this in the realise function */
 138     set_misa(env, 0);
 139     set_resetvec(env, DEFAULT_RSTVEC);
 140 }
 141
 142 static void rvxx_sifive_u_cpu_init(Object *obj)
 143 {
 144     CPURISCVState *env = &RISCV_CPU(obj)->env;
 145     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 146     set_priv_version(env, PRIV_VERSION_1_10_0);
 147     set_resetvec(env, 0x1004);
 148 }
 149
 150 static void rvxx_sifive_e_cpu_init(Object *obj)
 151 {
 152     CPURISCVState *env = &RISCV_CPU(obj)->env;
 153     set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
 154     set_priv_version(env, PRIV_VERSION_1_10_0);
 155     set_resetvec(env, 0x1004);
 156     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 157 }
 158
 159 #if defined(TARGET_RISCV32)
 160
 161 static void rv32_ibex_cpu_init(Object *obj)
 162 {
 163     CPURISCVState *env = &RISCV_CPU(obj)->env;
 164     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
 165     set_priv_version(env, PRIV_VERSION_1_10_0);
 166     set_resetvec(env, 0x8090);
 167     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 168 }
 169
 170 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 171 {
 172     CPURISCVState *env = &RISCV_CPU(obj)->env;
 173     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 174     set_priv_version(env, PRIV_VERSION_1_10_0);
 175     set_resetvec(env, DEFAULT_RSTVEC);
 176     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 177 }
 178
 179 #endif
 180
 181 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 182 {
 183     ObjectClass *oc;
 184     char *typename;
 185     char **cpuname;
 186
 187     cpuname = g_strsplit(cpu_model, ",", 1);
 188     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 189     oc = object_class_by_name(typename);
 190     g_strfreev(cpuname);
 191     g_free(typename);
 192     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 193         object_class_is_abstract(oc)) {
 194         return NULL;
 195     }
 196     return oc;
 197 }
 198
 199 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 200 {
 201     RISCVCPU *cpu = RISCV_CPU(cs);
 202     CPURISCVState *env = &cpu->env;
 203     int i;
 204
 205 #if !defined(CONFIG_USER_ONLY)
 206     if (riscv_has_ext(env, RVH)) {
 207         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 208     }
 209 #endif
 210     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 211 #ifndef CONFIG_USER_ONLY
 212     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 213     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
 214 #ifdef TARGET_RISCV32
 215     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
 216 #endif
 217     if (riscv_has_ext(env, RVH)) {
 218         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 219         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
 220     }
 221     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 222     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 223     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 224     if (riscv_has_ext(env, RVH)) {
 225         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 226     }
 227     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 228     if (riscv_has_ext(env, RVH)) {
 229         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 230     }
 231     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 232     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 233     if (riscv_has_ext(env, RVH)) {
 234         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 235     }
 236     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 237     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 238     if (riscv_has_ext(env, RVH)) {
 239         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 240     }
 241     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 242     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 243     if (riscv_has_ext(env, RVH)) {
 244         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 245     }
 246     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
 247     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
 248     if (riscv_has_ext(env, RVH)) {
 249         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
 250         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 251     }
 252 #endif
 253
 254     for (i = 0; i < 32; i++) {
 255         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 256                      riscv_int_regnames[i], env->gpr[i]);
 257         if ((i & 3) == 3) {
 258             qemu_fprintf(f, "\n");
 259         }
 260     }
 261     if (flags & CPU_DUMP_FPU) {
 262         for (i = 0; i < 32; i++) {
 263             qemu_fprintf(f, " %s %016" PRIx64,
 264                          riscv_fpr_regnames[i], env->fpr[i]);
 265             if ((i & 3) == 3) {
 266                 qemu_fprintf(f, "\n");
 267             }
 268         }
 269     }
 270 }
 271
 272 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 273 {
 274     RISCVCPU *cpu = RISCV_CPU(cs);
 275     CPURISCVState *env = &cpu->env;
 276     env->pc = value;
 277 }
 278
 279 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
 280 {
 281     RISCVCPU *cpu = RISCV_CPU(cs);
 282     CPURISCVState *env = &cpu->env;
 283     env->pc = tb->pc;
 284 }
 285
 286 static bool riscv_cpu_has_work(CPUState *cs)
 287 {
 288 #ifndef CONFIG_USER_ONLY
 289     RISCVCPU *cpu = RISCV_CPU(cs);
 290     CPURISCVState *env = &cpu->env;
 291     /*
 292      * Definition of the WFI instruction requires it to ignore the privilege
 293      * mode and delegation registers, but respect individual enables
 294      */
 295     return (env->mip & env->mie) != 0;
 296 #else
 297     return true;
 298 #endif
 299 }
 300
 301 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 302                           target_ulong *data)
 303 {
 304     env->pc = data[0];
 305 }
 306
 307 static void riscv_cpu_reset(DeviceState *dev)
 308 {
 309     CPUState *cs = CPU(dev);
 310     RISCVCPU *cpu = RISCV_CPU(cs);
 311     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 312     CPURISCVState *env = &cpu->env;
 313
 314     mcc->parent_reset(dev);
 315 #ifndef CONFIG_USER_ONLY
 316     env->priv = PRV_M;
 317     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 318     env->mcause = 0;
 319     env->pc = env->resetvec;
 320 #endif
 321     cs->exception_index = EXCP_NONE;
 322     env->load_res = -1;
 323     set_default_nan_mode(1, &env->fp_status);
 324 }
 325
 326 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 327 {
 328 #if defined(TARGET_RISCV32)
 329     info->print_insn = print_insn_riscv32;
 330 #elif defined(TARGET_RISCV64)
 331     info->print_insn = print_insn_riscv64;
 332 #endif
 333 }
 334
 335 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 336 {
 337     CPUState *cs = CPU(dev);
 338     RISCVCPU *cpu = RISCV_CPU(dev);
 339     CPURISCVState *env = &cpu->env;
 340     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 341     int priv_version = PRIV_VERSION_1_11_0;
 342     int vext_version = VEXT_VERSION_0_07_1;
 343     target_ulong target_misa = 0;
 344     Error *local_err = NULL;
 345
 346     cpu_exec_realizefn(cs, &local_err);
 347     if (local_err != NULL) {
 348         error_propagate(errp, local_err);
 349         return;
 350     }
 351
 352     if (cpu->cfg.priv_spec) {
 353         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 354             priv_version = PRIV_VERSION_1_11_0;
 355         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 356             priv_version = PRIV_VERSION_1_10_0;
 357         } else {
 358             error_setg(errp,
 359                        "Unsupported privilege spec version '%s'",
 360                        cpu->cfg.priv_spec);
 361             return;
 362         }
 363     }
 364
 365     set_priv_version(env, priv_version);
 366     set_vext_version(env, vext_version);
 367
 368     if (cpu->cfg.mmu) {
 369         set_feature(env, RISCV_FEATURE_MMU);
 370     }
 371
 372     if (cpu->cfg.pmp) {
 373         set_feature(env, RISCV_FEATURE_PMP);
 374     }
 375
 376     /* If misa isn't set (rv32 and rv64 machines) set it here */
 377     if (!env->misa) {
 378         /* Do some ISA extension error checking */
 379         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 380             error_setg(errp,
 381                        "I and E extensions are incompatible");
 382                        return;
 383        }
 384
 385         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 386             error_setg(errp,
 387                        "Either I or E extension must be set");
 388                        return;
 389        }
 390
 391        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 392                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 393                                cpu->cfg.ext_d)) {
 394             warn_report("Setting G will also set IMAFD");
 395             cpu->cfg.ext_i = true;
 396             cpu->cfg.ext_m = true;
 397             cpu->cfg.ext_a = true;
 398             cpu->cfg.ext_f = true;
 399             cpu->cfg.ext_d = true;
 400         }
 401
 402         /* Set the ISA extensions, checks should have happened above */
 403         if (cpu->cfg.ext_i) {
 404             target_misa |= RVI;
 405         }
 406         if (cpu->cfg.ext_e) {
 407             target_misa |= RVE;
 408         }
 409         if (cpu->cfg.ext_m) {
 410             target_misa |= RVM;
 411         }
 412         if (cpu->cfg.ext_a) {
 413             target_misa |= RVA;
 414         }
 415         if (cpu->cfg.ext_f) {
 416             target_misa |= RVF;
 417         }
 418         if (cpu->cfg.ext_d) {
 419             target_misa |= RVD;
 420         }
 421         if (cpu->cfg.ext_c) {
 422             target_misa |= RVC;
 423         }
 424         if (cpu->cfg.ext_s) {
 425             target_misa |= RVS;
 426         }
 427         if (cpu->cfg.ext_u) {
 428             target_misa |= RVU;
 429         }
 430         if (cpu->cfg.ext_h) {
 431             target_misa |= RVH;
 432         }
 433         if (cpu->cfg.ext_v) {
 434             target_misa |= RVV;
 435             if (!is_power_of_2(cpu->cfg.vlen)) {
 436                 error_setg(errp,
 437                         "Vector extension VLEN must be power of 2");
 438                 return;
 439             }
 440             if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 441                 error_setg(errp,
 442                         "Vector extension implementation only supports VLEN "
 443                         "in the range [128, %d]", RV_VLEN_MAX);
 444                 return;
 445             }
 446             if (!is_power_of_2(cpu->cfg.elen)) {
 447                 error_setg(errp,
 448                         "Vector extension ELEN must be power of 2");
 449                 return;
 450             }
 451             if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
 452                 error_setg(errp,
 453                         "Vector extension implementation only supports ELEN "
 454                         "in the range [8, 64]");
 455                 return;
 456             }
 457             if (cpu->cfg.vext_spec) {
 458                 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
 459                     vext_version = VEXT_VERSION_0_07_1;
 460                 } else {
 461                     error_setg(errp,
 462                            "Unsupported vector spec version '%s'",
 463                            cpu->cfg.vext_spec);
 464                     return;
 465                 }
 466             } else {
 467                 qemu_log("vector verison is not specified, "
 468                         "use the default value v0.7.1\n");
 469             }
 470             set_vext_version(env, vext_version);
 471         }
 472
 473         set_misa(env, RVXLEN | target_misa);
 474     }
 475
 476     riscv_cpu_register_gdb_regs_for_features(cs);
 477
 478     qemu_init_vcpu(cs);
 479     cpu_reset(cs);
 480
 481     mcc->parent_realize(dev, errp);
 482 }
 483
 484 static void riscv_cpu_init(Object *obj)
 485 {
 486     RISCVCPU *cpu = RISCV_CPU(obj);
 487
 488     cpu_set_cpustate_pointers(cpu);
 489 }
 490
 491 #ifndef CONFIG_USER_ONLY
 492 static const VMStateDescription vmstate_riscv_cpu = {
 493     .name = "cpu",
 494     .unmigratable = 1,
 495 };
 496 #endif
 497
 498 static Property riscv_cpu_properties[] = {
 499     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 500     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 501     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 502     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 503     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 504     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 505     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 506     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 507     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 508     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 509     /* This is experimental so mark with 'x-' */
 510     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 511     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
 512     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 513     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 514     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 515     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 516     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
 517     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 518     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 519     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 520     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 521     DEFINE_PROP_END_OF_LIST(),
 522 };
 523
 524 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 525 {
 526     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 527     CPUClass *cc = CPU_CLASS(c);
 528     DeviceClass *dc = DEVICE_CLASS(c);
 529
 530     device_class_set_parent_realize(dc, riscv_cpu_realize,
 531                                     &mcc->parent_realize);
 532
 533     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 534
 535     cc->class_by_name = riscv_cpu_class_by_name;
 536     cc->has_work = riscv_cpu_has_work;
 537     cc->do_interrupt = riscv_cpu_do_interrupt;
 538     cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
 539     cc->dump_state = riscv_cpu_dump_state;
 540     cc->set_pc = riscv_cpu_set_pc;
 541     cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
 542     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 543     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 544     cc->gdb_num_core_regs = 33;
 545 #if defined(TARGET_RISCV32)
 546     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 547 #elif defined(TARGET_RISCV64)
 548     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 549 #endif
 550     cc->gdb_stop_before_watchpoint = true;
 551     cc->disas_set_info = riscv_cpu_disas_set_info;
 552 #ifndef CONFIG_USER_ONLY
 553     cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
 554     cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
 555     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 556     /* For now, mark unmigratable: */
 557     cc->vmsd = &vmstate_riscv_cpu;
 558 #endif
 559 #ifdef CONFIG_TCG
 560     cc->tcg_initialize = riscv_translate_init;
 561     cc->tlb_fill = riscv_cpu_tlb_fill;
 562 #endif
 563     device_class_set_props(dc, riscv_cpu_properties);
 564 }
 565
 566 char *riscv_isa_string(RISCVCPU *cpu)
 567 {
 568     int i;
 569     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 570     char *isa_str = g_new(char, maxlen);
 571     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 572     for (i = 0; i < sizeof(riscv_exts); i++) {
 573         if (cpu->env.misa & RV(riscv_exts[i])) {
 574             *p++ = qemu_tolower(riscv_exts[i]);
 575         }
 576     }
 577     *p = '\0';
 578     return isa_str;
 579 }
 580
 581 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 582 {
 583     ObjectClass *class_a = (ObjectClass *)a;
 584     ObjectClass *class_b = (ObjectClass *)b;
 585     const char *name_a, *name_b;
 586
 587     name_a = object_class_get_name(class_a);
 588     name_b = object_class_get_name(class_b);
 589     return strcmp(name_a, name_b);
 590 }
 591
 592 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 593 {
 594     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 595     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 596
 597     qemu_printf("%.*s\n", len, typename);
 598 }
 599
 600 void riscv_cpu_list(void)
 601 {
 602     GSList *list;
 603
 604     list = object_class_get_list(TYPE_RISCV_CPU, false);
 605     list = g_slist_sort(list, riscv_cpu_list_compare);
 606     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 607     g_slist_free(list);
 608 }
 609
 610 #define DEFINE_CPU(type_name, initfn)      \
 611     {                                      \
 612         .name = type_name,                 \
 613         .parent = TYPE_RISCV_CPU,          \
 614         .instance_init = initfn            \
 615     }
 616
 617 static const TypeInfo riscv_cpu_type_infos[] = {
 618     {
 619         .name = TYPE_RISCV_CPU,
 620         .parent = TYPE_CPU,
 621         .instance_size = sizeof(RISCVCPU),
 622         .instance_init = riscv_cpu_init,
 623         .abstract = true,
 624         .class_size = sizeof(RISCVCPUClass),
 625         .class_init = riscv_cpu_class_init,
 626     },
 627     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 628 #if defined(TARGET_RISCV32)
 629     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base_cpu_init),
 630     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 631     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rvxx_sifive_e_cpu_init),
 632     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
 633     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rvxx_sifive_u_cpu_init),
 634 #elif defined(TARGET_RISCV64)
 635     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base_cpu_init),
 636     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rvxx_sifive_e_cpu_init),
 637     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rvxx_sifive_u_cpu_init),
 638 #endif
 639 };
 640
 641 DEFINE_TYPES(riscv_cpu_type_infos)