2 #include "host-utils.h"
4 #if !defined(CONFIG_USER_ONLY)
5 #include "softmmu_exec.h"
6 #endif /* !defined(CONFIG_USER_ONLY) */
10 //#define DEBUG_UNALIGNED
11 //#define DEBUG_UNASSIGNED
14 //#define DEBUG_PSTATE
17 #define DPRINTF_MMU(fmt, ...) \
18 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
20 #define DPRINTF_MMU(fmt, ...) do {} while (0)
24 #define DPRINTF_MXCC(fmt, ...) \
25 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
27 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
31 #define DPRINTF_ASI(fmt, ...) \
32 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
36 #define DPRINTF_PSTATE(fmt, ...) \
37 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
39 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
44 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
46 #define AM_CHECK(env1) (1)
50 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
51 // Calculates TSB pointer value for fault page size 8k or 64k
52 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
53 uint64_t tag_access_register
,
56 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
57 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
58 int tsb_size
= tsb_register
& 0xf;
60 // discard lower 13 bits which hold tag access context
61 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
64 uint64_t tsb_base_mask
= ~0x1fffULL
;
65 uint64_t va
= tag_access_va
;
67 // move va bits to correct position
68 if (page_size
== 8*1024) {
70 } else if (page_size
== 64*1024) {
75 tsb_base_mask
<<= tsb_size
;
78 // calculate tsb_base mask and adjust va if split is in use
80 if (page_size
== 8*1024) {
81 va
&= ~(1ULL << (13 + tsb_size
));
82 } else if (page_size
== 64*1024) {
83 va
|= (1ULL << (13 + tsb_size
));
88 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
91 // Calculates tag target register value by reordering bits
92 // in tag access register
93 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
95 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
98 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
99 uint64_t tlb_tag
, uint64_t tlb_tte
,
102 target_ulong mask
, size
, va
, offset
;
104 // flush page range if translation is valid
105 if (TTE_IS_VALID(tlb
->tte
)) {
107 mask
= 0xffffffffffffe000ULL
;
108 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
111 va
= tlb
->tag
& mask
;
113 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
114 tlb_flush_page(env1
, va
+ offset
);
122 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
123 const char* strmmu
, CPUState
*env1
)
128 for (i
= 0; i
< 64; i
++) {
129 if (TTE_IS_VALID(tlb
[i
].tte
)) {
131 mask
= 0xffffffffffffe000ULL
;
132 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
134 if ((demap_addr
& mask
) == (tlb
[i
].tag
& mask
)) {
135 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
137 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
147 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
148 uint64_t tlb_tag
, uint64_t tlb_tte
,
149 const char* strmmu
, CPUState
*env1
)
151 unsigned int i
, replace_used
;
153 // Try replacing invalid entry
154 for (i
= 0; i
< 64; i
++) {
155 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
156 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
158 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
165 // All entries are valid, try replacing unlocked entry
167 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
169 // Used entries are not replaced on first pass
171 for (i
= 0; i
< 64; i
++) {
172 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
174 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
176 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
177 strmmu
, (replace_used
?"used":"unused"), i
);
184 // Now reset used bit and search for unused entries again
186 for (i
= 0; i
< 64; i
++) {
187 TTE_SET_UNUSED(tlb
[i
].tte
);
192 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
199 static inline void address_mask(CPUState
*env1
, target_ulong
*addr
)
201 #ifdef TARGET_SPARC64
203 *addr
&= 0xffffffffULL
;
207 static void raise_exception(int tt
)
209 env
->exception_index
= tt
;
213 void HELPER(raise_exception
)(int tt
)
218 static inline void set_cwp(int new_cwp
)
220 cpu_set_cwp(env
, new_cwp
);
223 void helper_check_align(target_ulong addr
, uint32_t align
)
226 #ifdef DEBUG_UNALIGNED
227 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
228 "\n", addr
, env
->pc
);
230 raise_exception(TT_UNALIGNED
);
234 #define F_HELPER(name, p) void helper_f##name##p(void)
236 #define F_BINOP(name) \
237 float32 helper_f ## name ## s (float32 src1, float32 src2) \
239 return float32_ ## name (src1, src2, &env->fp_status); \
243 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
247 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
256 void helper_fsmuld(float32 src1
, float32 src2
)
258 DT0
= float64_mul(float32_to_float64(src1
, &env
->fp_status
),
259 float32_to_float64(src2
, &env
->fp_status
),
263 void helper_fdmulq(void)
265 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
266 float64_to_float128(DT1
, &env
->fp_status
),
270 float32
helper_fnegs(float32 src
)
272 return float32_chs(src
);
275 #ifdef TARGET_SPARC64
278 DT0
= float64_chs(DT1
);
283 QT0
= float128_chs(QT1
);
287 /* Integer to float conversion. */
288 float32
helper_fitos(int32_t src
)
290 return int32_to_float32(src
, &env
->fp_status
);
293 void helper_fitod(int32_t src
)
295 DT0
= int32_to_float64(src
, &env
->fp_status
);
298 void helper_fitoq(int32_t src
)
300 QT0
= int32_to_float128(src
, &env
->fp_status
);
303 #ifdef TARGET_SPARC64
304 float32
helper_fxtos(void)
306 return int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
311 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
316 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
321 /* floating point conversion */
322 float32
helper_fdtos(void)
324 return float64_to_float32(DT1
, &env
->fp_status
);
327 void helper_fstod(float32 src
)
329 DT0
= float32_to_float64(src
, &env
->fp_status
);
332 float32
helper_fqtos(void)
334 return float128_to_float32(QT1
, &env
->fp_status
);
337 void helper_fstoq(float32 src
)
339 QT0
= float32_to_float128(src
, &env
->fp_status
);
342 void helper_fqtod(void)
344 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
347 void helper_fdtoq(void)
349 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
352 /* Float to integer conversion. */
353 int32_t helper_fstoi(float32 src
)
355 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
358 int32_t helper_fdtoi(void)
360 return float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
363 int32_t helper_fqtoi(void)
365 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
368 #ifdef TARGET_SPARC64
369 void helper_fstox(float32 src
)
371 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(src
, &env
->fp_status
);
374 void helper_fdtox(void)
376 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
379 void helper_fqtox(void)
381 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
384 void helper_faligndata(void)
388 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
389 /* on many architectures a shift of 64 does nothing */
390 if ((env
->gsr
& 7) != 0) {
391 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
393 *((uint64_t *)&DT0
) = tmp
;
396 #ifdef HOST_WORDS_BIGENDIAN
397 #define VIS_B64(n) b[7 - (n)]
398 #define VIS_W64(n) w[3 - (n)]
399 #define VIS_SW64(n) sw[3 - (n)]
400 #define VIS_L64(n) l[1 - (n)]
401 #define VIS_B32(n) b[3 - (n)]
402 #define VIS_W32(n) w[1 - (n)]
404 #define VIS_B64(n) b[n]
405 #define VIS_W64(n) w[n]
406 #define VIS_SW64(n) sw[n]
407 #define VIS_L64(n) l[n]
408 #define VIS_B32(n) b[n]
409 #define VIS_W32(n) w[n]
427 void helper_fpmerge(void)
434 // Reverse calculation order to handle overlap
435 d
.VIS_B64(7) = s
.VIS_B64(3);
436 d
.VIS_B64(6) = d
.VIS_B64(3);
437 d
.VIS_B64(5) = s
.VIS_B64(2);
438 d
.VIS_B64(4) = d
.VIS_B64(2);
439 d
.VIS_B64(3) = s
.VIS_B64(1);
440 d
.VIS_B64(2) = d
.VIS_B64(1);
441 d
.VIS_B64(1) = s
.VIS_B64(0);
442 //d.VIS_B64(0) = d.VIS_B64(0);
447 void helper_fmul8x16(void)
456 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
457 if ((tmp & 0xff) > 0x7f) \
459 d.VIS_W64(r) = tmp >> 8;
470 void helper_fmul8x16al(void)
479 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
480 if ((tmp & 0xff) > 0x7f) \
482 d.VIS_W64(r) = tmp >> 8;
493 void helper_fmul8x16au(void)
502 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
503 if ((tmp & 0xff) > 0x7f) \
505 d.VIS_W64(r) = tmp >> 8;
516 void helper_fmul8sux16(void)
525 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
526 if ((tmp & 0xff) > 0x7f) \
528 d.VIS_W64(r) = tmp >> 8;
539 void helper_fmul8ulx16(void)
548 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
549 if ((tmp & 0xff) > 0x7f) \
551 d.VIS_W64(r) = tmp >> 8;
562 void helper_fmuld8sux16(void)
571 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
572 if ((tmp & 0xff) > 0x7f) \
576 // Reverse calculation order to handle overlap
584 void helper_fmuld8ulx16(void)
593 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
594 if ((tmp & 0xff) > 0x7f) \
598 // Reverse calculation order to handle overlap
606 void helper_fexpand(void)
611 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
613 d
.VIS_W64(0) = s
.VIS_B32(0) << 4;
614 d
.VIS_W64(1) = s
.VIS_B32(1) << 4;
615 d
.VIS_W64(2) = s
.VIS_B32(2) << 4;
616 d
.VIS_W64(3) = s
.VIS_B32(3) << 4;
621 #define VIS_HELPER(name, F) \
622 void name##16(void) \
629 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
630 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
631 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
632 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
637 uint32_t name##16s(uint32_t src1, uint32_t src2) \
644 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
645 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
650 void name##32(void) \
657 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
658 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
663 uint32_t name##32s(uint32_t src1, uint32_t src2) \
675 #define FADD(a, b) ((a) + (b))
676 #define FSUB(a, b) ((a) - (b))
677 VIS_HELPER(helper_fpadd
, FADD
)
678 VIS_HELPER(helper_fpsub
, FSUB
)
680 #define VIS_CMPHELPER(name, F) \
681 void name##16(void) \
688 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
689 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
690 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
691 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
696 void name##32(void) \
703 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
704 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
709 #define FCMPGT(a, b) ((a) > (b))
710 #define FCMPEQ(a, b) ((a) == (b))
711 #define FCMPLE(a, b) ((a) <= (b))
712 #define FCMPNE(a, b) ((a) != (b))
714 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
715 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
716 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
717 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
720 void helper_check_ieee_exceptions(void)
724 status
= get_float_exception_flags(&env
->fp_status
);
726 /* Copy IEEE 754 flags into FSR */
727 if (status
& float_flag_invalid
)
729 if (status
& float_flag_overflow
)
731 if (status
& float_flag_underflow
)
733 if (status
& float_flag_divbyzero
)
735 if (status
& float_flag_inexact
)
738 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
739 /* Unmasked exception, generate a trap */
740 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
741 raise_exception(TT_FP_EXCP
);
743 /* Accumulate exceptions */
744 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
749 void helper_clear_float_exceptions(void)
751 set_float_exception_flags(0, &env
->fp_status
);
754 float32
helper_fabss(float32 src
)
756 return float32_abs(src
);
759 #ifdef TARGET_SPARC64
760 void helper_fabsd(void)
762 DT0
= float64_abs(DT1
);
765 void helper_fabsq(void)
767 QT0
= float128_abs(QT1
);
771 float32
helper_fsqrts(float32 src
)
773 return float32_sqrt(src
, &env
->fp_status
);
776 void helper_fsqrtd(void)
778 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
781 void helper_fsqrtq(void)
783 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
786 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
787 void glue(helper_, name) (void) \
789 target_ulong new_fsr; \
791 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
792 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
793 case float_relation_unordered: \
794 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
795 if ((env->fsr & FSR_NVM) || TRAP) { \
796 env->fsr |= new_fsr; \
797 env->fsr |= FSR_NVC; \
798 env->fsr |= FSR_FTT_IEEE_EXCP; \
799 raise_exception(TT_FP_EXCP); \
801 env->fsr |= FSR_NVA; \
804 case float_relation_less: \
805 new_fsr = FSR_FCC0 << FS; \
807 case float_relation_greater: \
808 new_fsr = FSR_FCC1 << FS; \
814 env->fsr |= new_fsr; \
816 #define GEN_FCMPS(name, size, FS, TRAP) \
817 void glue(helper_, name)(float32 src1, float32 src2) \
819 target_ulong new_fsr; \
821 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
822 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
823 case float_relation_unordered: \
824 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
825 if ((env->fsr & FSR_NVM) || TRAP) { \
826 env->fsr |= new_fsr; \
827 env->fsr |= FSR_NVC; \
828 env->fsr |= FSR_FTT_IEEE_EXCP; \
829 raise_exception(TT_FP_EXCP); \
831 env->fsr |= FSR_NVA; \
834 case float_relation_less: \
835 new_fsr = FSR_FCC0 << FS; \
837 case float_relation_greater: \
838 new_fsr = FSR_FCC1 << FS; \
844 env->fsr |= new_fsr; \
847 GEN_FCMPS(fcmps
, float32
, 0, 0);
848 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
850 GEN_FCMPS(fcmpes
, float32
, 0, 1);
851 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
853 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
854 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
856 static uint32_t compute_all_flags(void)
858 return env
->psr
& PSR_ICC
;
861 static uint32_t compute_C_flags(void)
863 return env
->psr
& PSR_CARRY
;
866 static inline uint32_t get_NZ_icc(target_ulong dst
)
870 if (!(dst
& 0xffffffffULL
))
872 if ((int32_t) (dst
& 0xffffffffULL
) < 0)
877 #ifdef TARGET_SPARC64
878 static uint32_t compute_all_flags_xcc(void)
880 return env
->xcc
& PSR_ICC
;
883 static uint32_t compute_C_flags_xcc(void)
885 return env
->xcc
& PSR_CARRY
;
888 static inline uint32_t get_NZ_xcc(target_ulong dst
)
894 if ((int64_t)dst
< 0)
900 static inline uint32_t get_V_div_icc(target_ulong src2
)
909 static uint32_t compute_all_div(void)
913 ret
= get_NZ_icc(CC_DST
);
914 ret
|= get_V_div_icc(CC_SRC2
);
918 static uint32_t compute_C_div(void)
923 /* carry = (src1[31] & src2[31]) | ( ~dst[31] & (src1[31] | src2[31])) */
924 static inline uint32_t get_C_add_icc(target_ulong dst
, target_ulong src1
,
929 if (((src1
& (1ULL << 31)) & (src2
& (1ULL << 31)))
930 | ((~(dst
& (1ULL << 31)))
931 & ((src1
& (1ULL << 31)) | (src2
& (1ULL << 31)))))
936 static inline uint32_t get_V_add_icc(target_ulong dst
, target_ulong src1
,
941 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 31))
946 #ifdef TARGET_SPARC64
947 static inline uint32_t get_C_add_xcc(target_ulong dst
, target_ulong src1
)
956 static inline uint32_t get_V_add_xcc(target_ulong dst
, target_ulong src1
,
961 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 63))
966 static uint32_t compute_all_add_xcc(void)
970 ret
= get_NZ_xcc(CC_DST
);
971 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
972 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
976 static uint32_t compute_C_add_xcc(void)
978 return get_C_add_xcc(CC_DST
, CC_SRC
);
982 static uint32_t compute_all_add(void)
986 ret
= get_NZ_icc(CC_DST
);
987 ret
|= get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
988 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
992 static uint32_t compute_C_add(void)
994 return get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
997 #ifdef TARGET_SPARC64
998 static uint32_t compute_all_addx_xcc(void)
1002 ret
= get_NZ_xcc(CC_DST
);
1003 ret
|= get_C_add_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1004 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1005 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1009 static uint32_t compute_C_addx_xcc(void)
1013 ret
= get_C_add_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1014 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1019 static inline uint32_t get_V_tag_icc(target_ulong src1
, target_ulong src2
)
1023 if ((src1
| src2
) & 0x3)
1028 static uint32_t compute_all_tadd(void)
1032 ret
= get_NZ_icc(CC_DST
);
1033 ret
|= get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1034 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1035 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1039 static uint32_t compute_C_tadd(void)
1041 return get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1044 static uint32_t compute_all_taddtv(void)
1048 ret
= get_NZ_icc(CC_DST
);
1049 ret
|= get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1053 static uint32_t compute_C_taddtv(void)
1055 return get_C_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1058 /* carry = (~src1[31] & src2[31]) | ( dst[31] & (~src1[31] | src2[31])) */
1059 static inline uint32_t get_C_sub_icc(target_ulong dst
, target_ulong src1
,
1064 if (((~(src1
& (1ULL << 31))) & (src2
& (1ULL << 31)))
1065 | ((dst
& (1ULL << 31)) & (( ~(src1
& (1ULL << 31)))
1066 | (src2
& (1ULL << 31)))))
1071 static inline uint32_t get_V_sub_icc(target_ulong dst
, target_ulong src1
,
1076 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 31))
1082 #ifdef TARGET_SPARC64
1083 static inline uint32_t get_C_sub_xcc(target_ulong src1
, target_ulong src2
)
1092 static inline uint32_t get_V_sub_xcc(target_ulong dst
, target_ulong src1
,
1097 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 63))
1102 static uint32_t compute_all_sub_xcc(void)
1106 ret
= get_NZ_xcc(CC_DST
);
1107 ret
|= get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1108 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1112 static uint32_t compute_C_sub_xcc(void)
1114 return get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1118 static uint32_t compute_all_sub(void)
1122 ret
= get_NZ_icc(CC_DST
);
1123 ret
|= get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1124 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1128 static uint32_t compute_C_sub(void)
1130 return get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1133 #ifdef TARGET_SPARC64
1134 static uint32_t compute_all_subx_xcc(void)
1138 ret
= get_NZ_xcc(CC_DST
);
1139 ret
|= get_C_sub_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1140 ret
|= get_C_sub_xcc(CC_DST
, CC_SRC2
);
1141 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1145 static uint32_t compute_C_subx_xcc(void)
1149 ret
= get_C_sub_xcc(CC_DST
- CC_SRC2
, CC_SRC
);
1150 ret
|= get_C_sub_xcc(CC_DST
, CC_SRC2
);
1155 static uint32_t compute_all_tsub(void)
1159 ret
= get_NZ_icc(CC_DST
);
1160 ret
|= get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1161 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1162 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1166 static uint32_t compute_C_tsub(void)
1168 return get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1171 static uint32_t compute_all_tsubtv(void)
1175 ret
= get_NZ_icc(CC_DST
);
1176 ret
|= get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1180 static uint32_t compute_C_tsubtv(void)
1182 return get_C_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1185 static uint32_t compute_all_logic(void)
1187 return get_NZ_icc(CC_DST
);
1190 static uint32_t compute_C_logic(void)
1195 #ifdef TARGET_SPARC64
1196 static uint32_t compute_all_logic_xcc(void)
1198 return get_NZ_xcc(CC_DST
);
1202 typedef struct CCTable
{
1203 uint32_t (*compute_all
)(void); /* return all the flags */
1204 uint32_t (*compute_c
)(void); /* return the C flag */
1207 static const CCTable icc_table
[CC_OP_NB
] = {
1208 /* CC_OP_DYNAMIC should never happen */
1209 [CC_OP_FLAGS
] = { compute_all_flags
, compute_C_flags
},
1210 [CC_OP_DIV
] = { compute_all_div
, compute_C_div
},
1211 [CC_OP_ADD
] = { compute_all_add
, compute_C_add
},
1212 [CC_OP_ADDX
] = { compute_all_add
, compute_C_add
},
1213 [CC_OP_TADD
] = { compute_all_tadd
, compute_C_tadd
},
1214 [CC_OP_TADDTV
] = { compute_all_taddtv
, compute_C_taddtv
},
1215 [CC_OP_SUB
] = { compute_all_sub
, compute_C_sub
},
1216 [CC_OP_SUBX
] = { compute_all_sub
, compute_C_sub
},
1217 [CC_OP_TSUB
] = { compute_all_tsub
, compute_C_tsub
},
1218 [CC_OP_TSUBTV
] = { compute_all_tsubtv
, compute_C_tsubtv
},
1219 [CC_OP_LOGIC
] = { compute_all_logic
, compute_C_logic
},
1222 #ifdef TARGET_SPARC64
1223 static const CCTable xcc_table
[CC_OP_NB
] = {
1224 /* CC_OP_DYNAMIC should never happen */
1225 [CC_OP_FLAGS
] = { compute_all_flags_xcc
, compute_C_flags_xcc
},
1226 [CC_OP_DIV
] = { compute_all_logic_xcc
, compute_C_logic
},
1227 [CC_OP_ADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1228 [CC_OP_ADDX
] = { compute_all_addx_xcc
, compute_C_addx_xcc
},
1229 [CC_OP_TADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1230 [CC_OP_TADDTV
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1231 [CC_OP_SUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1232 [CC_OP_SUBX
] = { compute_all_subx_xcc
, compute_C_subx_xcc
},
1233 [CC_OP_TSUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1234 [CC_OP_TSUBTV
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1235 [CC_OP_LOGIC
] = { compute_all_logic_xcc
, compute_C_logic
},
1239 void helper_compute_psr(void)
1243 new_psr
= icc_table
[CC_OP
].compute_all();
1245 #ifdef TARGET_SPARC64
1246 new_psr
= xcc_table
[CC_OP
].compute_all();
1249 CC_OP
= CC_OP_FLAGS
;
1252 uint32_t helper_compute_C_icc(void)
1256 ret
= icc_table
[CC_OP
].compute_c() >> PSR_CARRY_SHIFT
;
1260 #ifdef TARGET_SPARC64
1261 GEN_FCMPS(fcmps_fcc1
, float32
, 22, 0);
1262 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
1263 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
1265 GEN_FCMPS(fcmps_fcc2
, float32
, 24, 0);
1266 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
1267 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
1269 GEN_FCMPS(fcmps_fcc3
, float32
, 26, 0);
1270 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
1271 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
1273 GEN_FCMPS(fcmpes_fcc1
, float32
, 22, 1);
1274 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
1275 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
1277 GEN_FCMPS(fcmpes_fcc2
, float32
, 24, 1);
1278 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
1279 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
1281 GEN_FCMPS(fcmpes_fcc3
, float32
, 26, 1);
1282 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
1283 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
1287 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1289 static void dump_mxcc(CPUState
*env
)
1291 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1293 env
->mxccdata
[0], env
->mxccdata
[1],
1294 env
->mxccdata
[2], env
->mxccdata
[3]);
1295 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1297 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1299 env
->mxccregs
[0], env
->mxccregs
[1],
1300 env
->mxccregs
[2], env
->mxccregs
[3],
1301 env
->mxccregs
[4], env
->mxccregs
[5],
1302 env
->mxccregs
[6], env
->mxccregs
[7]);
1306 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1307 && defined(DEBUG_ASI)
1308 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
1314 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
1315 addr
, asi
, r1
& 0xff);
1318 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
1319 addr
, asi
, r1
& 0xffff);
1322 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
1323 addr
, asi
, r1
& 0xffffffff);
1326 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
1333 #ifndef TARGET_SPARC64
1334 #ifndef CONFIG_USER_ONLY
1335 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1338 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1339 uint32_t last_addr
= addr
;
1342 helper_check_align(addr
, size
- 1);
1344 case 2: /* SuperSparc MXCC registers */
1346 case 0x01c00a00: /* MXCC control register */
1348 ret
= env
->mxccregs
[3];
1350 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1353 case 0x01c00a04: /* MXCC control register */
1355 ret
= env
->mxccregs
[3];
1357 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1360 case 0x01c00c00: /* Module reset register */
1362 ret
= env
->mxccregs
[5];
1363 // should we do something here?
1365 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1368 case 0x01c00f00: /* MBus port address register */
1370 ret
= env
->mxccregs
[7];
1372 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1376 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1380 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1381 "addr = %08x -> ret = %" PRIx64
","
1382 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
1387 case 3: /* MMU probe */
1391 mmulev
= (addr
>> 8) & 15;
1395 ret
= mmu_probe(env
, addr
, mmulev
);
1396 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
1400 case 4: /* read MMU regs */
1402 int reg
= (addr
>> 8) & 0x1f;
1404 ret
= env
->mmuregs
[reg
];
1405 if (reg
== 3) /* Fault status cleared on read */
1406 env
->mmuregs
[3] = 0;
1407 else if (reg
== 0x13) /* Fault status read */
1408 ret
= env
->mmuregs
[3];
1409 else if (reg
== 0x14) /* Fault address read */
1410 ret
= env
->mmuregs
[4];
1411 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
1414 case 5: // Turbosparc ITLB Diagnostic
1415 case 6: // Turbosparc DTLB Diagnostic
1416 case 7: // Turbosparc IOTLB Diagnostic
1418 case 9: /* Supervisor code access */
1421 ret
= ldub_code(addr
);
1424 ret
= lduw_code(addr
);
1428 ret
= ldl_code(addr
);
1431 ret
= ldq_code(addr
);
1435 case 0xa: /* User data access */
1438 ret
= ldub_user(addr
);
1441 ret
= lduw_user(addr
);
1445 ret
= ldl_user(addr
);
1448 ret
= ldq_user(addr
);
1452 case 0xb: /* Supervisor data access */
1455 ret
= ldub_kernel(addr
);
1458 ret
= lduw_kernel(addr
);
1462 ret
= ldl_kernel(addr
);
1465 ret
= ldq_kernel(addr
);
1469 case 0xc: /* I-cache tag */
1470 case 0xd: /* I-cache data */
1471 case 0xe: /* D-cache tag */
1472 case 0xf: /* D-cache data */
1474 case 0x20: /* MMU passthrough */
1477 ret
= ldub_phys(addr
);
1480 ret
= lduw_phys(addr
);
1484 ret
= ldl_phys(addr
);
1487 ret
= ldq_phys(addr
);
1491 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1494 ret
= ldub_phys((target_phys_addr_t
)addr
1495 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1498 ret
= lduw_phys((target_phys_addr_t
)addr
1499 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1503 ret
= ldl_phys((target_phys_addr_t
)addr
1504 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1507 ret
= ldq_phys((target_phys_addr_t
)addr
1508 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1512 case 0x30: // Turbosparc secondary cache diagnostic
1513 case 0x31: // Turbosparc RAM snoop
1514 case 0x32: // Turbosparc page table descriptor diagnostic
1515 case 0x39: /* data cache diagnostic register */
1518 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1520 int reg
= (addr
>> 8) & 3;
1523 case 0: /* Breakpoint Value (Addr) */
1524 ret
= env
->mmubpregs
[reg
];
1526 case 1: /* Breakpoint Mask */
1527 ret
= env
->mmubpregs
[reg
];
1529 case 2: /* Breakpoint Control */
1530 ret
= env
->mmubpregs
[reg
];
1532 case 3: /* Breakpoint Status */
1533 ret
= env
->mmubpregs
[reg
];
1534 env
->mmubpregs
[reg
] = 0ULL;
1537 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
1541 case 8: /* User code access, XXX */
1543 do_unassigned_access(addr
, 0, 0, asi
, size
);
1553 ret
= (int16_t) ret
;
1556 ret
= (int32_t) ret
;
1563 dump_asi("read ", last_addr
, asi
, size
, ret
);
1568 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
1570 helper_check_align(addr
, size
- 1);
1572 case 2: /* SuperSparc MXCC registers */
1574 case 0x01c00000: /* MXCC stream data register 0 */
1576 env
->mxccdata
[0] = val
;
1578 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1581 case 0x01c00008: /* MXCC stream data register 1 */
1583 env
->mxccdata
[1] = val
;
1585 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1588 case 0x01c00010: /* MXCC stream data register 2 */
1590 env
->mxccdata
[2] = val
;
1592 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1595 case 0x01c00018: /* MXCC stream data register 3 */
1597 env
->mxccdata
[3] = val
;
1599 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1602 case 0x01c00100: /* MXCC stream source */
1604 env
->mxccregs
[0] = val
;
1606 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1608 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1610 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1612 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1614 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1617 case 0x01c00200: /* MXCC stream destination */
1619 env
->mxccregs
[1] = val
;
1621 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1623 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
1625 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
1627 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
1629 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
1632 case 0x01c00a00: /* MXCC control register */
1634 env
->mxccregs
[3] = val
;
1636 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1639 case 0x01c00a04: /* MXCC control register */
1641 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
1644 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1647 case 0x01c00e00: /* MXCC error register */
1648 // writing a 1 bit clears the error
1650 env
->mxccregs
[6] &= ~val
;
1652 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1655 case 0x01c00f00: /* MBus port address register */
1657 env
->mxccregs
[7] = val
;
1659 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1663 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1667 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
1668 asi
, size
, addr
, val
);
1673 case 3: /* MMU flush */
1677 mmulev
= (addr
>> 8) & 15;
1678 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
1680 case 0: // flush page
1681 tlb_flush_page(env
, addr
& 0xfffff000);
1683 case 1: // flush segment (256k)
1684 case 2: // flush region (16M)
1685 case 3: // flush context (4G)
1686 case 4: // flush entire
1697 case 4: /* write MMU regs */
1699 int reg
= (addr
>> 8) & 0x1f;
1702 oldreg
= env
->mmuregs
[reg
];
1704 case 0: // Control Register
1705 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1707 // Mappings generated during no-fault mode or MMU
1708 // disabled mode are invalid in normal mode
1709 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
1710 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)))
1713 case 1: // Context Table Pointer Register
1714 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
1716 case 2: // Context Register
1717 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
1718 if (oldreg
!= env
->mmuregs
[reg
]) {
1719 /* we flush when the MMU context changes because
1720 QEMU has no MMU context support */
1724 case 3: // Synchronous Fault Status Register with Clear
1725 case 4: // Synchronous Fault Address Register
1727 case 0x10: // TLB Replacement Control Register
1728 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
1730 case 0x13: // Synchronous Fault Status Register with Read and Clear
1731 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
1733 case 0x14: // Synchronous Fault Address Register
1734 env
->mmuregs
[4] = val
;
1737 env
->mmuregs
[reg
] = val
;
1740 if (oldreg
!= env
->mmuregs
[reg
]) {
1741 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1742 reg
, oldreg
, env
->mmuregs
[reg
]);
1749 case 5: // Turbosparc ITLB Diagnostic
1750 case 6: // Turbosparc DTLB Diagnostic
1751 case 7: // Turbosparc IOTLB Diagnostic
1753 case 0xa: /* User data access */
1756 stb_user(addr
, val
);
1759 stw_user(addr
, val
);
1763 stl_user(addr
, val
);
1766 stq_user(addr
, val
);
1770 case 0xb: /* Supervisor data access */
1773 stb_kernel(addr
, val
);
1776 stw_kernel(addr
, val
);
1780 stl_kernel(addr
, val
);
1783 stq_kernel(addr
, val
);
1787 case 0xc: /* I-cache tag */
1788 case 0xd: /* I-cache data */
1789 case 0xe: /* D-cache tag */
1790 case 0xf: /* D-cache data */
1791 case 0x10: /* I/D-cache flush page */
1792 case 0x11: /* I/D-cache flush segment */
1793 case 0x12: /* I/D-cache flush region */
1794 case 0x13: /* I/D-cache flush context */
1795 case 0x14: /* I/D-cache flush user */
1797 case 0x17: /* Block copy, sta access */
1803 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
1805 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
1806 temp
= ldl_kernel(src
);
1807 stl_kernel(dst
, temp
);
1811 case 0x1f: /* Block fill, stda access */
1814 // fill 32 bytes with val
1816 uint32_t dst
= addr
& 7;
1818 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
1819 stq_kernel(dst
, val
);
1822 case 0x20: /* MMU passthrough */
1826 stb_phys(addr
, val
);
1829 stw_phys(addr
, val
);
1833 stl_phys(addr
, val
);
1836 stq_phys(addr
, val
);
1841 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1845 stb_phys((target_phys_addr_t
)addr
1846 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1849 stw_phys((target_phys_addr_t
)addr
1850 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1854 stl_phys((target_phys_addr_t
)addr
1855 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1858 stq_phys((target_phys_addr_t
)addr
1859 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
1864 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1865 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1866 // Turbosparc snoop RAM
1867 case 0x32: // store buffer control or Turbosparc page table
1868 // descriptor diagnostic
1869 case 0x36: /* I-cache flash clear */
1870 case 0x37: /* D-cache flash clear */
1871 case 0x4c: /* breakpoint action */
1873 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1875 int reg
= (addr
>> 8) & 3;
1878 case 0: /* Breakpoint Value (Addr) */
1879 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1881 case 1: /* Breakpoint Mask */
1882 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1884 case 2: /* Breakpoint Control */
1885 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1887 case 3: /* Breakpoint Status */
1888 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1891 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1895 case 8: /* User code access, XXX */
1896 case 9: /* Supervisor code access, XXX */
1898 do_unassigned_access(addr
, 1, 0, asi
, size
);
1902 dump_asi("write", addr
, asi
, size
, val
);
1906 #endif /* CONFIG_USER_ONLY */
1907 #else /* TARGET_SPARC64 */
1909 #ifdef CONFIG_USER_ONLY
1910 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1913 #if defined(DEBUG_ASI)
1914 target_ulong last_addr
= addr
;
1918 raise_exception(TT_PRIV_ACT
);
1920 helper_check_align(addr
, size
- 1);
1921 address_mask(env
, &addr
);
1924 case 0x82: // Primary no-fault
1925 case 0x8a: // Primary no-fault LE
1926 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1928 dump_asi("read ", last_addr
, asi
, size
, ret
);
1933 case 0x80: // Primary
1934 case 0x88: // Primary LE
1938 ret
= ldub_raw(addr
);
1941 ret
= lduw_raw(addr
);
1944 ret
= ldl_raw(addr
);
1948 ret
= ldq_raw(addr
);
1953 case 0x83: // Secondary no-fault
1954 case 0x8b: // Secondary no-fault LE
1955 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1957 dump_asi("read ", last_addr
, asi
, size
, ret
);
1962 case 0x81: // Secondary
1963 case 0x89: // Secondary LE
1970 /* Convert from little endian */
1972 case 0x88: // Primary LE
1973 case 0x89: // Secondary LE
1974 case 0x8a: // Primary no-fault LE
1975 case 0x8b: // Secondary no-fault LE
1993 /* Convert to signed number */
2000 ret
= (int16_t) ret
;
2003 ret
= (int32_t) ret
;
2010 dump_asi("read ", last_addr
, asi
, size
, ret
);
2015 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2018 dump_asi("write", addr
, asi
, size
, val
);
2021 raise_exception(TT_PRIV_ACT
);
2023 helper_check_align(addr
, size
- 1);
2024 address_mask(env
, &addr
);
2026 /* Convert to little endian */
2028 case 0x88: // Primary LE
2029 case 0x89: // Secondary LE
2048 case 0x80: // Primary
2049 case 0x88: // Primary LE
2068 case 0x81: // Secondary
2069 case 0x89: // Secondary LE
2073 case 0x82: // Primary no-fault, RO
2074 case 0x83: // Secondary no-fault, RO
2075 case 0x8a: // Primary no-fault LE, RO
2076 case 0x8b: // Secondary no-fault LE, RO
2078 do_unassigned_access(addr
, 1, 0, 1, size
);
2083 #else /* CONFIG_USER_ONLY */
2085 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2088 #if defined(DEBUG_ASI)
2089 target_ulong last_addr
= addr
;
2094 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2095 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2096 && asi
>= 0x30 && asi
< 0x80
2097 && !(env
->hpstate
& HS_PRIV
)))
2098 raise_exception(TT_PRIV_ACT
);
2100 helper_check_align(addr
, size
- 1);
2102 case 0x82: // Primary no-fault
2103 case 0x8a: // Primary no-fault LE
2104 if (cpu_get_phys_page_debug(env
, addr
) == -1ULL) {
2106 dump_asi("read ", last_addr
, asi
, size
, ret
);
2111 case 0x10: // As if user primary
2112 case 0x18: // As if user primary LE
2113 case 0x80: // Primary
2114 case 0x88: // Primary LE
2115 case 0xe2: // UA2007 Primary block init
2116 case 0xe3: // UA2007 Secondary block init
2117 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2118 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
2119 && env
->hpstate
& HS_PRIV
) {
2122 ret
= ldub_hypv(addr
);
2125 ret
= lduw_hypv(addr
);
2128 ret
= ldl_hypv(addr
);
2132 ret
= ldq_hypv(addr
);
2138 ret
= ldub_kernel(addr
);
2141 ret
= lduw_kernel(addr
);
2144 ret
= ldl_kernel(addr
);
2148 ret
= ldq_kernel(addr
);
2155 ret
= ldub_user(addr
);
2158 ret
= lduw_user(addr
);
2161 ret
= ldl_user(addr
);
2165 ret
= ldq_user(addr
);
2170 case 0x14: // Bypass
2171 case 0x15: // Bypass, non-cacheable
2172 case 0x1c: // Bypass LE
2173 case 0x1d: // Bypass, non-cacheable LE
2177 ret
= ldub_phys(addr
);
2180 ret
= lduw_phys(addr
);
2183 ret
= ldl_phys(addr
);
2187 ret
= ldq_phys(addr
);
2192 case 0x24: // Nucleus quad LDD 128 bit atomic
2193 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2194 // Only ldda allowed
2195 raise_exception(TT_ILL_INSN
);
2197 case 0x83: // Secondary no-fault
2198 case 0x8b: // Secondary no-fault LE
2199 if (cpu_get_phys_page_debug(env
, addr
) == -1ULL) {
2201 dump_asi("read ", last_addr
, asi
, size
, ret
);
2206 case 0x04: // Nucleus
2207 case 0x0c: // Nucleus Little Endian (LE)
2208 case 0x11: // As if user secondary
2209 case 0x19: // As if user secondary LE
2210 case 0x4a: // UPA config
2211 case 0x81: // Secondary
2212 case 0x89: // Secondary LE
2218 case 0x50: // I-MMU regs
2220 int reg
= (addr
>> 3) & 0xf;
2223 // I-TSB Tag Target register
2224 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
2226 ret
= env
->immuregs
[reg
];
2231 case 0x51: // I-MMU 8k TSB pointer
2233 // env->immuregs[5] holds I-MMU TSB register value
2234 // env->immuregs[6] holds I-MMU Tag Access register value
2235 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2239 case 0x52: // I-MMU 64k TSB pointer
2241 // env->immuregs[5] holds I-MMU TSB register value
2242 // env->immuregs[6] holds I-MMU Tag Access register value
2243 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2247 case 0x55: // I-MMU data access
2249 int reg
= (addr
>> 3) & 0x3f;
2251 ret
= env
->itlb
[reg
].tte
;
2254 case 0x56: // I-MMU tag read
2256 int reg
= (addr
>> 3) & 0x3f;
2258 ret
= env
->itlb
[reg
].tag
;
2261 case 0x58: // D-MMU regs
2263 int reg
= (addr
>> 3) & 0xf;
2266 // D-TSB Tag Target register
2267 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
2269 ret
= env
->dmmuregs
[reg
];
2273 case 0x59: // D-MMU 8k TSB pointer
2275 // env->dmmuregs[5] holds D-MMU TSB register value
2276 // env->dmmuregs[6] holds D-MMU Tag Access register value
2277 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2281 case 0x5a: // D-MMU 64k TSB pointer
2283 // env->dmmuregs[5] holds D-MMU TSB register value
2284 // env->dmmuregs[6] holds D-MMU Tag Access register value
2285 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2289 case 0x5d: // D-MMU data access
2291 int reg
= (addr
>> 3) & 0x3f;
2293 ret
= env
->dtlb
[reg
].tte
;
2296 case 0x5e: // D-MMU tag read
2298 int reg
= (addr
>> 3) & 0x3f;
2300 ret
= env
->dtlb
[reg
].tag
;
2303 case 0x46: // D-cache data
2304 case 0x47: // D-cache tag access
2305 case 0x4b: // E-cache error enable
2306 case 0x4c: // E-cache asynchronous fault status
2307 case 0x4d: // E-cache asynchronous fault address
2308 case 0x4e: // E-cache tag data
2309 case 0x66: // I-cache instruction access
2310 case 0x67: // I-cache tag access
2311 case 0x6e: // I-cache predecode
2312 case 0x6f: // I-cache LRU etc.
2313 case 0x76: // E-cache tag
2314 case 0x7e: // E-cache tag
2316 case 0x5b: // D-MMU data pointer
2317 case 0x48: // Interrupt dispatch, RO
2318 case 0x49: // Interrupt data receive
2319 case 0x7f: // Incoming interrupt vector, RO
2322 case 0x54: // I-MMU data in, WO
2323 case 0x57: // I-MMU demap, WO
2324 case 0x5c: // D-MMU data in, WO
2325 case 0x5f: // D-MMU demap, WO
2326 case 0x77: // Interrupt vector, WO
2328 do_unassigned_access(addr
, 0, 0, 1, size
);
2333 /* Convert from little endian */
2335 case 0x0c: // Nucleus Little Endian (LE)
2336 case 0x18: // As if user primary LE
2337 case 0x19: // As if user secondary LE
2338 case 0x1c: // Bypass LE
2339 case 0x1d: // Bypass, non-cacheable LE
2340 case 0x88: // Primary LE
2341 case 0x89: // Secondary LE
2342 case 0x8a: // Primary no-fault LE
2343 case 0x8b: // Secondary no-fault LE
2361 /* Convert to signed number */
2368 ret
= (int16_t) ret
;
2371 ret
= (int32_t) ret
;
2378 dump_asi("read ", last_addr
, asi
, size
, ret
);
2383 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2386 dump_asi("write", addr
, asi
, size
, val
);
2391 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2392 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2393 && asi
>= 0x30 && asi
< 0x80
2394 && !(env
->hpstate
& HS_PRIV
)))
2395 raise_exception(TT_PRIV_ACT
);
2397 helper_check_align(addr
, size
- 1);
2398 /* Convert to little endian */
2400 case 0x0c: // Nucleus Little Endian (LE)
2401 case 0x18: // As if user primary LE
2402 case 0x19: // As if user secondary LE
2403 case 0x1c: // Bypass LE
2404 case 0x1d: // Bypass, non-cacheable LE
2405 case 0x88: // Primary LE
2406 case 0x89: // Secondary LE
2425 case 0x10: // As if user primary
2426 case 0x18: // As if user primary LE
2427 case 0x80: // Primary
2428 case 0x88: // Primary LE
2429 case 0xe2: // UA2007 Primary block init
2430 case 0xe3: // UA2007 Secondary block init
2431 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2432 if ((env
->def
->features
& CPU_FEATURE_HYPV
)
2433 && env
->hpstate
& HS_PRIV
) {
2436 stb_hypv(addr
, val
);
2439 stw_hypv(addr
, val
);
2442 stl_hypv(addr
, val
);
2446 stq_hypv(addr
, val
);
2452 stb_kernel(addr
, val
);
2455 stw_kernel(addr
, val
);
2458 stl_kernel(addr
, val
);
2462 stq_kernel(addr
, val
);
2469 stb_user(addr
, val
);
2472 stw_user(addr
, val
);
2475 stl_user(addr
, val
);
2479 stq_user(addr
, val
);
2484 case 0x14: // Bypass
2485 case 0x15: // Bypass, non-cacheable
2486 case 0x1c: // Bypass LE
2487 case 0x1d: // Bypass, non-cacheable LE
2491 stb_phys(addr
, val
);
2494 stw_phys(addr
, val
);
2497 stl_phys(addr
, val
);
2501 stq_phys(addr
, val
);
2506 case 0x24: // Nucleus quad LDD 128 bit atomic
2507 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2508 // Only ldda allowed
2509 raise_exception(TT_ILL_INSN
);
2511 case 0x04: // Nucleus
2512 case 0x0c: // Nucleus Little Endian (LE)
2513 case 0x11: // As if user secondary
2514 case 0x19: // As if user secondary LE
2515 case 0x4a: // UPA config
2516 case 0x81: // Secondary
2517 case 0x89: // Secondary LE
2525 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
2526 // Mappings generated during D/I MMU disabled mode are
2527 // invalid in normal mode
2528 if (oldreg
!= env
->lsu
) {
2529 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
2538 case 0x50: // I-MMU regs
2540 int reg
= (addr
>> 3) & 0xf;
2543 oldreg
= env
->immuregs
[reg
];
2547 case 1: // Not in I-MMU
2552 val
= 0; // Clear SFSR
2553 env
->immu
.sfsr
= val
;
2557 case 5: // TSB access
2558 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
2559 PRIx64
"\n", env
->immu
.tsb
, val
);
2560 env
->immu
.tsb
= val
;
2562 case 6: // Tag access
2563 env
->immu
.tag_access
= val
;
2572 if (oldreg
!= env
->immuregs
[reg
]) {
2573 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2574 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
2581 case 0x54: // I-MMU data in
2582 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
2584 case 0x55: // I-MMU data access
2588 unsigned int i
= (addr
>> 3) & 0x3f;
2590 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
2593 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
2598 case 0x57: // I-MMU demap
2599 demap_tlb(env
->itlb
, val
, "immu", env
);
2601 case 0x58: // D-MMU regs
2603 int reg
= (addr
>> 3) & 0xf;
2606 oldreg
= env
->dmmuregs
[reg
];
2612 if ((val
& 1) == 0) {
2613 val
= 0; // Clear SFSR, Fault address
2616 env
->dmmu
.sfsr
= val
;
2618 case 1: // Primary context
2619 env
->dmmu
.mmu_primary_context
= val
;
2621 case 2: // Secondary context
2622 env
->dmmu
.mmu_secondary_context
= val
;
2624 case 5: // TSB access
2625 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
2626 PRIx64
"\n", env
->dmmu
.tsb
, val
);
2627 env
->dmmu
.tsb
= val
;
2629 case 6: // Tag access
2630 env
->dmmu
.tag_access
= val
;
2632 case 7: // Virtual Watchpoint
2633 case 8: // Physical Watchpoint
2635 env
->dmmuregs
[reg
] = val
;
2639 if (oldreg
!= env
->dmmuregs
[reg
]) {
2640 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2641 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
2648 case 0x5c: // D-MMU data in
2649 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
2651 case 0x5d: // D-MMU data access
2653 unsigned int i
= (addr
>> 3) & 0x3f;
2655 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
2658 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
2663 case 0x5f: // D-MMU demap
2664 demap_tlb(env
->dtlb
, val
, "dmmu", env
);
2666 case 0x49: // Interrupt data receive
2669 case 0x46: // D-cache data
2670 case 0x47: // D-cache tag access
2671 case 0x4b: // E-cache error enable
2672 case 0x4c: // E-cache asynchronous fault status
2673 case 0x4d: // E-cache asynchronous fault address
2674 case 0x4e: // E-cache tag data
2675 case 0x66: // I-cache instruction access
2676 case 0x67: // I-cache tag access
2677 case 0x6e: // I-cache predecode
2678 case 0x6f: // I-cache LRU etc.
2679 case 0x76: // E-cache tag
2680 case 0x7e: // E-cache tag
2682 case 0x51: // I-MMU 8k TSB pointer, RO
2683 case 0x52: // I-MMU 64k TSB pointer, RO
2684 case 0x56: // I-MMU tag read, RO
2685 case 0x59: // D-MMU 8k TSB pointer, RO
2686 case 0x5a: // D-MMU 64k TSB pointer, RO
2687 case 0x5b: // D-MMU data pointer, RO
2688 case 0x5e: // D-MMU tag read, RO
2689 case 0x48: // Interrupt dispatch, RO
2690 case 0x7f: // Incoming interrupt vector, RO
2691 case 0x82: // Primary no-fault, RO
2692 case 0x83: // Secondary no-fault, RO
2693 case 0x8a: // Primary no-fault LE, RO
2694 case 0x8b: // Secondary no-fault LE, RO
2696 do_unassigned_access(addr
, 1, 0, 1, size
);
2700 #endif /* CONFIG_USER_ONLY */
2702 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
2704 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2705 || ((env
->def
->features
& CPU_FEATURE_HYPV
)
2706 && asi
>= 0x30 && asi
< 0x80
2707 && !(env
->hpstate
& HS_PRIV
)))
2708 raise_exception(TT_PRIV_ACT
);
2711 case 0x24: // Nucleus quad LDD 128 bit atomic
2712 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2713 helper_check_align(addr
, 0xf);
2715 env
->gregs
[1] = ldq_kernel(addr
+ 8);
2717 bswap64s(&env
->gregs
[1]);
2718 } else if (rd
< 8) {
2719 env
->gregs
[rd
] = ldq_kernel(addr
);
2720 env
->gregs
[rd
+ 1] = ldq_kernel(addr
+ 8);
2722 bswap64s(&env
->gregs
[rd
]);
2723 bswap64s(&env
->gregs
[rd
+ 1]);
2726 env
->regwptr
[rd
] = ldq_kernel(addr
);
2727 env
->regwptr
[rd
+ 1] = ldq_kernel(addr
+ 8);
2729 bswap64s(&env
->regwptr
[rd
]);
2730 bswap64s(&env
->regwptr
[rd
+ 1]);
2735 helper_check_align(addr
, 0x3);
2737 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2739 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2740 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2742 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
2743 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
2749 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2754 helper_check_align(addr
, 3);
2756 case 0xf0: // Block load primary
2757 case 0xf1: // Block load secondary
2758 case 0xf8: // Block load primary LE
2759 case 0xf9: // Block load secondary LE
2761 raise_exception(TT_ILL_INSN
);
2764 helper_check_align(addr
, 0x3f);
2765 for (i
= 0; i
< 16; i
++) {
2766 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
2776 val
= helper_ld_asi(addr
, asi
, size
, 0);
2780 *((uint32_t *)&env
->fpr
[rd
]) = val
;
2783 *((int64_t *)&DT0
) = val
;
2791 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
2794 target_ulong val
= 0;
2796 helper_check_align(addr
, 3);
2798 case 0xe0: // UA2007 Block commit store primary (cache flush)
2799 case 0xe1: // UA2007 Block commit store secondary (cache flush)
2800 case 0xf0: // Block store primary
2801 case 0xf1: // Block store secondary
2802 case 0xf8: // Block store primary LE
2803 case 0xf9: // Block store secondary LE
2805 raise_exception(TT_ILL_INSN
);
2808 helper_check_align(addr
, 0x3f);
2809 for (i
= 0; i
< 16; i
++) {
2810 val
= *(uint32_t *)&env
->fpr
[rd
++];
2811 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
2823 val
= *((uint32_t *)&env
->fpr
[rd
]);
2826 val
= *((int64_t *)&DT0
);
2832 helper_st_asi(addr
, val
, asi
, size
);
2835 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
2836 target_ulong val2
, uint32_t asi
)
2840 val2
&= 0xffffffffUL
;
2841 ret
= helper_ld_asi(addr
, asi
, 4, 0);
2842 ret
&= 0xffffffffUL
;
2844 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
2848 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
2849 target_ulong val2
, uint32_t asi
)
2853 ret
= helper_ld_asi(addr
, asi
, 8, 0);
2855 helper_st_asi(addr
, val1
, asi
, 8);
2858 #endif /* TARGET_SPARC64 */
2860 #ifndef TARGET_SPARC64
2861 void helper_rett(void)
2865 if (env
->psret
== 1)
2866 raise_exception(TT_ILL_INSN
);
2869 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1) ;
2870 if (env
->wim
& (1 << cwp
)) {
2871 raise_exception(TT_WIN_UNF
);
2874 env
->psrs
= env
->psrps
;
2878 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
2883 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
2887 raise_exception(TT_DIV_ZERO
);
2891 if (x0
> 0xffffffff) {
2900 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
2905 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
2909 raise_exception(TT_DIV_ZERO
);
2913 if ((int32_t) x0
!= x0
) {
2915 return x0
< 0? 0x80000000: 0x7fffffff;
2922 void helper_stdf(target_ulong addr
, int mem_idx
)
2924 helper_check_align(addr
, 7);
2925 #if !defined(CONFIG_USER_ONLY)
2928 stfq_user(addr
, DT0
);
2931 stfq_kernel(addr
, DT0
);
2933 #ifdef TARGET_SPARC64
2935 stfq_hypv(addr
, DT0
);
2942 address_mask(env
, &addr
);
2943 stfq_raw(addr
, DT0
);
2947 void helper_lddf(target_ulong addr
, int mem_idx
)
2949 helper_check_align(addr
, 7);
2950 #if !defined(CONFIG_USER_ONLY)
2953 DT0
= ldfq_user(addr
);
2956 DT0
= ldfq_kernel(addr
);
2958 #ifdef TARGET_SPARC64
2960 DT0
= ldfq_hypv(addr
);
2967 address_mask(env
, &addr
);
2968 DT0
= ldfq_raw(addr
);
2972 void helper_ldqf(target_ulong addr
, int mem_idx
)
2974 // XXX add 128 bit load
2977 helper_check_align(addr
, 7);
2978 #if !defined(CONFIG_USER_ONLY)
2981 u
.ll
.upper
= ldq_user(addr
);
2982 u
.ll
.lower
= ldq_user(addr
+ 8);
2986 u
.ll
.upper
= ldq_kernel(addr
);
2987 u
.ll
.lower
= ldq_kernel(addr
+ 8);
2990 #ifdef TARGET_SPARC64
2992 u
.ll
.upper
= ldq_hypv(addr
);
2993 u
.ll
.lower
= ldq_hypv(addr
+ 8);
3001 address_mask(env
, &addr
);
3002 u
.ll
.upper
= ldq_raw(addr
);
3003 u
.ll
.lower
= ldq_raw((addr
+ 8) & 0xffffffffULL
);
3008 void helper_stqf(target_ulong addr
, int mem_idx
)
3010 // XXX add 128 bit store
3013 helper_check_align(addr
, 7);
3014 #if !defined(CONFIG_USER_ONLY)
3018 stq_user(addr
, u
.ll
.upper
);
3019 stq_user(addr
+ 8, u
.ll
.lower
);
3023 stq_kernel(addr
, u
.ll
.upper
);
3024 stq_kernel(addr
+ 8, u
.ll
.lower
);
3026 #ifdef TARGET_SPARC64
3029 stq_hypv(addr
, u
.ll
.upper
);
3030 stq_hypv(addr
+ 8, u
.ll
.lower
);
3038 address_mask(env
, &addr
);
3039 stq_raw(addr
, u
.ll
.upper
);
3040 stq_raw((addr
+ 8) & 0xffffffffULL
, u
.ll
.lower
);
3044 static inline void set_fsr(void)
3048 switch (env
->fsr
& FSR_RD_MASK
) {
3049 case FSR_RD_NEAREST
:
3050 rnd_mode
= float_round_nearest_even
;
3054 rnd_mode
= float_round_to_zero
;
3057 rnd_mode
= float_round_up
;
3060 rnd_mode
= float_round_down
;
3063 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
3066 void helper_ldfsr(uint32_t new_fsr
)
3068 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
3072 #ifdef TARGET_SPARC64
3073 void helper_ldxfsr(uint64_t new_fsr
)
3075 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);
3080 void helper_debug(void)
3082 env
->exception_index
= EXCP_DEBUG
;
3086 #ifndef TARGET_SPARC64
3087 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3089 void helper_save(void)
3093 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
3094 if (env
->wim
& (1 << cwp
)) {
3095 raise_exception(TT_WIN_OVF
);
3100 void helper_restore(void)
3104 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
3105 if (env
->wim
& (1 << cwp
)) {
3106 raise_exception(TT_WIN_UNF
);
3111 void helper_wrpsr(target_ulong new_psr
)
3113 if ((new_psr
& PSR_CWP
) >= env
->nwindows
)
3114 raise_exception(TT_ILL_INSN
);
3116 PUT_PSR(env
, new_psr
);
3119 target_ulong
helper_rdpsr(void)
3121 return GET_PSR(env
);
3125 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3127 void helper_save(void)
3131 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
3132 if (env
->cansave
== 0) {
3133 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3134 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3135 ((env
->wstate
& 0x7) << 2)));
3137 if (env
->cleanwin
- env
->canrestore
== 0) {
3138 // XXX Clean windows without trap
3139 raise_exception(TT_CLRWIN
);
3148 void helper_restore(void)
3152 cwp
= cpu_cwp_inc(env
, env
->cwp
+ 1);
3153 if (env
->canrestore
== 0) {
3154 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
3155 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3156 ((env
->wstate
& 0x7) << 2)));
3164 void helper_flushw(void)
3166 if (env
->cansave
!= env
->nwindows
- 2) {
3167 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3168 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3169 ((env
->wstate
& 0x7) << 2)));
3173 void helper_saved(void)
3176 if (env
->otherwin
== 0)
3182 void helper_restored(void)
3185 if (env
->cleanwin
< env
->nwindows
- 1)
3187 if (env
->otherwin
== 0)
3193 target_ulong
helper_rdccr(void)
3195 return GET_CCR(env
);
3198 void helper_wrccr(target_ulong new_ccr
)
3200 PUT_CCR(env
, new_ccr
);
3203 // CWP handling is reversed in V9, but we still use the V8 register
3205 target_ulong
helper_rdcwp(void)
3207 return GET_CWP64(env
);
3210 void helper_wrcwp(target_ulong new_cwp
)
3212 PUT_CWP64(env
, new_cwp
);
3215 // This function uses non-native bit order
3216 #define GET_FIELD(X, FROM, TO) \
3217 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3219 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3220 #define GET_FIELD_SP(X, FROM, TO) \
3221 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3223 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
3225 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
3226 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
3227 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
3228 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
3229 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
3230 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
3231 (((pixel_addr
>> 55) & 1) << 4) |
3232 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
3233 GET_FIELD_SP(pixel_addr
, 11, 12);
3236 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
3240 tmp
= addr
+ offset
;
3242 env
->gsr
|= tmp
& 7ULL;
3246 target_ulong
helper_popc(target_ulong val
)
3248 return ctpop64(val
);
3251 static inline uint64_t *get_gregset(uint32_t pstate
)
3255 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3257 (pstate
& PS_IG
) ? " IG" : "",
3258 (pstate
& PS_MG
) ? " MG" : "",
3259 (pstate
& PS_AG
) ? " AG" : "");
3260 /* pass through to normal set of global registers */
3272 static inline void change_pstate(uint32_t new_pstate
)
3274 uint32_t pstate_regs
, new_pstate_regs
;
3275 uint64_t *src
, *dst
;
3277 if (env
->def
->features
& CPU_FEATURE_GL
) {
3278 // PS_AG is not implemented in this case
3279 new_pstate
&= ~PS_AG
;
3282 pstate_regs
= env
->pstate
& 0xc01;
3283 new_pstate_regs
= new_pstate
& 0xc01;
3285 if (new_pstate_regs
!= pstate_regs
) {
3286 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3287 pstate_regs
, new_pstate_regs
);
3288 // Switch global register bank
3289 src
= get_gregset(new_pstate_regs
);
3290 dst
= get_gregset(pstate_regs
);
3291 memcpy32(dst
, env
->gregs
);
3292 memcpy32(env
->gregs
, src
);
3295 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3298 env
->pstate
= new_pstate
;
3301 void helper_wrpstate(target_ulong new_state
)
3303 change_pstate(new_state
& 0xf3f);
3305 #if !defined(CONFIG_USER_ONLY)
3306 if (cpu_interrupts_enabled(env
)) {
3307 cpu_check_irqs(env
);
3312 void helper_wrpil(target_ulong new_pil
)
3314 #if !defined(CONFIG_USER_ONLY)
3315 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
3316 env
->psrpil
, (uint32_t)new_pil
);
3318 env
->psrpil
= new_pil
;
3320 if (cpu_interrupts_enabled(env
)) {
3321 cpu_check_irqs(env
);
3326 void helper_done(void)
3328 trap_state
* tsptr
= cpu_tsptr(env
);
3330 env
->pc
= tsptr
->tnpc
;
3331 env
->npc
= tsptr
->tnpc
+ 4;
3332 PUT_CCR(env
, tsptr
->tstate
>> 32);
3333 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3334 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3335 PUT_CWP64(env
, tsptr
->tstate
& 0xff);
3338 DPRINTF_PSTATE("... helper_done tl=%d\n", env
->tl
);
3340 #if !defined(CONFIG_USER_ONLY)
3341 if (cpu_interrupts_enabled(env
)) {
3342 cpu_check_irqs(env
);
3347 void helper_retry(void)
3349 trap_state
* tsptr
= cpu_tsptr(env
);
3351 env
->pc
= tsptr
->tpc
;
3352 env
->npc
= tsptr
->tnpc
;
3353 PUT_CCR(env
, tsptr
->tstate
>> 32);
3354 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3355 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3356 PUT_CWP64(env
, tsptr
->tstate
& 0xff);
3359 DPRINTF_PSTATE("... helper_retry tl=%d\n", env
->tl
);
3361 #if !defined(CONFIG_USER_ONLY)
3362 if (cpu_interrupts_enabled(env
)) {
3363 cpu_check_irqs(env
);
3368 static void do_modify_softint(const char* operation
, uint32_t value
)
3370 if (env
->softint
!= value
) {
3371 env
->softint
= value
;
3372 DPRINTF_PSTATE(": %s new %08x\n", operation
, env
->softint
);
3373 #if !defined(CONFIG_USER_ONLY)
3374 if (cpu_interrupts_enabled(env
)) {
3375 cpu_check_irqs(env
);
3381 void helper_set_softint(uint64_t value
)
3383 do_modify_softint("helper_set_softint", env
->softint
| (uint32_t)value
);
3386 void helper_clear_softint(uint64_t value
)
3388 do_modify_softint("helper_clear_softint", env
->softint
& (uint32_t)~value
);
3391 void helper_write_softint(uint64_t value
)
3393 do_modify_softint("helper_write_softint", (uint32_t)value
);
3397 void helper_flush(target_ulong addr
)
3400 tb_invalidate_page_range(addr
, addr
+ 8);
3403 #ifdef TARGET_SPARC64
3405 static const char * const excp_names
[0x80] = {
3406 [TT_TFAULT
] = "Instruction Access Fault",
3407 [TT_TMISS
] = "Instruction Access MMU Miss",
3408 [TT_CODE_ACCESS
] = "Instruction Access Error",
3409 [TT_ILL_INSN
] = "Illegal Instruction",
3410 [TT_PRIV_INSN
] = "Privileged Instruction",
3411 [TT_NFPU_INSN
] = "FPU Disabled",
3412 [TT_FP_EXCP
] = "FPU Exception",
3413 [TT_TOVF
] = "Tag Overflow",
3414 [TT_CLRWIN
] = "Clean Windows",
3415 [TT_DIV_ZERO
] = "Division By Zero",
3416 [TT_DFAULT
] = "Data Access Fault",
3417 [TT_DMISS
] = "Data Access MMU Miss",
3418 [TT_DATA_ACCESS
] = "Data Access Error",
3419 [TT_DPROT
] = "Data Protection Error",
3420 [TT_UNALIGNED
] = "Unaligned Memory Access",
3421 [TT_PRIV_ACT
] = "Privileged Action",
3422 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3423 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3424 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3425 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3426 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3427 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3428 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3429 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3430 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3431 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3432 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3433 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3434 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3435 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3436 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3440 trap_state
* cpu_tsptr(CPUState
* env
)
3442 return &env
->ts
[env
->tl
& MAXTL_MASK
];
3445 void do_interrupt(CPUState
*env
)
3447 int intno
= env
->exception_index
;
3451 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
3455 if (intno
< 0 || intno
>= 0x180)
3457 else if (intno
>= 0x100)
3458 name
= "Trap Instruction";
3459 else if (intno
>= 0xc0)
3460 name
= "Window Fill";
3461 else if (intno
>= 0x80)
3462 name
= "Window Spill";
3464 name
= excp_names
[intno
];
3469 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64
" npc=%016" PRIx64
3470 " SP=%016" PRIx64
"\n",
3473 env
->npc
, env
->regwptr
[6]);
3474 log_cpu_state(env
, 0);
3481 ptr
= (uint8_t *)env
->pc
;
3482 for(i
= 0; i
< 16; i
++) {
3483 qemu_log(" %02x", ldub(ptr
+ i
));
3491 #if !defined(CONFIG_USER_ONLY)
3492 if (env
->tl
>= env
->maxtl
) {
3493 cpu_abort(env
, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
3494 " Error state", env
->exception_index
, env
->tl
, env
->maxtl
);
3498 if (env
->tl
< env
->maxtl
- 1) {
3501 env
->pstate
|= PS_RED
;
3502 if (env
->tl
< env
->maxtl
)
3505 tsptr
= cpu_tsptr(env
);
3507 tsptr
->tstate
= ((uint64_t)GET_CCR(env
) << 32) |
3508 ((env
->asi
& 0xff) << 24) | ((env
->pstate
& 0xf3f) << 8) |
3510 tsptr
->tpc
= env
->pc
;
3511 tsptr
->tnpc
= env
->npc
;
3516 change_pstate(PS_PEF
| PS_PRIV
| PS_IG
);
3520 case TT_TMISS
... TT_TMISS
+ 3:
3521 case TT_DMISS
... TT_DMISS
+ 3:
3522 case TT_DPROT
... TT_DPROT
+ 3:
3523 change_pstate(PS_PEF
| PS_PRIV
| PS_MG
);
3526 change_pstate(PS_PEF
| PS_PRIV
| PS_AG
);
3530 if (intno
== TT_CLRWIN
)
3531 cpu_set_cwp(env
, cpu_cwp_dec(env
, env
->cwp
- 1));
3532 else if ((intno
& 0x1c0) == TT_SPILL
)
3533 cpu_set_cwp(env
, cpu_cwp_dec(env
, env
->cwp
- env
->cansave
- 2));
3534 else if ((intno
& 0x1c0) == TT_FILL
)
3535 cpu_set_cwp(env
, cpu_cwp_inc(env
, env
->cwp
+ 1));
3536 env
->tbr
&= ~0x7fffULL
;
3537 env
->tbr
|= ((env
->tl
> 1) ? 1 << 14 : 0) | (intno
<< 5);
3539 env
->npc
= env
->pc
+ 4;
3540 env
->exception_index
= -1;
3544 static const char * const excp_names
[0x80] = {
3545 [TT_TFAULT
] = "Instruction Access Fault",
3546 [TT_ILL_INSN
] = "Illegal Instruction",
3547 [TT_PRIV_INSN
] = "Privileged Instruction",
3548 [TT_NFPU_INSN
] = "FPU Disabled",
3549 [TT_WIN_OVF
] = "Window Overflow",
3550 [TT_WIN_UNF
] = "Window Underflow",
3551 [TT_UNALIGNED
] = "Unaligned Memory Access",
3552 [TT_FP_EXCP
] = "FPU Exception",
3553 [TT_DFAULT
] = "Data Access Fault",
3554 [TT_TOVF
] = "Tag Overflow",
3555 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3556 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3557 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3558 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3559 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3560 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3561 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3562 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3563 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3564 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3565 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3566 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3567 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3568 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3569 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3570 [TT_TOVF
] = "Tag Overflow",
3571 [TT_CODE_ACCESS
] = "Instruction Access Error",
3572 [TT_DATA_ACCESS
] = "Data Access Error",
3573 [TT_DIV_ZERO
] = "Division By Zero",
3574 [TT_NCP_INSN
] = "Coprocessor Disabled",
3578 void do_interrupt(CPUState
*env
)
3580 int cwp
, intno
= env
->exception_index
;
3583 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
3587 if (intno
< 0 || intno
>= 0x100)
3589 else if (intno
>= 0x80)
3590 name
= "Trap Instruction";
3592 name
= excp_names
[intno
];
3597 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
3600 env
->npc
, env
->regwptr
[6]);
3601 log_cpu_state(env
, 0);
3608 ptr
= (uint8_t *)env
->pc
;
3609 for(i
= 0; i
< 16; i
++) {
3610 qemu_log(" %02x", ldub(ptr
+ i
));
3618 #if !defined(CONFIG_USER_ONLY)
3619 if (env
->psret
== 0) {
3620 cpu_abort(env
, "Trap 0x%02x while interrupts disabled, Error state",
3621 env
->exception_index
);
3626 cwp
= cpu_cwp_dec(env
, env
->cwp
- 1);
3627 cpu_set_cwp(env
, cwp
);
3628 env
->regwptr
[9] = env
->pc
;
3629 env
->regwptr
[10] = env
->npc
;
3630 env
->psrps
= env
->psrs
;
3632 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
3634 env
->npc
= env
->pc
+ 4;
3635 env
->exception_index
= -1;
3639 #if !defined(CONFIG_USER_ONLY)
3641 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
3644 #define MMUSUFFIX _mmu
3645 #define ALIGNED_ONLY
3648 #include "softmmu_template.h"
3651 #include "softmmu_template.h"
3654 #include "softmmu_template.h"
3657 #include "softmmu_template.h"
3659 /* XXX: make it generic ? */
3660 static void cpu_restore_state2(void *retaddr
)
3662 TranslationBlock
*tb
;
3666 /* now we have a real cpu fault */
3667 pc
= (unsigned long)retaddr
;
3668 tb
= tb_find_pc(pc
);
3670 /* the PC is inside the translated code. It means that we have
3671 a virtual CPU fault */
3672 cpu_restore_state(tb
, env
, pc
, (void *)(long)env
->cond
);
3677 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
3680 #ifdef DEBUG_UNALIGNED
3681 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
3682 "\n", addr
, env
->pc
);
3684 cpu_restore_state2(retaddr
);
3685 raise_exception(TT_UNALIGNED
);
3688 /* try to fill the TLB and return an exception if error. If retaddr is
3689 NULL, it means that the function was called in C code (i.e. not
3690 from generated code or from helper.c) */
3691 /* XXX: fix it to restore all registers */
3692 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
3695 CPUState
*saved_env
;
3697 /* XXX: hack to restore env in all cases, even if not called from
3700 env
= cpu_single_env
;
3702 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
3704 cpu_restore_state2(retaddr
);
3712 #ifndef TARGET_SPARC64
3713 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
3714 int is_asi
, int size
)
3716 CPUState
*saved_env
;
3719 /* XXX: hack to restore env in all cases, even if not called from
3722 env
= cpu_single_env
;
3723 #ifdef DEBUG_UNASSIGNED
3725 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3726 " asi 0x%02x from " TARGET_FMT_lx
"\n",
3727 is_exec
? "exec" : is_write
? "write" : "read", size
,
3728 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
3730 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3731 " from " TARGET_FMT_lx
"\n",
3732 is_exec
? "exec" : is_write
? "write" : "read", size
,
3733 size
== 1 ? "" : "s", addr
, env
->pc
);
3735 /* Don't overwrite translation and access faults */
3736 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
3737 if ((fault_type
> 4) || (fault_type
== 0)) {
3738 env
->mmuregs
[3] = 0; /* Fault status register */
3740 env
->mmuregs
[3] |= 1 << 16;
3742 env
->mmuregs
[3] |= 1 << 5;
3744 env
->mmuregs
[3] |= 1 << 6;
3746 env
->mmuregs
[3] |= 1 << 7;
3747 env
->mmuregs
[3] |= (5 << 2) | 2;
3748 /* SuperSPARC will never place instruction fault addresses in the FAR */
3750 env
->mmuregs
[4] = addr
; /* Fault address register */
3753 /* overflow (same type fault was not read before another fault) */
3754 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
3755 env
->mmuregs
[3] |= 1;
3758 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
3760 raise_exception(TT_CODE_ACCESS
);
3762 raise_exception(TT_DATA_ACCESS
);
3766 /* flush neverland mappings created during no-fault mode,
3767 so the sequential MMU faults report proper fault types */
3768 if (env
->mmuregs
[0] & MMU_NF
) {
3773 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
3774 int is_asi
, int size
)
3776 CPUState
*saved_env
;
3778 /* XXX: hack to restore env in all cases, even if not called from
3781 env
= cpu_single_env
;
3783 #ifdef DEBUG_UNASSIGNED
3784 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
3785 "\n", addr
, env
->pc
);
3789 raise_exception(TT_CODE_ACCESS
);
3791 raise_exception(TT_DATA_ACCESS
);
3797 #ifdef TARGET_SPARC64
3798 void helper_tick_set_count(void *opaque
, uint64_t count
)
3800 #if !defined(CONFIG_USER_ONLY)
3801 cpu_tick_set_count(opaque
, count
);
3805 uint64_t helper_tick_get_count(void *opaque
)
3807 #if !defined(CONFIG_USER_ONLY)
3808 return cpu_tick_get_count(opaque
);
3814 void helper_tick_set_limit(void *opaque
, uint64_t limit
)
3816 #if !defined(CONFIG_USER_ONLY)
3817 cpu_tick_set_limit(opaque
, limit
);