4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
42 #define X86_64_ONLY(x) x
43 #define X86_64_DEF(...) __VA_ARGS__
44 #define CODE64(s) ((s)->code64)
45 #define REX_X(s) ((s)->rex_x)
46 #define REX_B(s) ((s)->rex_b)
47 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
49 #define BUGGY_64(x) NULL
52 #define X86_64_ONLY(x) NULL
53 #define X86_64_DEF(...)
59 //#define MACRO_TEST 1
61 /* global register indexes */
62 static TCGv_ptr cpu_env
;
63 static TCGv cpu_A0
, cpu_cc_src
, cpu_cc_dst
, cpu_cc_tmp
;
64 static TCGv_i32 cpu_cc_op
;
66 static TCGv cpu_T
[2], cpu_T3
;
67 /* local register indexes (only used inside old micro ops) */
68 static TCGv cpu_tmp0
, cpu_tmp4
;
69 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
70 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
71 static TCGv_i64 cpu_tmp1_i64
;
72 static TCGv cpu_tmp5
, cpu_tmp6
;
74 #include "gen-icount.h"
77 static int x86_64_hregs
;
80 typedef struct DisasContext
{
81 /* current insn context */
82 int override
; /* -1 if no override */
85 target_ulong pc
; /* pc = eip + cs_base */
86 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
87 static state change (stop translation) */
88 /* current block context */
89 target_ulong cs_base
; /* base of CS segment */
90 int pe
; /* protected mode */
91 int code32
; /* 32 bit code segment */
93 int lma
; /* long mode active */
94 int code64
; /* 64 bit code segment */
97 int ss32
; /* 32 bit stack segment */
98 int cc_op
; /* current CC operation */
99 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
100 int f_st
; /* currently unused */
101 int vm86
; /* vm86 mode */
104 int tf
; /* TF cpu flag */
105 int singlestep_enabled
; /* "hardware" single step enabled */
106 int jmp_opt
; /* use direct block chaining for direct jumps */
107 int mem_index
; /* select memory access functions */
108 uint64_t flags
; /* all execution flags */
109 struct TranslationBlock
*tb
;
110 int popl_esp_hack
; /* for correct popl with esp base handling */
111 int rip_offset
; /* only used in x86_64, but left for simplicity */
113 int cpuid_ext_features
;
114 int cpuid_ext2_features
;
115 int cpuid_ext3_features
;
118 static void gen_eob(DisasContext
*s
);
119 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
120 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
122 /* i386 arith/logic operations */
142 OP_SHL1
, /* undocumented */
166 /* I386 int registers */
167 OR_EAX
, /* MUST be even numbered */
176 OR_TMP0
= 16, /* temporary operand register */
178 OR_A0
, /* temporary register used when doing address evaluation */
181 static inline void gen_op_movl_T0_0(void)
183 tcg_gen_movi_tl(cpu_T
[0], 0);
186 static inline void gen_op_movl_T0_im(int32_t val
)
188 tcg_gen_movi_tl(cpu_T
[0], val
);
191 static inline void gen_op_movl_T0_imu(uint32_t val
)
193 tcg_gen_movi_tl(cpu_T
[0], val
);
196 static inline void gen_op_movl_T1_im(int32_t val
)
198 tcg_gen_movi_tl(cpu_T
[1], val
);
201 static inline void gen_op_movl_T1_imu(uint32_t val
)
203 tcg_gen_movi_tl(cpu_T
[1], val
);
206 static inline void gen_op_movl_A0_im(uint32_t val
)
208 tcg_gen_movi_tl(cpu_A0
, val
);
212 static inline void gen_op_movq_A0_im(int64_t val
)
214 tcg_gen_movi_tl(cpu_A0
, val
);
218 static inline void gen_movtl_T0_im(target_ulong val
)
220 tcg_gen_movi_tl(cpu_T
[0], val
);
223 static inline void gen_movtl_T1_im(target_ulong val
)
225 tcg_gen_movi_tl(cpu_T
[1], val
);
228 static inline void gen_op_andl_T0_ffff(void)
230 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
233 static inline void gen_op_andl_T0_im(uint32_t val
)
235 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
238 static inline void gen_op_movl_T0_T1(void)
240 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
243 static inline void gen_op_andl_A0_ffff(void)
245 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
250 #define NB_OP_SIZES 4
252 #else /* !TARGET_X86_64 */
254 #define NB_OP_SIZES 3
256 #endif /* !TARGET_X86_64 */
258 #if defined(HOST_WORDS_BIGENDIAN)
259 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
260 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
261 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
262 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
263 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
265 #define REG_B_OFFSET 0
266 #define REG_H_OFFSET 1
267 #define REG_W_OFFSET 0
268 #define REG_L_OFFSET 0
269 #define REG_LH_OFFSET 4
272 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
276 if (reg
< 4 X86_64_DEF( || reg
>= 8 || x86_64_hregs
)) {
277 tcg_gen_st8_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_B_OFFSET
);
279 tcg_gen_st8_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
- 4]) + REG_H_OFFSET
);
283 tcg_gen_st16_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_W_OFFSET
);
287 tcg_gen_st32_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
288 /* high part of register set to zero */
289 tcg_gen_movi_tl(cpu_tmp0
, 0);
290 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_LH_OFFSET
);
294 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
299 tcg_gen_st32_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
305 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
307 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
310 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
312 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
315 static inline void gen_op_mov_reg_A0(int size
, int reg
)
319 tcg_gen_st16_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_W_OFFSET
);
323 tcg_gen_st32_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
324 /* high part of register set to zero */
325 tcg_gen_movi_tl(cpu_tmp0
, 0);
326 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_LH_OFFSET
);
330 tcg_gen_st_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
335 tcg_gen_st32_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
341 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
345 if (reg
< 4 X86_64_DEF( || reg
>= 8 || x86_64_hregs
)) {
348 tcg_gen_ld8u_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
- 4]) + REG_H_OFFSET
);
353 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
358 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
360 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
363 static inline void gen_op_movl_A0_reg(int reg
)
365 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
368 static inline void gen_op_addl_A0_im(int32_t val
)
370 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
372 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
377 static inline void gen_op_addq_A0_im(int64_t val
)
379 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
383 static void gen_add_A0_im(DisasContext
*s
, int val
)
387 gen_op_addq_A0_im(val
);
390 gen_op_addl_A0_im(val
);
393 static inline void gen_op_addl_T0_T1(void)
395 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
398 static inline void gen_op_jmp_T0(void)
400 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, eip
));
403 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
407 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
408 tcg_gen_addi_tl(cpu_tmp0
, cpu_tmp0
, val
);
409 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_W_OFFSET
);
412 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
413 tcg_gen_addi_tl(cpu_tmp0
, cpu_tmp0
, val
);
415 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0xffffffff);
417 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
421 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
422 tcg_gen_addi_tl(cpu_tmp0
, cpu_tmp0
, val
);
423 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
429 static inline void gen_op_add_reg_T0(int size
, int reg
)
433 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
434 tcg_gen_add_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[0]);
435 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_W_OFFSET
);
438 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
439 tcg_gen_add_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[0]);
441 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0xffffffff);
443 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
447 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
448 tcg_gen_add_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[0]);
449 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
455 static inline void gen_op_set_cc_op(int32_t val
)
457 tcg_gen_movi_i32(cpu_cc_op
, val
);
460 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
462 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
464 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
465 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
467 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
471 static inline void gen_op_movl_A0_seg(int reg
)
473 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
) + REG_L_OFFSET
);
476 static inline void gen_op_addl_A0_seg(int reg
)
478 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
479 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
481 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
486 static inline void gen_op_movq_A0_seg(int reg
)
488 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
491 static inline void gen_op_addq_A0_seg(int reg
)
493 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
494 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
497 static inline void gen_op_movq_A0_reg(int reg
)
499 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
502 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
504 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
506 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
507 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
511 static inline void gen_op_lds_T0_A0(int idx
)
513 int mem_index
= (idx
>> 2) - 1;
516 tcg_gen_qemu_ld8s(cpu_T
[0], cpu_A0
, mem_index
);
519 tcg_gen_qemu_ld16s(cpu_T
[0], cpu_A0
, mem_index
);
523 tcg_gen_qemu_ld32s(cpu_T
[0], cpu_A0
, mem_index
);
528 static inline void gen_op_ld_v(int idx
, TCGv t0
, TCGv a0
)
530 int mem_index
= (idx
>> 2) - 1;
533 tcg_gen_qemu_ld8u(t0
, a0
, mem_index
);
536 tcg_gen_qemu_ld16u(t0
, a0
, mem_index
);
539 tcg_gen_qemu_ld32u(t0
, a0
, mem_index
);
543 /* Should never happen on 32-bit targets. */
545 tcg_gen_qemu_ld64(t0
, a0
, mem_index
);
551 /* XXX: always use ldu or lds */
552 static inline void gen_op_ld_T0_A0(int idx
)
554 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
557 static inline void gen_op_ldu_T0_A0(int idx
)
559 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
562 static inline void gen_op_ld_T1_A0(int idx
)
564 gen_op_ld_v(idx
, cpu_T
[1], cpu_A0
);
567 static inline void gen_op_st_v(int idx
, TCGv t0
, TCGv a0
)
569 int mem_index
= (idx
>> 2) - 1;
572 tcg_gen_qemu_st8(t0
, a0
, mem_index
);
575 tcg_gen_qemu_st16(t0
, a0
, mem_index
);
578 tcg_gen_qemu_st32(t0
, a0
, mem_index
);
582 /* Should never happen on 32-bit targets. */
584 tcg_gen_qemu_st64(t0
, a0
, mem_index
);
590 static inline void gen_op_st_T0_A0(int idx
)
592 gen_op_st_v(idx
, cpu_T
[0], cpu_A0
);
595 static inline void gen_op_st_T1_A0(int idx
)
597 gen_op_st_v(idx
, cpu_T
[1], cpu_A0
);
600 static inline void gen_jmp_im(target_ulong pc
)
602 tcg_gen_movi_tl(cpu_tmp0
, pc
);
603 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, eip
));
606 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
610 override
= s
->override
;
614 gen_op_movq_A0_seg(override
);
615 gen_op_addq_A0_reg_sN(0, R_ESI
);
617 gen_op_movq_A0_reg(R_ESI
);
623 if (s
->addseg
&& override
< 0)
626 gen_op_movl_A0_seg(override
);
627 gen_op_addl_A0_reg_sN(0, R_ESI
);
629 gen_op_movl_A0_reg(R_ESI
);
632 /* 16 address, always override */
635 gen_op_movl_A0_reg(R_ESI
);
636 gen_op_andl_A0_ffff();
637 gen_op_addl_A0_seg(override
);
641 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
645 gen_op_movq_A0_reg(R_EDI
);
650 gen_op_movl_A0_seg(R_ES
);
651 gen_op_addl_A0_reg_sN(0, R_EDI
);
653 gen_op_movl_A0_reg(R_EDI
);
656 gen_op_movl_A0_reg(R_EDI
);
657 gen_op_andl_A0_ffff();
658 gen_op_addl_A0_seg(R_ES
);
662 static inline void gen_op_movl_T0_Dshift(int ot
)
664 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, df
));
665 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
668 static void gen_extu(int ot
, TCGv reg
)
672 tcg_gen_ext8u_tl(reg
, reg
);
675 tcg_gen_ext16u_tl(reg
, reg
);
678 tcg_gen_ext32u_tl(reg
, reg
);
685 static void gen_exts(int ot
, TCGv reg
)
689 tcg_gen_ext8s_tl(reg
, reg
);
692 tcg_gen_ext16s_tl(reg
, reg
);
695 tcg_gen_ext32s_tl(reg
, reg
);
702 static inline void gen_op_jnz_ecx(int size
, int label1
)
704 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[R_ECX
]));
705 gen_extu(size
+ 1, cpu_tmp0
);
706 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
709 static inline void gen_op_jz_ecx(int size
, int label1
)
711 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[R_ECX
]));
712 gen_extu(size
+ 1, cpu_tmp0
);
713 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
716 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
719 case 0: gen_helper_inb(v
, n
); break;
720 case 1: gen_helper_inw(v
, n
); break;
721 case 2: gen_helper_inl(v
, n
); break;
726 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
729 case 0: gen_helper_outb(v
, n
); break;
730 case 1: gen_helper_outw(v
, n
); break;
731 case 2: gen_helper_outl(v
, n
); break;
736 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
740 target_ulong next_eip
;
743 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
744 if (s
->cc_op
!= CC_OP_DYNAMIC
)
745 gen_op_set_cc_op(s
->cc_op
);
748 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
750 case 0: gen_helper_check_iob(cpu_tmp2_i32
); break;
751 case 1: gen_helper_check_iow(cpu_tmp2_i32
); break;
752 case 2: gen_helper_check_iol(cpu_tmp2_i32
); break;
755 if(s
->flags
& HF_SVMI_MASK
) {
757 if (s
->cc_op
!= CC_OP_DYNAMIC
)
758 gen_op_set_cc_op(s
->cc_op
);
762 svm_flags
|= (1 << (4 + ot
));
763 next_eip
= s
->pc
- s
->cs_base
;
764 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
765 gen_helper_svm_check_io(cpu_tmp2_i32
, tcg_const_i32(svm_flags
),
766 tcg_const_i32(next_eip
- cur_eip
));
770 static inline void gen_movs(DisasContext
*s
, int ot
)
772 gen_string_movl_A0_ESI(s
);
773 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
774 gen_string_movl_A0_EDI(s
);
775 gen_op_st_T0_A0(ot
+ s
->mem_index
);
776 gen_op_movl_T0_Dshift(ot
);
777 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
778 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
781 static inline void gen_update_cc_op(DisasContext
*s
)
783 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
784 gen_op_set_cc_op(s
->cc_op
);
785 s
->cc_op
= CC_OP_DYNAMIC
;
789 static void gen_op_update1_cc(void)
791 tcg_gen_discard_tl(cpu_cc_src
);
792 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
795 static void gen_op_update2_cc(void)
797 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
798 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
801 static inline void gen_op_cmpl_T0_T1_cc(void)
803 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
804 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
807 static inline void gen_op_testl_T0_T1_cc(void)
809 tcg_gen_discard_tl(cpu_cc_src
);
810 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
813 static void gen_op_update_neg_cc(void)
815 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
816 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
819 /* compute eflags.C to reg */
820 static void gen_compute_eflags_c(TCGv reg
)
822 gen_helper_cc_compute_c(cpu_tmp2_i32
, cpu_cc_op
);
823 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
826 /* compute all eflags to cc_src */
827 static void gen_compute_eflags(TCGv reg
)
829 gen_helper_cc_compute_all(cpu_tmp2_i32
, cpu_cc_op
);
830 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
833 static inline void gen_setcc_slow_T0(DisasContext
*s
, int jcc_op
)
835 if (s
->cc_op
!= CC_OP_DYNAMIC
)
836 gen_op_set_cc_op(s
->cc_op
);
839 gen_compute_eflags(cpu_T
[0]);
840 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 11);
841 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
844 gen_compute_eflags_c(cpu_T
[0]);
847 gen_compute_eflags(cpu_T
[0]);
848 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 6);
849 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
852 gen_compute_eflags(cpu_tmp0
);
853 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 6);
854 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
855 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
858 gen_compute_eflags(cpu_T
[0]);
859 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 7);
860 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
863 gen_compute_eflags(cpu_T
[0]);
864 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 2);
865 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
868 gen_compute_eflags(cpu_tmp0
);
869 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 11); /* CC_O */
870 tcg_gen_shri_tl(cpu_tmp0
, cpu_tmp0
, 7); /* CC_S */
871 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
872 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
876 gen_compute_eflags(cpu_tmp0
);
877 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 11); /* CC_O */
878 tcg_gen_shri_tl(cpu_tmp4
, cpu_tmp0
, 7); /* CC_S */
879 tcg_gen_shri_tl(cpu_tmp0
, cpu_tmp0
, 6); /* CC_Z */
880 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
881 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
882 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
887 /* return true if setcc_slow is not needed (WARNING: must be kept in
888 sync with gen_jcc1) */
889 static int is_fast_jcc_case(DisasContext
*s
, int b
)
892 jcc_op
= (b
>> 1) & 7;
894 /* we optimize the cmp/jcc case */
899 if (jcc_op
== JCC_O
|| jcc_op
== JCC_P
)
903 /* some jumps are easy to compute */
928 if (jcc_op
!= JCC_Z
&& jcc_op
!= JCC_S
)
938 /* generate a conditional jump to label 'l1' according to jump opcode
939 value 'b'. In the fast case, T0 is guaranted not to be used. */
940 static inline void gen_jcc1(DisasContext
*s
, int cc_op
, int b
, int l1
)
942 int inv
, jcc_op
, size
, cond
;
946 jcc_op
= (b
>> 1) & 7;
949 /* we optimize the cmp/jcc case */
955 size
= cc_op
- CC_OP_SUBB
;
961 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xff);
965 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xffff);
970 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xffffffff);
978 tcg_gen_brcondi_tl(inv
? TCG_COND_NE
: TCG_COND_EQ
, t0
, 0, l1
);
984 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x80);
985 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
989 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x8000);
990 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
995 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x80000000);
996 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
1001 tcg_gen_brcondi_tl(inv
? TCG_COND_GE
: TCG_COND_LT
, cpu_cc_dst
,
1008 cond
= inv
? TCG_COND_GEU
: TCG_COND_LTU
;
1011 cond
= inv
? TCG_COND_GTU
: TCG_COND_LEU
;
1013 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1017 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xff);
1018 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xff);
1022 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xffff);
1023 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xffff);
1025 #ifdef TARGET_X86_64
1028 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xffffffff);
1029 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xffffffff);
1036 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1040 cond
= inv
? TCG_COND_GE
: TCG_COND_LT
;
1043 cond
= inv
? TCG_COND_GT
: TCG_COND_LE
;
1045 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1049 tcg_gen_ext8s_tl(cpu_tmp4
, cpu_tmp4
);
1050 tcg_gen_ext8s_tl(t0
, cpu_cc_src
);
1054 tcg_gen_ext16s_tl(cpu_tmp4
, cpu_tmp4
);
1055 tcg_gen_ext16s_tl(t0
, cpu_cc_src
);
1057 #ifdef TARGET_X86_64
1060 tcg_gen_ext32s_tl(cpu_tmp4
, cpu_tmp4
);
1061 tcg_gen_ext32s_tl(t0
, cpu_cc_src
);
1068 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1076 /* some jumps are easy to compute */
1118 size
= (cc_op
- CC_OP_ADDB
) & 3;
1121 size
= (cc_op
- CC_OP_ADDB
) & 3;
1129 gen_setcc_slow_T0(s
, jcc_op
);
1130 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
,
1136 /* XXX: does not work with gdbstub "ice" single step - not a
1138 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1142 l1
= gen_new_label();
1143 l2
= gen_new_label();
1144 gen_op_jnz_ecx(s
->aflag
, l1
);
1146 gen_jmp_tb(s
, next_eip
, 1);
1151 static inline void gen_stos(DisasContext
*s
, int ot
)
1153 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1154 gen_string_movl_A0_EDI(s
);
1155 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1156 gen_op_movl_T0_Dshift(ot
);
1157 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1160 static inline void gen_lods(DisasContext
*s
, int ot
)
1162 gen_string_movl_A0_ESI(s
);
1163 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1164 gen_op_mov_reg_T0(ot
, R_EAX
);
1165 gen_op_movl_T0_Dshift(ot
);
1166 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1169 static inline void gen_scas(DisasContext
*s
, int ot
)
1171 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1172 gen_string_movl_A0_EDI(s
);
1173 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1174 gen_op_cmpl_T0_T1_cc();
1175 gen_op_movl_T0_Dshift(ot
);
1176 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1179 static inline void gen_cmps(DisasContext
*s
, int ot
)
1181 gen_string_movl_A0_ESI(s
);
1182 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1183 gen_string_movl_A0_EDI(s
);
1184 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1185 gen_op_cmpl_T0_T1_cc();
1186 gen_op_movl_T0_Dshift(ot
);
1187 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1188 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1191 static inline void gen_ins(DisasContext
*s
, int ot
)
1195 gen_string_movl_A0_EDI(s
);
1196 /* Note: we must do this dummy write first to be restartable in
1197 case of page fault. */
1199 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1200 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1201 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1202 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1203 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1204 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1205 gen_op_movl_T0_Dshift(ot
);
1206 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1211 static inline void gen_outs(DisasContext
*s
, int ot
)
1215 gen_string_movl_A0_ESI(s
);
1216 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1218 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1219 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1220 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1221 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1222 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1224 gen_op_movl_T0_Dshift(ot
);
1225 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1230 /* same method as Valgrind : we generate jumps to current or next
1232 #define GEN_REPZ(op) \
1233 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1234 target_ulong cur_eip, target_ulong next_eip) \
1237 gen_update_cc_op(s); \
1238 l2 = gen_jz_ecx_string(s, next_eip); \
1239 gen_ ## op(s, ot); \
1240 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1241 /* a loop would cause two single step exceptions if ECX = 1 \
1242 before rep string_insn */ \
1244 gen_op_jz_ecx(s->aflag, l2); \
1245 gen_jmp(s, cur_eip); \
1248 #define GEN_REPZ2(op) \
1249 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1250 target_ulong cur_eip, \
1251 target_ulong next_eip, \
1255 gen_update_cc_op(s); \
1256 l2 = gen_jz_ecx_string(s, next_eip); \
1257 gen_ ## op(s, ot); \
1258 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1259 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1260 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1262 gen_op_jz_ecx(s->aflag, l2); \
1263 gen_jmp(s, cur_eip); \
1274 static void gen_helper_fp_arith_ST0_FT0(int op
)
1277 case 0: gen_helper_fadd_ST0_FT0(); break;
1278 case 1: gen_helper_fmul_ST0_FT0(); break;
1279 case 2: gen_helper_fcom_ST0_FT0(); break;
1280 case 3: gen_helper_fcom_ST0_FT0(); break;
1281 case 4: gen_helper_fsub_ST0_FT0(); break;
1282 case 5: gen_helper_fsubr_ST0_FT0(); break;
1283 case 6: gen_helper_fdiv_ST0_FT0(); break;
1284 case 7: gen_helper_fdivr_ST0_FT0(); break;
1288 /* NOTE the exception in "r" op ordering */
1289 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1291 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1293 case 0: gen_helper_fadd_STN_ST0(tmp
); break;
1294 case 1: gen_helper_fmul_STN_ST0(tmp
); break;
1295 case 4: gen_helper_fsubr_STN_ST0(tmp
); break;
1296 case 5: gen_helper_fsub_STN_ST0(tmp
); break;
1297 case 6: gen_helper_fdivr_STN_ST0(tmp
); break;
1298 case 7: gen_helper_fdiv_STN_ST0(tmp
); break;
1302 /* if d == OR_TMP0, it means memory operand (address in A0) */
1303 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1306 gen_op_mov_TN_reg(ot
, 0, d
);
1308 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1312 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1313 gen_op_set_cc_op(s1
->cc_op
);
1314 gen_compute_eflags_c(cpu_tmp4
);
1315 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1316 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1318 gen_op_mov_reg_T0(ot
, d
);
1320 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1321 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1322 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1323 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1324 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1325 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_ADDB
+ ot
);
1326 s1
->cc_op
= CC_OP_DYNAMIC
;
1329 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1330 gen_op_set_cc_op(s1
->cc_op
);
1331 gen_compute_eflags_c(cpu_tmp4
);
1332 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1333 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1335 gen_op_mov_reg_T0(ot
, d
);
1337 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1338 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1339 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1340 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1341 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1342 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_SUBB
+ ot
);
1343 s1
->cc_op
= CC_OP_DYNAMIC
;
1346 gen_op_addl_T0_T1();
1348 gen_op_mov_reg_T0(ot
, d
);
1350 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1351 gen_op_update2_cc();
1352 s1
->cc_op
= CC_OP_ADDB
+ ot
;
1355 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1357 gen_op_mov_reg_T0(ot
, d
);
1359 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1360 gen_op_update2_cc();
1361 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1365 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1367 gen_op_mov_reg_T0(ot
, d
);
1369 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1370 gen_op_update1_cc();
1371 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1374 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1376 gen_op_mov_reg_T0(ot
, d
);
1378 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1379 gen_op_update1_cc();
1380 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1383 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1385 gen_op_mov_reg_T0(ot
, d
);
1387 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1388 gen_op_update1_cc();
1389 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1392 gen_op_cmpl_T0_T1_cc();
1393 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1398 /* if d == OR_TMP0, it means memory operand (address in A0) */
1399 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1402 gen_op_mov_TN_reg(ot
, 0, d
);
1404 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1405 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1406 gen_op_set_cc_op(s1
->cc_op
);
1408 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1409 s1
->cc_op
= CC_OP_INCB
+ ot
;
1411 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1412 s1
->cc_op
= CC_OP_DECB
+ ot
;
1415 gen_op_mov_reg_T0(ot
, d
);
1417 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1418 gen_compute_eflags_c(cpu_cc_src
);
1419 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1422 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1423 int is_right
, int is_arith
)
1436 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1438 gen_op_mov_TN_reg(ot
, 0, op1
);
1440 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1442 tcg_gen_addi_tl(cpu_tmp5
, cpu_T
[1], -1);
1446 gen_exts(ot
, cpu_T
[0]);
1447 tcg_gen_sar_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1448 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1450 gen_extu(ot
, cpu_T
[0]);
1451 tcg_gen_shr_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1452 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1455 tcg_gen_shl_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1456 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1461 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1463 gen_op_mov_reg_T0(ot
, op1
);
1465 /* update eflags if non zero shift */
1466 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1467 gen_op_set_cc_op(s
->cc_op
);
1469 /* XXX: inefficient */
1470 t0
= tcg_temp_local_new();
1471 t1
= tcg_temp_local_new();
1473 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1474 tcg_gen_mov_tl(t1
, cpu_T3
);
1476 shift_label
= gen_new_label();
1477 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_T
[1], 0, shift_label
);
1479 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1480 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1482 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1484 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1486 gen_set_label(shift_label
);
1487 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1493 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1494 int is_right
, int is_arith
)
1505 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1507 gen_op_mov_TN_reg(ot
, 0, op1
);
1513 gen_exts(ot
, cpu_T
[0]);
1514 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1515 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1517 gen_extu(ot
, cpu_T
[0]);
1518 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1519 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1522 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1523 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1529 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1531 gen_op_mov_reg_T0(ot
, op1
);
1533 /* update eflags if non zero shift */
1535 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1536 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1538 s
->cc_op
= CC_OP_SARB
+ ot
;
1540 s
->cc_op
= CC_OP_SHLB
+ ot
;
1544 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1547 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1549 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1552 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
,
1556 int label1
, label2
, data_bits
;
1557 TCGv t0
, t1
, t2
, a0
;
1559 /* XXX: inefficient, but we must use local temps */
1560 t0
= tcg_temp_local_new();
1561 t1
= tcg_temp_local_new();
1562 t2
= tcg_temp_local_new();
1563 a0
= tcg_temp_local_new();
1571 if (op1
== OR_TMP0
) {
1572 tcg_gen_mov_tl(a0
, cpu_A0
);
1573 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1575 gen_op_mov_v_reg(ot
, t0
, op1
);
1578 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1580 tcg_gen_andi_tl(t1
, t1
, mask
);
1582 /* Must test zero case to avoid using undefined behaviour in TCG
1584 label1
= gen_new_label();
1585 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label1
);
1588 tcg_gen_andi_tl(cpu_tmp0
, t1
, (1 << (3 + ot
)) - 1);
1590 tcg_gen_mov_tl(cpu_tmp0
, t1
);
1593 tcg_gen_mov_tl(t2
, t0
);
1595 data_bits
= 8 << ot
;
1596 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1597 fix TCG definition) */
1599 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1600 tcg_gen_sub_tl(cpu_tmp0
, tcg_const_tl(data_bits
), cpu_tmp0
);
1601 tcg_gen_shl_tl(t0
, t0
, cpu_tmp0
);
1603 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1604 tcg_gen_sub_tl(cpu_tmp0
, tcg_const_tl(data_bits
), cpu_tmp0
);
1605 tcg_gen_shr_tl(t0
, t0
, cpu_tmp0
);
1607 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1609 gen_set_label(label1
);
1611 if (op1
== OR_TMP0
) {
1612 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1614 gen_op_mov_reg_v(ot
, op1
, t0
);
1618 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1619 gen_op_set_cc_op(s
->cc_op
);
1621 label2
= gen_new_label();
1622 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label2
);
1624 gen_compute_eflags(cpu_cc_src
);
1625 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1626 tcg_gen_xor_tl(cpu_tmp0
, t2
, t0
);
1627 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1628 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1629 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1631 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1633 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1634 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1636 tcg_gen_discard_tl(cpu_cc_dst
);
1637 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1639 gen_set_label(label2
);
1640 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1648 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1655 /* XXX: inefficient, but we must use local temps */
1656 t0
= tcg_temp_local_new();
1657 t1
= tcg_temp_local_new();
1658 a0
= tcg_temp_local_new();
1666 if (op1
== OR_TMP0
) {
1667 tcg_gen_mov_tl(a0
, cpu_A0
);
1668 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1670 gen_op_mov_v_reg(ot
, t0
, op1
);
1674 tcg_gen_mov_tl(t1
, t0
);
1677 data_bits
= 8 << ot
;
1679 int shift
= op2
& ((1 << (3 + ot
)) - 1);
1681 tcg_gen_shri_tl(cpu_tmp4
, t0
, shift
);
1682 tcg_gen_shli_tl(t0
, t0
, data_bits
- shift
);
1685 tcg_gen_shli_tl(cpu_tmp4
, t0
, shift
);
1686 tcg_gen_shri_tl(t0
, t0
, data_bits
- shift
);
1688 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1692 if (op1
== OR_TMP0
) {
1693 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1695 gen_op_mov_reg_v(ot
, op1
, t0
);
1700 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1701 gen_op_set_cc_op(s
->cc_op
);
1703 gen_compute_eflags(cpu_cc_src
);
1704 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1705 tcg_gen_xor_tl(cpu_tmp0
, t1
, t0
);
1706 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1707 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1708 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1710 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1712 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1713 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1715 tcg_gen_discard_tl(cpu_cc_dst
);
1716 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1717 s
->cc_op
= CC_OP_EFLAGS
;
1725 /* XXX: add faster immediate = 1 case */
1726 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1731 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1732 gen_op_set_cc_op(s
->cc_op
);
1736 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1738 gen_op_mov_TN_reg(ot
, 0, op1
);
1742 case 0: gen_helper_rcrb(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1743 case 1: gen_helper_rcrw(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1744 case 2: gen_helper_rcrl(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1745 #ifdef TARGET_X86_64
1746 case 3: gen_helper_rcrq(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1751 case 0: gen_helper_rclb(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1752 case 1: gen_helper_rclw(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1753 case 2: gen_helper_rcll(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1754 #ifdef TARGET_X86_64
1755 case 3: gen_helper_rclq(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1761 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1763 gen_op_mov_reg_T0(ot
, op1
);
1766 label1
= gen_new_label();
1767 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_cc_tmp
, -1, label1
);
1769 tcg_gen_mov_tl(cpu_cc_src
, cpu_cc_tmp
);
1770 tcg_gen_discard_tl(cpu_cc_dst
);
1771 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1773 gen_set_label(label1
);
1774 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1777 /* XXX: add faster immediate case */
1778 static void gen_shiftd_rm_T1_T3(DisasContext
*s
, int ot
, int op1
,
1781 int label1
, label2
, data_bits
;
1783 TCGv t0
, t1
, t2
, a0
;
1785 t0
= tcg_temp_local_new();
1786 t1
= tcg_temp_local_new();
1787 t2
= tcg_temp_local_new();
1788 a0
= tcg_temp_local_new();
1796 if (op1
== OR_TMP0
) {
1797 tcg_gen_mov_tl(a0
, cpu_A0
);
1798 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1800 gen_op_mov_v_reg(ot
, t0
, op1
);
1803 tcg_gen_andi_tl(cpu_T3
, cpu_T3
, mask
);
1805 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1806 tcg_gen_mov_tl(t2
, cpu_T3
);
1808 /* Must test zero case to avoid using undefined behaviour in TCG
1810 label1
= gen_new_label();
1811 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
1813 tcg_gen_addi_tl(cpu_tmp5
, t2
, -1);
1814 if (ot
== OT_WORD
) {
1815 /* Note: we implement the Intel behaviour for shift count > 16 */
1817 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1818 tcg_gen_shli_tl(cpu_tmp0
, t1
, 16);
1819 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1820 tcg_gen_ext32u_tl(t0
, t0
);
1822 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1824 /* only needed if count > 16, but a test would complicate */
1825 tcg_gen_sub_tl(cpu_tmp5
, tcg_const_tl(32), t2
);
1826 tcg_gen_shl_tl(cpu_tmp0
, t0
, cpu_tmp5
);
1828 tcg_gen_shr_tl(t0
, t0
, t2
);
1830 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1832 /* XXX: not optimal */
1833 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1834 tcg_gen_shli_tl(t1
, t1
, 16);
1835 tcg_gen_or_tl(t1
, t1
, t0
);
1836 tcg_gen_ext32u_tl(t1
, t1
);
1838 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1839 tcg_gen_sub_tl(cpu_tmp0
, tcg_const_tl(32), cpu_tmp5
);
1840 tcg_gen_shr_tl(cpu_tmp6
, t1
, cpu_tmp0
);
1841 tcg_gen_or_tl(cpu_tmp4
, cpu_tmp4
, cpu_tmp6
);
1843 tcg_gen_shl_tl(t0
, t0
, t2
);
1844 tcg_gen_sub_tl(cpu_tmp5
, tcg_const_tl(32), t2
);
1845 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1846 tcg_gen_or_tl(t0
, t0
, t1
);
1849 data_bits
= 8 << ot
;
1852 tcg_gen_ext32u_tl(t0
, t0
);
1854 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1856 tcg_gen_shr_tl(t0
, t0
, t2
);
1857 tcg_gen_sub_tl(cpu_tmp5
, tcg_const_tl(data_bits
), t2
);
1858 tcg_gen_shl_tl(t1
, t1
, cpu_tmp5
);
1859 tcg_gen_or_tl(t0
, t0
, t1
);
1863 tcg_gen_ext32u_tl(t1
, t1
);
1865 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1867 tcg_gen_shl_tl(t0
, t0
, t2
);
1868 tcg_gen_sub_tl(cpu_tmp5
, tcg_const_tl(data_bits
), t2
);
1869 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1870 tcg_gen_or_tl(t0
, t0
, t1
);
1873 tcg_gen_mov_tl(t1
, cpu_tmp4
);
1875 gen_set_label(label1
);
1877 if (op1
== OR_TMP0
) {
1878 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1880 gen_op_mov_reg_v(ot
, op1
, t0
);
1884 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1885 gen_op_set_cc_op(s
->cc_op
);
1887 label2
= gen_new_label();
1888 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label2
);
1890 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1891 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1893 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1895 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1897 gen_set_label(label2
);
1898 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1906 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
1909 gen_op_mov_TN_reg(ot
, 1, s
);
1912 gen_rot_rm_T1(s1
, ot
, d
, 0);
1915 gen_rot_rm_T1(s1
, ot
, d
, 1);
1919 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1922 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1925 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1928 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1931 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1936 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
1940 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1943 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1947 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1950 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1953 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1956 /* currently not optimized */
1957 gen_op_movl_T1_im(c
);
1958 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1963 static void gen_lea_modrm(DisasContext
*s
, int modrm
, int *reg_ptr
, int *offset_ptr
)
1971 int mod
, rm
, code
, override
, must_add_seg
;
1973 override
= s
->override
;
1974 must_add_seg
= s
->addseg
;
1977 mod
= (modrm
>> 6) & 3;
1989 code
= ldub_code(s
->pc
++);
1990 scale
= (code
>> 6) & 3;
1991 index
= ((code
>> 3) & 7) | REX_X(s
);
1998 if ((base
& 7) == 5) {
2000 disp
= (int32_t)ldl_code(s
->pc
);
2002 if (CODE64(s
) && !havesib
) {
2003 disp
+= s
->pc
+ s
->rip_offset
;
2010 disp
= (int8_t)ldub_code(s
->pc
++);
2014 disp
= ldl_code(s
->pc
);
2020 /* for correct popl handling with esp */
2021 if (base
== 4 && s
->popl_esp_hack
)
2022 disp
+= s
->popl_esp_hack
;
2023 #ifdef TARGET_X86_64
2024 if (s
->aflag
== 2) {
2025 gen_op_movq_A0_reg(base
);
2027 gen_op_addq_A0_im(disp
);
2032 gen_op_movl_A0_reg(base
);
2034 gen_op_addl_A0_im(disp
);
2037 #ifdef TARGET_X86_64
2038 if (s
->aflag
== 2) {
2039 gen_op_movq_A0_im(disp
);
2043 gen_op_movl_A0_im(disp
);
2046 /* XXX: index == 4 is always invalid */
2047 if (havesib
&& (index
!= 4 || scale
!= 0)) {
2048 #ifdef TARGET_X86_64
2049 if (s
->aflag
== 2) {
2050 gen_op_addq_A0_reg_sN(scale
, index
);
2054 gen_op_addl_A0_reg_sN(scale
, index
);
2059 if (base
== R_EBP
|| base
== R_ESP
)
2064 #ifdef TARGET_X86_64
2065 if (s
->aflag
== 2) {
2066 gen_op_addq_A0_seg(override
);
2070 gen_op_addl_A0_seg(override
);
2077 disp
= lduw_code(s
->pc
);
2079 gen_op_movl_A0_im(disp
);
2080 rm
= 0; /* avoid SS override */
2087 disp
= (int8_t)ldub_code(s
->pc
++);
2091 disp
= lduw_code(s
->pc
);
2097 gen_op_movl_A0_reg(R_EBX
);
2098 gen_op_addl_A0_reg_sN(0, R_ESI
);
2101 gen_op_movl_A0_reg(R_EBX
);
2102 gen_op_addl_A0_reg_sN(0, R_EDI
);
2105 gen_op_movl_A0_reg(R_EBP
);
2106 gen_op_addl_A0_reg_sN(0, R_ESI
);
2109 gen_op_movl_A0_reg(R_EBP
);
2110 gen_op_addl_A0_reg_sN(0, R_EDI
);
2113 gen_op_movl_A0_reg(R_ESI
);
2116 gen_op_movl_A0_reg(R_EDI
);
2119 gen_op_movl_A0_reg(R_EBP
);
2123 gen_op_movl_A0_reg(R_EBX
);
2127 gen_op_addl_A0_im(disp
);
2128 gen_op_andl_A0_ffff();
2132 if (rm
== 2 || rm
== 3 || rm
== 6)
2137 gen_op_addl_A0_seg(override
);
2147 static void gen_nop_modrm(DisasContext
*s
, int modrm
)
2149 int mod
, rm
, base
, code
;
2151 mod
= (modrm
>> 6) & 3;
2161 code
= ldub_code(s
->pc
++);
2197 /* used for LEA and MOV AX, mem */
2198 static void gen_add_A0_ds_seg(DisasContext
*s
)
2200 int override
, must_add_seg
;
2201 must_add_seg
= s
->addseg
;
2203 if (s
->override
>= 0) {
2204 override
= s
->override
;
2210 #ifdef TARGET_X86_64
2212 gen_op_addq_A0_seg(override
);
2216 gen_op_addl_A0_seg(override
);
2221 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2223 static void gen_ldst_modrm(DisasContext
*s
, int modrm
, int ot
, int reg
, int is_store
)
2225 int mod
, rm
, opreg
, disp
;
2227 mod
= (modrm
>> 6) & 3;
2228 rm
= (modrm
& 7) | REX_B(s
);
2232 gen_op_mov_TN_reg(ot
, 0, reg
);
2233 gen_op_mov_reg_T0(ot
, rm
);
2235 gen_op_mov_TN_reg(ot
, 0, rm
);
2237 gen_op_mov_reg_T0(ot
, reg
);
2240 gen_lea_modrm(s
, modrm
, &opreg
, &disp
);
2243 gen_op_mov_TN_reg(ot
, 0, reg
);
2244 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2246 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
2248 gen_op_mov_reg_T0(ot
, reg
);
2253 static inline uint32_t insn_get(DisasContext
*s
, int ot
)
2259 ret
= ldub_code(s
->pc
);
2263 ret
= lduw_code(s
->pc
);
2268 ret
= ldl_code(s
->pc
);
2275 static inline int insn_const_size(unsigned int ot
)
2283 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2285 TranslationBlock
*tb
;
2288 pc
= s
->cs_base
+ eip
;
2290 /* NOTE: we handle the case where the TB spans two pages here */
2291 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2292 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2293 /* jump to same page: we can use a direct jump */
2294 tcg_gen_goto_tb(tb_num
);
2296 tcg_gen_exit_tb((long)tb
+ tb_num
);
2298 /* jump to another page: currently not optimized */
2304 static inline void gen_jcc(DisasContext
*s
, int b
,
2305 target_ulong val
, target_ulong next_eip
)
2310 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
2311 gen_op_set_cc_op(s
->cc_op
);
2312 s
->cc_op
= CC_OP_DYNAMIC
;
2315 l1
= gen_new_label();
2316 gen_jcc1(s
, cc_op
, b
, l1
);
2318 gen_goto_tb(s
, 0, next_eip
);
2321 gen_goto_tb(s
, 1, val
);
2325 l1
= gen_new_label();
2326 l2
= gen_new_label();
2327 gen_jcc1(s
, cc_op
, b
, l1
);
2329 gen_jmp_im(next_eip
);
2339 static void gen_setcc(DisasContext
*s
, int b
)
2341 int inv
, jcc_op
, l1
;
2344 if (is_fast_jcc_case(s
, b
)) {
2345 /* nominal case: we use a jump */
2346 /* XXX: make it faster by adding new instructions in TCG */
2347 t0
= tcg_temp_local_new();
2348 tcg_gen_movi_tl(t0
, 0);
2349 l1
= gen_new_label();
2350 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
2351 tcg_gen_movi_tl(t0
, 1);
2353 tcg_gen_mov_tl(cpu_T
[0], t0
);
2356 /* slow case: it is more efficient not to generate a jump,
2357 although it is questionnable whether this optimization is
2360 jcc_op
= (b
>> 1) & 7;
2361 gen_setcc_slow_T0(s
, jcc_op
);
2363 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], 1);
2368 static inline void gen_op_movl_T0_seg(int seg_reg
)
2370 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2371 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2374 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2376 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2377 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2378 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2379 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2380 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2381 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2384 /* move T0 to seg_reg and compute if the CPU state may change. Never
2385 call this function with seg_reg == R_CS */
2386 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2388 if (s
->pe
&& !s
->vm86
) {
2389 /* XXX: optimize by finding processor state dynamically */
2390 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2391 gen_op_set_cc_op(s
->cc_op
);
2392 gen_jmp_im(cur_eip
);
2393 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2394 gen_helper_load_seg(tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2395 /* abort translation because the addseg value may change or
2396 because ss32 may change. For R_SS, translation must always
2397 stop as a special handling must be done to disable hardware
2398 interrupts for the next instruction */
2399 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2402 gen_op_movl_seg_T0_vm(seg_reg
);
2403 if (seg_reg
== R_SS
)
2408 static inline int svm_is_rep(int prefixes
)
2410 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2414 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2415 uint32_t type
, uint64_t param
)
2417 /* no SVM activated; fast case */
2418 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2420 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2421 gen_op_set_cc_op(s
->cc_op
);
2422 gen_jmp_im(pc_start
- s
->cs_base
);
2423 gen_helper_svm_check_intercept_param(tcg_const_i32(type
),
2424 tcg_const_i64(param
));
2428 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2430 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2433 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2435 #ifdef TARGET_X86_64
2437 gen_op_add_reg_im(2, R_ESP
, addend
);
2441 gen_op_add_reg_im(1, R_ESP
, addend
);
2443 gen_op_add_reg_im(0, R_ESP
, addend
);
2447 /* generate a push. It depends on ss32, addseg and dflag */
2448 static void gen_push_T0(DisasContext
*s
)
2450 #ifdef TARGET_X86_64
2452 gen_op_movq_A0_reg(R_ESP
);
2454 gen_op_addq_A0_im(-8);
2455 gen_op_st_T0_A0(OT_QUAD
+ s
->mem_index
);
2457 gen_op_addq_A0_im(-2);
2458 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2460 gen_op_mov_reg_A0(2, R_ESP
);
2464 gen_op_movl_A0_reg(R_ESP
);
2466 gen_op_addl_A0_im(-2);
2468 gen_op_addl_A0_im(-4);
2471 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2472 gen_op_addl_A0_seg(R_SS
);
2475 gen_op_andl_A0_ffff();
2476 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2477 gen_op_addl_A0_seg(R_SS
);
2479 gen_op_st_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2480 if (s
->ss32
&& !s
->addseg
)
2481 gen_op_mov_reg_A0(1, R_ESP
);
2483 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2487 /* generate a push. It depends on ss32, addseg and dflag */
2488 /* slower version for T1, only used for call Ev */
2489 static void gen_push_T1(DisasContext
*s
)
2491 #ifdef TARGET_X86_64
2493 gen_op_movq_A0_reg(R_ESP
);
2495 gen_op_addq_A0_im(-8);
2496 gen_op_st_T1_A0(OT_QUAD
+ s
->mem_index
);
2498 gen_op_addq_A0_im(-2);
2499 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2501 gen_op_mov_reg_A0(2, R_ESP
);
2505 gen_op_movl_A0_reg(R_ESP
);
2507 gen_op_addl_A0_im(-2);
2509 gen_op_addl_A0_im(-4);
2512 gen_op_addl_A0_seg(R_SS
);
2515 gen_op_andl_A0_ffff();
2516 gen_op_addl_A0_seg(R_SS
);
2518 gen_op_st_T1_A0(s
->dflag
+ 1 + s
->mem_index
);
2520 if (s
->ss32
&& !s
->addseg
)
2521 gen_op_mov_reg_A0(1, R_ESP
);
2523 gen_stack_update(s
, (-2) << s
->dflag
);
2527 /* two step pop is necessary for precise exceptions */
2528 static void gen_pop_T0(DisasContext
*s
)
2530 #ifdef TARGET_X86_64
2532 gen_op_movq_A0_reg(R_ESP
);
2533 gen_op_ld_T0_A0((s
->dflag
? OT_QUAD
: OT_WORD
) + s
->mem_index
);
2537 gen_op_movl_A0_reg(R_ESP
);
2540 gen_op_addl_A0_seg(R_SS
);
2542 gen_op_andl_A0_ffff();
2543 gen_op_addl_A0_seg(R_SS
);
2545 gen_op_ld_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2549 static void gen_pop_update(DisasContext
*s
)
2551 #ifdef TARGET_X86_64
2552 if (CODE64(s
) && s
->dflag
) {
2553 gen_stack_update(s
, 8);
2557 gen_stack_update(s
, 2 << s
->dflag
);
2561 static void gen_stack_A0(DisasContext
*s
)
2563 gen_op_movl_A0_reg(R_ESP
);
2565 gen_op_andl_A0_ffff();
2566 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2568 gen_op_addl_A0_seg(R_SS
);
2571 /* NOTE: wrap around in 16 bit not fully handled */
2572 static void gen_pusha(DisasContext
*s
)
2575 gen_op_movl_A0_reg(R_ESP
);
2576 gen_op_addl_A0_im(-16 << s
->dflag
);
2578 gen_op_andl_A0_ffff();
2579 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2581 gen_op_addl_A0_seg(R_SS
);
2582 for(i
= 0;i
< 8; i
++) {
2583 gen_op_mov_TN_reg(OT_LONG
, 0, 7 - i
);
2584 gen_op_st_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2585 gen_op_addl_A0_im(2 << s
->dflag
);
2587 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2590 /* NOTE: wrap around in 16 bit not fully handled */
2591 static void gen_popa(DisasContext
*s
)
2594 gen_op_movl_A0_reg(R_ESP
);
2596 gen_op_andl_A0_ffff();
2597 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2598 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2600 gen_op_addl_A0_seg(R_SS
);
2601 for(i
= 0;i
< 8; i
++) {
2602 /* ESP is not reloaded */
2604 gen_op_ld_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2605 gen_op_mov_reg_T0(OT_WORD
+ s
->dflag
, 7 - i
);
2607 gen_op_addl_A0_im(2 << s
->dflag
);
2609 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2612 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2617 #ifdef TARGET_X86_64
2619 ot
= s
->dflag
? OT_QUAD
: OT_WORD
;
2622 gen_op_movl_A0_reg(R_ESP
);
2623 gen_op_addq_A0_im(-opsize
);
2624 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2627 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2628 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2630 /* XXX: must save state */
2631 gen_helper_enter64_level(tcg_const_i32(level
),
2632 tcg_const_i32((ot
== OT_QUAD
)),
2635 gen_op_mov_reg_T1(ot
, R_EBP
);
2636 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2637 gen_op_mov_reg_T1(OT_QUAD
, R_ESP
);
2641 ot
= s
->dflag
+ OT_WORD
;
2642 opsize
= 2 << s
->dflag
;
2644 gen_op_movl_A0_reg(R_ESP
);
2645 gen_op_addl_A0_im(-opsize
);
2647 gen_op_andl_A0_ffff();
2648 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2650 gen_op_addl_A0_seg(R_SS
);
2652 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2653 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2655 /* XXX: must save state */
2656 gen_helper_enter_level(tcg_const_i32(level
),
2657 tcg_const_i32(s
->dflag
),
2660 gen_op_mov_reg_T1(ot
, R_EBP
);
2661 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2662 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2666 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2668 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2669 gen_op_set_cc_op(s
->cc_op
);
2670 gen_jmp_im(cur_eip
);
2671 gen_helper_raise_exception(tcg_const_i32(trapno
));
2675 /* an interrupt is different from an exception because of the
2677 static void gen_interrupt(DisasContext
*s
, int intno
,
2678 target_ulong cur_eip
, target_ulong next_eip
)
2680 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2681 gen_op_set_cc_op(s
->cc_op
);
2682 gen_jmp_im(cur_eip
);
2683 gen_helper_raise_interrupt(tcg_const_i32(intno
),
2684 tcg_const_i32(next_eip
- cur_eip
));
2688 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2690 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2691 gen_op_set_cc_op(s
->cc_op
);
2692 gen_jmp_im(cur_eip
);
2697 /* generate a generic end of block. Trace exception is also generated
2699 static void gen_eob(DisasContext
*s
)
2701 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2702 gen_op_set_cc_op(s
->cc_op
);
2703 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2704 gen_helper_reset_inhibit_irq();
2706 if (s
->tb
->flags
& HF_RF_MASK
) {
2707 gen_helper_reset_rf();
2709 if (s
->singlestep_enabled
) {
2712 gen_helper_single_step();
2719 /* generate a jump to eip. No segment change must happen before as a
2720 direct call to the next block may occur */
2721 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2724 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
2725 gen_op_set_cc_op(s
->cc_op
);
2726 s
->cc_op
= CC_OP_DYNAMIC
;
2728 gen_goto_tb(s
, tb_num
, eip
);
2736 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2738 gen_jmp_tb(s
, eip
, 0);
2741 static inline void gen_ldq_env_A0(int idx
, int offset
)
2743 int mem_index
= (idx
>> 2) - 1;
2744 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2745 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2748 static inline void gen_stq_env_A0(int idx
, int offset
)
2750 int mem_index
= (idx
>> 2) - 1;
2751 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2752 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2755 static inline void gen_ldo_env_A0(int idx
, int offset
)
2757 int mem_index
= (idx
>> 2) - 1;
2758 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2759 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2760 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2761 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2762 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2765 static inline void gen_sto_env_A0(int idx
, int offset
)
2767 int mem_index
= (idx
>> 2) - 1;
2768 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2769 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2770 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2771 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2772 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2775 static inline void gen_op_movo(int d_offset
, int s_offset
)
2777 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2778 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2779 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2780 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2783 static inline void gen_op_movq(int d_offset
, int s_offset
)
2785 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2786 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2789 static inline void gen_op_movl(int d_offset
, int s_offset
)
2791 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2792 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2795 static inline void gen_op_movq_env_0(int d_offset
)
2797 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2798 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2801 #define SSE_SPECIAL ((void *)1)
2802 #define SSE_DUMMY ((void *)2)
2804 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2805 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2806 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2808 static void *sse_op_table1
[256][4] = {
2809 /* 3DNow! extensions */
2810 [0x0e] = { SSE_DUMMY
}, /* femms */
2811 [0x0f] = { SSE_DUMMY
}, /* pf... */
2812 /* pure SSE operations */
2813 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2814 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2815 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2816 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2817 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2818 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2819 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2820 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2822 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2823 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2824 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2825 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd */
2826 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2827 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2828 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2829 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2830 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2831 [0x51] = SSE_FOP(sqrt
),
2832 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2833 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2834 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2835 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2836 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2837 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2838 [0x58] = SSE_FOP(add
),
2839 [0x59] = SSE_FOP(mul
),
2840 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2841 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2842 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2843 [0x5c] = SSE_FOP(sub
),
2844 [0x5d] = SSE_FOP(min
),
2845 [0x5e] = SSE_FOP(div
),
2846 [0x5f] = SSE_FOP(max
),
2848 [0xc2] = SSE_FOP(cmpeq
),
2849 [0xc6] = { gen_helper_shufps
, gen_helper_shufpd
},
2851 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2852 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2854 /* MMX ops and their SSE extensions */
2855 [0x60] = MMX_OP2(punpcklbw
),
2856 [0x61] = MMX_OP2(punpcklwd
),
2857 [0x62] = MMX_OP2(punpckldq
),
2858 [0x63] = MMX_OP2(packsswb
),
2859 [0x64] = MMX_OP2(pcmpgtb
),
2860 [0x65] = MMX_OP2(pcmpgtw
),
2861 [0x66] = MMX_OP2(pcmpgtl
),
2862 [0x67] = MMX_OP2(packuswb
),
2863 [0x68] = MMX_OP2(punpckhbw
),
2864 [0x69] = MMX_OP2(punpckhwd
),
2865 [0x6a] = MMX_OP2(punpckhdq
),
2866 [0x6b] = MMX_OP2(packssdw
),
2867 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2868 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2869 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2870 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2871 [0x70] = { gen_helper_pshufw_mmx
,
2872 gen_helper_pshufd_xmm
,
2873 gen_helper_pshufhw_xmm
,
2874 gen_helper_pshuflw_xmm
},
2875 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2876 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2877 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2878 [0x74] = MMX_OP2(pcmpeqb
),
2879 [0x75] = MMX_OP2(pcmpeqw
),
2880 [0x76] = MMX_OP2(pcmpeql
),
2881 [0x77] = { SSE_DUMMY
}, /* emms */
2882 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2883 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2884 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2885 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2886 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2887 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2888 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2889 [0xd1] = MMX_OP2(psrlw
),
2890 [0xd2] = MMX_OP2(psrld
),
2891 [0xd3] = MMX_OP2(psrlq
),
2892 [0xd4] = MMX_OP2(paddq
),
2893 [0xd5] = MMX_OP2(pmullw
),
2894 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2895 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2896 [0xd8] = MMX_OP2(psubusb
),
2897 [0xd9] = MMX_OP2(psubusw
),
2898 [0xda] = MMX_OP2(pminub
),
2899 [0xdb] = MMX_OP2(pand
),
2900 [0xdc] = MMX_OP2(paddusb
),
2901 [0xdd] = MMX_OP2(paddusw
),
2902 [0xde] = MMX_OP2(pmaxub
),
2903 [0xdf] = MMX_OP2(pandn
),
2904 [0xe0] = MMX_OP2(pavgb
),
2905 [0xe1] = MMX_OP2(psraw
),
2906 [0xe2] = MMX_OP2(psrad
),
2907 [0xe3] = MMX_OP2(pavgw
),
2908 [0xe4] = MMX_OP2(pmulhuw
),
2909 [0xe5] = MMX_OP2(pmulhw
),
2910 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2911 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2912 [0xe8] = MMX_OP2(psubsb
),
2913 [0xe9] = MMX_OP2(psubsw
),
2914 [0xea] = MMX_OP2(pminsw
),
2915 [0xeb] = MMX_OP2(por
),
2916 [0xec] = MMX_OP2(paddsb
),
2917 [0xed] = MMX_OP2(paddsw
),
2918 [0xee] = MMX_OP2(pmaxsw
),
2919 [0xef] = MMX_OP2(pxor
),
2920 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2921 [0xf1] = MMX_OP2(psllw
),
2922 [0xf2] = MMX_OP2(pslld
),
2923 [0xf3] = MMX_OP2(psllq
),
2924 [0xf4] = MMX_OP2(pmuludq
),
2925 [0xf5] = MMX_OP2(pmaddwd
),
2926 [0xf6] = MMX_OP2(psadbw
),
2927 [0xf7] = MMX_OP2(maskmov
),
2928 [0xf8] = MMX_OP2(psubb
),
2929 [0xf9] = MMX_OP2(psubw
),
2930 [0xfa] = MMX_OP2(psubl
),
2931 [0xfb] = MMX_OP2(psubq
),
2932 [0xfc] = MMX_OP2(paddb
),
2933 [0xfd] = MMX_OP2(paddw
),
2934 [0xfe] = MMX_OP2(paddl
),
2937 static void *sse_op_table2
[3 * 8][2] = {
2938 [0 + 2] = MMX_OP2(psrlw
),
2939 [0 + 4] = MMX_OP2(psraw
),
2940 [0 + 6] = MMX_OP2(psllw
),
2941 [8 + 2] = MMX_OP2(psrld
),
2942 [8 + 4] = MMX_OP2(psrad
),
2943 [8 + 6] = MMX_OP2(pslld
),
2944 [16 + 2] = MMX_OP2(psrlq
),
2945 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2946 [16 + 6] = MMX_OP2(psllq
),
2947 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2950 static void *sse_op_table3
[4 * 3] = {
2951 gen_helper_cvtsi2ss
,
2952 gen_helper_cvtsi2sd
,
2953 X86_64_ONLY(gen_helper_cvtsq2ss
),
2954 X86_64_ONLY(gen_helper_cvtsq2sd
),
2956 gen_helper_cvttss2si
,
2957 gen_helper_cvttsd2si
,
2958 X86_64_ONLY(gen_helper_cvttss2sq
),
2959 X86_64_ONLY(gen_helper_cvttsd2sq
),
2961 gen_helper_cvtss2si
,
2962 gen_helper_cvtsd2si
,
2963 X86_64_ONLY(gen_helper_cvtss2sq
),
2964 X86_64_ONLY(gen_helper_cvtsd2sq
),
2967 static void *sse_op_table4
[8][4] = {
2978 static void *sse_op_table5
[256] = {
2979 [0x0c] = gen_helper_pi2fw
,
2980 [0x0d] = gen_helper_pi2fd
,
2981 [0x1c] = gen_helper_pf2iw
,
2982 [0x1d] = gen_helper_pf2id
,
2983 [0x8a] = gen_helper_pfnacc
,
2984 [0x8e] = gen_helper_pfpnacc
,
2985 [0x90] = gen_helper_pfcmpge
,
2986 [0x94] = gen_helper_pfmin
,
2987 [0x96] = gen_helper_pfrcp
,
2988 [0x97] = gen_helper_pfrsqrt
,
2989 [0x9a] = gen_helper_pfsub
,
2990 [0x9e] = gen_helper_pfadd
,
2991 [0xa0] = gen_helper_pfcmpgt
,
2992 [0xa4] = gen_helper_pfmax
,
2993 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2994 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2995 [0xaa] = gen_helper_pfsubr
,
2996 [0xae] = gen_helper_pfacc
,
2997 [0xb0] = gen_helper_pfcmpeq
,
2998 [0xb4] = gen_helper_pfmul
,
2999 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
3000 [0xb7] = gen_helper_pmulhrw_mmx
,
3001 [0xbb] = gen_helper_pswapd
,
3002 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
3005 struct sse_op_helper_s
{
3006 void *op
[2]; uint32_t ext_mask
;
3008 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3009 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3010 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3011 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3012 static struct sse_op_helper_s sse_op_table6
[256] = {
3013 [0x00] = SSSE3_OP(pshufb
),
3014 [0x01] = SSSE3_OP(phaddw
),
3015 [0x02] = SSSE3_OP(phaddd
),
3016 [0x03] = SSSE3_OP(phaddsw
),
3017 [0x04] = SSSE3_OP(pmaddubsw
),
3018 [0x05] = SSSE3_OP(phsubw
),
3019 [0x06] = SSSE3_OP(phsubd
),
3020 [0x07] = SSSE3_OP(phsubsw
),
3021 [0x08] = SSSE3_OP(psignb
),
3022 [0x09] = SSSE3_OP(psignw
),
3023 [0x0a] = SSSE3_OP(psignd
),
3024 [0x0b] = SSSE3_OP(pmulhrsw
),
3025 [0x10] = SSE41_OP(pblendvb
),
3026 [0x14] = SSE41_OP(blendvps
),
3027 [0x15] = SSE41_OP(blendvpd
),
3028 [0x17] = SSE41_OP(ptest
),
3029 [0x1c] = SSSE3_OP(pabsb
),
3030 [0x1d] = SSSE3_OP(pabsw
),
3031 [0x1e] = SSSE3_OP(pabsd
),
3032 [0x20] = SSE41_OP(pmovsxbw
),
3033 [0x21] = SSE41_OP(pmovsxbd
),
3034 [0x22] = SSE41_OP(pmovsxbq
),
3035 [0x23] = SSE41_OP(pmovsxwd
),
3036 [0x24] = SSE41_OP(pmovsxwq
),
3037 [0x25] = SSE41_OP(pmovsxdq
),
3038 [0x28] = SSE41_OP(pmuldq
),
3039 [0x29] = SSE41_OP(pcmpeqq
),
3040 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3041 [0x2b] = SSE41_OP(packusdw
),
3042 [0x30] = SSE41_OP(pmovzxbw
),
3043 [0x31] = SSE41_OP(pmovzxbd
),
3044 [0x32] = SSE41_OP(pmovzxbq
),
3045 [0x33] = SSE41_OP(pmovzxwd
),
3046 [0x34] = SSE41_OP(pmovzxwq
),
3047 [0x35] = SSE41_OP(pmovzxdq
),
3048 [0x37] = SSE42_OP(pcmpgtq
),
3049 [0x38] = SSE41_OP(pminsb
),
3050 [0x39] = SSE41_OP(pminsd
),
3051 [0x3a] = SSE41_OP(pminuw
),
3052 [0x3b] = SSE41_OP(pminud
),
3053 [0x3c] = SSE41_OP(pmaxsb
),
3054 [0x3d] = SSE41_OP(pmaxsd
),
3055 [0x3e] = SSE41_OP(pmaxuw
),
3056 [0x3f] = SSE41_OP(pmaxud
),
3057 [0x40] = SSE41_OP(pmulld
),
3058 [0x41] = SSE41_OP(phminposuw
),
3061 static struct sse_op_helper_s sse_op_table7
[256] = {
3062 [0x08] = SSE41_OP(roundps
),
3063 [0x09] = SSE41_OP(roundpd
),
3064 [0x0a] = SSE41_OP(roundss
),
3065 [0x0b] = SSE41_OP(roundsd
),
3066 [0x0c] = SSE41_OP(blendps
),
3067 [0x0d] = SSE41_OP(blendpd
),
3068 [0x0e] = SSE41_OP(pblendw
),
3069 [0x0f] = SSSE3_OP(palignr
),
3070 [0x14] = SSE41_SPECIAL
, /* pextrb */
3071 [0x15] = SSE41_SPECIAL
, /* pextrw */
3072 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3073 [0x17] = SSE41_SPECIAL
, /* extractps */
3074 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3075 [0x21] = SSE41_SPECIAL
, /* insertps */
3076 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3077 [0x40] = SSE41_OP(dpps
),
3078 [0x41] = SSE41_OP(dppd
),
3079 [0x42] = SSE41_OP(mpsadbw
),
3080 [0x60] = SSE42_OP(pcmpestrm
),
3081 [0x61] = SSE42_OP(pcmpestri
),
3082 [0x62] = SSE42_OP(pcmpistrm
),
3083 [0x63] = SSE42_OP(pcmpistri
),
3086 static void gen_sse(DisasContext
*s
, int b
, target_ulong pc_start
, int rex_r
)
3088 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3089 int modrm
, mod
, rm
, reg
, reg_addr
, offset_addr
;
3093 if (s
->prefix
& PREFIX_DATA
)
3095 else if (s
->prefix
& PREFIX_REPZ
)
3097 else if (s
->prefix
& PREFIX_REPNZ
)
3101 sse_op2
= sse_op_table1
[b
][b1
];
3104 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3114 /* simple MMX/SSE operation */
3115 if (s
->flags
& HF_TS_MASK
) {
3116 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3119 if (s
->flags
& HF_EM_MASK
) {
3121 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3124 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3125 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3128 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3139 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3140 the static cpu state) */
3142 gen_helper_enter_mmx();
3145 modrm
= ldub_code(s
->pc
++);
3146 reg
= ((modrm
>> 3) & 7);
3149 mod
= (modrm
>> 6) & 3;
3150 if (sse_op2
== SSE_SPECIAL
) {
3153 case 0x0e7: /* movntq */
3156 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3157 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3159 case 0x1e7: /* movntdq */
3160 case 0x02b: /* movntps */
3161 case 0x12b: /* movntps */
3162 case 0x3f0: /* lddqu */
3165 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3166 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3168 case 0x6e: /* movd mm, ea */
3169 #ifdef TARGET_X86_64
3170 if (s
->dflag
== 2) {
3171 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3172 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3176 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3177 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3178 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3179 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3180 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3183 case 0x16e: /* movd xmm, ea */
3184 #ifdef TARGET_X86_64
3185 if (s
->dflag
== 2) {
3186 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3187 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3188 offsetof(CPUX86State
,xmm_regs
[reg
]));
3189 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3193 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3194 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3195 offsetof(CPUX86State
,xmm_regs
[reg
]));
3196 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3197 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3200 case 0x6f: /* movq mm, ea */
3202 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3203 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3206 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3207 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3208 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3209 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3212 case 0x010: /* movups */
3213 case 0x110: /* movupd */
3214 case 0x028: /* movaps */
3215 case 0x128: /* movapd */
3216 case 0x16f: /* movdqa xmm, ea */
3217 case 0x26f: /* movdqu xmm, ea */
3219 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3220 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3222 rm
= (modrm
& 7) | REX_B(s
);
3223 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3224 offsetof(CPUX86State
,xmm_regs
[rm
]));
3227 case 0x210: /* movss xmm, ea */
3229 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3230 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3231 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3233 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3234 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3235 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3237 rm
= (modrm
& 7) | REX_B(s
);
3238 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3239 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3242 case 0x310: /* movsd xmm, ea */
3244 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3245 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3247 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3248 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3250 rm
= (modrm
& 7) | REX_B(s
);
3251 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3252 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3255 case 0x012: /* movlps */
3256 case 0x112: /* movlpd */
3258 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3259 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3262 rm
= (modrm
& 7) | REX_B(s
);
3263 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3264 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3267 case 0x212: /* movsldup */
3269 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3270 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3272 rm
= (modrm
& 7) | REX_B(s
);
3273 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3274 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3275 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3276 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3278 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3279 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3280 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3281 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3283 case 0x312: /* movddup */
3285 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3286 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3288 rm
= (modrm
& 7) | REX_B(s
);
3289 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3290 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3292 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3293 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3295 case 0x016: /* movhps */
3296 case 0x116: /* movhpd */
3298 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3299 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3302 rm
= (modrm
& 7) | REX_B(s
);
3303 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3304 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3307 case 0x216: /* movshdup */
3309 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3310 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3312 rm
= (modrm
& 7) | REX_B(s
);
3313 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3314 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3315 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3316 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3318 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3319 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3320 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3321 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3323 case 0x7e: /* movd ea, mm */
3324 #ifdef TARGET_X86_64
3325 if (s
->dflag
== 2) {
3326 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3327 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3328 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3332 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3333 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3334 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3337 case 0x17e: /* movd ea, xmm */
3338 #ifdef TARGET_X86_64
3339 if (s
->dflag
== 2) {
3340 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3341 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3342 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3346 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3347 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3348 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3351 case 0x27e: /* movq xmm, ea */
3353 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3354 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3356 rm
= (modrm
& 7) | REX_B(s
);
3357 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3358 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3360 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3362 case 0x7f: /* movq ea, mm */
3364 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3365 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3368 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3369 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3372 case 0x011: /* movups */
3373 case 0x111: /* movupd */
3374 case 0x029: /* movaps */
3375 case 0x129: /* movapd */
3376 case 0x17f: /* movdqa ea, xmm */
3377 case 0x27f: /* movdqu ea, xmm */
3379 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3380 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3382 rm
= (modrm
& 7) | REX_B(s
);
3383 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3384 offsetof(CPUX86State
,xmm_regs
[reg
]));
3387 case 0x211: /* movss ea, xmm */
3389 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3390 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3391 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3393 rm
= (modrm
& 7) | REX_B(s
);
3394 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3395 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3398 case 0x311: /* movsd ea, xmm */
3400 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3401 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3403 rm
= (modrm
& 7) | REX_B(s
);
3404 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3405 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3408 case 0x013: /* movlps */
3409 case 0x113: /* movlpd */
3411 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3412 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3417 case 0x017: /* movhps */
3418 case 0x117: /* movhpd */
3420 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3421 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3426 case 0x71: /* shift mm, im */
3429 case 0x171: /* shift xmm, im */
3432 val
= ldub_code(s
->pc
++);
3434 gen_op_movl_T0_im(val
);
3435 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3437 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3438 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3440 gen_op_movl_T0_im(val
);
3441 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3443 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3444 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3446 sse_op2
= sse_op_table2
[((b
- 1) & 3) * 8 + (((modrm
>> 3)) & 7)][b1
];
3450 rm
= (modrm
& 7) | REX_B(s
);
3451 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3454 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3456 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3457 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3458 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
3460 case 0x050: /* movmskps */
3461 rm
= (modrm
& 7) | REX_B(s
);
3462 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3463 offsetof(CPUX86State
,xmm_regs
[rm
]));
3464 gen_helper_movmskps(cpu_tmp2_i32
, cpu_ptr0
);
3465 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3466 gen_op_mov_reg_T0(OT_LONG
, reg
);
3468 case 0x150: /* movmskpd */
3469 rm
= (modrm
& 7) | REX_B(s
);
3470 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3471 offsetof(CPUX86State
,xmm_regs
[rm
]));
3472 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_ptr0
);
3473 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3474 gen_op_mov_reg_T0(OT_LONG
, reg
);
3476 case 0x02a: /* cvtpi2ps */
3477 case 0x12a: /* cvtpi2pd */
3478 gen_helper_enter_mmx();
3480 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3481 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3482 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3485 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3487 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3488 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3489 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3492 gen_helper_cvtpi2ps(cpu_ptr0
, cpu_ptr1
);
3496 gen_helper_cvtpi2pd(cpu_ptr0
, cpu_ptr1
);
3500 case 0x22a: /* cvtsi2ss */
3501 case 0x32a: /* cvtsi2sd */
3502 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3503 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
3504 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3505 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3506 sse_op2
= sse_op_table3
[(s
->dflag
== 2) * 2 + ((b
>> 8) - 2)];
3507 if (ot
== OT_LONG
) {
3508 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3509 ((void (*)(TCGv_ptr
, TCGv_i32
))sse_op2
)(cpu_ptr0
, cpu_tmp2_i32
);
3511 ((void (*)(TCGv_ptr
, TCGv
))sse_op2
)(cpu_ptr0
, cpu_T
[0]);
3514 case 0x02c: /* cvttps2pi */
3515 case 0x12c: /* cvttpd2pi */
3516 case 0x02d: /* cvtps2pi */
3517 case 0x12d: /* cvtpd2pi */
3518 gen_helper_enter_mmx();
3520 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3521 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3522 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3524 rm
= (modrm
& 7) | REX_B(s
);
3525 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3527 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3528 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3529 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3532 gen_helper_cvttps2pi(cpu_ptr0
, cpu_ptr1
);
3535 gen_helper_cvttpd2pi(cpu_ptr0
, cpu_ptr1
);
3538 gen_helper_cvtps2pi(cpu_ptr0
, cpu_ptr1
);
3541 gen_helper_cvtpd2pi(cpu_ptr0
, cpu_ptr1
);
3545 case 0x22c: /* cvttss2si */
3546 case 0x32c: /* cvttsd2si */
3547 case 0x22d: /* cvtss2si */
3548 case 0x32d: /* cvtsd2si */
3549 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3551 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3553 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_Q(0)));
3555 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3556 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3558 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3560 rm
= (modrm
& 7) | REX_B(s
);
3561 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3563 sse_op2
= sse_op_table3
[(s
->dflag
== 2) * 2 + ((b
>> 8) - 2) + 4 +
3565 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3566 if (ot
== OT_LONG
) {
3567 ((void (*)(TCGv_i32
, TCGv_ptr
))sse_op2
)(cpu_tmp2_i32
, cpu_ptr0
);
3568 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3570 ((void (*)(TCGv
, TCGv_ptr
))sse_op2
)(cpu_T
[0], cpu_ptr0
);
3572 gen_op_mov_reg_T0(ot
, reg
);
3574 case 0xc4: /* pinsrw */
3577 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3578 val
= ldub_code(s
->pc
++);
3581 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3582 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3585 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3586 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3589 case 0xc5: /* pextrw */
3593 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3594 val
= ldub_code(s
->pc
++);
3597 rm
= (modrm
& 7) | REX_B(s
);
3598 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3599 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3603 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3604 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3606 reg
= ((modrm
>> 3) & 7) | rex_r
;
3607 gen_op_mov_reg_T0(ot
, reg
);
3609 case 0x1d6: /* movq ea, xmm */
3611 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3612 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3614 rm
= (modrm
& 7) | REX_B(s
);
3615 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3616 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3617 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3620 case 0x2d6: /* movq2dq */
3621 gen_helper_enter_mmx();
3623 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3624 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3625 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3627 case 0x3d6: /* movdq2q */
3628 gen_helper_enter_mmx();
3629 rm
= (modrm
& 7) | REX_B(s
);
3630 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3631 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3633 case 0xd7: /* pmovmskb */
3638 rm
= (modrm
& 7) | REX_B(s
);
3639 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3640 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_ptr0
);
3643 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3644 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_ptr0
);
3646 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3647 reg
= ((modrm
>> 3) & 7) | rex_r
;
3648 gen_op_mov_reg_T0(OT_LONG
, reg
);
3651 if (s
->prefix
& PREFIX_REPNZ
)
3655 modrm
= ldub_code(s
->pc
++);
3657 reg
= ((modrm
>> 3) & 7) | rex_r
;
3658 mod
= (modrm
>> 6) & 3;
3660 sse_op2
= sse_op_table6
[b
].op
[b1
];
3663 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3667 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3669 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3671 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3672 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3674 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3675 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3676 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3677 gen_ldq_env_A0(s
->mem_index
, op2_offset
+
3678 offsetof(XMMReg
, XMM_Q(0)));
3680 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3681 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3682 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3683 (s
->mem_index
>> 2) - 1);
3684 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3685 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3686 offsetof(XMMReg
, XMM_L(0)));
3688 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3689 tcg_gen_qemu_ld16u(cpu_tmp0
, cpu_A0
,
3690 (s
->mem_index
>> 2) - 1);
3691 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3692 offsetof(XMMReg
, XMM_W(0)));
3694 case 0x2a: /* movntqda */
3695 gen_ldo_env_A0(s
->mem_index
, op1_offset
);
3698 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3702 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3704 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3706 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3707 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3708 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3711 if (sse_op2
== SSE_SPECIAL
)
3714 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3715 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3716 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
3719 s
->cc_op
= CC_OP_EFLAGS
;
3721 case 0x338: /* crc32 */
3724 modrm
= ldub_code(s
->pc
++);
3725 reg
= ((modrm
>> 3) & 7) | rex_r
;
3727 if (b
!= 0xf0 && b
!= 0xf1)
3729 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
))
3734 else if (b
== 0xf1 && s
->dflag
!= 2)
3735 if (s
->prefix
& PREFIX_DATA
)
3742 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
3743 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3744 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
3745 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3746 cpu_T
[0], tcg_const_i32(8 << ot
));
3748 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3749 gen_op_mov_reg_T0(ot
, reg
);
3754 modrm
= ldub_code(s
->pc
++);
3756 reg
= ((modrm
>> 3) & 7) | rex_r
;
3757 mod
= (modrm
>> 6) & 3;
3759 sse_op2
= sse_op_table7
[b
].op
[b1
];
3762 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
3765 if (sse_op2
== SSE_SPECIAL
) {
3766 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3767 rm
= (modrm
& 7) | REX_B(s
);
3769 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3770 reg
= ((modrm
>> 3) & 7) | rex_r
;
3771 val
= ldub_code(s
->pc
++);
3773 case 0x14: /* pextrb */
3774 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3775 xmm_regs
[reg
].XMM_B(val
& 15)));
3777 gen_op_mov_reg_T0(ot
, rm
);
3779 tcg_gen_qemu_st8(cpu_T
[0], cpu_A0
,
3780 (s
->mem_index
>> 2) - 1);
3782 case 0x15: /* pextrw */
3783 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3784 xmm_regs
[reg
].XMM_W(val
& 7)));
3786 gen_op_mov_reg_T0(ot
, rm
);
3788 tcg_gen_qemu_st16(cpu_T
[0], cpu_A0
,
3789 (s
->mem_index
>> 2) - 1);
3792 if (ot
== OT_LONG
) { /* pextrd */
3793 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
3794 offsetof(CPUX86State
,
3795 xmm_regs
[reg
].XMM_L(val
& 3)));
3796 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3798 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
3800 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
3801 (s
->mem_index
>> 2) - 1);
3802 } else { /* pextrq */
3803 #ifdef TARGET_X86_64
3804 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3805 offsetof(CPUX86State
,
3806 xmm_regs
[reg
].XMM_Q(val
& 1)));
3808 gen_op_mov_reg_v(ot
, rm
, cpu_tmp1_i64
);
3810 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
3811 (s
->mem_index
>> 2) - 1);
3817 case 0x17: /* extractps */
3818 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3819 xmm_regs
[reg
].XMM_L(val
& 3)));
3821 gen_op_mov_reg_T0(ot
, rm
);
3823 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
3824 (s
->mem_index
>> 2) - 1);
3826 case 0x20: /* pinsrb */
3828 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
3830 tcg_gen_qemu_ld8u(cpu_tmp0
, cpu_A0
,
3831 (s
->mem_index
>> 2) - 1);
3832 tcg_gen_st8_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
,
3833 xmm_regs
[reg
].XMM_B(val
& 15)));
3835 case 0x21: /* insertps */
3837 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
3838 offsetof(CPUX86State
,xmm_regs
[rm
]
3839 .XMM_L((val
>> 6) & 3)));
3841 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3842 (s
->mem_index
>> 2) - 1);
3843 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3845 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
3846 offsetof(CPUX86State
,xmm_regs
[reg
]
3847 .XMM_L((val
>> 4) & 3)));
3849 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3850 cpu_env
, offsetof(CPUX86State
,
3851 xmm_regs
[reg
].XMM_L(0)));
3853 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3854 cpu_env
, offsetof(CPUX86State
,
3855 xmm_regs
[reg
].XMM_L(1)));
3857 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3858 cpu_env
, offsetof(CPUX86State
,
3859 xmm_regs
[reg
].XMM_L(2)));
3861 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3862 cpu_env
, offsetof(CPUX86State
,
3863 xmm_regs
[reg
].XMM_L(3)));
3866 if (ot
== OT_LONG
) { /* pinsrd */
3868 gen_op_mov_v_reg(ot
, cpu_tmp0
, rm
);
3870 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3871 (s
->mem_index
>> 2) - 1);
3872 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3873 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
3874 offsetof(CPUX86State
,
3875 xmm_regs
[reg
].XMM_L(val
& 3)));
3876 } else { /* pinsrq */
3877 #ifdef TARGET_X86_64
3879 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
3881 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
3882 (s
->mem_index
>> 2) - 1);
3883 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3884 offsetof(CPUX86State
,
3885 xmm_regs
[reg
].XMM_Q(val
& 1)));
3896 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3898 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3900 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3901 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3902 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3905 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3907 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3909 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3910 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3911 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3914 val
= ldub_code(s
->pc
++);
3916 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
3917 s
->cc_op
= CC_OP_EFLAGS
;
3920 /* The helper must use entire 64-bit gp registers */
3924 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3925 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3926 ((void (*)(TCGv_ptr
, TCGv_ptr
, TCGv_i32
))sse_op2
)(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
3932 /* generic MMX or SSE operation */
3934 case 0x70: /* pshufx insn */
3935 case 0xc6: /* pshufx insn */
3936 case 0xc2: /* compare insns */
3943 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3945 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3946 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3947 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
3949 /* specific case for SSE single instructions */
3952 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3953 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3956 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_D(0)));
3959 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3962 rm
= (modrm
& 7) | REX_B(s
);
3963 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3966 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3968 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3969 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3970 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3973 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3977 case 0x0f: /* 3DNow! data insns */
3978 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3980 val
= ldub_code(s
->pc
++);
3981 sse_op2
= sse_op_table5
[val
];
3984 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3985 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3986 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
3988 case 0x70: /* pshufx insn */
3989 case 0xc6: /* pshufx insn */
3990 val
= ldub_code(s
->pc
++);
3991 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3992 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3993 ((void (*)(TCGv_ptr
, TCGv_ptr
, TCGv_i32
))sse_op2
)(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
3997 val
= ldub_code(s
->pc
++);
4000 sse_op2
= sse_op_table4
[val
][b1
];
4001 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4002 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4003 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
4006 /* maskmov : we must prepare A0 */
4009 #ifdef TARGET_X86_64
4010 if (s
->aflag
== 2) {
4011 gen_op_movq_A0_reg(R_EDI
);
4015 gen_op_movl_A0_reg(R_EDI
);
4017 gen_op_andl_A0_ffff();
4019 gen_add_A0_ds_seg(s
);
4021 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4022 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4023 ((void (*)(TCGv_ptr
, TCGv_ptr
, TCGv
))sse_op2
)(cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4026 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4027 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4028 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
4031 if (b
== 0x2e || b
== 0x2f) {
4032 s
->cc_op
= CC_OP_EFLAGS
;
4037 /* convert one instruction. s->is_jmp is set if the translation must
4038 be stopped. Return the next pc value */
4039 static target_ulong
disas_insn(DisasContext
*s
, target_ulong pc_start
)
4041 int b
, prefixes
, aflag
, dflag
;
4043 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
4044 target_ulong next_eip
, tval
;
4047 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
4048 tcg_gen_debug_insn_start(pc_start
);
4056 #ifdef TARGET_X86_64
4061 s
->rip_offset
= 0; /* for relative ip address */
4063 b
= ldub_code(s
->pc
);
4065 /* check prefixes */
4066 #ifdef TARGET_X86_64
4070 prefixes
|= PREFIX_REPZ
;
4073 prefixes
|= PREFIX_REPNZ
;
4076 prefixes
|= PREFIX_LOCK
;
4097 prefixes
|= PREFIX_DATA
;
4100 prefixes
|= PREFIX_ADR
;
4104 rex_w
= (b
>> 3) & 1;
4105 rex_r
= (b
& 0x4) << 1;
4106 s
->rex_x
= (b
& 0x2) << 2;
4107 REX_B(s
) = (b
& 0x1) << 3;
4108 x86_64_hregs
= 1; /* select uniform byte register addressing */
4112 /* 0x66 is ignored if rex.w is set */
4115 if (prefixes
& PREFIX_DATA
)
4118 if (!(prefixes
& PREFIX_ADR
))
4125 prefixes
|= PREFIX_REPZ
;
4128 prefixes
|= PREFIX_REPNZ
;
4131 prefixes
|= PREFIX_LOCK
;
4152 prefixes
|= PREFIX_DATA
;
4155 prefixes
|= PREFIX_ADR
;
4158 if (prefixes
& PREFIX_DATA
)
4160 if (prefixes
& PREFIX_ADR
)
4164 s
->prefix
= prefixes
;
4168 /* lock generation */
4169 if (prefixes
& PREFIX_LOCK
)
4172 /* now check op code */
4176 /**************************/
4177 /* extended op code */
4178 b
= ldub_code(s
->pc
++) | 0x100;
4181 /**************************/
4199 ot
= dflag
+ OT_WORD
;
4202 case 0: /* OP Ev, Gv */
4203 modrm
= ldub_code(s
->pc
++);
4204 reg
= ((modrm
>> 3) & 7) | rex_r
;
4205 mod
= (modrm
>> 6) & 3;
4206 rm
= (modrm
& 7) | REX_B(s
);
4208 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4210 } else if (op
== OP_XORL
&& rm
== reg
) {
4212 /* xor reg, reg optimisation */
4214 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4215 gen_op_mov_reg_T0(ot
, reg
);
4216 gen_op_update1_cc();
4221 gen_op_mov_TN_reg(ot
, 1, reg
);
4222 gen_op(s
, op
, ot
, opreg
);
4224 case 1: /* OP Gv, Ev */
4225 modrm
= ldub_code(s
->pc
++);
4226 mod
= (modrm
>> 6) & 3;
4227 reg
= ((modrm
>> 3) & 7) | rex_r
;
4228 rm
= (modrm
& 7) | REX_B(s
);
4230 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4231 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4232 } else if (op
== OP_XORL
&& rm
== reg
) {
4235 gen_op_mov_TN_reg(ot
, 1, rm
);
4237 gen_op(s
, op
, ot
, reg
);
4239 case 2: /* OP A, Iv */
4240 val
= insn_get(s
, ot
);
4241 gen_op_movl_T1_im(val
);
4242 gen_op(s
, op
, ot
, OR_EAX
);
4251 case 0x80: /* GRP1 */
4260 ot
= dflag
+ OT_WORD
;
4262 modrm
= ldub_code(s
->pc
++);
4263 mod
= (modrm
>> 6) & 3;
4264 rm
= (modrm
& 7) | REX_B(s
);
4265 op
= (modrm
>> 3) & 7;
4271 s
->rip_offset
= insn_const_size(ot
);
4272 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4283 val
= insn_get(s
, ot
);
4286 val
= (int8_t)insn_get(s
, OT_BYTE
);
4289 gen_op_movl_T1_im(val
);
4290 gen_op(s
, op
, ot
, opreg
);
4294 /**************************/
4295 /* inc, dec, and other misc arith */
4296 case 0x40 ... 0x47: /* inc Gv */
4297 ot
= dflag
? OT_LONG
: OT_WORD
;
4298 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4300 case 0x48 ... 0x4f: /* dec Gv */
4301 ot
= dflag
? OT_LONG
: OT_WORD
;
4302 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4304 case 0xf6: /* GRP3 */
4309 ot
= dflag
+ OT_WORD
;
4311 modrm
= ldub_code(s
->pc
++);
4312 mod
= (modrm
>> 6) & 3;
4313 rm
= (modrm
& 7) | REX_B(s
);
4314 op
= (modrm
>> 3) & 7;
4317 s
->rip_offset
= insn_const_size(ot
);
4318 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4319 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4321 gen_op_mov_TN_reg(ot
, 0, rm
);
4326 val
= insn_get(s
, ot
);
4327 gen_op_movl_T1_im(val
);
4328 gen_op_testl_T0_T1_cc();
4329 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4332 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4334 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4336 gen_op_mov_reg_T0(ot
, rm
);
4340 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4342 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4344 gen_op_mov_reg_T0(ot
, rm
);
4346 gen_op_update_neg_cc();
4347 s
->cc_op
= CC_OP_SUBB
+ ot
;
4352 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4353 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4354 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4355 /* XXX: use 32 bit mul which could be faster */
4356 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4357 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4358 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4359 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4360 s
->cc_op
= CC_OP_MULB
;
4363 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4364 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4365 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4366 /* XXX: use 32 bit mul which could be faster */
4367 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4368 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4369 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4370 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4371 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4372 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4373 s
->cc_op
= CC_OP_MULW
;
4377 #ifdef TARGET_X86_64
4378 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4379 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4380 tcg_gen_ext32u_tl(cpu_T
[1], cpu_T
[1]);
4381 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4382 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4383 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4384 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4385 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4386 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4390 t0
= tcg_temp_new_i64();
4391 t1
= tcg_temp_new_i64();
4392 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4393 tcg_gen_extu_i32_i64(t0
, cpu_T
[0]);
4394 tcg_gen_extu_i32_i64(t1
, cpu_T
[1]);
4395 tcg_gen_mul_i64(t0
, t0
, t1
);
4396 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4397 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4398 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4399 tcg_gen_shri_i64(t0
, t0
, 32);
4400 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4401 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4402 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4405 s
->cc_op
= CC_OP_MULL
;
4407 #ifdef TARGET_X86_64
4409 gen_helper_mulq_EAX_T0(cpu_T
[0]);
4410 s
->cc_op
= CC_OP_MULQ
;
4418 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4419 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4420 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4421 /* XXX: use 32 bit mul which could be faster */
4422 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4423 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4424 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4425 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4426 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4427 s
->cc_op
= CC_OP_MULB
;
4430 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4431 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4432 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4433 /* XXX: use 32 bit mul which could be faster */
4434 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4435 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4436 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4437 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4438 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4439 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4440 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4441 s
->cc_op
= CC_OP_MULW
;
4445 #ifdef TARGET_X86_64
4446 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4447 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4448 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4449 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4450 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4451 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4452 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4453 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4454 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4455 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4459 t0
= tcg_temp_new_i64();
4460 t1
= tcg_temp_new_i64();
4461 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4462 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4463 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4464 tcg_gen_mul_i64(t0
, t0
, t1
);
4465 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4466 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4467 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4468 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4469 tcg_gen_shri_i64(t0
, t0
, 32);
4470 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4471 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4472 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4475 s
->cc_op
= CC_OP_MULL
;
4477 #ifdef TARGET_X86_64
4479 gen_helper_imulq_EAX_T0(cpu_T
[0]);
4480 s
->cc_op
= CC_OP_MULQ
;
4488 gen_jmp_im(pc_start
- s
->cs_base
);
4489 gen_helper_divb_AL(cpu_T
[0]);
4492 gen_jmp_im(pc_start
- s
->cs_base
);
4493 gen_helper_divw_AX(cpu_T
[0]);
4497 gen_jmp_im(pc_start
- s
->cs_base
);
4498 gen_helper_divl_EAX(cpu_T
[0]);
4500 #ifdef TARGET_X86_64
4502 gen_jmp_im(pc_start
- s
->cs_base
);
4503 gen_helper_divq_EAX(cpu_T
[0]);
4511 gen_jmp_im(pc_start
- s
->cs_base
);
4512 gen_helper_idivb_AL(cpu_T
[0]);
4515 gen_jmp_im(pc_start
- s
->cs_base
);
4516 gen_helper_idivw_AX(cpu_T
[0]);
4520 gen_jmp_im(pc_start
- s
->cs_base
);
4521 gen_helper_idivl_EAX(cpu_T
[0]);
4523 #ifdef TARGET_X86_64
4525 gen_jmp_im(pc_start
- s
->cs_base
);
4526 gen_helper_idivq_EAX(cpu_T
[0]);
4536 case 0xfe: /* GRP4 */
4537 case 0xff: /* GRP5 */
4541 ot
= dflag
+ OT_WORD
;
4543 modrm
= ldub_code(s
->pc
++);
4544 mod
= (modrm
>> 6) & 3;
4545 rm
= (modrm
& 7) | REX_B(s
);
4546 op
= (modrm
>> 3) & 7;
4547 if (op
>= 2 && b
== 0xfe) {
4551 if (op
== 2 || op
== 4) {
4552 /* operand size for jumps is 64 bit */
4554 } else if (op
== 3 || op
== 5) {
4555 /* for call calls, the operand is 16 or 32 bit, even
4557 ot
= dflag
? OT_LONG
: OT_WORD
;
4558 } else if (op
== 6) {
4559 /* default push size is 64 bit */
4560 ot
= dflag
? OT_QUAD
: OT_WORD
;
4564 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4565 if (op
>= 2 && op
!= 3 && op
!= 5)
4566 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4568 gen_op_mov_TN_reg(ot
, 0, rm
);
4572 case 0: /* inc Ev */
4577 gen_inc(s
, ot
, opreg
, 1);
4579 case 1: /* dec Ev */
4584 gen_inc(s
, ot
, opreg
, -1);
4586 case 2: /* call Ev */
4587 /* XXX: optimize if memory (no 'and' is necessary) */
4589 gen_op_andl_T0_ffff();
4590 next_eip
= s
->pc
- s
->cs_base
;
4591 gen_movtl_T1_im(next_eip
);
4596 case 3: /* lcall Ev */
4597 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4598 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4599 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4601 if (s
->pe
&& !s
->vm86
) {
4602 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4603 gen_op_set_cc_op(s
->cc_op
);
4604 gen_jmp_im(pc_start
- s
->cs_base
);
4605 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4606 gen_helper_lcall_protected(cpu_tmp2_i32
, cpu_T
[1],
4607 tcg_const_i32(dflag
),
4608 tcg_const_i32(s
->pc
- pc_start
));
4610 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4611 gen_helper_lcall_real(cpu_tmp2_i32
, cpu_T
[1],
4612 tcg_const_i32(dflag
),
4613 tcg_const_i32(s
->pc
- s
->cs_base
));
4617 case 4: /* jmp Ev */
4619 gen_op_andl_T0_ffff();
4623 case 5: /* ljmp Ev */
4624 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4625 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4626 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4628 if (s
->pe
&& !s
->vm86
) {
4629 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4630 gen_op_set_cc_op(s
->cc_op
);
4631 gen_jmp_im(pc_start
- s
->cs_base
);
4632 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4633 gen_helper_ljmp_protected(cpu_tmp2_i32
, cpu_T
[1],
4634 tcg_const_i32(s
->pc
- pc_start
));
4636 gen_op_movl_seg_T0_vm(R_CS
);
4637 gen_op_movl_T0_T1();
4642 case 6: /* push Ev */
4650 case 0x84: /* test Ev, Gv */
4655 ot
= dflag
+ OT_WORD
;
4657 modrm
= ldub_code(s
->pc
++);
4658 mod
= (modrm
>> 6) & 3;
4659 rm
= (modrm
& 7) | REX_B(s
);
4660 reg
= ((modrm
>> 3) & 7) | rex_r
;
4662 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4663 gen_op_mov_TN_reg(ot
, 1, reg
);
4664 gen_op_testl_T0_T1_cc();
4665 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4668 case 0xa8: /* test eAX, Iv */
4673 ot
= dflag
+ OT_WORD
;
4674 val
= insn_get(s
, ot
);
4676 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
4677 gen_op_movl_T1_im(val
);
4678 gen_op_testl_T0_T1_cc();
4679 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4682 case 0x98: /* CWDE/CBW */
4683 #ifdef TARGET_X86_64
4685 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4686 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4687 gen_op_mov_reg_T0(OT_QUAD
, R_EAX
);
4691 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4692 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4693 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4695 gen_op_mov_TN_reg(OT_BYTE
, 0, R_EAX
);
4696 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4697 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4700 case 0x99: /* CDQ/CWD */
4701 #ifdef TARGET_X86_64
4703 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4704 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
4705 gen_op_mov_reg_T0(OT_QUAD
, R_EDX
);
4709 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4710 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4711 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
4712 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4714 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4715 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4716 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
4717 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4720 case 0x1af: /* imul Gv, Ev */
4721 case 0x69: /* imul Gv, Ev, I */
4723 ot
= dflag
+ OT_WORD
;
4724 modrm
= ldub_code(s
->pc
++);
4725 reg
= ((modrm
>> 3) & 7) | rex_r
;
4727 s
->rip_offset
= insn_const_size(ot
);
4730 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4732 val
= insn_get(s
, ot
);
4733 gen_op_movl_T1_im(val
);
4734 } else if (b
== 0x6b) {
4735 val
= (int8_t)insn_get(s
, OT_BYTE
);
4736 gen_op_movl_T1_im(val
);
4738 gen_op_mov_TN_reg(ot
, 1, reg
);
4741 #ifdef TARGET_X86_64
4742 if (ot
== OT_QUAD
) {
4743 gen_helper_imulq_T0_T1(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4746 if (ot
== OT_LONG
) {
4747 #ifdef TARGET_X86_64
4748 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4749 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4750 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4751 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4752 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4753 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4757 t0
= tcg_temp_new_i64();
4758 t1
= tcg_temp_new_i64();
4759 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4760 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4761 tcg_gen_mul_i64(t0
, t0
, t1
);
4762 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4763 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4764 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4765 tcg_gen_shri_i64(t0
, t0
, 32);
4766 tcg_gen_trunc_i64_i32(cpu_T
[1], t0
);
4767 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[1], cpu_tmp0
);
4771 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4772 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4773 /* XXX: use 32 bit mul which could be faster */
4774 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4775 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4776 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4777 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4779 gen_op_mov_reg_T0(ot
, reg
);
4780 s
->cc_op
= CC_OP_MULB
+ ot
;
4783 case 0x1c1: /* xadd Ev, Gv */
4787 ot
= dflag
+ OT_WORD
;
4788 modrm
= ldub_code(s
->pc
++);
4789 reg
= ((modrm
>> 3) & 7) | rex_r
;
4790 mod
= (modrm
>> 6) & 3;
4792 rm
= (modrm
& 7) | REX_B(s
);
4793 gen_op_mov_TN_reg(ot
, 0, reg
);
4794 gen_op_mov_TN_reg(ot
, 1, rm
);
4795 gen_op_addl_T0_T1();
4796 gen_op_mov_reg_T1(ot
, reg
);
4797 gen_op_mov_reg_T0(ot
, rm
);
4799 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4800 gen_op_mov_TN_reg(ot
, 0, reg
);
4801 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4802 gen_op_addl_T0_T1();
4803 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4804 gen_op_mov_reg_T1(ot
, reg
);
4806 gen_op_update2_cc();
4807 s
->cc_op
= CC_OP_ADDB
+ ot
;
4810 case 0x1b1: /* cmpxchg Ev, Gv */
4813 TCGv t0
, t1
, t2
, a0
;
4818 ot
= dflag
+ OT_WORD
;
4819 modrm
= ldub_code(s
->pc
++);
4820 reg
= ((modrm
>> 3) & 7) | rex_r
;
4821 mod
= (modrm
>> 6) & 3;
4822 t0
= tcg_temp_local_new();
4823 t1
= tcg_temp_local_new();
4824 t2
= tcg_temp_local_new();
4825 a0
= tcg_temp_local_new();
4826 gen_op_mov_v_reg(ot
, t1
, reg
);
4828 rm
= (modrm
& 7) | REX_B(s
);
4829 gen_op_mov_v_reg(ot
, t0
, rm
);
4831 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4832 tcg_gen_mov_tl(a0
, cpu_A0
);
4833 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
4834 rm
= 0; /* avoid warning */
4836 label1
= gen_new_label();
4837 tcg_gen_ld_tl(t2
, cpu_env
, offsetof(CPUState
, regs
[R_EAX
]));
4838 tcg_gen_sub_tl(t2
, t2
, t0
);
4840 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
4842 label2
= gen_new_label();
4843 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
4845 gen_set_label(label1
);
4846 gen_op_mov_reg_v(ot
, rm
, t1
);
4847 gen_set_label(label2
);
4849 tcg_gen_mov_tl(t1
, t0
);
4850 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
4851 gen_set_label(label1
);
4853 gen_op_st_v(ot
+ s
->mem_index
, t1
, a0
);
4855 tcg_gen_mov_tl(cpu_cc_src
, t0
);
4856 tcg_gen_mov_tl(cpu_cc_dst
, t2
);
4857 s
->cc_op
= CC_OP_SUBB
+ ot
;
4864 case 0x1c7: /* cmpxchg8b */
4865 modrm
= ldub_code(s
->pc
++);
4866 mod
= (modrm
>> 6) & 3;
4867 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
4869 #ifdef TARGET_X86_64
4871 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
4873 gen_jmp_im(pc_start
- s
->cs_base
);
4874 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4875 gen_op_set_cc_op(s
->cc_op
);
4876 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4877 gen_helper_cmpxchg16b(cpu_A0
);
4881 if (!(s
->cpuid_features
& CPUID_CX8
))
4883 gen_jmp_im(pc_start
- s
->cs_base
);
4884 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4885 gen_op_set_cc_op(s
->cc_op
);
4886 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4887 gen_helper_cmpxchg8b(cpu_A0
);
4889 s
->cc_op
= CC_OP_EFLAGS
;
4892 /**************************/
4894 case 0x50 ... 0x57: /* push */
4895 gen_op_mov_TN_reg(OT_LONG
, 0, (b
& 7) | REX_B(s
));
4898 case 0x58 ... 0x5f: /* pop */
4900 ot
= dflag
? OT_QUAD
: OT_WORD
;
4902 ot
= dflag
+ OT_WORD
;
4905 /* NOTE: order is important for pop %sp */
4907 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
4909 case 0x60: /* pusha */
4914 case 0x61: /* popa */
4919 case 0x68: /* push Iv */
4922 ot
= dflag
? OT_QUAD
: OT_WORD
;
4924 ot
= dflag
+ OT_WORD
;
4927 val
= insn_get(s
, ot
);
4929 val
= (int8_t)insn_get(s
, OT_BYTE
);
4930 gen_op_movl_T0_im(val
);
4933 case 0x8f: /* pop Ev */
4935 ot
= dflag
? OT_QUAD
: OT_WORD
;
4937 ot
= dflag
+ OT_WORD
;
4939 modrm
= ldub_code(s
->pc
++);
4940 mod
= (modrm
>> 6) & 3;
4943 /* NOTE: order is important for pop %sp */
4945 rm
= (modrm
& 7) | REX_B(s
);
4946 gen_op_mov_reg_T0(ot
, rm
);
4948 /* NOTE: order is important too for MMU exceptions */
4949 s
->popl_esp_hack
= 1 << ot
;
4950 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
4951 s
->popl_esp_hack
= 0;
4955 case 0xc8: /* enter */
4958 val
= lduw_code(s
->pc
);
4960 level
= ldub_code(s
->pc
++);
4961 gen_enter(s
, val
, level
);
4964 case 0xc9: /* leave */
4965 /* XXX: exception not precise (ESP is updated before potential exception) */
4967 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EBP
);
4968 gen_op_mov_reg_T0(OT_QUAD
, R_ESP
);
4969 } else if (s
->ss32
) {
4970 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
4971 gen_op_mov_reg_T0(OT_LONG
, R_ESP
);
4973 gen_op_mov_TN_reg(OT_WORD
, 0, R_EBP
);
4974 gen_op_mov_reg_T0(OT_WORD
, R_ESP
);
4978 ot
= dflag
? OT_QUAD
: OT_WORD
;
4980 ot
= dflag
+ OT_WORD
;
4982 gen_op_mov_reg_T0(ot
, R_EBP
);
4985 case 0x06: /* push es */
4986 case 0x0e: /* push cs */
4987 case 0x16: /* push ss */
4988 case 0x1e: /* push ds */
4991 gen_op_movl_T0_seg(b
>> 3);
4994 case 0x1a0: /* push fs */
4995 case 0x1a8: /* push gs */
4996 gen_op_movl_T0_seg((b
>> 3) & 7);
4999 case 0x07: /* pop es */
5000 case 0x17: /* pop ss */
5001 case 0x1f: /* pop ds */
5006 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5009 /* if reg == SS, inhibit interrupts/trace. */
5010 /* If several instructions disable interrupts, only the
5012 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5013 gen_helper_set_inhibit_irq();
5017 gen_jmp_im(s
->pc
- s
->cs_base
);
5021 case 0x1a1: /* pop fs */
5022 case 0x1a9: /* pop gs */
5024 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5027 gen_jmp_im(s
->pc
- s
->cs_base
);
5032 /**************************/
5035 case 0x89: /* mov Gv, Ev */
5039 ot
= dflag
+ OT_WORD
;
5040 modrm
= ldub_code(s
->pc
++);
5041 reg
= ((modrm
>> 3) & 7) | rex_r
;
5043 /* generate a generic store */
5044 gen_ldst_modrm(s
, modrm
, ot
, reg
, 1);
5047 case 0xc7: /* mov Ev, Iv */
5051 ot
= dflag
+ OT_WORD
;
5052 modrm
= ldub_code(s
->pc
++);
5053 mod
= (modrm
>> 6) & 3;
5055 s
->rip_offset
= insn_const_size(ot
);
5056 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5058 val
= insn_get(s
, ot
);
5059 gen_op_movl_T0_im(val
);
5061 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5063 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5066 case 0x8b: /* mov Ev, Gv */
5070 ot
= OT_WORD
+ dflag
;
5071 modrm
= ldub_code(s
->pc
++);
5072 reg
= ((modrm
>> 3) & 7) | rex_r
;
5074 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
5075 gen_op_mov_reg_T0(ot
, reg
);
5077 case 0x8e: /* mov seg, Gv */
5078 modrm
= ldub_code(s
->pc
++);
5079 reg
= (modrm
>> 3) & 7;
5080 if (reg
>= 6 || reg
== R_CS
)
5082 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
5083 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5085 /* if reg == SS, inhibit interrupts/trace */
5086 /* If several instructions disable interrupts, only the
5088 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5089 gen_helper_set_inhibit_irq();
5093 gen_jmp_im(s
->pc
- s
->cs_base
);
5097 case 0x8c: /* mov Gv, seg */
5098 modrm
= ldub_code(s
->pc
++);
5099 reg
= (modrm
>> 3) & 7;
5100 mod
= (modrm
>> 6) & 3;
5103 gen_op_movl_T0_seg(reg
);
5105 ot
= OT_WORD
+ dflag
;
5108 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
5111 case 0x1b6: /* movzbS Gv, Eb */
5112 case 0x1b7: /* movzwS Gv, Eb */
5113 case 0x1be: /* movsbS Gv, Eb */
5114 case 0x1bf: /* movswS Gv, Eb */
5117 /* d_ot is the size of destination */
5118 d_ot
= dflag
+ OT_WORD
;
5119 /* ot is the size of source */
5120 ot
= (b
& 1) + OT_BYTE
;
5121 modrm
= ldub_code(s
->pc
++);
5122 reg
= ((modrm
>> 3) & 7) | rex_r
;
5123 mod
= (modrm
>> 6) & 3;
5124 rm
= (modrm
& 7) | REX_B(s
);
5127 gen_op_mov_TN_reg(ot
, 0, rm
);
5128 switch(ot
| (b
& 8)) {
5130 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5133 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5136 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5140 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5143 gen_op_mov_reg_T0(d_ot
, reg
);
5145 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5147 gen_op_lds_T0_A0(ot
+ s
->mem_index
);
5149 gen_op_ldu_T0_A0(ot
+ s
->mem_index
);
5151 gen_op_mov_reg_T0(d_ot
, reg
);
5156 case 0x8d: /* lea */
5157 ot
= dflag
+ OT_WORD
;
5158 modrm
= ldub_code(s
->pc
++);
5159 mod
= (modrm
>> 6) & 3;
5162 reg
= ((modrm
>> 3) & 7) | rex_r
;
5163 /* we must ensure that no segment is added */
5167 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5169 gen_op_mov_reg_A0(ot
- OT_WORD
, reg
);
5172 case 0xa0: /* mov EAX, Ov */
5174 case 0xa2: /* mov Ov, EAX */
5177 target_ulong offset_addr
;
5182 ot
= dflag
+ OT_WORD
;
5183 #ifdef TARGET_X86_64
5184 if (s
->aflag
== 2) {
5185 offset_addr
= ldq_code(s
->pc
);
5187 gen_op_movq_A0_im(offset_addr
);
5192 offset_addr
= insn_get(s
, OT_LONG
);
5194 offset_addr
= insn_get(s
, OT_WORD
);
5196 gen_op_movl_A0_im(offset_addr
);
5198 gen_add_A0_ds_seg(s
);
5200 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
5201 gen_op_mov_reg_T0(ot
, R_EAX
);
5203 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5204 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5208 case 0xd7: /* xlat */
5209 #ifdef TARGET_X86_64
5210 if (s
->aflag
== 2) {
5211 gen_op_movq_A0_reg(R_EBX
);
5212 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
5213 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5214 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5218 gen_op_movl_A0_reg(R_EBX
);
5219 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
5220 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5221 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5223 gen_op_andl_A0_ffff();
5225 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5227 gen_add_A0_ds_seg(s
);
5228 gen_op_ldu_T0_A0(OT_BYTE
+ s
->mem_index
);
5229 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
5231 case 0xb0 ... 0xb7: /* mov R, Ib */
5232 val
= insn_get(s
, OT_BYTE
);
5233 gen_op_movl_T0_im(val
);
5234 gen_op_mov_reg_T0(OT_BYTE
, (b
& 7) | REX_B(s
));
5236 case 0xb8 ... 0xbf: /* mov R, Iv */
5237 #ifdef TARGET_X86_64
5241 tmp
= ldq_code(s
->pc
);
5243 reg
= (b
& 7) | REX_B(s
);
5244 gen_movtl_T0_im(tmp
);
5245 gen_op_mov_reg_T0(OT_QUAD
, reg
);
5249 ot
= dflag
? OT_LONG
: OT_WORD
;
5250 val
= insn_get(s
, ot
);
5251 reg
= (b
& 7) | REX_B(s
);
5252 gen_op_movl_T0_im(val
);
5253 gen_op_mov_reg_T0(ot
, reg
);
5257 case 0x91 ... 0x97: /* xchg R, EAX */
5258 ot
= dflag
+ OT_WORD
;
5259 reg
= (b
& 7) | REX_B(s
);
5263 case 0x87: /* xchg Ev, Gv */
5267 ot
= dflag
+ OT_WORD
;
5268 modrm
= ldub_code(s
->pc
++);
5269 reg
= ((modrm
>> 3) & 7) | rex_r
;
5270 mod
= (modrm
>> 6) & 3;
5272 rm
= (modrm
& 7) | REX_B(s
);
5274 gen_op_mov_TN_reg(ot
, 0, reg
);
5275 gen_op_mov_TN_reg(ot
, 1, rm
);
5276 gen_op_mov_reg_T0(ot
, rm
);
5277 gen_op_mov_reg_T1(ot
, reg
);
5279 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5280 gen_op_mov_TN_reg(ot
, 0, reg
);
5281 /* for xchg, lock is implicit */
5282 if (!(prefixes
& PREFIX_LOCK
))
5284 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5285 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5286 if (!(prefixes
& PREFIX_LOCK
))
5287 gen_helper_unlock();
5288 gen_op_mov_reg_T1(ot
, reg
);
5291 case 0xc4: /* les Gv */
5296 case 0xc5: /* lds Gv */
5301 case 0x1b2: /* lss Gv */
5304 case 0x1b4: /* lfs Gv */
5307 case 0x1b5: /* lgs Gv */
5310 ot
= dflag
? OT_LONG
: OT_WORD
;
5311 modrm
= ldub_code(s
->pc
++);
5312 reg
= ((modrm
>> 3) & 7) | rex_r
;
5313 mod
= (modrm
>> 6) & 3;
5316 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5317 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5318 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
5319 /* load the segment first to handle exceptions properly */
5320 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
5321 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5322 /* then put the data */
5323 gen_op_mov_reg_T1(ot
, reg
);
5325 gen_jmp_im(s
->pc
- s
->cs_base
);
5330 /************************/
5341 ot
= dflag
+ OT_WORD
;
5343 modrm
= ldub_code(s
->pc
++);
5344 mod
= (modrm
>> 6) & 3;
5345 op
= (modrm
>> 3) & 7;
5351 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5354 opreg
= (modrm
& 7) | REX_B(s
);
5359 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5362 shift
= ldub_code(s
->pc
++);
5364 gen_shifti(s
, op
, ot
, opreg
, shift
);
5379 case 0x1a4: /* shld imm */
5383 case 0x1a5: /* shld cl */
5387 case 0x1ac: /* shrd imm */
5391 case 0x1ad: /* shrd cl */
5395 ot
= dflag
+ OT_WORD
;
5396 modrm
= ldub_code(s
->pc
++);
5397 mod
= (modrm
>> 6) & 3;
5398 rm
= (modrm
& 7) | REX_B(s
);
5399 reg
= ((modrm
>> 3) & 7) | rex_r
;
5401 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5406 gen_op_mov_TN_reg(ot
, 1, reg
);
5409 val
= ldub_code(s
->pc
++);
5410 tcg_gen_movi_tl(cpu_T3
, val
);
5412 tcg_gen_ld_tl(cpu_T3
, cpu_env
, offsetof(CPUState
, regs
[R_ECX
]));
5414 gen_shiftd_rm_T1_T3(s
, ot
, opreg
, op
);
5417 /************************/
5420 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5421 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5422 /* XXX: what to do if illegal op ? */
5423 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5426 modrm
= ldub_code(s
->pc
++);
5427 mod
= (modrm
>> 6) & 3;
5429 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5432 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5434 case 0x00 ... 0x07: /* fxxxs */
5435 case 0x10 ... 0x17: /* fixxxl */
5436 case 0x20 ... 0x27: /* fxxxl */
5437 case 0x30 ... 0x37: /* fixxx */
5444 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5445 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5446 gen_helper_flds_FT0(cpu_tmp2_i32
);
5449 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5450 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5451 gen_helper_fildl_FT0(cpu_tmp2_i32
);
5454 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5455 (s
->mem_index
>> 2) - 1);
5456 gen_helper_fldl_FT0(cpu_tmp1_i64
);
5460 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5461 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5462 gen_helper_fildl_FT0(cpu_tmp2_i32
);
5466 gen_helper_fp_arith_ST0_FT0(op1
);
5468 /* fcomp needs pop */
5473 case 0x08: /* flds */
5474 case 0x0a: /* fsts */
5475 case 0x0b: /* fstps */
5476 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5477 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5478 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5483 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5484 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5485 gen_helper_flds_ST0(cpu_tmp2_i32
);
5488 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5489 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5490 gen_helper_fildl_ST0(cpu_tmp2_i32
);
5493 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5494 (s
->mem_index
>> 2) - 1);
5495 gen_helper_fldl_ST0(cpu_tmp1_i64
);
5499 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5500 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5501 gen_helper_fildl_ST0(cpu_tmp2_i32
);
5506 /* XXX: the corresponding CPUID bit must be tested ! */
5509 gen_helper_fisttl_ST0(cpu_tmp2_i32
);
5510 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5511 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5514 gen_helper_fisttll_ST0(cpu_tmp1_i64
);
5515 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5516 (s
->mem_index
>> 2) - 1);
5520 gen_helper_fistt_ST0(cpu_tmp2_i32
);
5521 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5522 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5530 gen_helper_fsts_ST0(cpu_tmp2_i32
);
5531 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5532 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5535 gen_helper_fistl_ST0(cpu_tmp2_i32
);
5536 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5537 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5540 gen_helper_fstl_ST0(cpu_tmp1_i64
);
5541 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5542 (s
->mem_index
>> 2) - 1);
5546 gen_helper_fist_ST0(cpu_tmp2_i32
);
5547 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5548 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5556 case 0x0c: /* fldenv mem */
5557 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5558 gen_op_set_cc_op(s
->cc_op
);
5559 gen_jmp_im(pc_start
- s
->cs_base
);
5561 cpu_A0
, tcg_const_i32(s
->dflag
));
5563 case 0x0d: /* fldcw mem */
5564 gen_op_ld_T0_A0(OT_WORD
+ s
->mem_index
);
5565 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5566 gen_helper_fldcw(cpu_tmp2_i32
);
5568 case 0x0e: /* fnstenv mem */
5569 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5570 gen_op_set_cc_op(s
->cc_op
);
5571 gen_jmp_im(pc_start
- s
->cs_base
);
5572 gen_helper_fstenv(cpu_A0
, tcg_const_i32(s
->dflag
));
5574 case 0x0f: /* fnstcw mem */
5575 gen_helper_fnstcw(cpu_tmp2_i32
);
5576 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5577 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5579 case 0x1d: /* fldt mem */
5580 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5581 gen_op_set_cc_op(s
->cc_op
);
5582 gen_jmp_im(pc_start
- s
->cs_base
);
5583 gen_helper_fldt_ST0(cpu_A0
);
5585 case 0x1f: /* fstpt mem */
5586 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5587 gen_op_set_cc_op(s
->cc_op
);
5588 gen_jmp_im(pc_start
- s
->cs_base
);
5589 gen_helper_fstt_ST0(cpu_A0
);
5592 case 0x2c: /* frstor mem */
5593 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5594 gen_op_set_cc_op(s
->cc_op
);
5595 gen_jmp_im(pc_start
- s
->cs_base
);
5596 gen_helper_frstor(cpu_A0
, tcg_const_i32(s
->dflag
));
5598 case 0x2e: /* fnsave mem */
5599 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5600 gen_op_set_cc_op(s
->cc_op
);
5601 gen_jmp_im(pc_start
- s
->cs_base
);
5602 gen_helper_fsave(cpu_A0
, tcg_const_i32(s
->dflag
));
5604 case 0x2f: /* fnstsw mem */
5605 gen_helper_fnstsw(cpu_tmp2_i32
);
5606 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5607 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5609 case 0x3c: /* fbld */
5610 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5611 gen_op_set_cc_op(s
->cc_op
);
5612 gen_jmp_im(pc_start
- s
->cs_base
);
5613 gen_helper_fbld_ST0(cpu_A0
);
5615 case 0x3e: /* fbstp */
5616 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5617 gen_op_set_cc_op(s
->cc_op
);
5618 gen_jmp_im(pc_start
- s
->cs_base
);
5619 gen_helper_fbst_ST0(cpu_A0
);
5622 case 0x3d: /* fildll */
5623 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5624 (s
->mem_index
>> 2) - 1);
5625 gen_helper_fildll_ST0(cpu_tmp1_i64
);
5627 case 0x3f: /* fistpll */
5628 gen_helper_fistll_ST0(cpu_tmp1_i64
);
5629 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5630 (s
->mem_index
>> 2) - 1);
5637 /* register float ops */
5641 case 0x08: /* fld sti */
5643 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg
+ 1) & 7));
5645 case 0x09: /* fxchg sti */
5646 case 0x29: /* fxchg4 sti, undocumented op */
5647 case 0x39: /* fxchg7 sti, undocumented op */
5648 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg
));
5650 case 0x0a: /* grp d9/2 */
5653 /* check exceptions (FreeBSD FPU probe) */
5654 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5655 gen_op_set_cc_op(s
->cc_op
);
5656 gen_jmp_im(pc_start
- s
->cs_base
);
5663 case 0x0c: /* grp d9/4 */
5666 gen_helper_fchs_ST0();
5669 gen_helper_fabs_ST0();
5672 gen_helper_fldz_FT0();
5673 gen_helper_fcom_ST0_FT0();
5676 gen_helper_fxam_ST0();
5682 case 0x0d: /* grp d9/5 */
5687 gen_helper_fld1_ST0();
5691 gen_helper_fldl2t_ST0();
5695 gen_helper_fldl2e_ST0();
5699 gen_helper_fldpi_ST0();
5703 gen_helper_fldlg2_ST0();
5707 gen_helper_fldln2_ST0();
5711 gen_helper_fldz_ST0();
5718 case 0x0e: /* grp d9/6 */
5729 case 3: /* fpatan */
5730 gen_helper_fpatan();
5732 case 4: /* fxtract */
5733 gen_helper_fxtract();
5735 case 5: /* fprem1 */
5736 gen_helper_fprem1();
5738 case 6: /* fdecstp */
5739 gen_helper_fdecstp();
5742 case 7: /* fincstp */
5743 gen_helper_fincstp();
5747 case 0x0f: /* grp d9/7 */
5752 case 1: /* fyl2xp1 */
5753 gen_helper_fyl2xp1();
5758 case 3: /* fsincos */
5759 gen_helper_fsincos();
5761 case 5: /* fscale */
5762 gen_helper_fscale();
5764 case 4: /* frndint */
5765 gen_helper_frndint();
5776 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5777 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5778 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5784 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
5788 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5789 gen_helper_fp_arith_ST0_FT0(op1
);
5793 case 0x02: /* fcom */
5794 case 0x22: /* fcom2, undocumented op */
5795 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5796 gen_helper_fcom_ST0_FT0();
5798 case 0x03: /* fcomp */
5799 case 0x23: /* fcomp3, undocumented op */
5800 case 0x32: /* fcomp5, undocumented op */
5801 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5802 gen_helper_fcom_ST0_FT0();
5805 case 0x15: /* da/5 */
5807 case 1: /* fucompp */
5808 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5809 gen_helper_fucom_ST0_FT0();
5819 case 0: /* feni (287 only, just do nop here) */
5821 case 1: /* fdisi (287 only, just do nop here) */
5826 case 3: /* fninit */
5827 gen_helper_fninit();
5829 case 4: /* fsetpm (287 only, just do nop here) */
5835 case 0x1d: /* fucomi */
5836 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5837 gen_op_set_cc_op(s
->cc_op
);
5838 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5839 gen_helper_fucomi_ST0_FT0();
5840 s
->cc_op
= CC_OP_EFLAGS
;
5842 case 0x1e: /* fcomi */
5843 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5844 gen_op_set_cc_op(s
->cc_op
);
5845 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5846 gen_helper_fcomi_ST0_FT0();
5847 s
->cc_op
= CC_OP_EFLAGS
;
5849 case 0x28: /* ffree sti */
5850 gen_helper_ffree_STN(tcg_const_i32(opreg
));
5852 case 0x2a: /* fst sti */
5853 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg
));
5855 case 0x2b: /* fstp sti */
5856 case 0x0b: /* fstp1 sti, undocumented op */
5857 case 0x3a: /* fstp8 sti, undocumented op */
5858 case 0x3b: /* fstp9 sti, undocumented op */
5859 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg
));
5862 case 0x2c: /* fucom st(i) */
5863 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5864 gen_helper_fucom_ST0_FT0();
5866 case 0x2d: /* fucomp st(i) */
5867 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5868 gen_helper_fucom_ST0_FT0();
5871 case 0x33: /* de/3 */
5873 case 1: /* fcompp */
5874 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5875 gen_helper_fcom_ST0_FT0();
5883 case 0x38: /* ffreep sti, undocumented op */
5884 gen_helper_ffree_STN(tcg_const_i32(opreg
));
5887 case 0x3c: /* df/4 */
5890 gen_helper_fnstsw(cpu_tmp2_i32
);
5891 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5892 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
5898 case 0x3d: /* fucomip */
5899 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5900 gen_op_set_cc_op(s
->cc_op
);
5901 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5902 gen_helper_fucomi_ST0_FT0();
5904 s
->cc_op
= CC_OP_EFLAGS
;
5906 case 0x3e: /* fcomip */
5907 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5908 gen_op_set_cc_op(s
->cc_op
);
5909 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5910 gen_helper_fcomi_ST0_FT0();
5912 s
->cc_op
= CC_OP_EFLAGS
;
5914 case 0x10 ... 0x13: /* fcmovxx */
5918 static const uint8_t fcmov_cc
[8] = {
5924 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
5925 l1
= gen_new_label();
5926 gen_jcc1(s
, s
->cc_op
, op1
, l1
);
5927 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg
));
5936 /************************/
5939 case 0xa4: /* movsS */
5944 ot
= dflag
+ OT_WORD
;
5946 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5947 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5953 case 0xaa: /* stosS */
5958 ot
= dflag
+ OT_WORD
;
5960 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5961 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5966 case 0xac: /* lodsS */
5971 ot
= dflag
+ OT_WORD
;
5972 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5973 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5978 case 0xae: /* scasS */
5983 ot
= dflag
+ OT_WORD
;
5984 if (prefixes
& PREFIX_REPNZ
) {
5985 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
5986 } else if (prefixes
& PREFIX_REPZ
) {
5987 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
5990 s
->cc_op
= CC_OP_SUBB
+ ot
;
5994 case 0xa6: /* cmpsS */
5999 ot
= dflag
+ OT_WORD
;
6000 if (prefixes
& PREFIX_REPNZ
) {
6001 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6002 } else if (prefixes
& PREFIX_REPZ
) {
6003 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6006 s
->cc_op
= CC_OP_SUBB
+ ot
;
6009 case 0x6c: /* insS */
6014 ot
= dflag
? OT_LONG
: OT_WORD
;
6015 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6016 gen_op_andl_T0_ffff();
6017 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6018 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6019 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6020 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6024 gen_jmp(s
, s
->pc
- s
->cs_base
);
6028 case 0x6e: /* outsS */
6033 ot
= dflag
? OT_LONG
: OT_WORD
;
6034 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6035 gen_op_andl_T0_ffff();
6036 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6037 svm_is_rep(prefixes
) | 4);
6038 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6039 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6043 gen_jmp(s
, s
->pc
- s
->cs_base
);
6048 /************************/
6056 ot
= dflag
? OT_LONG
: OT_WORD
;
6057 val
= ldub_code(s
->pc
++);
6058 gen_op_movl_T0_im(val
);
6059 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6060 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6063 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6064 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6065 gen_op_mov_reg_T1(ot
, R_EAX
);
6068 gen_jmp(s
, s
->pc
- s
->cs_base
);
6076 ot
= dflag
? OT_LONG
: OT_WORD
;
6077 val
= ldub_code(s
->pc
++);
6078 gen_op_movl_T0_im(val
);
6079 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6080 svm_is_rep(prefixes
));
6081 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6085 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6086 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
6087 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6088 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6091 gen_jmp(s
, s
->pc
- s
->cs_base
);
6099 ot
= dflag
? OT_LONG
: OT_WORD
;
6100 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6101 gen_op_andl_T0_ffff();
6102 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6103 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6106 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6107 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6108 gen_op_mov_reg_T1(ot
, R_EAX
);
6111 gen_jmp(s
, s
->pc
- s
->cs_base
);
6119 ot
= dflag
? OT_LONG
: OT_WORD
;
6120 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6121 gen_op_andl_T0_ffff();
6122 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6123 svm_is_rep(prefixes
));
6124 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6128 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6129 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
6130 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6131 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6134 gen_jmp(s
, s
->pc
- s
->cs_base
);
6138 /************************/
6140 case 0xc2: /* ret im */
6141 val
= ldsw_code(s
->pc
);
6144 if (CODE64(s
) && s
->dflag
)
6146 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6148 gen_op_andl_T0_ffff();
6152 case 0xc3: /* ret */
6156 gen_op_andl_T0_ffff();
6160 case 0xca: /* lret im */
6161 val
= ldsw_code(s
->pc
);
6164 if (s
->pe
&& !s
->vm86
) {
6165 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6166 gen_op_set_cc_op(s
->cc_op
);
6167 gen_jmp_im(pc_start
- s
->cs_base
);
6168 gen_helper_lret_protected(tcg_const_i32(s
->dflag
),
6169 tcg_const_i32(val
));
6173 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6175 gen_op_andl_T0_ffff();
6176 /* NOTE: keeping EIP updated is not a problem in case of
6180 gen_op_addl_A0_im(2 << s
->dflag
);
6181 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6182 gen_op_movl_seg_T0_vm(R_CS
);
6183 /* add stack offset */
6184 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6188 case 0xcb: /* lret */
6191 case 0xcf: /* iret */
6192 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6195 gen_helper_iret_real(tcg_const_i32(s
->dflag
));
6196 s
->cc_op
= CC_OP_EFLAGS
;
6197 } else if (s
->vm86
) {
6199 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6201 gen_helper_iret_real(tcg_const_i32(s
->dflag
));
6202 s
->cc_op
= CC_OP_EFLAGS
;
6205 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6206 gen_op_set_cc_op(s
->cc_op
);
6207 gen_jmp_im(pc_start
- s
->cs_base
);
6208 gen_helper_iret_protected(tcg_const_i32(s
->dflag
),
6209 tcg_const_i32(s
->pc
- s
->cs_base
));
6210 s
->cc_op
= CC_OP_EFLAGS
;
6214 case 0xe8: /* call im */
6217 tval
= (int32_t)insn_get(s
, OT_LONG
);
6219 tval
= (int16_t)insn_get(s
, OT_WORD
);
6220 next_eip
= s
->pc
- s
->cs_base
;
6224 gen_movtl_T0_im(next_eip
);
6229 case 0x9a: /* lcall im */
6231 unsigned int selector
, offset
;
6235 ot
= dflag
? OT_LONG
: OT_WORD
;
6236 offset
= insn_get(s
, ot
);
6237 selector
= insn_get(s
, OT_WORD
);
6239 gen_op_movl_T0_im(selector
);
6240 gen_op_movl_T1_imu(offset
);
6243 case 0xe9: /* jmp im */
6245 tval
= (int32_t)insn_get(s
, OT_LONG
);
6247 tval
= (int16_t)insn_get(s
, OT_WORD
);
6248 tval
+= s
->pc
- s
->cs_base
;
6255 case 0xea: /* ljmp im */
6257 unsigned int selector
, offset
;
6261 ot
= dflag
? OT_LONG
: OT_WORD
;
6262 offset
= insn_get(s
, ot
);
6263 selector
= insn_get(s
, OT_WORD
);
6265 gen_op_movl_T0_im(selector
);
6266 gen_op_movl_T1_imu(offset
);
6269 case 0xeb: /* jmp Jb */
6270 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6271 tval
+= s
->pc
- s
->cs_base
;
6276 case 0x70 ... 0x7f: /* jcc Jb */
6277 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6279 case 0x180 ... 0x18f: /* jcc Jv */
6281 tval
= (int32_t)insn_get(s
, OT_LONG
);
6283 tval
= (int16_t)insn_get(s
, OT_WORD
);
6286 next_eip
= s
->pc
- s
->cs_base
;
6290 gen_jcc(s
, b
, tval
, next_eip
);
6293 case 0x190 ... 0x19f: /* setcc Gv */
6294 modrm
= ldub_code(s
->pc
++);
6296 gen_ldst_modrm(s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
6298 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6303 ot
= dflag
+ OT_WORD
;
6304 modrm
= ldub_code(s
->pc
++);
6305 reg
= ((modrm
>> 3) & 7) | rex_r
;
6306 mod
= (modrm
>> 6) & 3;
6307 t0
= tcg_temp_local_new();
6309 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6310 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
6312 rm
= (modrm
& 7) | REX_B(s
);
6313 gen_op_mov_v_reg(ot
, t0
, rm
);
6315 #ifdef TARGET_X86_64
6316 if (ot
== OT_LONG
) {
6317 /* XXX: specific Intel behaviour ? */
6318 l1
= gen_new_label();
6319 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
6320 tcg_gen_st32_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
6322 tcg_gen_movi_tl(cpu_tmp0
, 0);
6323 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_LH_OFFSET
);
6327 l1
= gen_new_label();
6328 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
6329 gen_op_mov_reg_v(ot
, reg
, t0
);
6336 /************************/
6338 case 0x9c: /* pushf */
6339 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6340 if (s
->vm86
&& s
->iopl
!= 3) {
6341 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6343 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6344 gen_op_set_cc_op(s
->cc_op
);
6345 gen_helper_read_eflags(cpu_T
[0]);
6349 case 0x9d: /* popf */
6350 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6351 if (s
->vm86
&& s
->iopl
!= 3) {
6352 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6357 gen_helper_write_eflags(cpu_T
[0],
6358 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
| IOPL_MASK
)));
6360 gen_helper_write_eflags(cpu_T
[0],
6361 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
| IOPL_MASK
) & 0xffff));
6364 if (s
->cpl
<= s
->iopl
) {
6366 gen_helper_write_eflags(cpu_T
[0],
6367 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
)));
6369 gen_helper_write_eflags(cpu_T
[0],
6370 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
) & 0xffff));
6374 gen_helper_write_eflags(cpu_T
[0],
6375 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
)));
6377 gen_helper_write_eflags(cpu_T
[0],
6378 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
) & 0xffff));
6383 s
->cc_op
= CC_OP_EFLAGS
;
6384 /* abort translation because TF flag may change */
6385 gen_jmp_im(s
->pc
- s
->cs_base
);
6389 case 0x9e: /* sahf */
6390 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6392 gen_op_mov_TN_reg(OT_BYTE
, 0, R_AH
);
6393 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6394 gen_op_set_cc_op(s
->cc_op
);
6395 gen_compute_eflags(cpu_cc_src
);
6396 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6397 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6398 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6399 s
->cc_op
= CC_OP_EFLAGS
;
6401 case 0x9f: /* lahf */
6402 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6404 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6405 gen_op_set_cc_op(s
->cc_op
);
6406 gen_compute_eflags(cpu_T
[0]);
6407 /* Note: gen_compute_eflags() only gives the condition codes */
6408 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], 0x02);
6409 gen_op_mov_reg_T0(OT_BYTE
, R_AH
);
6411 case 0xf5: /* cmc */
6412 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6413 gen_op_set_cc_op(s
->cc_op
);
6414 gen_compute_eflags(cpu_cc_src
);
6415 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6416 s
->cc_op
= CC_OP_EFLAGS
;
6418 case 0xf8: /* clc */
6419 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6420 gen_op_set_cc_op(s
->cc_op
);
6421 gen_compute_eflags(cpu_cc_src
);
6422 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6423 s
->cc_op
= CC_OP_EFLAGS
;
6425 case 0xf9: /* stc */
6426 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6427 gen_op_set_cc_op(s
->cc_op
);
6428 gen_compute_eflags(cpu_cc_src
);
6429 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6430 s
->cc_op
= CC_OP_EFLAGS
;
6432 case 0xfc: /* cld */
6433 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6434 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUState
, df
));
6436 case 0xfd: /* std */
6437 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6438 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUState
, df
));
6441 /************************/
6442 /* bit operations */
6443 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6444 ot
= dflag
+ OT_WORD
;
6445 modrm
= ldub_code(s
->pc
++);
6446 op
= (modrm
>> 3) & 7;
6447 mod
= (modrm
>> 6) & 3;
6448 rm
= (modrm
& 7) | REX_B(s
);
6451 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6452 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6454 gen_op_mov_TN_reg(ot
, 0, rm
);
6457 val
= ldub_code(s
->pc
++);
6458 gen_op_movl_T1_im(val
);
6463 case 0x1a3: /* bt Gv, Ev */
6466 case 0x1ab: /* bts */
6469 case 0x1b3: /* btr */
6472 case 0x1bb: /* btc */
6475 ot
= dflag
+ OT_WORD
;
6476 modrm
= ldub_code(s
->pc
++);
6477 reg
= ((modrm
>> 3) & 7) | rex_r
;
6478 mod
= (modrm
>> 6) & 3;
6479 rm
= (modrm
& 7) | REX_B(s
);
6480 gen_op_mov_TN_reg(OT_LONG
, 1, reg
);
6482 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6483 /* specific case: we need to add a displacement */
6484 gen_exts(ot
, cpu_T
[1]);
6485 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6486 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6487 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6488 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6490 gen_op_mov_TN_reg(ot
, 0, rm
);
6493 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6496 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6497 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6500 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6501 tcg_gen_movi_tl(cpu_tmp0
, 1);
6502 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6503 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6506 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6507 tcg_gen_movi_tl(cpu_tmp0
, 1);
6508 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6509 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6510 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6514 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6515 tcg_gen_movi_tl(cpu_tmp0
, 1);
6516 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6517 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6520 s
->cc_op
= CC_OP_SARB
+ ot
;
6523 gen_op_st_T0_A0(ot
+ s
->mem_index
);
6525 gen_op_mov_reg_T0(ot
, rm
);
6526 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6527 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6530 case 0x1bc: /* bsf */
6531 case 0x1bd: /* bsr */
6536 ot
= dflag
+ OT_WORD
;
6537 modrm
= ldub_code(s
->pc
++);
6538 reg
= ((modrm
>> 3) & 7) | rex_r
;
6539 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
6540 gen_extu(ot
, cpu_T
[0]);
6541 label1
= gen_new_label();
6542 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6543 t0
= tcg_temp_local_new();
6544 tcg_gen_mov_tl(t0
, cpu_T
[0]);
6545 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, label1
);
6547 gen_helper_bsr(cpu_T
[0], t0
);
6549 gen_helper_bsf(cpu_T
[0], t0
);
6551 gen_op_mov_reg_T0(ot
, reg
);
6552 tcg_gen_movi_tl(cpu_cc_dst
, 1);
6553 gen_set_label(label1
);
6554 tcg_gen_discard_tl(cpu_cc_src
);
6555 s
->cc_op
= CC_OP_LOGICB
+ ot
;
6559 /************************/
6561 case 0x27: /* daa */
6564 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6565 gen_op_set_cc_op(s
->cc_op
);
6567 s
->cc_op
= CC_OP_EFLAGS
;
6569 case 0x2f: /* das */
6572 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6573 gen_op_set_cc_op(s
->cc_op
);
6575 s
->cc_op
= CC_OP_EFLAGS
;
6577 case 0x37: /* aaa */
6580 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6581 gen_op_set_cc_op(s
->cc_op
);
6583 s
->cc_op
= CC_OP_EFLAGS
;
6585 case 0x3f: /* aas */
6588 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6589 gen_op_set_cc_op(s
->cc_op
);
6591 s
->cc_op
= CC_OP_EFLAGS
;
6593 case 0xd4: /* aam */
6596 val
= ldub_code(s
->pc
++);
6598 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6600 gen_helper_aam(tcg_const_i32(val
));
6601 s
->cc_op
= CC_OP_LOGICB
;
6604 case 0xd5: /* aad */
6607 val
= ldub_code(s
->pc
++);
6608 gen_helper_aad(tcg_const_i32(val
));
6609 s
->cc_op
= CC_OP_LOGICB
;
6611 /************************/
6613 case 0x90: /* nop */
6614 /* XXX: xchg + rex handling */
6615 /* XXX: correct lock test for all insn */
6616 if (prefixes
& PREFIX_LOCK
)
6618 if (prefixes
& PREFIX_REPZ
) {
6619 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PAUSE
);
6622 case 0x9b: /* fwait */
6623 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6624 (HF_MP_MASK
| HF_TS_MASK
)) {
6625 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6627 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6628 gen_op_set_cc_op(s
->cc_op
);
6629 gen_jmp_im(pc_start
- s
->cs_base
);
6633 case 0xcc: /* int3 */
6634 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6636 case 0xcd: /* int N */
6637 val
= ldub_code(s
->pc
++);
6638 if (s
->vm86
&& s
->iopl
!= 3) {
6639 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6641 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6644 case 0xce: /* into */
6647 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6648 gen_op_set_cc_op(s
->cc_op
);
6649 gen_jmp_im(pc_start
- s
->cs_base
);
6650 gen_helper_into(tcg_const_i32(s
->pc
- pc_start
));
6653 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6654 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6656 gen_debug(s
, pc_start
- s
->cs_base
);
6659 tb_flush(cpu_single_env
);
6660 cpu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6664 case 0xfa: /* cli */
6666 if (s
->cpl
<= s
->iopl
) {
6669 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6675 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6679 case 0xfb: /* sti */
6681 if (s
->cpl
<= s
->iopl
) {
6684 /* interruptions are enabled only the first insn after sti */
6685 /* If several instructions disable interrupts, only the
6687 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6688 gen_helper_set_inhibit_irq();
6689 /* give a chance to handle pending irqs */
6690 gen_jmp_im(s
->pc
- s
->cs_base
);
6693 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6699 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6703 case 0x62: /* bound */
6706 ot
= dflag
? OT_LONG
: OT_WORD
;
6707 modrm
= ldub_code(s
->pc
++);
6708 reg
= (modrm
>> 3) & 7;
6709 mod
= (modrm
>> 6) & 3;
6712 gen_op_mov_TN_reg(ot
, 0, reg
);
6713 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6714 gen_jmp_im(pc_start
- s
->cs_base
);
6715 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6717 gen_helper_boundw(cpu_A0
, cpu_tmp2_i32
);
6719 gen_helper_boundl(cpu_A0
, cpu_tmp2_i32
);
6721 case 0x1c8 ... 0x1cf: /* bswap reg */
6722 reg
= (b
& 7) | REX_B(s
);
6723 #ifdef TARGET_X86_64
6725 gen_op_mov_TN_reg(OT_QUAD
, 0, reg
);
6726 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6727 gen_op_mov_reg_T0(OT_QUAD
, reg
);
6731 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6732 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6733 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6734 gen_op_mov_reg_T0(OT_LONG
, reg
);
6737 case 0xd6: /* salc */
6740 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6741 gen_op_set_cc_op(s
->cc_op
);
6742 gen_compute_eflags_c(cpu_T
[0]);
6743 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6744 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
6746 case 0xe0: /* loopnz */
6747 case 0xe1: /* loopz */
6748 case 0xe2: /* loop */
6749 case 0xe3: /* jecxz */
6753 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6754 next_eip
= s
->pc
- s
->cs_base
;
6759 l1
= gen_new_label();
6760 l2
= gen_new_label();
6761 l3
= gen_new_label();
6764 case 0: /* loopnz */
6766 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6767 gen_op_set_cc_op(s
->cc_op
);
6768 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6769 gen_op_jz_ecx(s
->aflag
, l3
);
6770 gen_compute_eflags(cpu_tmp0
);
6771 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_Z
);
6773 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, l1
);
6775 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, l1
);
6779 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6780 gen_op_jnz_ecx(s
->aflag
, l1
);
6784 gen_op_jz_ecx(s
->aflag
, l1
);
6789 gen_jmp_im(next_eip
);
6798 case 0x130: /* wrmsr */
6799 case 0x132: /* rdmsr */
6801 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6803 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6804 gen_op_set_cc_op(s
->cc_op
);
6805 gen_jmp_im(pc_start
- s
->cs_base
);
6813 case 0x131: /* rdtsc */
6814 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6815 gen_op_set_cc_op(s
->cc_op
);
6816 gen_jmp_im(pc_start
- s
->cs_base
);
6822 gen_jmp(s
, s
->pc
- s
->cs_base
);
6825 case 0x133: /* rdpmc */
6826 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6827 gen_op_set_cc_op(s
->cc_op
);
6828 gen_jmp_im(pc_start
- s
->cs_base
);
6831 case 0x134: /* sysenter */
6832 /* For Intel SYSENTER is valid on 64-bit */
6833 if (CODE64(s
) && cpu_single_env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
6836 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6838 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6839 gen_op_set_cc_op(s
->cc_op
);
6840 s
->cc_op
= CC_OP_DYNAMIC
;
6842 gen_jmp_im(pc_start
- s
->cs_base
);
6843 gen_helper_sysenter();
6847 case 0x135: /* sysexit */
6848 /* For Intel SYSEXIT is valid on 64-bit */
6849 if (CODE64(s
) && cpu_single_env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
6852 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6854 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6855 gen_op_set_cc_op(s
->cc_op
);
6856 s
->cc_op
= CC_OP_DYNAMIC
;
6858 gen_jmp_im(pc_start
- s
->cs_base
);
6859 gen_helper_sysexit(tcg_const_i32(dflag
));
6863 #ifdef TARGET_X86_64
6864 case 0x105: /* syscall */
6865 /* XXX: is it usable in real mode ? */
6866 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6867 gen_op_set_cc_op(s
->cc_op
);
6868 s
->cc_op
= CC_OP_DYNAMIC
;
6870 gen_jmp_im(pc_start
- s
->cs_base
);
6871 gen_helper_syscall(tcg_const_i32(s
->pc
- pc_start
));
6874 case 0x107: /* sysret */
6876 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6878 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6879 gen_op_set_cc_op(s
->cc_op
);
6880 s
->cc_op
= CC_OP_DYNAMIC
;
6882 gen_jmp_im(pc_start
- s
->cs_base
);
6883 gen_helper_sysret(tcg_const_i32(s
->dflag
));
6884 /* condition codes are modified only in long mode */
6886 s
->cc_op
= CC_OP_EFLAGS
;
6891 case 0x1a2: /* cpuid */
6892 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6893 gen_op_set_cc_op(s
->cc_op
);
6894 gen_jmp_im(pc_start
- s
->cs_base
);
6897 case 0xf4: /* hlt */
6899 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6901 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6902 gen_op_set_cc_op(s
->cc_op
);
6903 gen_jmp_im(pc_start
- s
->cs_base
);
6904 gen_helper_hlt(tcg_const_i32(s
->pc
- pc_start
));
6909 modrm
= ldub_code(s
->pc
++);
6910 mod
= (modrm
>> 6) & 3;
6911 op
= (modrm
>> 3) & 7;
6914 if (!s
->pe
|| s
->vm86
)
6916 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
6917 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
6921 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
6924 if (!s
->pe
|| s
->vm86
)
6927 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6929 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
6930 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6931 gen_jmp_im(pc_start
- s
->cs_base
);
6932 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6933 gen_helper_lldt(cpu_tmp2_i32
);
6937 if (!s
->pe
|| s
->vm86
)
6939 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
6940 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
6944 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
6947 if (!s
->pe
|| s
->vm86
)
6950 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6952 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
6953 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6954 gen_jmp_im(pc_start
- s
->cs_base
);
6955 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6956 gen_helper_ltr(cpu_tmp2_i32
);
6961 if (!s
->pe
|| s
->vm86
)
6963 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6964 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6965 gen_op_set_cc_op(s
->cc_op
);
6967 gen_helper_verr(cpu_T
[0]);
6969 gen_helper_verw(cpu_T
[0]);
6970 s
->cc_op
= CC_OP_EFLAGS
;
6977 modrm
= ldub_code(s
->pc
++);
6978 mod
= (modrm
>> 6) & 3;
6979 op
= (modrm
>> 3) & 7;
6985 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
6986 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6987 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
6988 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
6989 gen_add_A0_im(s
, 2);
6990 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
6992 gen_op_andl_T0_im(0xffffff);
6993 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
6998 case 0: /* monitor */
6999 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7002 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7003 gen_op_set_cc_op(s
->cc_op
);
7004 gen_jmp_im(pc_start
- s
->cs_base
);
7005 #ifdef TARGET_X86_64
7006 if (s
->aflag
== 2) {
7007 gen_op_movq_A0_reg(R_EAX
);
7011 gen_op_movl_A0_reg(R_EAX
);
7013 gen_op_andl_A0_ffff();
7015 gen_add_A0_ds_seg(s
);
7016 gen_helper_monitor(cpu_A0
);
7019 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7022 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
7023 gen_op_set_cc_op(s
->cc_op
);
7024 s
->cc_op
= CC_OP_DYNAMIC
;
7026 gen_jmp_im(pc_start
- s
->cs_base
);
7027 gen_helper_mwait(tcg_const_i32(s
->pc
- pc_start
));
7034 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7035 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7036 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7037 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7038 gen_add_A0_im(s
, 2);
7039 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7041 gen_op_andl_T0_im(0xffffff);
7042 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7048 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7049 gen_op_set_cc_op(s
->cc_op
);
7050 gen_jmp_im(pc_start
- s
->cs_base
);
7053 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7056 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7059 gen_helper_vmrun(tcg_const_i32(s
->aflag
),
7060 tcg_const_i32(s
->pc
- pc_start
));
7065 case 1: /* VMMCALL */
7066 if (!(s
->flags
& HF_SVME_MASK
))
7068 gen_helper_vmmcall();
7070 case 2: /* VMLOAD */
7071 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7074 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7077 gen_helper_vmload(tcg_const_i32(s
->aflag
));
7080 case 3: /* VMSAVE */
7081 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7084 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7087 gen_helper_vmsave(tcg_const_i32(s
->aflag
));
7091 if ((!(s
->flags
& HF_SVME_MASK
) &&
7092 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7096 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7103 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7106 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7112 case 6: /* SKINIT */
7113 if ((!(s
->flags
& HF_SVME_MASK
) &&
7114 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7117 gen_helper_skinit();
7119 case 7: /* INVLPGA */
7120 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7123 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7126 gen_helper_invlpga(tcg_const_i32(s
->aflag
));
7132 } else if (s
->cpl
!= 0) {
7133 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7135 gen_svm_check_intercept(s
, pc_start
,
7136 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7137 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7138 gen_op_ld_T1_A0(OT_WORD
+ s
->mem_index
);
7139 gen_add_A0_im(s
, 2);
7140 gen_op_ld_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7142 gen_op_andl_T0_im(0xffffff);
7144 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7145 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7147 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7148 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7153 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7154 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7155 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7157 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7159 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 1);
7163 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7165 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7166 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7167 gen_helper_lmsw(cpu_T
[0]);
7168 gen_jmp_im(s
->pc
- s
->cs_base
);
7172 case 7: /* invlpg */
7174 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7177 #ifdef TARGET_X86_64
7178 if (CODE64(s
) && rm
== 0) {
7180 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,segs
[R_GS
].base
));
7181 tcg_gen_ld_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,kernelgsbase
));
7182 tcg_gen_st_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,segs
[R_GS
].base
));
7183 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,kernelgsbase
));
7190 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7191 gen_op_set_cc_op(s
->cc_op
);
7192 gen_jmp_im(pc_start
- s
->cs_base
);
7193 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7194 gen_helper_invlpg(cpu_A0
);
7195 gen_jmp_im(s
->pc
- s
->cs_base
);
7204 case 0x108: /* invd */
7205 case 0x109: /* wbinvd */
7207 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7209 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7213 case 0x63: /* arpl or movslS (x86_64) */
7214 #ifdef TARGET_X86_64
7217 /* d_ot is the size of destination */
7218 d_ot
= dflag
+ OT_WORD
;
7220 modrm
= ldub_code(s
->pc
++);
7221 reg
= ((modrm
>> 3) & 7) | rex_r
;
7222 mod
= (modrm
>> 6) & 3;
7223 rm
= (modrm
& 7) | REX_B(s
);
7226 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
7228 if (d_ot
== OT_QUAD
)
7229 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7230 gen_op_mov_reg_T0(d_ot
, reg
);
7232 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7233 if (d_ot
== OT_QUAD
) {
7234 gen_op_lds_T0_A0(OT_LONG
+ s
->mem_index
);
7236 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7238 gen_op_mov_reg_T0(d_ot
, reg
);
7246 if (!s
->pe
|| s
->vm86
)
7248 t0
= tcg_temp_local_new();
7249 t1
= tcg_temp_local_new();
7250 t2
= tcg_temp_local_new();
7252 modrm
= ldub_code(s
->pc
++);
7253 reg
= (modrm
>> 3) & 7;
7254 mod
= (modrm
>> 6) & 3;
7257 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7258 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7260 gen_op_mov_v_reg(ot
, t0
, rm
);
7262 gen_op_mov_v_reg(ot
, t1
, reg
);
7263 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7264 tcg_gen_andi_tl(t1
, t1
, 3);
7265 tcg_gen_movi_tl(t2
, 0);
7266 label1
= gen_new_label();
7267 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7268 tcg_gen_andi_tl(t0
, t0
, ~3);
7269 tcg_gen_or_tl(t0
, t0
, t1
);
7270 tcg_gen_movi_tl(t2
, CC_Z
);
7271 gen_set_label(label1
);
7273 gen_op_st_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7275 gen_op_mov_reg_v(ot
, rm
, t0
);
7277 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7278 gen_op_set_cc_op(s
->cc_op
);
7279 gen_compute_eflags(cpu_cc_src
);
7280 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7281 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7282 s
->cc_op
= CC_OP_EFLAGS
;
7288 case 0x102: /* lar */
7289 case 0x103: /* lsl */
7293 if (!s
->pe
|| s
->vm86
)
7295 ot
= dflag
? OT_LONG
: OT_WORD
;
7296 modrm
= ldub_code(s
->pc
++);
7297 reg
= ((modrm
>> 3) & 7) | rex_r
;
7298 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7299 t0
= tcg_temp_local_new();
7300 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7301 gen_op_set_cc_op(s
->cc_op
);
7303 gen_helper_lar(t0
, cpu_T
[0]);
7305 gen_helper_lsl(t0
, cpu_T
[0]);
7306 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7307 label1
= gen_new_label();
7308 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7309 gen_op_mov_reg_v(ot
, reg
, t0
);
7310 gen_set_label(label1
);
7311 s
->cc_op
= CC_OP_EFLAGS
;
7316 modrm
= ldub_code(s
->pc
++);
7317 mod
= (modrm
>> 6) & 3;
7318 op
= (modrm
>> 3) & 7;
7320 case 0: /* prefetchnta */
7321 case 1: /* prefetchnt0 */
7322 case 2: /* prefetchnt0 */
7323 case 3: /* prefetchnt0 */
7326 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7327 /* nothing more to do */
7329 default: /* nop (multi byte) */
7330 gen_nop_modrm(s
, modrm
);
7334 case 0x119 ... 0x11f: /* nop (multi byte) */
7335 modrm
= ldub_code(s
->pc
++);
7336 gen_nop_modrm(s
, modrm
);
7338 case 0x120: /* mov reg, crN */
7339 case 0x122: /* mov crN, reg */
7341 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7343 modrm
= ldub_code(s
->pc
++);
7344 if ((modrm
& 0xc0) != 0xc0)
7346 rm
= (modrm
& 7) | REX_B(s
);
7347 reg
= ((modrm
>> 3) & 7) | rex_r
;
7358 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7359 gen_op_set_cc_op(s
->cc_op
);
7360 gen_jmp_im(pc_start
- s
->cs_base
);
7362 gen_op_mov_TN_reg(ot
, 0, rm
);
7363 gen_helper_write_crN(tcg_const_i32(reg
), cpu_T
[0]);
7364 gen_jmp_im(s
->pc
- s
->cs_base
);
7367 gen_helper_read_crN(cpu_T
[0], tcg_const_i32(reg
));
7368 gen_op_mov_reg_T0(ot
, rm
);
7376 case 0x121: /* mov reg, drN */
7377 case 0x123: /* mov drN, reg */
7379 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7381 modrm
= ldub_code(s
->pc
++);
7382 if ((modrm
& 0xc0) != 0xc0)
7384 rm
= (modrm
& 7) | REX_B(s
);
7385 reg
= ((modrm
>> 3) & 7) | rex_r
;
7390 /* XXX: do it dynamically with CR4.DE bit */
7391 if (reg
== 4 || reg
== 5 || reg
>= 8)
7394 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7395 gen_op_mov_TN_reg(ot
, 0, rm
);
7396 gen_helper_movl_drN_T0(tcg_const_i32(reg
), cpu_T
[0]);
7397 gen_jmp_im(s
->pc
- s
->cs_base
);
7400 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7401 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7402 gen_op_mov_reg_T0(ot
, rm
);
7406 case 0x106: /* clts */
7408 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7410 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7412 /* abort block because static cpu state changed */
7413 gen_jmp_im(s
->pc
- s
->cs_base
);
7417 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7418 case 0x1c3: /* MOVNTI reg, mem */
7419 if (!(s
->cpuid_features
& CPUID_SSE2
))
7421 ot
= s
->dflag
== 2 ? OT_QUAD
: OT_LONG
;
7422 modrm
= ldub_code(s
->pc
++);
7423 mod
= (modrm
>> 6) & 3;
7426 reg
= ((modrm
>> 3) & 7) | rex_r
;
7427 /* generate a generic store */
7428 gen_ldst_modrm(s
, modrm
, ot
, reg
, 1);
7431 modrm
= ldub_code(s
->pc
++);
7432 mod
= (modrm
>> 6) & 3;
7433 op
= (modrm
>> 3) & 7;
7435 case 0: /* fxsave */
7436 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7437 (s
->flags
& HF_EM_MASK
))
7439 if (s
->flags
& HF_TS_MASK
) {
7440 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7443 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7444 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7445 gen_op_set_cc_op(s
->cc_op
);
7446 gen_jmp_im(pc_start
- s
->cs_base
);
7447 gen_helper_fxsave(cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7449 case 1: /* fxrstor */
7450 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7451 (s
->flags
& HF_EM_MASK
))
7453 if (s
->flags
& HF_TS_MASK
) {
7454 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7457 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7458 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7459 gen_op_set_cc_op(s
->cc_op
);
7460 gen_jmp_im(pc_start
- s
->cs_base
);
7461 gen_helper_fxrstor(cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7463 case 2: /* ldmxcsr */
7464 case 3: /* stmxcsr */
7465 if (s
->flags
& HF_TS_MASK
) {
7466 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7469 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7472 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7474 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7475 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7477 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7478 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
7481 case 5: /* lfence */
7482 case 6: /* mfence */
7483 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE
))
7486 case 7: /* sfence / clflush */
7487 if ((modrm
& 0xc7) == 0xc0) {
7489 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7490 if (!(s
->cpuid_features
& CPUID_SSE
))
7494 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7496 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7503 case 0x10d: /* 3DNow! prefetch(w) */
7504 modrm
= ldub_code(s
->pc
++);
7505 mod
= (modrm
>> 6) & 3;
7508 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7509 /* ignore for now */
7511 case 0x1aa: /* rsm */
7512 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7513 if (!(s
->flags
& HF_SMM_MASK
))
7515 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
7516 gen_op_set_cc_op(s
->cc_op
);
7517 s
->cc_op
= CC_OP_DYNAMIC
;
7519 gen_jmp_im(s
->pc
- s
->cs_base
);
7523 case 0x1b8: /* SSE4.2 popcnt */
7524 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7527 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7530 modrm
= ldub_code(s
->pc
++);
7531 reg
= ((modrm
>> 3) & 7);
7533 if (s
->prefix
& PREFIX_DATA
)
7535 else if (s
->dflag
!= 2)
7540 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
7541 gen_helper_popcnt(cpu_T
[0], cpu_T
[0], tcg_const_i32(ot
));
7542 gen_op_mov_reg_T0(ot
, reg
);
7544 s
->cc_op
= CC_OP_EFLAGS
;
7546 case 0x10e ... 0x10f:
7547 /* 3DNow! instructions, ignore prefixes */
7548 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7549 case 0x110 ... 0x117:
7550 case 0x128 ... 0x12f:
7551 case 0x138 ... 0x13a:
7552 case 0x150 ... 0x177:
7553 case 0x17c ... 0x17f:
7555 case 0x1c4 ... 0x1c6:
7556 case 0x1d0 ... 0x1fe:
7557 gen_sse(s
, b
, pc_start
, rex_r
);
7562 /* lock generation */
7563 if (s
->prefix
& PREFIX_LOCK
)
7564 gen_helper_unlock();
7567 if (s
->prefix
& PREFIX_LOCK
)
7568 gen_helper_unlock();
7569 /* XXX: ensure that no lock was generated */
7570 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7574 void optimize_flags_init(void)
7576 #if TCG_TARGET_REG_BITS == 32
7577 assert(sizeof(CCTable
) == (1 << 3));
7579 assert(sizeof(CCTable
) == (1 << 4));
7581 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7582 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7583 offsetof(CPUState
, cc_op
), "cc_op");
7584 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUState
, cc_src
),
7586 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUState
, cc_dst
),
7588 cpu_cc_tmp
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUState
, cc_tmp
),
7591 /* register helpers */
7592 #define GEN_HELPER 2
7596 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7597 basic block 'tb'. If search_pc is TRUE, also generate PC
7598 information for each intermediate instruction. */
7599 static inline void gen_intermediate_code_internal(CPUState
*env
,
7600 TranslationBlock
*tb
,
7603 DisasContext dc1
, *dc
= &dc1
;
7604 target_ulong pc_ptr
;
7605 uint16_t *gen_opc_end
;
7609 target_ulong pc_start
;
7610 target_ulong cs_base
;
7614 /* generate intermediate code */
7616 cs_base
= tb
->cs_base
;
7618 cflags
= tb
->cflags
;
7620 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7621 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7622 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7623 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7625 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7626 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7627 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7628 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7629 dc
->singlestep_enabled
= env
->singlestep_enabled
;
7630 dc
->cc_op
= CC_OP_DYNAMIC
;
7631 dc
->cs_base
= cs_base
;
7633 dc
->popl_esp_hack
= 0;
7634 /* select memory access functions */
7636 if (flags
& HF_SOFTMMU_MASK
) {
7638 dc
->mem_index
= 2 * 4;
7640 dc
->mem_index
= 1 * 4;
7642 dc
->cpuid_features
= env
->cpuid_features
;
7643 dc
->cpuid_ext_features
= env
->cpuid_ext_features
;
7644 dc
->cpuid_ext2_features
= env
->cpuid_ext2_features
;
7645 dc
->cpuid_ext3_features
= env
->cpuid_ext3_features
;
7646 #ifdef TARGET_X86_64
7647 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7648 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7651 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
7652 (flags
& HF_INHIBIT_IRQ_MASK
)
7653 #ifndef CONFIG_SOFTMMU
7654 || (flags
& HF_SOFTMMU_MASK
)
7658 /* check addseg logic */
7659 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7660 printf("ERROR addseg\n");
7663 cpu_T
[0] = tcg_temp_new();
7664 cpu_T
[1] = tcg_temp_new();
7665 cpu_A0
= tcg_temp_new();
7666 cpu_T3
= tcg_temp_new();
7668 cpu_tmp0
= tcg_temp_new();
7669 cpu_tmp1_i64
= tcg_temp_new_i64();
7670 cpu_tmp2_i32
= tcg_temp_new_i32();
7671 cpu_tmp3_i32
= tcg_temp_new_i32();
7672 cpu_tmp4
= tcg_temp_new();
7673 cpu_tmp5
= tcg_temp_new();
7674 cpu_tmp6
= tcg_temp_new();
7675 cpu_ptr0
= tcg_temp_new_ptr();
7676 cpu_ptr1
= tcg_temp_new_ptr();
7678 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
7680 dc
->is_jmp
= DISAS_NEXT
;
7684 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7686 max_insns
= CF_COUNT_MASK
;
7690 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
7691 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7692 if (bp
->pc
== pc_ptr
&&
7693 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
7694 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7700 j
= gen_opc_ptr
- gen_opc_buf
;
7704 gen_opc_instr_start
[lj
++] = 0;
7706 gen_opc_pc
[lj
] = pc_ptr
;
7707 gen_opc_cc_op
[lj
] = dc
->cc_op
;
7708 gen_opc_instr_start
[lj
] = 1;
7709 gen_opc_icount
[lj
] = num_insns
;
7711 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7714 pc_ptr
= disas_insn(dc
, pc_ptr
);
7716 /* stop translation if indicated */
7719 /* if single step mode, we generate only one instruction and
7720 generate an exception */
7721 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7722 the flag and abort the translation to give the irqs a
7723 change to be happen */
7724 if (dc
->tf
|| dc
->singlestep_enabled
||
7725 (flags
& HF_INHIBIT_IRQ_MASK
)) {
7726 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7730 /* if too long translation, stop generation too */
7731 if (gen_opc_ptr
>= gen_opc_end
||
7732 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
7733 num_insns
>= max_insns
) {
7734 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7739 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7744 if (tb
->cflags
& CF_LAST_IO
)
7746 gen_icount_end(tb
, num_insns
);
7747 *gen_opc_ptr
= INDEX_op_end
;
7748 /* we don't forget to fill the last values */
7750 j
= gen_opc_ptr
- gen_opc_buf
;
7753 gen_opc_instr_start
[lj
++] = 0;
7757 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, X86_DUMP_CCOP
);
7758 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
7760 qemu_log("----------------\n");
7761 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
7762 #ifdef TARGET_X86_64
7767 disas_flags
= !dc
->code32
;
7768 log_target_disas(pc_start
, pc_ptr
- pc_start
, disas_flags
);
7774 tb
->size
= pc_ptr
- pc_start
;
7775 tb
->icount
= num_insns
;
7779 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
7781 gen_intermediate_code_internal(env
, tb
, 0);
7784 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
7786 gen_intermediate_code_internal(env
, tb
, 1);
7789 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
7790 unsigned long searched_pc
, int pc_pos
, void *puc
)
7794 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
7796 qemu_log("RESTORE:\n");
7797 for(i
= 0;i
<= pc_pos
; i
++) {
7798 if (gen_opc_instr_start
[i
]) {
7799 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
, gen_opc_pc
[i
]);
7802 qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
7803 searched_pc
, pc_pos
, gen_opc_pc
[pc_pos
] - tb
->cs_base
,
7804 (uint32_t)tb
->cs_base
);
7807 env
->eip
= gen_opc_pc
[pc_pos
] - tb
->cs_base
;
7808 cc_op
= gen_opc_cc_op
[pc_pos
];
7809 if (cc_op
!= CC_OP_DYNAMIC
)