target-ppc/translate_init.c

   1 /*
   2  *  PowerPC CPU initialization for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /* A lot of PowerPC definition have been included here.
  21  * Most of them are not usable for now but have been kept
  22  * inside "#if defined(TODO) ... #endif" statements to make tests easier.
  23  */
  24
  25 #include "dis-asm.h"
  26 #include "gdbstub.h"
  27
  28 //#define PPC_DUMP_CPU
  29 //#define PPC_DEBUG_SPR
  30 //#define PPC_DUMP_SPR_ACCESSES
  31 #if defined(CONFIG_USER_ONLY)
  32 #define TODO_USER_ONLY 1
  33 #endif
  34
  35 struct ppc_def_t {
  36     const char *name;
  37     uint32_t pvr;
  38     uint32_t svr;
  39     uint64_t insns_flags;
  40     uint64_t msr_mask;
  41     powerpc_mmu_t   mmu_model;
  42     powerpc_excp_t  excp_model;
  43     powerpc_input_t bus_model;
  44     uint32_t flags;
  45     int bfd_mach;
  46     void (*init_proc)(CPUPPCState *env);
  47     int  (*check_pow)(CPUPPCState *env);
  48 };
  49
  50 /* For user-mode emulation, we don't emulate any IRQ controller */
  51 #if defined(CONFIG_USER_ONLY)
  52 #define PPC_IRQ_INIT_FN(name)                                                 \
  53 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
  54 {                                                                             \
  55 }
  56 #else
  57 #define PPC_IRQ_INIT_FN(name)                                                 \
  58 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
  59 #endif
  60
  61 PPC_IRQ_INIT_FN(40x);
  62 PPC_IRQ_INIT_FN(6xx);
  63 PPC_IRQ_INIT_FN(970);
  64 PPC_IRQ_INIT_FN(e500);
  65
  66 /* Generic callbacks:
  67  * do nothing but store/retrieve spr value
  68  */
  69 static void spr_read_generic (void *opaque, int gprn, int sprn)
  70 {
  71     gen_load_spr(cpu_gpr[gprn], sprn);
  72 #ifdef PPC_DUMP_SPR_ACCESSES
  73     {
  74         TCGv t0 = tcg_const_i32(sprn);
  75         gen_helper_load_dump_spr(t0);
  76         tcg_temp_free_i32(t0);
  77     }
  78 #endif
  79 }
  80
  81 static void spr_write_generic (void *opaque, int sprn, int gprn)
  82 {
  83     gen_store_spr(sprn, cpu_gpr[gprn]);
  84 #ifdef PPC_DUMP_SPR_ACCESSES
  85     {
  86         TCGv t0 = tcg_const_i32(sprn);
  87         gen_helper_store_dump_spr(t0);
  88         tcg_temp_free_i32(t0);
  89     }
  90 #endif
  91 }
  92
  93 #if !defined(CONFIG_USER_ONLY)
  94 static void spr_write_clear (void *opaque, int sprn, int gprn)
  95 {
  96     TCGv t0 = tcg_temp_new();
  97     TCGv t1 = tcg_temp_new();
  98     gen_load_spr(t0, sprn);
  99     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 100     tcg_gen_and_tl(t0, t0, t1);
 101     gen_store_spr(sprn, t0);
 102     tcg_temp_free(t0);
 103     tcg_temp_free(t1);
 104 }
 105 #endif
 106
 107 /* SPR common to all PowerPC */
 108 /* XER */
 109 static void spr_read_xer (void *opaque, int gprn, int sprn)
 110 {
 111     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
 112 }
 113
 114 static void spr_write_xer (void *opaque, int sprn, int gprn)
 115 {
 116     tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
 117 }
 118
 119 /* LR */
 120 static void spr_read_lr (void *opaque, int gprn, int sprn)
 121 {
 122     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 123 }
 124
 125 static void spr_write_lr (void *opaque, int sprn, int gprn)
 126 {
 127     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 128 }
 129
 130 /* CTR */
 131 static void spr_read_ctr (void *opaque, int gprn, int sprn)
 132 {
 133     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 134 }
 135
 136 static void spr_write_ctr (void *opaque, int sprn, int gprn)
 137 {
 138     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 139 }
 140
 141 /* User read access to SPR */
 142 /* USPRx */
 143 /* UMMCRx */
 144 /* UPMCx */
 145 /* USIA */
 146 /* UDECR */
 147 static void spr_read_ureg (void *opaque, int gprn, int sprn)
 148 {
 149     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 150 }
 151
 152 /* SPR common to all non-embedded PowerPC */
 153 /* DECR */
 154 #if !defined(CONFIG_USER_ONLY)
 155 static void spr_read_decr (void *opaque, int gprn, int sprn)
 156 {
 157     if (use_icount) {
 158         gen_io_start();
 159     }
 160     gen_helper_load_decr(cpu_gpr[gprn]);
 161     if (use_icount) {
 162         gen_io_end();
 163         gen_stop_exception(opaque);
 164     }
 165 }
 166
 167 static void spr_write_decr (void *opaque, int sprn, int gprn)
 168 {
 169     if (use_icount) {
 170         gen_io_start();
 171     }
 172     gen_helper_store_decr(cpu_gpr[gprn]);
 173     if (use_icount) {
 174         gen_io_end();
 175         gen_stop_exception(opaque);
 176     }
 177 }
 178 #endif
 179
 180 /* SPR common to all non-embedded PowerPC, except 601 */
 181 /* Time base */
 182 static void spr_read_tbl (void *opaque, int gprn, int sprn)
 183 {
 184     if (use_icount) {
 185         gen_io_start();
 186     }
 187     gen_helper_load_tbl(cpu_gpr[gprn]);
 188     if (use_icount) {
 189         gen_io_end();
 190         gen_stop_exception(opaque);
 191     }
 192 }
 193
 194 static void spr_read_tbu (void *opaque, int gprn, int sprn)
 195 {
 196     if (use_icount) {
 197         gen_io_start();
 198     }
 199     gen_helper_load_tbu(cpu_gpr[gprn]);
 200     if (use_icount) {
 201         gen_io_end();
 202         gen_stop_exception(opaque);
 203     }
 204 }
 205
 206 __attribute__ (( unused ))
 207 static void spr_read_atbl (void *opaque, int gprn, int sprn)
 208 {
 209     gen_helper_load_atbl(cpu_gpr[gprn]);
 210 }
 211
 212 __attribute__ (( unused ))
 213 static void spr_read_atbu (void *opaque, int gprn, int sprn)
 214 {
 215     gen_helper_load_atbu(cpu_gpr[gprn]);
 216 }
 217
 218 #if !defined(CONFIG_USER_ONLY)
 219 static void spr_write_tbl (void *opaque, int sprn, int gprn)
 220 {
 221     if (use_icount) {
 222         gen_io_start();
 223     }
 224     gen_helper_store_tbl(cpu_gpr[gprn]);
 225     if (use_icount) {
 226         gen_io_end();
 227         gen_stop_exception(opaque);
 228     }
 229 }
 230
 231 static void spr_write_tbu (void *opaque, int sprn, int gprn)
 232 {
 233     if (use_icount) {
 234         gen_io_start();
 235     }
 236     gen_helper_store_tbu(cpu_gpr[gprn]);
 237     if (use_icount) {
 238         gen_io_end();
 239         gen_stop_exception(opaque);
 240     }
 241 }
 242
 243 __attribute__ (( unused ))
 244 static void spr_write_atbl (void *opaque, int sprn, int gprn)
 245 {
 246     gen_helper_store_atbl(cpu_gpr[gprn]);
 247 }
 248
 249 __attribute__ (( unused ))
 250 static void spr_write_atbu (void *opaque, int sprn, int gprn)
 251 {
 252     gen_helper_store_atbu(cpu_gpr[gprn]);
 253 }
 254
 255 #if defined(TARGET_PPC64)
 256 __attribute__ (( unused ))
 257 static void spr_read_purr (void *opaque, int gprn, int sprn)
 258 {
 259     gen_helper_load_purr(cpu_gpr[gprn]);
 260 }
 261 #endif
 262 #endif
 263
 264 #if !defined(CONFIG_USER_ONLY)
 265 /* IBAT0U...IBAT0U */
 266 /* IBAT0L...IBAT7L */
 267 static void spr_read_ibat (void *opaque, int gprn, int sprn)
 268 {
 269     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 270 }
 271
 272 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
 273 {
 274     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
 275 }
 276
 277 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
 278 {
 279     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 280     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 281     tcg_temp_free_i32(t0);
 282 }
 283
 284 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
 285 {
 286     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
 287     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 288     tcg_temp_free_i32(t0);
 289 }
 290
 291 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
 292 {
 293     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 294     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 295     tcg_temp_free_i32(t0);
 296 }
 297
 298 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
 299 {
 300     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
 301     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 302     tcg_temp_free_i32(t0);
 303 }
 304
 305 /* DBAT0U...DBAT7U */
 306 /* DBAT0L...DBAT7L */
 307 static void spr_read_dbat (void *opaque, int gprn, int sprn)
 308 {
 309     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 310 }
 311
 312 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
 313 {
 314     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 315 }
 316
 317 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
 318 {
 319     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 320     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 321     tcg_temp_free_i32(t0);
 322 }
 323
 324 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
 325 {
 326     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 327     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 328     tcg_temp_free_i32(t0);
 329 }
 330
 331 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
 332 {
 333     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 334     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 335     tcg_temp_free_i32(t0);
 336 }
 337
 338 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
 339 {
 340     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 341     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 342     tcg_temp_free_i32(t0);
 343 }
 344
 345 /* SDR1 */
 346 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
 347 {
 348     gen_helper_store_sdr1(cpu_gpr[gprn]);
 349 }
 350
 351 /* 64 bits PowerPC specific SPRs */
 352 /* ASR */
 353 #if defined(TARGET_PPC64)
 354 static void spr_read_hior (void *opaque, int gprn, int sprn)
 355 {
 356     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
 357 }
 358
 359 static void spr_write_hior (void *opaque, int sprn, int gprn)
 360 {
 361     TCGv t0 = tcg_temp_new();
 362     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
 363     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 364     tcg_temp_free(t0);
 365 }
 366
 367 static void spr_read_asr (void *opaque, int gprn, int sprn)
 368 {
 369     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
 370 }
 371
 372 static void spr_write_asr (void *opaque, int sprn, int gprn)
 373 {
 374     gen_helper_store_asr(cpu_gpr[gprn]);
 375 }
 376 #endif
 377 #endif
 378
 379 /* PowerPC 601 specific registers */
 380 /* RTC */
 381 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
 382 {
 383     gen_helper_load_601_rtcl(cpu_gpr[gprn]);
 384 }
 385
 386 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
 387 {
 388     gen_helper_load_601_rtcu(cpu_gpr[gprn]);
 389 }
 390
 391 #if !defined(CONFIG_USER_ONLY)
 392 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
 393 {
 394     gen_helper_store_601_rtcu(cpu_gpr[gprn]);
 395 }
 396
 397 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
 398 {
 399     gen_helper_store_601_rtcl(cpu_gpr[gprn]);
 400 }
 401
 402 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
 403 {
 404     DisasContext *ctx = opaque;
 405
 406     gen_helper_store_hid0_601(cpu_gpr[gprn]);
 407     /* Must stop the translation as endianness may have changed */
 408     gen_stop_exception(ctx);
 409 }
 410 #endif
 411
 412 /* Unified bats */
 413 #if !defined(CONFIG_USER_ONLY)
 414 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
 415 {
 416     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 417 }
 418
 419 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
 420 {
 421     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 422     gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
 423     tcg_temp_free_i32(t0);
 424 }
 425
 426 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
 427 {
 428     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 429     gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
 430     tcg_temp_free_i32(t0);
 431 }
 432 #endif
 433
 434 /* PowerPC 40x specific registers */
 435 #if !defined(CONFIG_USER_ONLY)
 436 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
 437 {
 438     gen_helper_load_40x_pit(cpu_gpr[gprn]);
 439 }
 440
 441 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
 442 {
 443     gen_helper_store_40x_pit(cpu_gpr[gprn]);
 444 }
 445
 446 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
 447 {
 448     DisasContext *ctx = opaque;
 449
 450     gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
 451     /* We must stop translation as we may have rebooted */
 452     gen_stop_exception(ctx);
 453 }
 454
 455 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
 456 {
 457     gen_helper_store_40x_sler(cpu_gpr[gprn]);
 458 }
 459
 460 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
 461 {
 462     gen_helper_store_booke_tcr(cpu_gpr[gprn]);
 463 }
 464
 465 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
 466 {
 467     gen_helper_store_booke_tsr(cpu_gpr[gprn]);
 468 }
 469 #endif
 470
 471 /* PowerPC 403 specific registers */
 472 /* PBL1 / PBU1 / PBL2 / PBU2 */
 473 #if !defined(CONFIG_USER_ONLY)
 474 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
 475 {
 476     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
 477 }
 478
 479 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
 480 {
 481     TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 482     gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
 483     tcg_temp_free_i32(t0);
 484 }
 485
 486 static void spr_write_pir (void *opaque, int sprn, int gprn)
 487 {
 488     TCGv t0 = tcg_temp_new();
 489     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 490     gen_store_spr(SPR_PIR, t0);
 491     tcg_temp_free(t0);
 492 }
 493 #endif
 494
 495 /* SPE specific registers */
 496 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
 497 {
 498     TCGv_i32 t0 = tcg_temp_new_i32();
 499     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
 500     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
 501     tcg_temp_free_i32(t0);
 502 }
 503
 504 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
 505 {
 506     TCGv_i32 t0 = tcg_temp_new_i32();
 507     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
 508     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
 509     tcg_temp_free_i32(t0);
 510 }
 511
 512 #if !defined(CONFIG_USER_ONLY)
 513 /* Callback used to write the exception vector base */
 514 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
 515 {
 516     TCGv t0 = tcg_temp_new();
 517     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
 518     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 519     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 520     gen_store_spr(sprn, t0);
 521     tcg_temp_free(t0);
 522 }
 523
 524 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
 525 {
 526     DisasContext *ctx = opaque;
 527
 528     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 529         TCGv t0 = tcg_temp_new();
 530         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 531         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 532         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
 533         gen_store_spr(sprn, t0);
 534         tcg_temp_free(t0);
 535     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 536         TCGv t0 = tcg_temp_new();
 537         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 538         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 539         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
 540         gen_store_spr(sprn, t0);
 541         tcg_temp_free(t0);
 542     } else {
 543         printf("Trying to write an unknown exception vector %d %03x\n",
 544                sprn, sprn);
 545         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 546     }
 547 }
 548 #endif
 549
 550 static inline void vscr_init (CPUPPCState *env, uint32_t val)
 551 {
 552     env->vscr = val;
 553     /* Altivec always uses round-to-nearest */
 554     set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 555     set_flush_to_zero(vscr_nj, &env->vec_status);
 556 }
 557
 558 #if defined(CONFIG_USER_ONLY)
 559 #define spr_register(env, num, name, uea_read, uea_write,                     \
 560                      oea_read, oea_write, initial_value)                      \
 561 do {                                                                          \
 562      _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
 563 } while (0)
 564 static inline void _spr_register (CPUPPCState *env, int num,
 565                                   const char *name,
 566                                   void (*uea_read)(void *opaque, int gprn, int sprn),
 567                                   void (*uea_write)(void *opaque, int sprn, int gprn),
 568                                   target_ulong initial_value)
 569 #else
 570 static inline void spr_register (CPUPPCState *env, int num,
 571                                  const char *name,
 572                                  void (*uea_read)(void *opaque, int gprn, int sprn),
 573                                  void (*uea_write)(void *opaque, int sprn, int gprn),
 574                                  void (*oea_read)(void *opaque, int gprn, int sprn),
 575                                  void (*oea_write)(void *opaque, int sprn, int gprn),
 576                                  target_ulong initial_value)
 577 #endif
 578 {
 579     ppc_spr_t *spr;
 580
 581     spr = &env->spr_cb[num];
 582     if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
 583 #if !defined(CONFIG_USER_ONLY)
 584         spr->oea_read != NULL || spr->oea_write != NULL ||
 585 #endif
 586         spr->uea_read != NULL || spr->uea_write != NULL) {
 587         printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 588         exit(1);
 589     }
 590 #if defined(PPC_DEBUG_SPR)
 591     printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
 592            name, initial_value);
 593 #endif
 594     spr->name = name;
 595     spr->uea_read = uea_read;
 596     spr->uea_write = uea_write;
 597 #if !defined(CONFIG_USER_ONLY)
 598     spr->oea_read = oea_read;
 599     spr->oea_write = oea_write;
 600 #endif
 601     env->spr[num] = initial_value;
 602 }
 603
 604 /* Generic PowerPC SPRs */
 605 static void gen_spr_generic (CPUPPCState *env)
 606 {
 607     /* Integer processing */
 608     spr_register(env, SPR_XER, "XER",
 609                  &spr_read_xer, &spr_write_xer,
 610                  &spr_read_xer, &spr_write_xer,
 611                  0x00000000);
 612     /* Branch contol */
 613     spr_register(env, SPR_LR, "LR",
 614                  &spr_read_lr, &spr_write_lr,
 615                  &spr_read_lr, &spr_write_lr,
 616                  0x00000000);
 617     spr_register(env, SPR_CTR, "CTR",
 618                  &spr_read_ctr, &spr_write_ctr,
 619                  &spr_read_ctr, &spr_write_ctr,
 620                  0x00000000);
 621     /* Interrupt processing */
 622     spr_register(env, SPR_SRR0, "SRR0",
 623                  SPR_NOACCESS, SPR_NOACCESS,
 624                  &spr_read_generic, &spr_write_generic,
 625                  0x00000000);
 626     spr_register(env, SPR_SRR1, "SRR1",
 627                  SPR_NOACCESS, SPR_NOACCESS,
 628                  &spr_read_generic, &spr_write_generic,
 629                  0x00000000);
 630     /* Processor control */
 631     spr_register(env, SPR_SPRG0, "SPRG0",
 632                  SPR_NOACCESS, SPR_NOACCESS,
 633                  &spr_read_generic, &spr_write_generic,
 634                  0x00000000);
 635     spr_register(env, SPR_SPRG1, "SPRG1",
 636                  SPR_NOACCESS, SPR_NOACCESS,
 637                  &spr_read_generic, &spr_write_generic,
 638                  0x00000000);
 639     spr_register(env, SPR_SPRG2, "SPRG2",
 640                  SPR_NOACCESS, SPR_NOACCESS,
 641                  &spr_read_generic, &spr_write_generic,
 642                  0x00000000);
 643     spr_register(env, SPR_SPRG3, "SPRG3",
 644                  SPR_NOACCESS, SPR_NOACCESS,
 645                  &spr_read_generic, &spr_write_generic,
 646                  0x00000000);
 647 }
 648
 649 /* SPR common to all non-embedded PowerPC, including 601 */
 650 static void gen_spr_ne_601 (CPUPPCState *env)
 651 {
 652     /* Exception processing */
 653     spr_register(env, SPR_DSISR, "DSISR",
 654                  SPR_NOACCESS, SPR_NOACCESS,
 655                  &spr_read_generic, &spr_write_generic,
 656                  0x00000000);
 657     spr_register(env, SPR_DAR, "DAR",
 658                  SPR_NOACCESS, SPR_NOACCESS,
 659                  &spr_read_generic, &spr_write_generic,
 660                  0x00000000);
 661     /* Timer */
 662     spr_register(env, SPR_DECR, "DECR",
 663                  SPR_NOACCESS, SPR_NOACCESS,
 664                  &spr_read_decr, &spr_write_decr,
 665                  0x00000000);
 666     /* Memory management */
 667     spr_register(env, SPR_SDR1, "SDR1",
 668                  SPR_NOACCESS, SPR_NOACCESS,
 669                  &spr_read_generic, &spr_write_sdr1,
 670                  0x00000000);
 671 }
 672
 673 /* BATs 0-3 */
 674 static void gen_low_BATs (CPUPPCState *env)
 675 {
 676 #if !defined(CONFIG_USER_ONLY)
 677     spr_register(env, SPR_IBAT0U, "IBAT0U",
 678                  SPR_NOACCESS, SPR_NOACCESS,
 679                  &spr_read_ibat, &spr_write_ibatu,
 680                  0x00000000);
 681     spr_register(env, SPR_IBAT0L, "IBAT0L",
 682                  SPR_NOACCESS, SPR_NOACCESS,
 683                  &spr_read_ibat, &spr_write_ibatl,
 684                  0x00000000);
 685     spr_register(env, SPR_IBAT1U, "IBAT1U",
 686                  SPR_NOACCESS, SPR_NOACCESS,
 687                  &spr_read_ibat, &spr_write_ibatu,
 688                  0x00000000);
 689     spr_register(env, SPR_IBAT1L, "IBAT1L",
 690                  SPR_NOACCESS, SPR_NOACCESS,
 691                  &spr_read_ibat, &spr_write_ibatl,
 692                  0x00000000);
 693     spr_register(env, SPR_IBAT2U, "IBAT2U",
 694                  SPR_NOACCESS, SPR_NOACCESS,
 695                  &spr_read_ibat, &spr_write_ibatu,
 696                  0x00000000);
 697     spr_register(env, SPR_IBAT2L, "IBAT2L",
 698                  SPR_NOACCESS, SPR_NOACCESS,
 699                  &spr_read_ibat, &spr_write_ibatl,
 700                  0x00000000);
 701     spr_register(env, SPR_IBAT3U, "IBAT3U",
 702                  SPR_NOACCESS, SPR_NOACCESS,
 703                  &spr_read_ibat, &spr_write_ibatu,
 704                  0x00000000);
 705     spr_register(env, SPR_IBAT3L, "IBAT3L",
 706                  SPR_NOACCESS, SPR_NOACCESS,
 707                  &spr_read_ibat, &spr_write_ibatl,
 708                  0x00000000);
 709     spr_register(env, SPR_DBAT0U, "DBAT0U",
 710                  SPR_NOACCESS, SPR_NOACCESS,
 711                  &spr_read_dbat, &spr_write_dbatu,
 712                  0x00000000);
 713     spr_register(env, SPR_DBAT0L, "DBAT0L",
 714                  SPR_NOACCESS, SPR_NOACCESS,
 715                  &spr_read_dbat, &spr_write_dbatl,
 716                  0x00000000);
 717     spr_register(env, SPR_DBAT1U, "DBAT1U",
 718                  SPR_NOACCESS, SPR_NOACCESS,
 719                  &spr_read_dbat, &spr_write_dbatu,
 720                  0x00000000);
 721     spr_register(env, SPR_DBAT1L, "DBAT1L",
 722                  SPR_NOACCESS, SPR_NOACCESS,
 723                  &spr_read_dbat, &spr_write_dbatl,
 724                  0x00000000);
 725     spr_register(env, SPR_DBAT2U, "DBAT2U",
 726                  SPR_NOACCESS, SPR_NOACCESS,
 727                  &spr_read_dbat, &spr_write_dbatu,
 728                  0x00000000);
 729     spr_register(env, SPR_DBAT2L, "DBAT2L",
 730                  SPR_NOACCESS, SPR_NOACCESS,
 731                  &spr_read_dbat, &spr_write_dbatl,
 732                  0x00000000);
 733     spr_register(env, SPR_DBAT3U, "DBAT3U",
 734                  SPR_NOACCESS, SPR_NOACCESS,
 735                  &spr_read_dbat, &spr_write_dbatu,
 736                  0x00000000);
 737     spr_register(env, SPR_DBAT3L, "DBAT3L",
 738                  SPR_NOACCESS, SPR_NOACCESS,
 739                  &spr_read_dbat, &spr_write_dbatl,
 740                  0x00000000);
 741     env->nb_BATs += 4;
 742 #endif
 743 }
 744
 745 /* BATs 4-7 */
 746 static void gen_high_BATs (CPUPPCState *env)
 747 {
 748 #if !defined(CONFIG_USER_ONLY)
 749     spr_register(env, SPR_IBAT4U, "IBAT4U",
 750                  SPR_NOACCESS, SPR_NOACCESS,
 751                  &spr_read_ibat_h, &spr_write_ibatu_h,
 752                  0x00000000);
 753     spr_register(env, SPR_IBAT4L, "IBAT4L",
 754                  SPR_NOACCESS, SPR_NOACCESS,
 755                  &spr_read_ibat_h, &spr_write_ibatl_h,
 756                  0x00000000);
 757     spr_register(env, SPR_IBAT5U, "IBAT5U",
 758                  SPR_NOACCESS, SPR_NOACCESS,
 759                  &spr_read_ibat_h, &spr_write_ibatu_h,
 760                  0x00000000);
 761     spr_register(env, SPR_IBAT5L, "IBAT5L",
 762                  SPR_NOACCESS, SPR_NOACCESS,
 763                  &spr_read_ibat_h, &spr_write_ibatl_h,
 764                  0x00000000);
 765     spr_register(env, SPR_IBAT6U, "IBAT6U",
 766                  SPR_NOACCESS, SPR_NOACCESS,
 767                  &spr_read_ibat_h, &spr_write_ibatu_h,
 768                  0x00000000);
 769     spr_register(env, SPR_IBAT6L, "IBAT6L",
 770                  SPR_NOACCESS, SPR_NOACCESS,
 771                  &spr_read_ibat_h, &spr_write_ibatl_h,
 772                  0x00000000);
 773     spr_register(env, SPR_IBAT7U, "IBAT7U",
 774                  SPR_NOACCESS, SPR_NOACCESS,
 775                  &spr_read_ibat_h, &spr_write_ibatu_h,
 776                  0x00000000);
 777     spr_register(env, SPR_IBAT7L, "IBAT7L",
 778                  SPR_NOACCESS, SPR_NOACCESS,
 779                  &spr_read_ibat_h, &spr_write_ibatl_h,
 780                  0x00000000);
 781     spr_register(env, SPR_DBAT4U, "DBAT4U",
 782                  SPR_NOACCESS, SPR_NOACCESS,
 783                  &spr_read_dbat_h, &spr_write_dbatu_h,
 784                  0x00000000);
 785     spr_register(env, SPR_DBAT4L, "DBAT4L",
 786                  SPR_NOACCESS, SPR_NOACCESS,
 787                  &spr_read_dbat_h, &spr_write_dbatl_h,
 788                  0x00000000);
 789     spr_register(env, SPR_DBAT5U, "DBAT5U",
 790                  SPR_NOACCESS, SPR_NOACCESS,
 791                  &spr_read_dbat_h, &spr_write_dbatu_h,
 792                  0x00000000);
 793     spr_register(env, SPR_DBAT5L, "DBAT5L",
 794                  SPR_NOACCESS, SPR_NOACCESS,
 795                  &spr_read_dbat_h, &spr_write_dbatl_h,
 796                  0x00000000);
 797     spr_register(env, SPR_DBAT6U, "DBAT6U",
 798                  SPR_NOACCESS, SPR_NOACCESS,
 799                  &spr_read_dbat_h, &spr_write_dbatu_h,
 800                  0x00000000);
 801     spr_register(env, SPR_DBAT6L, "DBAT6L",
 802                  SPR_NOACCESS, SPR_NOACCESS,
 803                  &spr_read_dbat_h, &spr_write_dbatl_h,
 804                  0x00000000);
 805     spr_register(env, SPR_DBAT7U, "DBAT7U",
 806                  SPR_NOACCESS, SPR_NOACCESS,
 807                  &spr_read_dbat_h, &spr_write_dbatu_h,
 808                  0x00000000);
 809     spr_register(env, SPR_DBAT7L, "DBAT7L",
 810                  SPR_NOACCESS, SPR_NOACCESS,
 811                  &spr_read_dbat_h, &spr_write_dbatl_h,
 812                  0x00000000);
 813     env->nb_BATs += 4;
 814 #endif
 815 }
 816
 817 /* Generic PowerPC time base */
 818 static void gen_tbl (CPUPPCState *env)
 819 {
 820     spr_register(env, SPR_VTBL,  "TBL",
 821                  &spr_read_tbl, SPR_NOACCESS,
 822                  &spr_read_tbl, SPR_NOACCESS,
 823                  0x00000000);
 824     spr_register(env, SPR_TBL,   "TBL",
 825                  &spr_read_tbl, SPR_NOACCESS,
 826                  &spr_read_tbl, &spr_write_tbl,
 827                  0x00000000);
 828     spr_register(env, SPR_VTBU,  "TBU",
 829                  &spr_read_tbu, SPR_NOACCESS,
 830                  &spr_read_tbu, SPR_NOACCESS,
 831                  0x00000000);
 832     spr_register(env, SPR_TBU,   "TBU",
 833                  &spr_read_tbu, SPR_NOACCESS,
 834                  &spr_read_tbu, &spr_write_tbu,
 835                  0x00000000);
 836 }
 837
 838 /* Softare table search registers */
 839 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
 840 {
 841 #if !defined(CONFIG_USER_ONLY)
 842     env->nb_tlb = nb_tlbs;
 843     env->nb_ways = nb_ways;
 844     env->id_tlbs = 1;
 845     spr_register(env, SPR_DMISS, "DMISS",
 846                  SPR_NOACCESS, SPR_NOACCESS,
 847                  &spr_read_generic, SPR_NOACCESS,
 848                  0x00000000);
 849     spr_register(env, SPR_DCMP, "DCMP",
 850                  SPR_NOACCESS, SPR_NOACCESS,
 851                  &spr_read_generic, SPR_NOACCESS,
 852                  0x00000000);
 853     spr_register(env, SPR_HASH1, "HASH1",
 854                  SPR_NOACCESS, SPR_NOACCESS,
 855                  &spr_read_generic, SPR_NOACCESS,
 856                  0x00000000);
 857     spr_register(env, SPR_HASH2, "HASH2",
 858                  SPR_NOACCESS, SPR_NOACCESS,
 859                  &spr_read_generic, SPR_NOACCESS,
 860                  0x00000000);
 861     spr_register(env, SPR_IMISS, "IMISS",
 862                  SPR_NOACCESS, SPR_NOACCESS,
 863                  &spr_read_generic, SPR_NOACCESS,
 864                  0x00000000);
 865     spr_register(env, SPR_ICMP, "ICMP",
 866                  SPR_NOACCESS, SPR_NOACCESS,
 867                  &spr_read_generic, SPR_NOACCESS,
 868                  0x00000000);
 869     spr_register(env, SPR_RPA, "RPA",
 870                  SPR_NOACCESS, SPR_NOACCESS,
 871                  &spr_read_generic, &spr_write_generic,
 872                  0x00000000);
 873 #endif
 874 }
 875
 876 /* SPR common to MPC755 and G2 */
 877 static void gen_spr_G2_755 (CPUPPCState *env)
 878 {
 879     /* SGPRs */
 880     spr_register(env, SPR_SPRG4, "SPRG4",
 881                  SPR_NOACCESS, SPR_NOACCESS,
 882                  &spr_read_generic, &spr_write_generic,
 883                  0x00000000);
 884     spr_register(env, SPR_SPRG5, "SPRG5",
 885                  SPR_NOACCESS, SPR_NOACCESS,
 886                  &spr_read_generic, &spr_write_generic,
 887                  0x00000000);
 888     spr_register(env, SPR_SPRG6, "SPRG6",
 889                  SPR_NOACCESS, SPR_NOACCESS,
 890                  &spr_read_generic, &spr_write_generic,
 891                  0x00000000);
 892     spr_register(env, SPR_SPRG7, "SPRG7",
 893                  SPR_NOACCESS, SPR_NOACCESS,
 894                  &spr_read_generic, &spr_write_generic,
 895                  0x00000000);
 896 }
 897
 898 /* SPR common to all 7xx PowerPC implementations */
 899 static void gen_spr_7xx (CPUPPCState *env)
 900 {
 901     /* Breakpoints */
 902     /* XXX : not implemented */
 903     spr_register(env, SPR_DABR, "DABR",
 904                  SPR_NOACCESS, SPR_NOACCESS,
 905                  &spr_read_generic, &spr_write_generic,
 906                  0x00000000);
 907     /* XXX : not implemented */
 908     spr_register(env, SPR_IABR, "IABR",
 909                  SPR_NOACCESS, SPR_NOACCESS,
 910                  &spr_read_generic, &spr_write_generic,
 911                  0x00000000);
 912     /* Cache management */
 913     /* XXX : not implemented */
 914     spr_register(env, SPR_ICTC, "ICTC",
 915                  SPR_NOACCESS, SPR_NOACCESS,
 916                  &spr_read_generic, &spr_write_generic,
 917                  0x00000000);
 918     /* Performance monitors */
 919     /* XXX : not implemented */
 920     spr_register(env, SPR_MMCR0, "MMCR0",
 921                  SPR_NOACCESS, SPR_NOACCESS,
 922                  &spr_read_generic, &spr_write_generic,
 923                  0x00000000);
 924     /* XXX : not implemented */
 925     spr_register(env, SPR_MMCR1, "MMCR1",
 926                  SPR_NOACCESS, SPR_NOACCESS,
 927                  &spr_read_generic, &spr_write_generic,
 928                  0x00000000);
 929     /* XXX : not implemented */
 930     spr_register(env, SPR_PMC1, "PMC1",
 931                  SPR_NOACCESS, SPR_NOACCESS,
 932                  &spr_read_generic, &spr_write_generic,
 933                  0x00000000);
 934     /* XXX : not implemented */
 935     spr_register(env, SPR_PMC2, "PMC2",
 936                  SPR_NOACCESS, SPR_NOACCESS,
 937                  &spr_read_generic, &spr_write_generic,
 938                  0x00000000);
 939     /* XXX : not implemented */
 940     spr_register(env, SPR_PMC3, "PMC3",
 941                  SPR_NOACCESS, SPR_NOACCESS,
 942                  &spr_read_generic, &spr_write_generic,
 943                  0x00000000);
 944     /* XXX : not implemented */
 945     spr_register(env, SPR_PMC4, "PMC4",
 946                  SPR_NOACCESS, SPR_NOACCESS,
 947                  &spr_read_generic, &spr_write_generic,
 948                  0x00000000);
 949     /* XXX : not implemented */
 950     spr_register(env, SPR_SIAR, "SIAR",
 951                  SPR_NOACCESS, SPR_NOACCESS,
 952                  &spr_read_generic, SPR_NOACCESS,
 953                  0x00000000);
 954     /* XXX : not implemented */
 955     spr_register(env, SPR_UMMCR0, "UMMCR0",
 956                  &spr_read_ureg, SPR_NOACCESS,
 957                  &spr_read_ureg, SPR_NOACCESS,
 958                  0x00000000);
 959     /* XXX : not implemented */
 960     spr_register(env, SPR_UMMCR1, "UMMCR1",
 961                  &spr_read_ureg, SPR_NOACCESS,
 962                  &spr_read_ureg, SPR_NOACCESS,
 963                  0x00000000);
 964     /* XXX : not implemented */
 965     spr_register(env, SPR_UPMC1, "UPMC1",
 966                  &spr_read_ureg, SPR_NOACCESS,
 967                  &spr_read_ureg, SPR_NOACCESS,
 968                  0x00000000);
 969     /* XXX : not implemented */
 970     spr_register(env, SPR_UPMC2, "UPMC2",
 971                  &spr_read_ureg, SPR_NOACCESS,
 972                  &spr_read_ureg, SPR_NOACCESS,
 973                  0x00000000);
 974     /* XXX : not implemented */
 975     spr_register(env, SPR_UPMC3, "UPMC3",
 976                  &spr_read_ureg, SPR_NOACCESS,
 977                  &spr_read_ureg, SPR_NOACCESS,
 978                  0x00000000);
 979     /* XXX : not implemented */
 980     spr_register(env, SPR_UPMC4, "UPMC4",
 981                  &spr_read_ureg, SPR_NOACCESS,
 982                  &spr_read_ureg, SPR_NOACCESS,
 983                  0x00000000);
 984     /* XXX : not implemented */
 985     spr_register(env, SPR_USIAR, "USIAR",
 986                  &spr_read_ureg, SPR_NOACCESS,
 987                  &spr_read_ureg, SPR_NOACCESS,
 988                  0x00000000);
 989     /* External access control */
 990     /* XXX : not implemented */
 991     spr_register(env, SPR_EAR, "EAR",
 992                  SPR_NOACCESS, SPR_NOACCESS,
 993                  &spr_read_generic, &spr_write_generic,
 994                  0x00000000);
 995 }
 996
 997 static void gen_spr_thrm (CPUPPCState *env)
 998 {
 999     /* Thermal management */
1000     /* XXX : not implemented */
1001     spr_register(env, SPR_THRM1, "THRM1",
1002                  SPR_NOACCESS, SPR_NOACCESS,
1003                  &spr_read_generic, &spr_write_generic,
1004                  0x00000000);
1005     /* XXX : not implemented */
1006     spr_register(env, SPR_THRM2, "THRM2",
1007                  SPR_NOACCESS, SPR_NOACCESS,
1008                  &spr_read_generic, &spr_write_generic,
1009                  0x00000000);
1010     /* XXX : not implemented */
1011     spr_register(env, SPR_THRM3, "THRM3",
1012                  SPR_NOACCESS, SPR_NOACCESS,
1013                  &spr_read_generic, &spr_write_generic,
1014                  0x00000000);
1015 }
1016
1017 /* SPR specific to PowerPC 604 implementation */
1018 static void gen_spr_604 (CPUPPCState *env)
1019 {
1020     /* Processor identification */
1021     spr_register(env, SPR_PIR, "PIR",
1022                  SPR_NOACCESS, SPR_NOACCESS,
1023                  &spr_read_generic, &spr_write_pir,
1024                  0x00000000);
1025     /* Breakpoints */
1026     /* XXX : not implemented */
1027     spr_register(env, SPR_IABR, "IABR",
1028                  SPR_NOACCESS, SPR_NOACCESS,
1029                  &spr_read_generic, &spr_write_generic,
1030                  0x00000000);
1031     /* XXX : not implemented */
1032     spr_register(env, SPR_DABR, "DABR",
1033                  SPR_NOACCESS, SPR_NOACCESS,
1034                  &spr_read_generic, &spr_write_generic,
1035                  0x00000000);
1036     /* Performance counters */
1037     /* XXX : not implemented */
1038     spr_register(env, SPR_MMCR0, "MMCR0",
1039                  SPR_NOACCESS, SPR_NOACCESS,
1040                  &spr_read_generic, &spr_write_generic,
1041                  0x00000000);
1042     /* XXX : not implemented */
1043     spr_register(env, SPR_PMC1, "PMC1",
1044                  SPR_NOACCESS, SPR_NOACCESS,
1045                  &spr_read_generic, &spr_write_generic,
1046                  0x00000000);
1047     /* XXX : not implemented */
1048     spr_register(env, SPR_PMC2, "PMC2",
1049                  SPR_NOACCESS, SPR_NOACCESS,
1050                  &spr_read_generic, &spr_write_generic,
1051                  0x00000000);
1052     /* XXX : not implemented */
1053     spr_register(env, SPR_SIAR, "SIAR",
1054                  SPR_NOACCESS, SPR_NOACCESS,
1055                  &spr_read_generic, SPR_NOACCESS,
1056                  0x00000000);
1057     /* XXX : not implemented */
1058     spr_register(env, SPR_SDA, "SDA",
1059                  SPR_NOACCESS, SPR_NOACCESS,
1060                  &spr_read_generic, SPR_NOACCESS,
1061                  0x00000000);
1062     /* External access control */
1063     /* XXX : not implemented */
1064     spr_register(env, SPR_EAR, "EAR",
1065                  SPR_NOACCESS, SPR_NOACCESS,
1066                  &spr_read_generic, &spr_write_generic,
1067                  0x00000000);
1068 }
1069
1070 /* SPR specific to PowerPC 603 implementation */
1071 static void gen_spr_603 (CPUPPCState *env)
1072 {
1073     /* External access control */
1074     /* XXX : not implemented */
1075     spr_register(env, SPR_EAR, "EAR",
1076                  SPR_NOACCESS, SPR_NOACCESS,
1077                  &spr_read_generic, &spr_write_generic,
1078                  0x00000000);
1079 }
1080
1081 /* SPR specific to PowerPC G2 implementation */
1082 static void gen_spr_G2 (CPUPPCState *env)
1083 {
1084     /* Memory base address */
1085     /* MBAR */
1086     /* XXX : not implemented */
1087     spr_register(env, SPR_MBAR, "MBAR",
1088                  SPR_NOACCESS, SPR_NOACCESS,
1089                  &spr_read_generic, &spr_write_generic,
1090                  0x00000000);
1091     /* Exception processing */
1092     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1093                  SPR_NOACCESS, SPR_NOACCESS,
1094                  &spr_read_generic, &spr_write_generic,
1095                  0x00000000);
1096     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1097                  SPR_NOACCESS, SPR_NOACCESS,
1098                  &spr_read_generic, &spr_write_generic,
1099                  0x00000000);
1100     /* Breakpoints */
1101     /* XXX : not implemented */
1102     spr_register(env, SPR_DABR, "DABR",
1103                  SPR_NOACCESS, SPR_NOACCESS,
1104                  &spr_read_generic, &spr_write_generic,
1105                  0x00000000);
1106     /* XXX : not implemented */
1107     spr_register(env, SPR_DABR2, "DABR2",
1108                  SPR_NOACCESS, SPR_NOACCESS,
1109                  &spr_read_generic, &spr_write_generic,
1110                  0x00000000);
1111     /* XXX : not implemented */
1112     spr_register(env, SPR_IABR, "IABR",
1113                  SPR_NOACCESS, SPR_NOACCESS,
1114                  &spr_read_generic, &spr_write_generic,
1115                  0x00000000);
1116     /* XXX : not implemented */
1117     spr_register(env, SPR_IABR2, "IABR2",
1118                  SPR_NOACCESS, SPR_NOACCESS,
1119                  &spr_read_generic, &spr_write_generic,
1120                  0x00000000);
1121     /* XXX : not implemented */
1122     spr_register(env, SPR_IBCR, "IBCR",
1123                  SPR_NOACCESS, SPR_NOACCESS,
1124                  &spr_read_generic, &spr_write_generic,
1125                  0x00000000);
1126     /* XXX : not implemented */
1127     spr_register(env, SPR_DBCR, "DBCR",
1128                  SPR_NOACCESS, SPR_NOACCESS,
1129                  &spr_read_generic, &spr_write_generic,
1130                  0x00000000);
1131 }
1132
1133 /* SPR specific to PowerPC 602 implementation */
1134 static void gen_spr_602 (CPUPPCState *env)
1135 {
1136     /* ESA registers */
1137     /* XXX : not implemented */
1138     spr_register(env, SPR_SER, "SER",
1139                  SPR_NOACCESS, SPR_NOACCESS,
1140                  &spr_read_generic, &spr_write_generic,
1141                  0x00000000);
1142     /* XXX : not implemented */
1143     spr_register(env, SPR_SEBR, "SEBR",
1144                  SPR_NOACCESS, SPR_NOACCESS,
1145                  &spr_read_generic, &spr_write_generic,
1146                  0x00000000);
1147     /* XXX : not implemented */
1148     spr_register(env, SPR_ESASRR, "ESASRR",
1149                  SPR_NOACCESS, SPR_NOACCESS,
1150                  &spr_read_generic, &spr_write_generic,
1151                  0x00000000);
1152     /* Floating point status */
1153     /* XXX : not implemented */
1154     spr_register(env, SPR_SP, "SP",
1155                  SPR_NOACCESS, SPR_NOACCESS,
1156                  &spr_read_generic, &spr_write_generic,
1157                  0x00000000);
1158     /* XXX : not implemented */
1159     spr_register(env, SPR_LT, "LT",
1160                  SPR_NOACCESS, SPR_NOACCESS,
1161                  &spr_read_generic, &spr_write_generic,
1162                  0x00000000);
1163     /* Watchdog timer */
1164     /* XXX : not implemented */
1165     spr_register(env, SPR_TCR, "TCR",
1166                  SPR_NOACCESS, SPR_NOACCESS,
1167                  &spr_read_generic, &spr_write_generic,
1168                  0x00000000);
1169     /* Interrupt base */
1170     spr_register(env, SPR_IBR, "IBR",
1171                  SPR_NOACCESS, SPR_NOACCESS,
1172                  &spr_read_generic, &spr_write_generic,
1173                  0x00000000);
1174     /* XXX : not implemented */
1175     spr_register(env, SPR_IABR, "IABR",
1176                  SPR_NOACCESS, SPR_NOACCESS,
1177                  &spr_read_generic, &spr_write_generic,
1178                  0x00000000);
1179 }
1180
1181 /* SPR specific to PowerPC 601 implementation */
1182 static void gen_spr_601 (CPUPPCState *env)
1183 {
1184     /* Multiplication/division register */
1185     /* MQ */
1186     spr_register(env, SPR_MQ, "MQ",
1187                  &spr_read_generic, &spr_write_generic,
1188                  &spr_read_generic, &spr_write_generic,
1189                  0x00000000);
1190     /* RTC registers */
1191     spr_register(env, SPR_601_RTCU, "RTCU",
1192                  SPR_NOACCESS, SPR_NOACCESS,
1193                  SPR_NOACCESS, &spr_write_601_rtcu,
1194                  0x00000000);
1195     spr_register(env, SPR_601_VRTCU, "RTCU",
1196                  &spr_read_601_rtcu, SPR_NOACCESS,
1197                  &spr_read_601_rtcu, SPR_NOACCESS,
1198                  0x00000000);
1199     spr_register(env, SPR_601_RTCL, "RTCL",
1200                  SPR_NOACCESS, SPR_NOACCESS,
1201                  SPR_NOACCESS, &spr_write_601_rtcl,
1202                  0x00000000);
1203     spr_register(env, SPR_601_VRTCL, "RTCL",
1204                  &spr_read_601_rtcl, SPR_NOACCESS,
1205                  &spr_read_601_rtcl, SPR_NOACCESS,
1206                  0x00000000);
1207     /* Timer */
1208 #if 0 /* ? */
1209     spr_register(env, SPR_601_UDECR, "UDECR",
1210                  &spr_read_decr, SPR_NOACCESS,
1211                  &spr_read_decr, SPR_NOACCESS,
1212                  0x00000000);
1213 #endif
1214     /* External access control */
1215     /* XXX : not implemented */
1216     spr_register(env, SPR_EAR, "EAR",
1217                  SPR_NOACCESS, SPR_NOACCESS,
1218                  &spr_read_generic, &spr_write_generic,
1219                  0x00000000);
1220     /* Memory management */
1221 #if !defined(CONFIG_USER_ONLY)
1222     spr_register(env, SPR_IBAT0U, "IBAT0U",
1223                  SPR_NOACCESS, SPR_NOACCESS,
1224                  &spr_read_601_ubat, &spr_write_601_ubatu,
1225                  0x00000000);
1226     spr_register(env, SPR_IBAT0L, "IBAT0L",
1227                  SPR_NOACCESS, SPR_NOACCESS,
1228                  &spr_read_601_ubat, &spr_write_601_ubatl,
1229                  0x00000000);
1230     spr_register(env, SPR_IBAT1U, "IBAT1U",
1231                  SPR_NOACCESS, SPR_NOACCESS,
1232                  &spr_read_601_ubat, &spr_write_601_ubatu,
1233                  0x00000000);
1234     spr_register(env, SPR_IBAT1L, "IBAT1L",
1235                  SPR_NOACCESS, SPR_NOACCESS,
1236                  &spr_read_601_ubat, &spr_write_601_ubatl,
1237                  0x00000000);
1238     spr_register(env, SPR_IBAT2U, "IBAT2U",
1239                  SPR_NOACCESS, SPR_NOACCESS,
1240                  &spr_read_601_ubat, &spr_write_601_ubatu,
1241                  0x00000000);
1242     spr_register(env, SPR_IBAT2L, "IBAT2L",
1243                  SPR_NOACCESS, SPR_NOACCESS,
1244                  &spr_read_601_ubat, &spr_write_601_ubatl,
1245                  0x00000000);
1246     spr_register(env, SPR_IBAT3U, "IBAT3U",
1247                  SPR_NOACCESS, SPR_NOACCESS,
1248                  &spr_read_601_ubat, &spr_write_601_ubatu,
1249                  0x00000000);
1250     spr_register(env, SPR_IBAT3L, "IBAT3L",
1251                  SPR_NOACCESS, SPR_NOACCESS,
1252                  &spr_read_601_ubat, &spr_write_601_ubatl,
1253                  0x00000000);
1254     env->nb_BATs = 4;
1255 #endif
1256 }
1257
1258 static void gen_spr_74xx (CPUPPCState *env)
1259 {
1260     /* Processor identification */
1261     spr_register(env, SPR_PIR, "PIR",
1262                  SPR_NOACCESS, SPR_NOACCESS,
1263                  &spr_read_generic, &spr_write_pir,
1264                  0x00000000);
1265     /* XXX : not implemented */
1266     spr_register(env, SPR_MMCR2, "MMCR2",
1267                  SPR_NOACCESS, SPR_NOACCESS,
1268                  &spr_read_generic, &spr_write_generic,
1269                  0x00000000);
1270     /* XXX : not implemented */
1271     spr_register(env, SPR_UMMCR2, "UMMCR2",
1272                  &spr_read_ureg, SPR_NOACCESS,
1273                  &spr_read_ureg, SPR_NOACCESS,
1274                  0x00000000);
1275     /* XXX: not implemented */
1276     spr_register(env, SPR_BAMR, "BAMR",
1277                  SPR_NOACCESS, SPR_NOACCESS,
1278                  &spr_read_generic, &spr_write_generic,
1279                  0x00000000);
1280     /* XXX : not implemented */
1281     spr_register(env, SPR_MSSCR0, "MSSCR0",
1282                  SPR_NOACCESS, SPR_NOACCESS,
1283                  &spr_read_generic, &spr_write_generic,
1284                  0x00000000);
1285     /* Hardware implementation registers */
1286     /* XXX : not implemented */
1287     spr_register(env, SPR_HID0, "HID0",
1288                  SPR_NOACCESS, SPR_NOACCESS,
1289                  &spr_read_generic, &spr_write_generic,
1290                  0x00000000);
1291     /* XXX : not implemented */
1292     spr_register(env, SPR_HID1, "HID1",
1293                  SPR_NOACCESS, SPR_NOACCESS,
1294                  &spr_read_generic, &spr_write_generic,
1295                  0x00000000);
1296     /* Altivec */
1297     spr_register(env, SPR_VRSAVE, "VRSAVE",
1298                  &spr_read_generic, &spr_write_generic,
1299                  &spr_read_generic, &spr_write_generic,
1300                  0x00000000);
1301     /* XXX : not implemented */
1302     spr_register(env, SPR_L2CR, "L2CR",
1303                  SPR_NOACCESS, SPR_NOACCESS,
1304                  &spr_read_generic, &spr_write_generic,
1305                  0x00000000);
1306     /* Not strictly an SPR */
1307     vscr_init(env, 0x00010000);
1308 }
1309
1310 static void gen_l3_ctrl (CPUPPCState *env)
1311 {
1312     /* L3CR */
1313     /* XXX : not implemented */
1314     spr_register(env, SPR_L3CR, "L3CR",
1315                  SPR_NOACCESS, SPR_NOACCESS,
1316                  &spr_read_generic, &spr_write_generic,
1317                  0x00000000);
1318     /* L3ITCR0 */
1319     /* XXX : not implemented */
1320     spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1321                  SPR_NOACCESS, SPR_NOACCESS,
1322                  &spr_read_generic, &spr_write_generic,
1323                  0x00000000);
1324     /* L3PM */
1325     /* XXX : not implemented */
1326     spr_register(env, SPR_L3PM, "L3PM",
1327                  SPR_NOACCESS, SPR_NOACCESS,
1328                  &spr_read_generic, &spr_write_generic,
1329                  0x00000000);
1330 }
1331
1332 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1333 {
1334 #if !defined(CONFIG_USER_ONLY)
1335     env->nb_tlb = nb_tlbs;
1336     env->nb_ways = nb_ways;
1337     env->id_tlbs = 1;
1338     /* XXX : not implemented */
1339     spr_register(env, SPR_PTEHI, "PTEHI",
1340                  SPR_NOACCESS, SPR_NOACCESS,
1341                  &spr_read_generic, &spr_write_generic,
1342                  0x00000000);
1343     /* XXX : not implemented */
1344     spr_register(env, SPR_PTELO, "PTELO",
1345                  SPR_NOACCESS, SPR_NOACCESS,
1346                  &spr_read_generic, &spr_write_generic,
1347                  0x00000000);
1348     /* XXX : not implemented */
1349     spr_register(env, SPR_TLBMISS, "TLBMISS",
1350                  SPR_NOACCESS, SPR_NOACCESS,
1351                  &spr_read_generic, &spr_write_generic,
1352                  0x00000000);
1353 #endif
1354 }
1355
1356 static void gen_spr_usprgh (CPUPPCState *env)
1357 {
1358     spr_register(env, SPR_USPRG4, "USPRG4",
1359                  &spr_read_ureg, SPR_NOACCESS,
1360                  &spr_read_ureg, SPR_NOACCESS,
1361                  0x00000000);
1362     spr_register(env, SPR_USPRG5, "USPRG5",
1363                  &spr_read_ureg, SPR_NOACCESS,
1364                  &spr_read_ureg, SPR_NOACCESS,
1365                  0x00000000);
1366     spr_register(env, SPR_USPRG6, "USPRG6",
1367                  &spr_read_ureg, SPR_NOACCESS,
1368                  &spr_read_ureg, SPR_NOACCESS,
1369                  0x00000000);
1370     spr_register(env, SPR_USPRG7, "USPRG7",
1371                  &spr_read_ureg, SPR_NOACCESS,
1372                  &spr_read_ureg, SPR_NOACCESS,
1373                  0x00000000);
1374 }
1375
1376 /* PowerPC BookE SPR */
1377 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1378 {
1379     const char *ivor_names[64] = {
1380         "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1381         "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1382         "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1383         "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1384         "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1385         "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1386         "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1387         "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1388         "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1389         "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1390         "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1391         "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1392         "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1393         "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1394         "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1395         "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1396     };
1397 #define SPR_BOOKE_IVORxx (-1)
1398     int ivor_sprn[64] = {
1399         SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1400         SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1401         SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1402         SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1403         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1404         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1405         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1406         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1407         SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1408         SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1409         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1410         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1411         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1412         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1413         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1414         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1415     };
1416     int i;
1417
1418     /* Interrupt processing */
1419     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1420                  SPR_NOACCESS, SPR_NOACCESS,
1421                  &spr_read_generic, &spr_write_generic,
1422                  0x00000000);
1423     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1424                  SPR_NOACCESS, SPR_NOACCESS,
1425                  &spr_read_generic, &spr_write_generic,
1426                  0x00000000);
1427     /* Debug */
1428     /* XXX : not implemented */
1429     spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1430                  SPR_NOACCESS, SPR_NOACCESS,
1431                  &spr_read_generic, &spr_write_generic,
1432                  0x00000000);
1433     /* XXX : not implemented */
1434     spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1435                  SPR_NOACCESS, SPR_NOACCESS,
1436                  &spr_read_generic, &spr_write_generic,
1437                  0x00000000);
1438     /* XXX : not implemented */
1439     spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1440                  SPR_NOACCESS, SPR_NOACCESS,
1441                  &spr_read_generic, &spr_write_generic,
1442                  0x00000000);
1443     /* XXX : not implemented */
1444     spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1445                  SPR_NOACCESS, SPR_NOACCESS,
1446                  &spr_read_generic, &spr_write_generic,
1447                  0x00000000);
1448     /* XXX : not implemented */
1449     spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1450                  SPR_NOACCESS, SPR_NOACCESS,
1451                  &spr_read_generic, &spr_write_generic,
1452                  0x00000000);
1453     /* XXX : not implemented */
1454     spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1455                  SPR_NOACCESS, SPR_NOACCESS,
1456                  &spr_read_generic, &spr_write_generic,
1457                  0x00000000);
1458     /* XXX : not implemented */
1459     spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1460                  SPR_NOACCESS, SPR_NOACCESS,
1461                  &spr_read_generic, &spr_write_generic,
1462                  0x00000000);
1463     /* XXX : not implemented */
1464     spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1465                  SPR_NOACCESS, SPR_NOACCESS,
1466                  &spr_read_generic, &spr_write_clear,
1467                  0x00000000);
1468     spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1469                  SPR_NOACCESS, SPR_NOACCESS,
1470                  &spr_read_generic, &spr_write_generic,
1471                  0x00000000);
1472     spr_register(env, SPR_BOOKE_ESR, "ESR",
1473                  SPR_NOACCESS, SPR_NOACCESS,
1474                  &spr_read_generic, &spr_write_generic,
1475                  0x00000000);
1476     spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1477                  SPR_NOACCESS, SPR_NOACCESS,
1478                  &spr_read_generic, &spr_write_excp_prefix,
1479                  0x00000000);
1480     /* Exception vectors */
1481     for (i = 0; i < 64; i++) {
1482         if (ivor_mask & (1ULL << i)) {
1483             if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1484                 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1485                 exit(1);
1486             }
1487             spr_register(env, ivor_sprn[i], ivor_names[i],
1488                          SPR_NOACCESS, SPR_NOACCESS,
1489                          &spr_read_generic, &spr_write_excp_vector,
1490                          0x00000000);
1491         }
1492     }
1493     spr_register(env, SPR_BOOKE_PID, "PID",
1494                  SPR_NOACCESS, SPR_NOACCESS,
1495                  &spr_read_generic, &spr_write_generic,
1496                  0x00000000);
1497     spr_register(env, SPR_BOOKE_TCR, "TCR",
1498                  SPR_NOACCESS, SPR_NOACCESS,
1499                  &spr_read_generic, &spr_write_booke_tcr,
1500                  0x00000000);
1501     spr_register(env, SPR_BOOKE_TSR, "TSR",
1502                  SPR_NOACCESS, SPR_NOACCESS,
1503                  &spr_read_generic, &spr_write_booke_tsr,
1504                  0x00000000);
1505     /* Timer */
1506     spr_register(env, SPR_DECR, "DECR",
1507                  SPR_NOACCESS, SPR_NOACCESS,
1508                  &spr_read_decr, &spr_write_decr,
1509                  0x00000000);
1510     spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1511                  SPR_NOACCESS, SPR_NOACCESS,
1512                  SPR_NOACCESS, &spr_write_generic,
1513                  0x00000000);
1514     /* SPRGs */
1515     spr_register(env, SPR_USPRG0, "USPRG0",
1516                  &spr_read_generic, &spr_write_generic,
1517                  &spr_read_generic, &spr_write_generic,
1518                  0x00000000);
1519     spr_register(env, SPR_SPRG4, "SPRG4",
1520                  SPR_NOACCESS, SPR_NOACCESS,
1521                  &spr_read_generic, &spr_write_generic,
1522                  0x00000000);
1523     spr_register(env, SPR_SPRG5, "SPRG5",
1524                  SPR_NOACCESS, SPR_NOACCESS,
1525                  &spr_read_generic, &spr_write_generic,
1526                  0x00000000);
1527     spr_register(env, SPR_SPRG6, "SPRG6",
1528                  SPR_NOACCESS, SPR_NOACCESS,
1529                  &spr_read_generic, &spr_write_generic,
1530                  0x00000000);
1531     spr_register(env, SPR_SPRG7, "SPRG7",
1532                  SPR_NOACCESS, SPR_NOACCESS,
1533                  &spr_read_generic, &spr_write_generic,
1534                  0x00000000);
1535 }
1536
1537 /* FSL storage control registers */
1538 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1539 {
1540 #if !defined(CONFIG_USER_ONLY)
1541     const char *mas_names[8] = {
1542         "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1543     };
1544     int mas_sprn[8] = {
1545         SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1546         SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1547     };
1548     int i;
1549
1550     /* TLB assist registers */
1551     /* XXX : not implemented */
1552     for (i = 0; i < 8; i++) {
1553         if (mas_mask & (1 << i)) {
1554             spr_register(env, mas_sprn[i], mas_names[i],
1555                          SPR_NOACCESS, SPR_NOACCESS,
1556                          &spr_read_generic, &spr_write_generic,
1557                          0x00000000);
1558         }
1559     }
1560     if (env->nb_pids > 1) {
1561         /* XXX : not implemented */
1562         spr_register(env, SPR_BOOKE_PID1, "PID1",
1563                      SPR_NOACCESS, SPR_NOACCESS,
1564                      &spr_read_generic, &spr_write_generic,
1565                      0x00000000);
1566     }
1567     if (env->nb_pids > 2) {
1568         /* XXX : not implemented */
1569         spr_register(env, SPR_BOOKE_PID2, "PID2",
1570                      SPR_NOACCESS, SPR_NOACCESS,
1571                      &spr_read_generic, &spr_write_generic,
1572                      0x00000000);
1573     }
1574     /* XXX : not implemented */
1575     spr_register(env, SPR_MMUCFG, "MMUCFG",
1576                  SPR_NOACCESS, SPR_NOACCESS,
1577                  &spr_read_generic, SPR_NOACCESS,
1578                  0x00000000); /* TOFIX */
1579     /* XXX : not implemented */
1580     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1581                  SPR_NOACCESS, SPR_NOACCESS,
1582                  &spr_read_generic, &spr_write_generic,
1583                  0x00000000); /* TOFIX */
1584     switch (env->nb_ways) {
1585     case 4:
1586         /* XXX : not implemented */
1587         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1588                      SPR_NOACCESS, SPR_NOACCESS,
1589                      &spr_read_generic, SPR_NOACCESS,
1590                      0x00000000); /* TOFIX */
1591         /* Fallthru */
1592     case 3:
1593         /* XXX : not implemented */
1594         spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1595                      SPR_NOACCESS, SPR_NOACCESS,
1596                      &spr_read_generic, SPR_NOACCESS,
1597                      0x00000000); /* TOFIX */
1598         /* Fallthru */
1599     case 2:
1600         /* XXX : not implemented */
1601         spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1602                      SPR_NOACCESS, SPR_NOACCESS,
1603                      &spr_read_generic, SPR_NOACCESS,
1604                      0x00000000); /* TOFIX */
1605         /* Fallthru */
1606     case 1:
1607         /* XXX : not implemented */
1608         spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1609                      SPR_NOACCESS, SPR_NOACCESS,
1610                      &spr_read_generic, SPR_NOACCESS,
1611                      0x00000000); /* TOFIX */
1612         /* Fallthru */
1613     case 0:
1614     default:
1615         break;
1616     }
1617 #endif
1618 }
1619
1620 /* SPR specific to PowerPC 440 implementation */
1621 static void gen_spr_440 (CPUPPCState *env)
1622 {
1623     /* Cache control */
1624     /* XXX : not implemented */
1625     spr_register(env, SPR_440_DNV0, "DNV0",
1626                  SPR_NOACCESS, SPR_NOACCESS,
1627                  &spr_read_generic, &spr_write_generic,
1628                  0x00000000);
1629     /* XXX : not implemented */
1630     spr_register(env, SPR_440_DNV1, "DNV1",
1631                  SPR_NOACCESS, SPR_NOACCESS,
1632                  &spr_read_generic, &spr_write_generic,
1633                  0x00000000);
1634     /* XXX : not implemented */
1635     spr_register(env, SPR_440_DNV2, "DNV2",
1636                  SPR_NOACCESS, SPR_NOACCESS,
1637                  &spr_read_generic, &spr_write_generic,
1638                  0x00000000);
1639     /* XXX : not implemented */
1640     spr_register(env, SPR_440_DNV3, "DNV3",
1641                  SPR_NOACCESS, SPR_NOACCESS,
1642                  &spr_read_generic, &spr_write_generic,
1643                  0x00000000);
1644     /* XXX : not implemented */
1645     spr_register(env, SPR_440_DTV0, "DTV0",
1646                  SPR_NOACCESS, SPR_NOACCESS,
1647                  &spr_read_generic, &spr_write_generic,
1648                  0x00000000);
1649     /* XXX : not implemented */
1650     spr_register(env, SPR_440_DTV1, "DTV1",
1651                  SPR_NOACCESS, SPR_NOACCESS,
1652                  &spr_read_generic, &spr_write_generic,
1653                  0x00000000);
1654     /* XXX : not implemented */
1655     spr_register(env, SPR_440_DTV2, "DTV2",
1656                  SPR_NOACCESS, SPR_NOACCESS,
1657                  &spr_read_generic, &spr_write_generic,
1658                  0x00000000);
1659     /* XXX : not implemented */
1660     spr_register(env, SPR_440_DTV3, "DTV3",
1661                  SPR_NOACCESS, SPR_NOACCESS,
1662                  &spr_read_generic, &spr_write_generic,
1663                  0x00000000);
1664     /* XXX : not implemented */
1665     spr_register(env, SPR_440_DVLIM, "DVLIM",
1666                  SPR_NOACCESS, SPR_NOACCESS,
1667                  &spr_read_generic, &spr_write_generic,
1668                  0x00000000);
1669     /* XXX : not implemented */
1670     spr_register(env, SPR_440_INV0, "INV0",
1671                  SPR_NOACCESS, SPR_NOACCESS,
1672                  &spr_read_generic, &spr_write_generic,
1673                  0x00000000);
1674     /* XXX : not implemented */
1675     spr_register(env, SPR_440_INV1, "INV1",
1676                  SPR_NOACCESS, SPR_NOACCESS,
1677                  &spr_read_generic, &spr_write_generic,
1678                  0x00000000);
1679     /* XXX : not implemented */
1680     spr_register(env, SPR_440_INV2, "INV2",
1681                  SPR_NOACCESS, SPR_NOACCESS,
1682                  &spr_read_generic, &spr_write_generic,
1683                  0x00000000);
1684     /* XXX : not implemented */
1685     spr_register(env, SPR_440_INV3, "INV3",
1686                  SPR_NOACCESS, SPR_NOACCESS,
1687                  &spr_read_generic, &spr_write_generic,
1688                  0x00000000);
1689     /* XXX : not implemented */
1690     spr_register(env, SPR_440_ITV0, "ITV0",
1691                  SPR_NOACCESS, SPR_NOACCESS,
1692                  &spr_read_generic, &spr_write_generic,
1693                  0x00000000);
1694     /* XXX : not implemented */
1695     spr_register(env, SPR_440_ITV1, "ITV1",
1696                  SPR_NOACCESS, SPR_NOACCESS,
1697                  &spr_read_generic, &spr_write_generic,
1698                  0x00000000);
1699     /* XXX : not implemented */
1700     spr_register(env, SPR_440_ITV2, "ITV2",
1701                  SPR_NOACCESS, SPR_NOACCESS,
1702                  &spr_read_generic, &spr_write_generic,
1703                  0x00000000);
1704     /* XXX : not implemented */
1705     spr_register(env, SPR_440_ITV3, "ITV3",
1706                  SPR_NOACCESS, SPR_NOACCESS,
1707                  &spr_read_generic, &spr_write_generic,
1708                  0x00000000);
1709     /* XXX : not implemented */
1710     spr_register(env, SPR_440_IVLIM, "IVLIM",
1711                  SPR_NOACCESS, SPR_NOACCESS,
1712                  &spr_read_generic, &spr_write_generic,
1713                  0x00000000);
1714     /* Cache debug */
1715     /* XXX : not implemented */
1716     spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1717                  SPR_NOACCESS, SPR_NOACCESS,
1718                  &spr_read_generic, SPR_NOACCESS,
1719                  0x00000000);
1720     /* XXX : not implemented */
1721     spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1722                  SPR_NOACCESS, SPR_NOACCESS,
1723                  &spr_read_generic, SPR_NOACCESS,
1724                  0x00000000);
1725     /* XXX : not implemented */
1726     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1727                  SPR_NOACCESS, SPR_NOACCESS,
1728                  &spr_read_generic, SPR_NOACCESS,
1729                  0x00000000);
1730     /* XXX : not implemented */
1731     spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1732                  SPR_NOACCESS, SPR_NOACCESS,
1733                  &spr_read_generic, SPR_NOACCESS,
1734                  0x00000000);
1735     /* XXX : not implemented */
1736     spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1737                  SPR_NOACCESS, SPR_NOACCESS,
1738                  &spr_read_generic, SPR_NOACCESS,
1739                  0x00000000);
1740     /* XXX : not implemented */
1741     spr_register(env, SPR_440_DBDR, "DBDR",
1742                  SPR_NOACCESS, SPR_NOACCESS,
1743                  &spr_read_generic, &spr_write_generic,
1744                  0x00000000);
1745     /* Processor control */
1746     spr_register(env, SPR_4xx_CCR0, "CCR0",
1747                  SPR_NOACCESS, SPR_NOACCESS,
1748                  &spr_read_generic, &spr_write_generic,
1749                  0x00000000);
1750     spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1751                  SPR_NOACCESS, SPR_NOACCESS,
1752                  &spr_read_generic, SPR_NOACCESS,
1753                  0x00000000);
1754     /* Storage control */
1755     spr_register(env, SPR_440_MMUCR, "MMUCR",
1756                  SPR_NOACCESS, SPR_NOACCESS,
1757                  &spr_read_generic, &spr_write_generic,
1758                  0x00000000);
1759 }
1760
1761 /* SPR shared between PowerPC 40x implementations */
1762 static void gen_spr_40x (CPUPPCState *env)
1763 {
1764     /* Cache */
1765     /* not emulated, as Qemu do not emulate caches */
1766     spr_register(env, SPR_40x_DCCR, "DCCR",
1767                  SPR_NOACCESS, SPR_NOACCESS,
1768                  &spr_read_generic, &spr_write_generic,
1769                  0x00000000);
1770     /* not emulated, as Qemu do not emulate caches */
1771     spr_register(env, SPR_40x_ICCR, "ICCR",
1772                  SPR_NOACCESS, SPR_NOACCESS,
1773                  &spr_read_generic, &spr_write_generic,
1774                  0x00000000);
1775     /* not emulated, as Qemu do not emulate caches */
1776     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1777                  SPR_NOACCESS, SPR_NOACCESS,
1778                  &spr_read_generic, SPR_NOACCESS,
1779                  0x00000000);
1780     /* Exception */
1781     spr_register(env, SPR_40x_DEAR, "DEAR",
1782                  SPR_NOACCESS, SPR_NOACCESS,
1783                  &spr_read_generic, &spr_write_generic,
1784                  0x00000000);
1785     spr_register(env, SPR_40x_ESR, "ESR",
1786                  SPR_NOACCESS, SPR_NOACCESS,
1787                  &spr_read_generic, &spr_write_generic,
1788                  0x00000000);
1789     spr_register(env, SPR_40x_EVPR, "EVPR",
1790                  SPR_NOACCESS, SPR_NOACCESS,
1791                  &spr_read_generic, &spr_write_excp_prefix,
1792                  0x00000000);
1793     spr_register(env, SPR_40x_SRR2, "SRR2",
1794                  &spr_read_generic, &spr_write_generic,
1795                  &spr_read_generic, &spr_write_generic,
1796                  0x00000000);
1797     spr_register(env, SPR_40x_SRR3, "SRR3",
1798                  &spr_read_generic, &spr_write_generic,
1799                  &spr_read_generic, &spr_write_generic,
1800                  0x00000000);
1801     /* Timers */
1802     spr_register(env, SPR_40x_PIT, "PIT",
1803                  SPR_NOACCESS, SPR_NOACCESS,
1804                  &spr_read_40x_pit, &spr_write_40x_pit,
1805                  0x00000000);
1806     spr_register(env, SPR_40x_TCR, "TCR",
1807                  SPR_NOACCESS, SPR_NOACCESS,
1808                  &spr_read_generic, &spr_write_booke_tcr,
1809                  0x00000000);
1810     spr_register(env, SPR_40x_TSR, "TSR",
1811                  SPR_NOACCESS, SPR_NOACCESS,
1812                  &spr_read_generic, &spr_write_booke_tsr,
1813                  0x00000000);
1814 }
1815
1816 /* SPR specific to PowerPC 405 implementation */
1817 static void gen_spr_405 (CPUPPCState *env)
1818 {
1819     /* MMU */
1820     spr_register(env, SPR_40x_PID, "PID",
1821                  SPR_NOACCESS, SPR_NOACCESS,
1822                  &spr_read_generic, &spr_write_generic,
1823                  0x00000000);
1824     spr_register(env, SPR_4xx_CCR0, "CCR0",
1825                  SPR_NOACCESS, SPR_NOACCESS,
1826                  &spr_read_generic, &spr_write_generic,
1827                  0x00700000);
1828     /* Debug interface */
1829     /* XXX : not implemented */
1830     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1831                  SPR_NOACCESS, SPR_NOACCESS,
1832                  &spr_read_generic, &spr_write_40x_dbcr0,
1833                  0x00000000);
1834     /* XXX : not implemented */
1835     spr_register(env, SPR_405_DBCR1, "DBCR1",
1836                  SPR_NOACCESS, SPR_NOACCESS,
1837                  &spr_read_generic, &spr_write_generic,
1838                  0x00000000);
1839     /* XXX : not implemented */
1840     spr_register(env, SPR_40x_DBSR, "DBSR",
1841                  SPR_NOACCESS, SPR_NOACCESS,
1842                  &spr_read_generic, &spr_write_clear,
1843                  /* Last reset was system reset */
1844                  0x00000300);
1845     /* XXX : not implemented */
1846     spr_register(env, SPR_40x_DAC1, "DAC1",
1847                  SPR_NOACCESS, SPR_NOACCESS,
1848                  &spr_read_generic, &spr_write_generic,
1849                  0x00000000);
1850     spr_register(env, SPR_40x_DAC2, "DAC2",
1851                  SPR_NOACCESS, SPR_NOACCESS,
1852                  &spr_read_generic, &spr_write_generic,
1853                  0x00000000);
1854     /* XXX : not implemented */
1855     spr_register(env, SPR_405_DVC1, "DVC1",
1856                  SPR_NOACCESS, SPR_NOACCESS,
1857                  &spr_read_generic, &spr_write_generic,
1858                  0x00000000);
1859     /* XXX : not implemented */
1860     spr_register(env, SPR_405_DVC2, "DVC2",
1861                  SPR_NOACCESS, SPR_NOACCESS,
1862                  &spr_read_generic, &spr_write_generic,
1863                  0x00000000);
1864     /* XXX : not implemented */
1865     spr_register(env, SPR_40x_IAC1, "IAC1",
1866                  SPR_NOACCESS, SPR_NOACCESS,
1867                  &spr_read_generic, &spr_write_generic,
1868                  0x00000000);
1869     spr_register(env, SPR_40x_IAC2, "IAC2",
1870                  SPR_NOACCESS, SPR_NOACCESS,
1871                  &spr_read_generic, &spr_write_generic,
1872                  0x00000000);
1873     /* XXX : not implemented */
1874     spr_register(env, SPR_405_IAC3, "IAC3",
1875                  SPR_NOACCESS, SPR_NOACCESS,
1876                  &spr_read_generic, &spr_write_generic,
1877                  0x00000000);
1878     /* XXX : not implemented */
1879     spr_register(env, SPR_405_IAC4, "IAC4",
1880                  SPR_NOACCESS, SPR_NOACCESS,
1881                  &spr_read_generic, &spr_write_generic,
1882                  0x00000000);
1883     /* Storage control */
1884     /* XXX: TODO: not implemented */
1885     spr_register(env, SPR_405_SLER, "SLER",
1886                  SPR_NOACCESS, SPR_NOACCESS,
1887                  &spr_read_generic, &spr_write_40x_sler,
1888                  0x00000000);
1889     spr_register(env, SPR_40x_ZPR, "ZPR",
1890                  SPR_NOACCESS, SPR_NOACCESS,
1891                  &spr_read_generic, &spr_write_generic,
1892                  0x00000000);
1893     /* XXX : not implemented */
1894     spr_register(env, SPR_405_SU0R, "SU0R",
1895                  SPR_NOACCESS, SPR_NOACCESS,
1896                  &spr_read_generic, &spr_write_generic,
1897                  0x00000000);
1898     /* SPRG */
1899     spr_register(env, SPR_USPRG0, "USPRG0",
1900                  &spr_read_ureg, SPR_NOACCESS,
1901                  &spr_read_ureg, SPR_NOACCESS,
1902                  0x00000000);
1903     spr_register(env, SPR_SPRG4, "SPRG4",
1904                  SPR_NOACCESS, SPR_NOACCESS,
1905                  &spr_read_generic, &spr_write_generic,
1906                  0x00000000);
1907     spr_register(env, SPR_SPRG5, "SPRG5",
1908                  SPR_NOACCESS, SPR_NOACCESS,
1909                  spr_read_generic, &spr_write_generic,
1910                  0x00000000);
1911     spr_register(env, SPR_SPRG6, "SPRG6",
1912                  SPR_NOACCESS, SPR_NOACCESS,
1913                  spr_read_generic, &spr_write_generic,
1914                  0x00000000);
1915     spr_register(env, SPR_SPRG7, "SPRG7",
1916                  SPR_NOACCESS, SPR_NOACCESS,
1917                  spr_read_generic, &spr_write_generic,
1918                  0x00000000);
1919     gen_spr_usprgh(env);
1920 }
1921
1922 /* SPR shared between PowerPC 401 & 403 implementations */
1923 static void gen_spr_401_403 (CPUPPCState *env)
1924 {
1925     /* Time base */
1926     spr_register(env, SPR_403_VTBL,  "TBL",
1927                  &spr_read_tbl, SPR_NOACCESS,
1928                  &spr_read_tbl, SPR_NOACCESS,
1929                  0x00000000);
1930     spr_register(env, SPR_403_TBL,   "TBL",
1931                  SPR_NOACCESS, SPR_NOACCESS,
1932                  SPR_NOACCESS, &spr_write_tbl,
1933                  0x00000000);
1934     spr_register(env, SPR_403_VTBU,  "TBU",
1935                  &spr_read_tbu, SPR_NOACCESS,
1936                  &spr_read_tbu, SPR_NOACCESS,
1937                  0x00000000);
1938     spr_register(env, SPR_403_TBU,   "TBU",
1939                  SPR_NOACCESS, SPR_NOACCESS,
1940                  SPR_NOACCESS, &spr_write_tbu,
1941                  0x00000000);
1942     /* Debug */
1943     /* not emulated, as Qemu do not emulate caches */
1944     spr_register(env, SPR_403_CDBCR, "CDBCR",
1945                  SPR_NOACCESS, SPR_NOACCESS,
1946                  &spr_read_generic, &spr_write_generic,
1947                  0x00000000);
1948 }
1949
1950 /* SPR specific to PowerPC 401 implementation */
1951 static void gen_spr_401 (CPUPPCState *env)
1952 {
1953     /* Debug interface */
1954     /* XXX : not implemented */
1955     spr_register(env, SPR_40x_DBCR0, "DBCR",
1956                  SPR_NOACCESS, SPR_NOACCESS,
1957                  &spr_read_generic, &spr_write_40x_dbcr0,
1958                  0x00000000);
1959     /* XXX : not implemented */
1960     spr_register(env, SPR_40x_DBSR, "DBSR",
1961                  SPR_NOACCESS, SPR_NOACCESS,
1962                  &spr_read_generic, &spr_write_clear,
1963                  /* Last reset was system reset */
1964                  0x00000300);
1965     /* XXX : not implemented */
1966     spr_register(env, SPR_40x_DAC1, "DAC",
1967                  SPR_NOACCESS, SPR_NOACCESS,
1968                  &spr_read_generic, &spr_write_generic,
1969                  0x00000000);
1970     /* XXX : not implemented */
1971     spr_register(env, SPR_40x_IAC1, "IAC",
1972                  SPR_NOACCESS, SPR_NOACCESS,
1973                  &spr_read_generic, &spr_write_generic,
1974                  0x00000000);
1975     /* Storage control */
1976     /* XXX: TODO: not implemented */
1977     spr_register(env, SPR_405_SLER, "SLER",
1978                  SPR_NOACCESS, SPR_NOACCESS,
1979                  &spr_read_generic, &spr_write_40x_sler,
1980                  0x00000000);
1981     /* not emulated, as Qemu never does speculative access */
1982     spr_register(env, SPR_40x_SGR, "SGR",
1983                  SPR_NOACCESS, SPR_NOACCESS,
1984                  &spr_read_generic, &spr_write_generic,
1985                  0xFFFFFFFF);
1986     /* not emulated, as Qemu do not emulate caches */
1987     spr_register(env, SPR_40x_DCWR, "DCWR",
1988                  SPR_NOACCESS, SPR_NOACCESS,
1989                  &spr_read_generic, &spr_write_generic,
1990                  0x00000000);
1991 }
1992
1993 static void gen_spr_401x2 (CPUPPCState *env)
1994 {
1995     gen_spr_401(env);
1996     spr_register(env, SPR_40x_PID, "PID",
1997                  SPR_NOACCESS, SPR_NOACCESS,
1998                  &spr_read_generic, &spr_write_generic,
1999                  0x00000000);
2000     spr_register(env, SPR_40x_ZPR, "ZPR",
2001                  SPR_NOACCESS, SPR_NOACCESS,
2002                  &spr_read_generic, &spr_write_generic,
2003                  0x00000000);
2004 }
2005
2006 /* SPR specific to PowerPC 403 implementation */
2007 static void gen_spr_403 (CPUPPCState *env)
2008 {
2009     /* Debug interface */
2010     /* XXX : not implemented */
2011     spr_register(env, SPR_40x_DBCR0, "DBCR0",
2012                  SPR_NOACCESS, SPR_NOACCESS,
2013                  &spr_read_generic, &spr_write_40x_dbcr0,
2014                  0x00000000);
2015     /* XXX : not implemented */
2016     spr_register(env, SPR_40x_DBSR, "DBSR",
2017                  SPR_NOACCESS, SPR_NOACCESS,
2018                  &spr_read_generic, &spr_write_clear,
2019                  /* Last reset was system reset */
2020                  0x00000300);
2021     /* XXX : not implemented */
2022     spr_register(env, SPR_40x_DAC1, "DAC1",
2023                  SPR_NOACCESS, SPR_NOACCESS,
2024                  &spr_read_generic, &spr_write_generic,
2025                  0x00000000);
2026     /* XXX : not implemented */
2027     spr_register(env, SPR_40x_DAC2, "DAC2",
2028                  SPR_NOACCESS, SPR_NOACCESS,
2029                  &spr_read_generic, &spr_write_generic,
2030                  0x00000000);
2031     /* XXX : not implemented */
2032     spr_register(env, SPR_40x_IAC1, "IAC1",
2033                  SPR_NOACCESS, SPR_NOACCESS,
2034                  &spr_read_generic, &spr_write_generic,
2035                  0x00000000);
2036     /* XXX : not implemented */
2037     spr_register(env, SPR_40x_IAC2, "IAC2",
2038                  SPR_NOACCESS, SPR_NOACCESS,
2039                  &spr_read_generic, &spr_write_generic,
2040                  0x00000000);
2041 }
2042
2043 static void gen_spr_403_real (CPUPPCState *env)
2044 {
2045     spr_register(env, SPR_403_PBL1,  "PBL1",
2046                  SPR_NOACCESS, SPR_NOACCESS,
2047                  &spr_read_403_pbr, &spr_write_403_pbr,
2048                  0x00000000);
2049     spr_register(env, SPR_403_PBU1,  "PBU1",
2050                  SPR_NOACCESS, SPR_NOACCESS,
2051                  &spr_read_403_pbr, &spr_write_403_pbr,
2052                  0x00000000);
2053     spr_register(env, SPR_403_PBL2,  "PBL2",
2054                  SPR_NOACCESS, SPR_NOACCESS,
2055                  &spr_read_403_pbr, &spr_write_403_pbr,
2056                  0x00000000);
2057     spr_register(env, SPR_403_PBU2,  "PBU2",
2058                  SPR_NOACCESS, SPR_NOACCESS,
2059                  &spr_read_403_pbr, &spr_write_403_pbr,
2060                  0x00000000);
2061 }
2062
2063 static void gen_spr_403_mmu (CPUPPCState *env)
2064 {
2065     /* MMU */
2066     spr_register(env, SPR_40x_PID, "PID",
2067                  SPR_NOACCESS, SPR_NOACCESS,
2068                  &spr_read_generic, &spr_write_generic,
2069                  0x00000000);
2070     spr_register(env, SPR_40x_ZPR, "ZPR",
2071                  SPR_NOACCESS, SPR_NOACCESS,
2072                  &spr_read_generic, &spr_write_generic,
2073                  0x00000000);
2074 }
2075
2076 /* SPR specific to PowerPC compression coprocessor extension */
2077 static void gen_spr_compress (CPUPPCState *env)
2078 {
2079     /* XXX : not implemented */
2080     spr_register(env, SPR_401_SKR, "SKR",
2081                  SPR_NOACCESS, SPR_NOACCESS,
2082                  &spr_read_generic, &spr_write_generic,
2083                  0x00000000);
2084 }
2085
2086 #if defined (TARGET_PPC64)
2087 /* SPR specific to PowerPC 620 */
2088 static void gen_spr_620 (CPUPPCState *env)
2089 {
2090     /* Processor identification */
2091     spr_register(env, SPR_PIR, "PIR",
2092                  SPR_NOACCESS, SPR_NOACCESS,
2093                  &spr_read_generic, &spr_write_pir,
2094                  0x00000000);
2095     spr_register(env, SPR_ASR, "ASR",
2096                  SPR_NOACCESS, SPR_NOACCESS,
2097                  &spr_read_asr, &spr_write_asr,
2098                  0x00000000);
2099     /* Breakpoints */
2100     /* XXX : not implemented */
2101     spr_register(env, SPR_IABR, "IABR",
2102                  SPR_NOACCESS, SPR_NOACCESS,
2103                  &spr_read_generic, &spr_write_generic,
2104                  0x00000000);
2105     /* XXX : not implemented */
2106     spr_register(env, SPR_DABR, "DABR",
2107                  SPR_NOACCESS, SPR_NOACCESS,
2108                  &spr_read_generic, &spr_write_generic,
2109                  0x00000000);
2110     /* XXX : not implemented */
2111     spr_register(env, SPR_SIAR, "SIAR",
2112                  SPR_NOACCESS, SPR_NOACCESS,
2113                  &spr_read_generic, SPR_NOACCESS,
2114                  0x00000000);
2115     /* XXX : not implemented */
2116     spr_register(env, SPR_SDA, "SDA",
2117                  SPR_NOACCESS, SPR_NOACCESS,
2118                  &spr_read_generic, SPR_NOACCESS,
2119                  0x00000000);
2120     /* XXX : not implemented */
2121     spr_register(env, SPR_620_PMC1R, "PMC1",
2122                  SPR_NOACCESS, SPR_NOACCESS,
2123                  &spr_read_generic, SPR_NOACCESS,
2124                  0x00000000);
2125     spr_register(env, SPR_620_PMC1W, "PMC1",
2126                  SPR_NOACCESS, SPR_NOACCESS,
2127                   SPR_NOACCESS, &spr_write_generic,
2128                  0x00000000);
2129     /* XXX : not implemented */
2130     spr_register(env, SPR_620_PMC2R, "PMC2",
2131                  SPR_NOACCESS, SPR_NOACCESS,
2132                  &spr_read_generic, SPR_NOACCESS,
2133                  0x00000000);
2134     spr_register(env, SPR_620_PMC2W, "PMC2",
2135                  SPR_NOACCESS, SPR_NOACCESS,
2136                   SPR_NOACCESS, &spr_write_generic,
2137                  0x00000000);
2138     /* XXX : not implemented */
2139     spr_register(env, SPR_620_MMCR0R, "MMCR0",
2140                  SPR_NOACCESS, SPR_NOACCESS,
2141                  &spr_read_generic, SPR_NOACCESS,
2142                  0x00000000);
2143     spr_register(env, SPR_620_MMCR0W, "MMCR0",
2144                  SPR_NOACCESS, SPR_NOACCESS,
2145                   SPR_NOACCESS, &spr_write_generic,
2146                  0x00000000);
2147     /* External access control */
2148     /* XXX : not implemented */
2149     spr_register(env, SPR_EAR, "EAR",
2150                  SPR_NOACCESS, SPR_NOACCESS,
2151                  &spr_read_generic, &spr_write_generic,
2152                  0x00000000);
2153 #if 0 // XXX: check this
2154     /* XXX : not implemented */
2155     spr_register(env, SPR_620_PMR0, "PMR0",
2156                  SPR_NOACCESS, SPR_NOACCESS,
2157                  &spr_read_generic, &spr_write_generic,
2158                  0x00000000);
2159     /* XXX : not implemented */
2160     spr_register(env, SPR_620_PMR1, "PMR1",
2161                  SPR_NOACCESS, SPR_NOACCESS,
2162                  &spr_read_generic, &spr_write_generic,
2163                  0x00000000);
2164     /* XXX : not implemented */
2165     spr_register(env, SPR_620_PMR2, "PMR2",
2166                  SPR_NOACCESS, SPR_NOACCESS,
2167                  &spr_read_generic, &spr_write_generic,
2168                  0x00000000);
2169     /* XXX : not implemented */
2170     spr_register(env, SPR_620_PMR3, "PMR3",
2171                  SPR_NOACCESS, SPR_NOACCESS,
2172                  &spr_read_generic, &spr_write_generic,
2173                  0x00000000);
2174     /* XXX : not implemented */
2175     spr_register(env, SPR_620_PMR4, "PMR4",
2176                  SPR_NOACCESS, SPR_NOACCESS,
2177                  &spr_read_generic, &spr_write_generic,
2178                  0x00000000);
2179     /* XXX : not implemented */
2180     spr_register(env, SPR_620_PMR5, "PMR5",
2181                  SPR_NOACCESS, SPR_NOACCESS,
2182                  &spr_read_generic, &spr_write_generic,
2183                  0x00000000);
2184     /* XXX : not implemented */
2185     spr_register(env, SPR_620_PMR6, "PMR6",
2186                  SPR_NOACCESS, SPR_NOACCESS,
2187                  &spr_read_generic, &spr_write_generic,
2188                  0x00000000);
2189     /* XXX : not implemented */
2190     spr_register(env, SPR_620_PMR7, "PMR7",
2191                  SPR_NOACCESS, SPR_NOACCESS,
2192                  &spr_read_generic, &spr_write_generic,
2193                  0x00000000);
2194     /* XXX : not implemented */
2195     spr_register(env, SPR_620_PMR8, "PMR8",
2196                  SPR_NOACCESS, SPR_NOACCESS,
2197                  &spr_read_generic, &spr_write_generic,
2198                  0x00000000);
2199     /* XXX : not implemented */
2200     spr_register(env, SPR_620_PMR9, "PMR9",
2201                  SPR_NOACCESS, SPR_NOACCESS,
2202                  &spr_read_generic, &spr_write_generic,
2203                  0x00000000);
2204     /* XXX : not implemented */
2205     spr_register(env, SPR_620_PMRA, "PMR10",
2206                  SPR_NOACCESS, SPR_NOACCESS,
2207                  &spr_read_generic, &spr_write_generic,
2208                  0x00000000);
2209     /* XXX : not implemented */
2210     spr_register(env, SPR_620_PMRB, "PMR11",
2211                  SPR_NOACCESS, SPR_NOACCESS,
2212                  &spr_read_generic, &spr_write_generic,
2213                  0x00000000);
2214     /* XXX : not implemented */
2215     spr_register(env, SPR_620_PMRC, "PMR12",
2216                  SPR_NOACCESS, SPR_NOACCESS,
2217                  &spr_read_generic, &spr_write_generic,
2218                  0x00000000);
2219     /* XXX : not implemented */
2220     spr_register(env, SPR_620_PMRD, "PMR13",
2221                  SPR_NOACCESS, SPR_NOACCESS,
2222                  &spr_read_generic, &spr_write_generic,
2223                  0x00000000);
2224     /* XXX : not implemented */
2225     spr_register(env, SPR_620_PMRE, "PMR14",
2226                  SPR_NOACCESS, SPR_NOACCESS,
2227                  &spr_read_generic, &spr_write_generic,
2228                  0x00000000);
2229     /* XXX : not implemented */
2230     spr_register(env, SPR_620_PMRF, "PMR15",
2231                  SPR_NOACCESS, SPR_NOACCESS,
2232                  &spr_read_generic, &spr_write_generic,
2233                  0x00000000);
2234 #endif
2235     /* XXX : not implemented */
2236     spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2237                  SPR_NOACCESS, SPR_NOACCESS,
2238                  &spr_read_generic, &spr_write_generic,
2239                  0x00000000);
2240     /* XXX : not implemented */
2241     spr_register(env, SPR_620_L2CR, "L2CR",
2242                  SPR_NOACCESS, SPR_NOACCESS,
2243                  &spr_read_generic, &spr_write_generic,
2244                  0x00000000);
2245     /* XXX : not implemented */
2246     spr_register(env, SPR_620_L2SR, "L2SR",
2247                  SPR_NOACCESS, SPR_NOACCESS,
2248                  &spr_read_generic, &spr_write_generic,
2249                  0x00000000);
2250 }
2251 #endif /* defined (TARGET_PPC64) */
2252
2253 static void gen_spr_5xx_8xx (CPUPPCState *env)
2254 {
2255     /* Exception processing */
2256     spr_register(env, SPR_DSISR, "DSISR",
2257                  SPR_NOACCESS, SPR_NOACCESS,
2258                  &spr_read_generic, &spr_write_generic,
2259                  0x00000000);
2260     spr_register(env, SPR_DAR, "DAR",
2261                  SPR_NOACCESS, SPR_NOACCESS,
2262                  &spr_read_generic, &spr_write_generic,
2263                  0x00000000);
2264     /* Timer */
2265     spr_register(env, SPR_DECR, "DECR",
2266                  SPR_NOACCESS, SPR_NOACCESS,
2267                  &spr_read_decr, &spr_write_decr,
2268                  0x00000000);
2269     /* XXX : not implemented */
2270     spr_register(env, SPR_MPC_EIE, "EIE",
2271                  SPR_NOACCESS, SPR_NOACCESS,
2272                  &spr_read_generic, &spr_write_generic,
2273                  0x00000000);
2274     /* XXX : not implemented */
2275     spr_register(env, SPR_MPC_EID, "EID",
2276                  SPR_NOACCESS, SPR_NOACCESS,
2277                  &spr_read_generic, &spr_write_generic,
2278                  0x00000000);
2279     /* XXX : not implemented */
2280     spr_register(env, SPR_MPC_NRI, "NRI",
2281                  SPR_NOACCESS, SPR_NOACCESS,
2282                  &spr_read_generic, &spr_write_generic,
2283                  0x00000000);
2284     /* XXX : not implemented */
2285     spr_register(env, SPR_MPC_CMPA, "CMPA",
2286                  SPR_NOACCESS, SPR_NOACCESS,
2287                  &spr_read_generic, &spr_write_generic,
2288                  0x00000000);
2289     /* XXX : not implemented */
2290     spr_register(env, SPR_MPC_CMPB, "CMPB",
2291                  SPR_NOACCESS, SPR_NOACCESS,
2292                  &spr_read_generic, &spr_write_generic,
2293                  0x00000000);
2294     /* XXX : not implemented */
2295     spr_register(env, SPR_MPC_CMPC, "CMPC",
2296                  SPR_NOACCESS, SPR_NOACCESS,
2297                  &spr_read_generic, &spr_write_generic,
2298                  0x00000000);
2299     /* XXX : not implemented */
2300     spr_register(env, SPR_MPC_CMPD, "CMPD",
2301                  SPR_NOACCESS, SPR_NOACCESS,
2302                  &spr_read_generic, &spr_write_generic,
2303                  0x00000000);
2304     /* XXX : not implemented */
2305     spr_register(env, SPR_MPC_ECR, "ECR",
2306                  SPR_NOACCESS, SPR_NOACCESS,
2307                  &spr_read_generic, &spr_write_generic,
2308                  0x00000000);
2309     /* XXX : not implemented */
2310     spr_register(env, SPR_MPC_DER, "DER",
2311                  SPR_NOACCESS, SPR_NOACCESS,
2312                  &spr_read_generic, &spr_write_generic,
2313                  0x00000000);
2314     /* XXX : not implemented */
2315     spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2316                  SPR_NOACCESS, SPR_NOACCESS,
2317                  &spr_read_generic, &spr_write_generic,
2318                  0x00000000);
2319     /* XXX : not implemented */
2320     spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2321                  SPR_NOACCESS, SPR_NOACCESS,
2322                  &spr_read_generic, &spr_write_generic,
2323                  0x00000000);
2324     /* XXX : not implemented */
2325     spr_register(env, SPR_MPC_CMPE, "CMPE",
2326                  SPR_NOACCESS, SPR_NOACCESS,
2327                  &spr_read_generic, &spr_write_generic,
2328                  0x00000000);
2329     /* XXX : not implemented */
2330     spr_register(env, SPR_MPC_CMPF, "CMPF",
2331                  SPR_NOACCESS, SPR_NOACCESS,
2332                  &spr_read_generic, &spr_write_generic,
2333                  0x00000000);
2334     /* XXX : not implemented */
2335     spr_register(env, SPR_MPC_CMPG, "CMPG",
2336                  SPR_NOACCESS, SPR_NOACCESS,
2337                  &spr_read_generic, &spr_write_generic,
2338                  0x00000000);
2339     /* XXX : not implemented */
2340     spr_register(env, SPR_MPC_CMPH, "CMPH",
2341                  SPR_NOACCESS, SPR_NOACCESS,
2342                  &spr_read_generic, &spr_write_generic,
2343                  0x00000000);
2344     /* XXX : not implemented */
2345     spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2346                  SPR_NOACCESS, SPR_NOACCESS,
2347                  &spr_read_generic, &spr_write_generic,
2348                  0x00000000);
2349     /* XXX : not implemented */
2350     spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2351                  SPR_NOACCESS, SPR_NOACCESS,
2352                  &spr_read_generic, &spr_write_generic,
2353                  0x00000000);
2354     /* XXX : not implemented */
2355     spr_register(env, SPR_MPC_BAR, "BAR",
2356                  SPR_NOACCESS, SPR_NOACCESS,
2357                  &spr_read_generic, &spr_write_generic,
2358                  0x00000000);
2359     /* XXX : not implemented */
2360     spr_register(env, SPR_MPC_DPDR, "DPDR",
2361                  SPR_NOACCESS, SPR_NOACCESS,
2362                  &spr_read_generic, &spr_write_generic,
2363                  0x00000000);
2364     /* XXX : not implemented */
2365     spr_register(env, SPR_MPC_IMMR, "IMMR",
2366                  SPR_NOACCESS, SPR_NOACCESS,
2367                  &spr_read_generic, &spr_write_generic,
2368                  0x00000000);
2369 }
2370
2371 static void gen_spr_5xx (CPUPPCState *env)
2372 {
2373     /* XXX : not implemented */
2374     spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2375                  SPR_NOACCESS, SPR_NOACCESS,
2376                  &spr_read_generic, &spr_write_generic,
2377                  0x00000000);
2378     /* XXX : not implemented */
2379     spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2380                  SPR_NOACCESS, SPR_NOACCESS,
2381                  &spr_read_generic, &spr_write_generic,
2382                  0x00000000);
2383     /* XXX : not implemented */
2384     spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2385                  SPR_NOACCESS, SPR_NOACCESS,
2386                  &spr_read_generic, &spr_write_generic,
2387                  0x00000000);
2388     /* XXX : not implemented */
2389     spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2390                  SPR_NOACCESS, SPR_NOACCESS,
2391                  &spr_read_generic, &spr_write_generic,
2392                  0x00000000);
2393     /* XXX : not implemented */
2394     spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2395                  SPR_NOACCESS, SPR_NOACCESS,
2396                  &spr_read_generic, &spr_write_generic,
2397                  0x00000000);
2398     /* XXX : not implemented */
2399     spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2400                  SPR_NOACCESS, SPR_NOACCESS,
2401                  &spr_read_generic, &spr_write_generic,
2402                  0x00000000);
2403     /* XXX : not implemented */
2404     spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2405                  SPR_NOACCESS, SPR_NOACCESS,
2406                  &spr_read_generic, &spr_write_generic,
2407                  0x00000000);
2408     /* XXX : not implemented */
2409     spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2410                  SPR_NOACCESS, SPR_NOACCESS,
2411                  &spr_read_generic, &spr_write_generic,
2412                  0x00000000);
2413     /* XXX : not implemented */
2414     spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2415                  SPR_NOACCESS, SPR_NOACCESS,
2416                  &spr_read_generic, &spr_write_generic,
2417                  0x00000000);
2418     /* XXX : not implemented */
2419     spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2420                  SPR_NOACCESS, SPR_NOACCESS,
2421                  &spr_read_generic, &spr_write_generic,
2422                  0x00000000);
2423     /* XXX : not implemented */
2424     spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2425                  SPR_NOACCESS, SPR_NOACCESS,
2426                  &spr_read_generic, &spr_write_generic,
2427                  0x00000000);
2428     /* XXX : not implemented */
2429     spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2430                  SPR_NOACCESS, SPR_NOACCESS,
2431                  &spr_read_generic, &spr_write_generic,
2432                  0x00000000);
2433     /* XXX : not implemented */
2434     spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2435                  SPR_NOACCESS, SPR_NOACCESS,
2436                  &spr_read_generic, &spr_write_generic,
2437                  0x00000000);
2438     /* XXX : not implemented */
2439     spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2440                  SPR_NOACCESS, SPR_NOACCESS,
2441                  &spr_read_generic, &spr_write_generic,
2442                  0x00000000);
2443     /* XXX : not implemented */
2444     spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2445                  SPR_NOACCESS, SPR_NOACCESS,
2446                  &spr_read_generic, &spr_write_generic,
2447                  0x00000000);
2448     /* XXX : not implemented */
2449     spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2450                  SPR_NOACCESS, SPR_NOACCESS,
2451                  &spr_read_generic, &spr_write_generic,
2452                  0x00000000);
2453     /* XXX : not implemented */
2454     spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2455                  SPR_NOACCESS, SPR_NOACCESS,
2456                  &spr_read_generic, &spr_write_generic,
2457                  0x00000000);
2458     /* XXX : not implemented */
2459     spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2460                  SPR_NOACCESS, SPR_NOACCESS,
2461                  &spr_read_generic, &spr_write_generic,
2462                  0x00000000);
2463     /* XXX : not implemented */
2464     spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2465                  SPR_NOACCESS, SPR_NOACCESS,
2466                  &spr_read_generic, &spr_write_generic,
2467                  0x00000000);
2468     /* XXX : not implemented */
2469     spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2470                  SPR_NOACCESS, SPR_NOACCESS,
2471                  &spr_read_generic, &spr_write_generic,
2472                  0x00000000);
2473     /* XXX : not implemented */
2474     spr_register(env, SPR_RCPU_FPECR, "FPECR",
2475                  SPR_NOACCESS, SPR_NOACCESS,
2476                  &spr_read_generic, &spr_write_generic,
2477                  0x00000000);
2478 }
2479
2480 static void gen_spr_8xx (CPUPPCState *env)
2481 {
2482     /* XXX : not implemented */
2483     spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2484                  SPR_NOACCESS, SPR_NOACCESS,
2485                  &spr_read_generic, &spr_write_generic,
2486                  0x00000000);
2487     /* XXX : not implemented */
2488     spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2489                  SPR_NOACCESS, SPR_NOACCESS,
2490                  &spr_read_generic, &spr_write_generic,
2491                  0x00000000);
2492     /* XXX : not implemented */
2493     spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2494                  SPR_NOACCESS, SPR_NOACCESS,
2495                  &spr_read_generic, &spr_write_generic,
2496                  0x00000000);
2497     /* XXX : not implemented */
2498     spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2499                  SPR_NOACCESS, SPR_NOACCESS,
2500                  &spr_read_generic, &spr_write_generic,
2501                  0x00000000);
2502     /* XXX : not implemented */
2503     spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2504                  SPR_NOACCESS, SPR_NOACCESS,
2505                  &spr_read_generic, &spr_write_generic,
2506                  0x00000000);
2507     /* XXX : not implemented */
2508     spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2509                  SPR_NOACCESS, SPR_NOACCESS,
2510                  &spr_read_generic, &spr_write_generic,
2511                  0x00000000);
2512     /* XXX : not implemented */
2513     spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2514                  SPR_NOACCESS, SPR_NOACCESS,
2515                  &spr_read_generic, &spr_write_generic,
2516                  0x00000000);
2517     /* XXX : not implemented */
2518     spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2519                  SPR_NOACCESS, SPR_NOACCESS,
2520                  &spr_read_generic, &spr_write_generic,
2521                  0x00000000);
2522     /* XXX : not implemented */
2523     spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2524                  SPR_NOACCESS, SPR_NOACCESS,
2525                  &spr_read_generic, &spr_write_generic,
2526                  0x00000000);
2527     /* XXX : not implemented */
2528     spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2529                  SPR_NOACCESS, SPR_NOACCESS,
2530                  &spr_read_generic, &spr_write_generic,
2531                  0x00000000);
2532     /* XXX : not implemented */
2533     spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2534                  SPR_NOACCESS, SPR_NOACCESS,
2535                  &spr_read_generic, &spr_write_generic,
2536                  0x00000000);
2537     /* XXX : not implemented */
2538     spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2539                  SPR_NOACCESS, SPR_NOACCESS,
2540                  &spr_read_generic, &spr_write_generic,
2541                  0x00000000);
2542     /* XXX : not implemented */
2543     spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2544                  SPR_NOACCESS, SPR_NOACCESS,
2545                  &spr_read_generic, &spr_write_generic,
2546                  0x00000000);
2547     /* XXX : not implemented */
2548     spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2549                  SPR_NOACCESS, SPR_NOACCESS,
2550                  &spr_read_generic, &spr_write_generic,
2551                  0x00000000);
2552     /* XXX : not implemented */
2553     spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2554                  SPR_NOACCESS, SPR_NOACCESS,
2555                  &spr_read_generic, &spr_write_generic,
2556                  0x00000000);
2557     /* XXX : not implemented */
2558     spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2559                  SPR_NOACCESS, SPR_NOACCESS,
2560                  &spr_read_generic, &spr_write_generic,
2561                  0x00000000);
2562     /* XXX : not implemented */
2563     spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2564                  SPR_NOACCESS, SPR_NOACCESS,
2565                  &spr_read_generic, &spr_write_generic,
2566                  0x00000000);
2567     /* XXX : not implemented */
2568     spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2569                  SPR_NOACCESS, SPR_NOACCESS,
2570                  &spr_read_generic, &spr_write_generic,
2571                  0x00000000);
2572     /* XXX : not implemented */
2573     spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2574                  SPR_NOACCESS, SPR_NOACCESS,
2575                  &spr_read_generic, &spr_write_generic,
2576                  0x00000000);
2577     /* XXX : not implemented */
2578     spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2579                  SPR_NOACCESS, SPR_NOACCESS,
2580                  &spr_read_generic, &spr_write_generic,
2581                  0x00000000);
2582     /* XXX : not implemented */
2583     spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2584                  SPR_NOACCESS, SPR_NOACCESS,
2585                  &spr_read_generic, &spr_write_generic,
2586                  0x00000000);
2587     /* XXX : not implemented */
2588     spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2589                  SPR_NOACCESS, SPR_NOACCESS,
2590                  &spr_read_generic, &spr_write_generic,
2591                  0x00000000);
2592     /* XXX : not implemented */
2593     spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2594                  SPR_NOACCESS, SPR_NOACCESS,
2595                  &spr_read_generic, &spr_write_generic,
2596                  0x00000000);
2597     /* XXX : not implemented */
2598     spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2599                  SPR_NOACCESS, SPR_NOACCESS,
2600                  &spr_read_generic, &spr_write_generic,
2601                  0x00000000);
2602     /* XXX : not implemented */
2603     spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2604                  SPR_NOACCESS, SPR_NOACCESS,
2605                  &spr_read_generic, &spr_write_generic,
2606                  0x00000000);
2607 }
2608
2609 // XXX: TODO
2610 /*
2611  * AMR     => SPR 29 (Power 2.04)
2612  * CTRL    => SPR 136 (Power 2.04)
2613  * CTRL    => SPR 152 (Power 2.04)
2614  * SCOMC   => SPR 276 (64 bits ?)
2615  * SCOMD   => SPR 277 (64 bits ?)
2616  * TBU40   => SPR 286 (Power 2.04 hypv)
2617  * HSPRG0  => SPR 304 (Power 2.04 hypv)
2618  * HSPRG1  => SPR 305 (Power 2.04 hypv)
2619  * HDSISR  => SPR 306 (Power 2.04 hypv)
2620  * HDAR    => SPR 307 (Power 2.04 hypv)
2621  * PURR    => SPR 309 (Power 2.04 hypv)
2622  * HDEC    => SPR 310 (Power 2.04 hypv)
2623  * HIOR    => SPR 311 (hypv)
2624  * RMOR    => SPR 312 (970)
2625  * HRMOR   => SPR 313 (Power 2.04 hypv)
2626  * HSRR0   => SPR 314 (Power 2.04 hypv)
2627  * HSRR1   => SPR 315 (Power 2.04 hypv)
2628  * LPCR    => SPR 316 (970)
2629  * LPIDR   => SPR 317 (970)
2630  * EPR     => SPR 702 (Power 2.04 emb)
2631  * perf    => 768-783 (Power 2.04)
2632  * perf    => 784-799 (Power 2.04)
2633  * PPR     => SPR 896 (Power 2.04)
2634  * EPLC    => SPR 947 (Power 2.04 emb)
2635  * EPSC    => SPR 948 (Power 2.04 emb)
2636  * DABRX   => 1015    (Power 2.04 hypv)
2637  * FPECR   => SPR 1022 (?)
2638  * ... and more (thermal management, performance counters, ...)
2639  */
2640
2641 /*****************************************************************************/
2642 /* Exception vectors models                                                  */
2643 static void init_excp_4xx_real (CPUPPCState *env)
2644 {
2645 #if !defined(CONFIG_USER_ONLY)
2646     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2647     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2648     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2649     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2650     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2651     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2652     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2653     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2654     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2655     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2656     env->hreset_excp_prefix = 0x00000000UL;
2657     env->ivor_mask = 0x0000FFF0UL;
2658     env->ivpr_mask = 0xFFFF0000UL;
2659     /* Hardware reset vector */
2660     env->hreset_vector = 0xFFFFFFFCUL;
2661 #endif
2662 }
2663
2664 static void init_excp_4xx_softmmu (CPUPPCState *env)
2665 {
2666 #if !defined(CONFIG_USER_ONLY)
2667     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2668     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2669     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2670     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2671     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2672     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2673     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2674     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2675     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2676     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2677     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2678     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2679     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2680     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2681     env->hreset_excp_prefix = 0x00000000UL;
2682     env->ivor_mask = 0x0000FFF0UL;
2683     env->ivpr_mask = 0xFFFF0000UL;
2684     /* Hardware reset vector */
2685     env->hreset_vector = 0xFFFFFFFCUL;
2686 #endif
2687 }
2688
2689 static void init_excp_MPC5xx (CPUPPCState *env)
2690 {
2691 #if !defined(CONFIG_USER_ONLY)
2692     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2693     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2694     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2695     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2696     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2697     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2698     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2699     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2700     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2701     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2702     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2703     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2704     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2705     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2706     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2707     env->hreset_excp_prefix = 0x00000000UL;
2708     env->ivor_mask = 0x0000FFF0UL;
2709     env->ivpr_mask = 0xFFFF0000UL;
2710     /* Hardware reset vector */
2711     env->hreset_vector = 0xFFFFFFFCUL;
2712 #endif
2713 }
2714
2715 static void init_excp_MPC8xx (CPUPPCState *env)
2716 {
2717 #if !defined(CONFIG_USER_ONLY)
2718     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2719     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2720     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2721     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2722     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2723     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2724     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2725     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2726     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2727     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2728     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2729     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2730     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2731     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2732     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2733     env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2734     env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2735     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2736     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2737     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2738     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2739     env->hreset_excp_prefix = 0x00000000UL;
2740     env->ivor_mask = 0x0000FFF0UL;
2741     env->ivpr_mask = 0xFFFF0000UL;
2742     /* Hardware reset vector */
2743     env->hreset_vector = 0xFFFFFFFCUL;
2744 #endif
2745 }
2746
2747 static void init_excp_G2 (CPUPPCState *env)
2748 {
2749 #if !defined(CONFIG_USER_ONLY)
2750     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2751     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2752     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2753     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2754     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2755     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2756     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2757     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2758     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2759     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2760     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2761     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2762     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2763     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2764     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2765     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2766     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2767     env->hreset_excp_prefix = 0x00000000UL;
2768     /* Hardware reset vector */
2769     env->hreset_vector = 0xFFFFFFFCUL;
2770 #endif
2771 }
2772
2773 static void init_excp_e200 (CPUPPCState *env)
2774 {
2775 #if !defined(CONFIG_USER_ONLY)
2776     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2777     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2778     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2779     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2780     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2781     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2782     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2783     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2784     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2785     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2786     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2787     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2788     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2789     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2790     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2791     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2792     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2793     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2794     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2795     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2796     env->hreset_excp_prefix = 0x00000000UL;
2797     env->ivor_mask = 0x0000FFF7UL;
2798     env->ivpr_mask = 0xFFFF0000UL;
2799     /* Hardware reset vector */
2800     env->hreset_vector = 0xFFFFFFFCUL;
2801 #endif
2802 }
2803
2804 static void init_excp_BookE (CPUPPCState *env)
2805 {
2806 #if !defined(CONFIG_USER_ONLY)
2807     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2808     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2809     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2810     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2811     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2812     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2813     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2814     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2815     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2816     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2817     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2818     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2819     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2820     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2821     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2822     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2823     env->hreset_excp_prefix = 0x00000000UL;
2824     env->ivor_mask = 0x0000FFE0UL;
2825     env->ivpr_mask = 0xFFFF0000UL;
2826     /* Hardware reset vector */
2827     env->hreset_vector = 0xFFFFFFFCUL;
2828 #endif
2829 }
2830
2831 static void init_excp_601 (CPUPPCState *env)
2832 {
2833 #if !defined(CONFIG_USER_ONLY)
2834     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2835     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2836     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2837     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2838     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2839     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2840     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2841     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2842     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2843     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2844     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2845     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2846     env->hreset_excp_prefix = 0xFFF00000UL;
2847     /* Hardware reset vector */
2848     env->hreset_vector = 0x00000100UL;
2849 #endif
2850 }
2851
2852 static void init_excp_602 (CPUPPCState *env)
2853 {
2854 #if !defined(CONFIG_USER_ONLY)
2855     /* XXX: exception prefix has a special behavior on 602 */
2856     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2857     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2858     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2859     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2860     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2861     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2862     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2863     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2864     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2865     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2866     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2867     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2868     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2869     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2870     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2871     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2872     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2873     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2874     env->hreset_excp_prefix = 0xFFF00000UL;
2875     /* Hardware reset vector */
2876     env->hreset_vector = 0xFFFFFFFCUL;
2877 #endif
2878 }
2879
2880 static void init_excp_603 (CPUPPCState *env)
2881 {
2882 #if !defined(CONFIG_USER_ONLY)
2883     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2884     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2885     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2886     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2887     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2888     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2889     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2890     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2891     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2892     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2893     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2894     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2895     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2896     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2897     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2898     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2899     env->hreset_excp_prefix = 0x00000000UL;
2900     /* Hardware reset vector */
2901     env->hreset_vector = 0xFFFFFFFCUL;
2902 #endif
2903 }
2904
2905 static void init_excp_604 (CPUPPCState *env)
2906 {
2907 #if !defined(CONFIG_USER_ONLY)
2908     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2909     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2910     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2911     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2912     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2913     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2914     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2915     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2916     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2917     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2918     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2919     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2920     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2921     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2922     env->hreset_excp_prefix = 0xFFF00000UL;
2923     /* Hardware reset vector */
2924     env->hreset_vector = 0x00000100UL;
2925 #endif
2926 }
2927
2928 #if defined(TARGET_PPC64)
2929 static void init_excp_620 (CPUPPCState *env)
2930 {
2931 #if !defined(CONFIG_USER_ONLY)
2932     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2933     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2934     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2935     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2936     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2937     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2938     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2939     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2940     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2941     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2942     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2943     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2944     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2945     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2946     env->hreset_excp_prefix = 0xFFF00000UL;
2947     /* Hardware reset vector */
2948     env->hreset_vector = 0x0000000000000100ULL;
2949 #endif
2950 }
2951 #endif /* defined(TARGET_PPC64) */
2952
2953 static void init_excp_7x0 (CPUPPCState *env)
2954 {
2955 #if !defined(CONFIG_USER_ONLY)
2956     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2957     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2958     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2959     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2960     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2961     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2962     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2963     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2964     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2965     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2966     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2967     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2968     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2969     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2970     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2971     env->hreset_excp_prefix = 0x00000000UL;
2972     /* Hardware reset vector */
2973     env->hreset_vector = 0xFFFFFFFCUL;
2974 #endif
2975 }
2976
2977 static void init_excp_750cl (CPUPPCState *env)
2978 {
2979 #if !defined(CONFIG_USER_ONLY)
2980     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2981     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2982     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2983     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2984     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2985     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2986     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2987     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2988     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2989     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2990     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2991     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2992     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2993     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2994     env->hreset_excp_prefix = 0x00000000UL;
2995     /* Hardware reset vector */
2996     env->hreset_vector = 0xFFFFFFFCUL;
2997 #endif
2998 }
2999
3000 static void init_excp_750cx (CPUPPCState *env)
3001 {
3002 #if !defined(CONFIG_USER_ONLY)
3003     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3004     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3005     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3006     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3007     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3008     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3009     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3010     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3011     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3012     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3013     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3014     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3015     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3016     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3017     env->hreset_excp_prefix = 0x00000000UL;
3018     /* Hardware reset vector */
3019     env->hreset_vector = 0xFFFFFFFCUL;
3020 #endif
3021 }
3022
3023 /* XXX: Check if this is correct */
3024 static void init_excp_7x5 (CPUPPCState *env)
3025 {
3026 #if !defined(CONFIG_USER_ONLY)
3027     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3028     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3029     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3030     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3031     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3032     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3033     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3034     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3035     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3036     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3037     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3038     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3039     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3040     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3041     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3042     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3043     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3044     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3045     env->hreset_excp_prefix = 0x00000000UL;
3046     /* Hardware reset vector */
3047     env->hreset_vector = 0xFFFFFFFCUL;
3048 #endif
3049 }
3050
3051 static void init_excp_7400 (CPUPPCState *env)
3052 {
3053 #if !defined(CONFIG_USER_ONLY)
3054     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3055     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3056     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3057     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3058     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3059     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3060     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3061     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3062     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3063     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3064     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3065     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3066     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3067     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3068     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3069     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3070     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3071     env->hreset_excp_prefix = 0x00000000UL;
3072     /* Hardware reset vector */
3073     env->hreset_vector = 0xFFFFFFFCUL;
3074 #endif
3075 }
3076
3077 static void init_excp_7450 (CPUPPCState *env)
3078 {
3079 #if !defined(CONFIG_USER_ONLY)
3080     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3081     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3082     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3083     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3084     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3085     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3086     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3087     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3088     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3089     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3090     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3091     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3092     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3093     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3094     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3095     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3096     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3097     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3098     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3099     env->hreset_excp_prefix = 0x00000000UL;
3100     /* Hardware reset vector */
3101     env->hreset_vector = 0xFFFFFFFCUL;
3102 #endif
3103 }
3104
3105 #if defined (TARGET_PPC64)
3106 static void init_excp_970 (CPUPPCState *env)
3107 {
3108 #if !defined(CONFIG_USER_ONLY)
3109     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3110     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3111     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3112     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3113     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3114     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3115     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3116     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3117     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3118     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3119     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3120     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3121     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3122     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3123     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3124     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3125     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3126     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3127     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3128     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3129     env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3130     /* Hardware reset vector */
3131     env->hreset_vector = 0x0000000000000100ULL;
3132 #endif
3133 }
3134 #endif
3135
3136 /*****************************************************************************/
3137 /* Power management enable checks                                            */
3138 static int check_pow_none (CPUPPCState *env)
3139 {
3140     return 0;
3141 }
3142
3143 static int check_pow_nocheck (CPUPPCState *env)
3144 {
3145     return 1;
3146 }
3147
3148 static int check_pow_hid0 (CPUPPCState *env)
3149 {
3150     if (env->spr[SPR_HID0] & 0x00E00000)
3151         return 1;
3152
3153     return 0;
3154 }
3155
3156 static int check_pow_hid0_74xx (CPUPPCState *env)
3157 {
3158     if (env->spr[SPR_HID0] & 0x00600000)
3159         return 1;
3160
3161     return 0;
3162 }
3163
3164 /*****************************************************************************/
3165 /* PowerPC implementations definitions                                       */
3166
3167 /* PowerPC 401                                                               */
3168 #define POWERPC_INSNS_401    (PPC_INSNS_BASE | PPC_STRING |                   \
3169                               PPC_WRTEE | PPC_DCR |                           \
3170                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3171                               PPC_CACHE_DCBZ |                                \
3172                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3173                               PPC_4xx_COMMON | PPC_40x_EXCP)
3174 #define POWERPC_MSRM_401     (0x00000000000FD201ULL)
3175 #define POWERPC_MMU_401      (POWERPC_MMU_REAL)
3176 #define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
3177 #define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
3178 #define POWERPC_BFDM_401     (bfd_mach_ppc_403)
3179 #define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3180                               POWERPC_FLAG_BUS_CLK)
3181 #define check_pow_401        check_pow_nocheck
3182
3183 static void init_proc_401 (CPUPPCState *env)
3184 {
3185     gen_spr_40x(env);
3186     gen_spr_401_403(env);
3187     gen_spr_401(env);
3188     init_excp_4xx_real(env);
3189     env->dcache_line_size = 32;
3190     env->icache_line_size = 32;
3191     /* Allocate hardware IRQ controller */
3192     ppc40x_irq_init(env);
3193 }
3194
3195 /* PowerPC 401x2                                                             */
3196 #define POWERPC_INSNS_401x2  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3197                               PPC_DCR | PPC_WRTEE |                           \
3198                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3199                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3200                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3201                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3202                               PPC_4xx_COMMON | PPC_40x_EXCP)
3203 #define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
3204 #define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
3205 #define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
3206 #define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
3207 #define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
3208 #define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3209                               POWERPC_FLAG_BUS_CLK)
3210 #define check_pow_401x2      check_pow_nocheck
3211
3212 static void init_proc_401x2 (CPUPPCState *env)
3213 {
3214     gen_spr_40x(env);
3215     gen_spr_401_403(env);
3216     gen_spr_401x2(env);
3217     gen_spr_compress(env);
3218     /* Memory management */
3219 #if !defined(CONFIG_USER_ONLY)
3220     env->nb_tlb = 64;
3221     env->nb_ways = 1;
3222     env->id_tlbs = 0;
3223 #endif
3224     init_excp_4xx_softmmu(env);
3225     env->dcache_line_size = 32;
3226     env->icache_line_size = 32;
3227     /* Allocate hardware IRQ controller */
3228     ppc40x_irq_init(env);
3229 }
3230
3231 /* PowerPC 401x3                                                             */
3232 #define POWERPC_INSNS_401x3  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3233                               PPC_DCR | PPC_WRTEE |                           \
3234                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3235                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3236                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3237                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3238                               PPC_4xx_COMMON | PPC_40x_EXCP)
3239 #define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
3240 #define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
3241 #define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
3242 #define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
3243 #define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
3244 #define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3245                               POWERPC_FLAG_BUS_CLK)
3246 #define check_pow_401x3      check_pow_nocheck
3247
3248 __attribute__ (( unused ))
3249 static void init_proc_401x3 (CPUPPCState *env)
3250 {
3251     gen_spr_40x(env);
3252     gen_spr_401_403(env);
3253     gen_spr_401(env);
3254     gen_spr_401x2(env);
3255     gen_spr_compress(env);
3256     init_excp_4xx_softmmu(env);
3257     env->dcache_line_size = 32;
3258     env->icache_line_size = 32;
3259     /* Allocate hardware IRQ controller */
3260     ppc40x_irq_init(env);
3261 }
3262
3263 /* IOP480                                                                    */
3264 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING |                   \
3265                               PPC_DCR | PPC_WRTEE |                           \
3266                               PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |    \
3267                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3268                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3269                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3270                               PPC_4xx_COMMON | PPC_40x_EXCP)
3271 #define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
3272 #define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
3273 #define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
3274 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3275 #define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
3276 #define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3277                               POWERPC_FLAG_BUS_CLK)
3278 #define check_pow_IOP480     check_pow_nocheck
3279
3280 static void init_proc_IOP480 (CPUPPCState *env)
3281 {
3282     gen_spr_40x(env);
3283     gen_spr_401_403(env);
3284     gen_spr_401x2(env);
3285     gen_spr_compress(env);
3286     /* Memory management */
3287 #if !defined(CONFIG_USER_ONLY)
3288     env->nb_tlb = 64;
3289     env->nb_ways = 1;
3290     env->id_tlbs = 0;
3291 #endif
3292     init_excp_4xx_softmmu(env);
3293     env->dcache_line_size = 32;
3294     env->icache_line_size = 32;
3295     /* Allocate hardware IRQ controller */
3296     ppc40x_irq_init(env);
3297 }
3298
3299 /* PowerPC 403                                                               */
3300 #define POWERPC_INSNS_403    (PPC_INSNS_BASE | PPC_STRING |                   \
3301                               PPC_DCR | PPC_WRTEE |                           \
3302                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3303                               PPC_CACHE_DCBZ |                                \
3304                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3305                               PPC_4xx_COMMON | PPC_40x_EXCP)
3306 #define POWERPC_MSRM_403     (0x000000000007D00DULL)
3307 #define POWERPC_MMU_403      (POWERPC_MMU_REAL)
3308 #define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
3309 #define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
3310 #define POWERPC_BFDM_403     (bfd_mach_ppc_403)
3311 #define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3312                               POWERPC_FLAG_BUS_CLK)
3313 #define check_pow_403        check_pow_nocheck
3314
3315 static void init_proc_403 (CPUPPCState *env)
3316 {
3317     gen_spr_40x(env);
3318     gen_spr_401_403(env);
3319     gen_spr_403(env);
3320     gen_spr_403_real(env);
3321     init_excp_4xx_real(env);
3322     env->dcache_line_size = 32;
3323     env->icache_line_size = 32;
3324     /* Allocate hardware IRQ controller */
3325     ppc40x_irq_init(env);
3326 }
3327
3328 /* PowerPC 403 GCX                                                           */
3329 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING |                   \
3330                               PPC_DCR | PPC_WRTEE |                           \
3331                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3332                               PPC_CACHE_DCBZ |                                \
3333                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3334                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3335                               PPC_4xx_COMMON | PPC_40x_EXCP)
3336 #define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
3337 #define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
3338 #define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
3339 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3340 #define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
3341 #define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3342                               POWERPC_FLAG_BUS_CLK)
3343 #define check_pow_403GCX     check_pow_nocheck
3344
3345 static void init_proc_403GCX (CPUPPCState *env)
3346 {
3347     gen_spr_40x(env);
3348     gen_spr_401_403(env);
3349     gen_spr_403(env);
3350     gen_spr_403_real(env);
3351     gen_spr_403_mmu(env);
3352     /* Bus access control */
3353     /* not emulated, as Qemu never does speculative access */
3354     spr_register(env, SPR_40x_SGR, "SGR",
3355                  SPR_NOACCESS, SPR_NOACCESS,
3356                  &spr_read_generic, &spr_write_generic,
3357                  0xFFFFFFFF);
3358     /* not emulated, as Qemu do not emulate caches */
3359     spr_register(env, SPR_40x_DCWR, "DCWR",
3360                  SPR_NOACCESS, SPR_NOACCESS,
3361                  &spr_read_generic, &spr_write_generic,
3362                  0x00000000);
3363     /* Memory management */
3364 #if !defined(CONFIG_USER_ONLY)
3365     env->nb_tlb = 64;
3366     env->nb_ways = 1;
3367     env->id_tlbs = 0;
3368 #endif
3369     init_excp_4xx_softmmu(env);
3370     env->dcache_line_size = 32;
3371     env->icache_line_size = 32;
3372     /* Allocate hardware IRQ controller */
3373     ppc40x_irq_init(env);
3374 }
3375
3376 /* PowerPC 405                                                               */
3377 #define POWERPC_INSNS_405    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3378                               PPC_DCR | PPC_WRTEE |                           \
3379                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3380                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3381                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3382                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3383                               PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3384 #define POWERPC_MSRM_405     (0x000000000006E630ULL)
3385 #define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
3386 #define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
3387 #define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
3388 #define POWERPC_BFDM_405     (bfd_mach_ppc_403)
3389 #define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3390                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3391 #define check_pow_405        check_pow_nocheck
3392
3393 static void init_proc_405 (CPUPPCState *env)
3394 {
3395     /* Time base */
3396     gen_tbl(env);
3397     gen_spr_40x(env);
3398     gen_spr_405(env);
3399     /* Bus access control */
3400     /* not emulated, as Qemu never does speculative access */
3401     spr_register(env, SPR_40x_SGR, "SGR",
3402                  SPR_NOACCESS, SPR_NOACCESS,
3403                  &spr_read_generic, &spr_write_generic,
3404                  0xFFFFFFFF);
3405     /* not emulated, as Qemu do not emulate caches */
3406     spr_register(env, SPR_40x_DCWR, "DCWR",
3407                  SPR_NOACCESS, SPR_NOACCESS,
3408                  &spr_read_generic, &spr_write_generic,
3409                  0x00000000);
3410     /* Memory management */
3411 #if !defined(CONFIG_USER_ONLY)
3412     env->nb_tlb = 64;
3413     env->nb_ways = 1;
3414     env->id_tlbs = 0;
3415 #endif
3416     init_excp_4xx_softmmu(env);
3417     env->dcache_line_size = 32;
3418     env->icache_line_size = 32;
3419     /* Allocate hardware IRQ controller */
3420     ppc40x_irq_init(env);
3421 }
3422
3423 /* PowerPC 440 EP                                                            */
3424 #define POWERPC_INSNS_440EP  (PPC_INSNS_BASE | PPC_STRING |                   \
3425                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3426                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3427                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3428                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3429                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3430                               PPC_440_SPEC)
3431 #define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
3432 #define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
3433 #define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
3434 #define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
3435 #define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
3436 #define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3437                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3438 #define check_pow_440EP      check_pow_nocheck
3439
3440 __attribute__ (( unused ))
3441 static void init_proc_440EP (CPUPPCState *env)
3442 {
3443     /* Time base */
3444     gen_tbl(env);
3445     gen_spr_BookE(env, 0x000000000000FFFFULL);
3446     gen_spr_440(env);
3447     gen_spr_usprgh(env);
3448     /* Processor identification */
3449     spr_register(env, SPR_BOOKE_PIR, "PIR",
3450                  SPR_NOACCESS, SPR_NOACCESS,
3451                  &spr_read_generic, &spr_write_pir,
3452                  0x00000000);
3453     /* XXX : not implemented */
3454     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3455                  SPR_NOACCESS, SPR_NOACCESS,
3456                  &spr_read_generic, &spr_write_generic,
3457                  0x00000000);
3458     /* XXX : not implemented */
3459     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3460                  SPR_NOACCESS, SPR_NOACCESS,
3461                  &spr_read_generic, &spr_write_generic,
3462                  0x00000000);
3463     /* XXX : not implemented */
3464     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3465                  SPR_NOACCESS, SPR_NOACCESS,
3466                  &spr_read_generic, &spr_write_generic,
3467                  0x00000000);
3468     /* XXX : not implemented */
3469     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3470                  SPR_NOACCESS, SPR_NOACCESS,
3471                  &spr_read_generic, &spr_write_generic,
3472                  0x00000000);
3473     /* XXX : not implemented */
3474     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3475                  SPR_NOACCESS, SPR_NOACCESS,
3476                  &spr_read_generic, &spr_write_generic,
3477                  0x00000000);
3478     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3479                  SPR_NOACCESS, SPR_NOACCESS,
3480                  &spr_read_generic, &spr_write_generic,
3481                  0x00000000);
3482     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3483                  SPR_NOACCESS, SPR_NOACCESS,
3484                  &spr_read_generic, &spr_write_generic,
3485                  0x00000000);
3486     /* XXX : not implemented */
3487     spr_register(env, SPR_440_CCR1, "CCR1",
3488                  SPR_NOACCESS, SPR_NOACCESS,
3489                  &spr_read_generic, &spr_write_generic,
3490                  0x00000000);
3491     /* Memory management */
3492 #if !defined(CONFIG_USER_ONLY)
3493     env->nb_tlb = 64;
3494     env->nb_ways = 1;
3495     env->id_tlbs = 0;
3496 #endif
3497     init_excp_BookE(env);
3498     env->dcache_line_size = 32;
3499     env->icache_line_size = 32;
3500     /* XXX: TODO: allocate internal IRQ controller */
3501 }
3502
3503 /* PowerPC 440 GP                                                            */
3504 #define POWERPC_INSNS_440GP  (PPC_INSNS_BASE | PPC_STRING |                   \
3505                               PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |  \
3506                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3507                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3508                               PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |       \
3509                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3510                               PPC_440_SPEC)
3511 #define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
3512 #define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
3513 #define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
3514 #define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
3515 #define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
3516 #define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3517                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3518 #define check_pow_440GP      check_pow_nocheck
3519
3520 __attribute__ (( unused ))
3521 static void init_proc_440GP (CPUPPCState *env)
3522 {
3523     /* Time base */
3524     gen_tbl(env);
3525     gen_spr_BookE(env, 0x000000000000FFFFULL);
3526     gen_spr_440(env);
3527     gen_spr_usprgh(env);
3528     /* Processor identification */
3529     spr_register(env, SPR_BOOKE_PIR, "PIR",
3530                  SPR_NOACCESS, SPR_NOACCESS,
3531                  &spr_read_generic, &spr_write_pir,
3532                  0x00000000);
3533     /* XXX : not implemented */
3534     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3535                  SPR_NOACCESS, SPR_NOACCESS,
3536                  &spr_read_generic, &spr_write_generic,
3537                  0x00000000);
3538     /* XXX : not implemented */
3539     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3540                  SPR_NOACCESS, SPR_NOACCESS,
3541                  &spr_read_generic, &spr_write_generic,
3542                  0x00000000);
3543     /* XXX : not implemented */
3544     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3545                  SPR_NOACCESS, SPR_NOACCESS,
3546                  &spr_read_generic, &spr_write_generic,
3547                  0x00000000);
3548     /* XXX : not implemented */
3549     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3550                  SPR_NOACCESS, SPR_NOACCESS,
3551                  &spr_read_generic, &spr_write_generic,
3552                  0x00000000);
3553     /* Memory management */
3554 #if !defined(CONFIG_USER_ONLY)
3555     env->nb_tlb = 64;
3556     env->nb_ways = 1;
3557     env->id_tlbs = 0;
3558 #endif
3559     init_excp_BookE(env);
3560     env->dcache_line_size = 32;
3561     env->icache_line_size = 32;
3562     /* XXX: TODO: allocate internal IRQ controller */
3563 }
3564
3565 /* PowerPC 440x4                                                             */
3566 #define POWERPC_INSNS_440x4  (PPC_INSNS_BASE | PPC_STRING |                   \
3567                               PPC_DCR | PPC_WRTEE |                           \
3568                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3569                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3570                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3571                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3572                               PPC_440_SPEC)
3573 #define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
3574 #define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
3575 #define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
3576 #define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
3577 #define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
3578 #define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3579                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3580 #define check_pow_440x4      check_pow_nocheck
3581
3582 __attribute__ (( unused ))
3583 static void init_proc_440x4 (CPUPPCState *env)
3584 {
3585     /* Time base */
3586     gen_tbl(env);
3587     gen_spr_BookE(env, 0x000000000000FFFFULL);
3588     gen_spr_440(env);
3589     gen_spr_usprgh(env);
3590     /* Processor identification */
3591     spr_register(env, SPR_BOOKE_PIR, "PIR",
3592                  SPR_NOACCESS, SPR_NOACCESS,
3593                  &spr_read_generic, &spr_write_pir,
3594                  0x00000000);
3595     /* XXX : not implemented */
3596     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3597                  SPR_NOACCESS, SPR_NOACCESS,
3598                  &spr_read_generic, &spr_write_generic,
3599                  0x00000000);
3600     /* XXX : not implemented */
3601     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3602                  SPR_NOACCESS, SPR_NOACCESS,
3603                  &spr_read_generic, &spr_write_generic,
3604                  0x00000000);
3605     /* XXX : not implemented */
3606     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3607                  SPR_NOACCESS, SPR_NOACCESS,
3608                  &spr_read_generic, &spr_write_generic,
3609                  0x00000000);
3610     /* XXX : not implemented */
3611     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3612                  SPR_NOACCESS, SPR_NOACCESS,
3613                  &spr_read_generic, &spr_write_generic,
3614                  0x00000000);
3615     /* Memory management */
3616 #if !defined(CONFIG_USER_ONLY)
3617     env->nb_tlb = 64;
3618     env->nb_ways = 1;
3619     env->id_tlbs = 0;
3620 #endif
3621     init_excp_BookE(env);
3622     env->dcache_line_size = 32;
3623     env->icache_line_size = 32;
3624     /* XXX: TODO: allocate internal IRQ controller */
3625 }
3626
3627 /* PowerPC 440x5                                                             */
3628 #define POWERPC_INSNS_440x5  (PPC_INSNS_BASE | PPC_STRING |                   \
3629                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3630                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3631                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3632                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3633                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3634                               PPC_440_SPEC)
3635 #define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
3636 #define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
3637 #define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
3638 #define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
3639 #define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
3640 #define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
3641                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3642 #define check_pow_440x5      check_pow_nocheck
3643
3644 static void init_proc_440x5 (CPUPPCState *env)
3645 {
3646     /* Time base */
3647     gen_tbl(env);
3648     gen_spr_BookE(env, 0x000000000000FFFFULL);
3649     gen_spr_440(env);
3650     gen_spr_usprgh(env);
3651     /* Processor identification */
3652     spr_register(env, SPR_BOOKE_PIR, "PIR",
3653                  SPR_NOACCESS, SPR_NOACCESS,
3654                  &spr_read_generic, &spr_write_pir,
3655                  0x00000000);
3656     /* XXX : not implemented */
3657     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3658                  SPR_NOACCESS, SPR_NOACCESS,
3659                  &spr_read_generic, &spr_write_generic,
3660                  0x00000000);
3661     /* XXX : not implemented */
3662     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3663                  SPR_NOACCESS, SPR_NOACCESS,
3664                  &spr_read_generic, &spr_write_generic,
3665                  0x00000000);
3666     /* XXX : not implemented */
3667     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3668                  SPR_NOACCESS, SPR_NOACCESS,
3669                  &spr_read_generic, &spr_write_generic,
3670                  0x00000000);
3671     /* XXX : not implemented */
3672     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3673                  SPR_NOACCESS, SPR_NOACCESS,
3674                  &spr_read_generic, &spr_write_generic,
3675                  0x00000000);
3676     /* XXX : not implemented */
3677     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3678                  SPR_NOACCESS, SPR_NOACCESS,
3679                  &spr_read_generic, &spr_write_generic,
3680                  0x00000000);
3681     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3682                  SPR_NOACCESS, SPR_NOACCESS,
3683                  &spr_read_generic, &spr_write_generic,
3684                  0x00000000);
3685     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3686                  SPR_NOACCESS, SPR_NOACCESS,
3687                  &spr_read_generic, &spr_write_generic,
3688                  0x00000000);
3689     /* XXX : not implemented */
3690     spr_register(env, SPR_440_CCR1, "CCR1",
3691                  SPR_NOACCESS, SPR_NOACCESS,
3692                  &spr_read_generic, &spr_write_generic,
3693                  0x00000000);
3694     /* Memory management */
3695 #if !defined(CONFIG_USER_ONLY)
3696     env->nb_tlb = 64;
3697     env->nb_ways = 1;
3698     env->id_tlbs = 0;
3699 #endif
3700     init_excp_BookE(env);
3701     env->dcache_line_size = 32;
3702     env->icache_line_size = 32;
3703     ppc40x_irq_init(env);
3704 }
3705
3706 /* PowerPC 460 (guessed)                                                     */
3707 #define POWERPC_INSNS_460    (PPC_INSNS_BASE | PPC_STRING |                   \
3708                               PPC_DCR | PPC_DCRX  | PPC_DCRUX |               \
3709                               PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |            \
3710                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3711                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3712                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3713                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3714                               PPC_440_SPEC)
3715 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3716 #define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3717 #define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3718 #define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3719 #define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3720 #define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3721                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3722 #define check_pow_460        check_pow_nocheck
3723
3724 __attribute__ (( unused ))
3725 static void init_proc_460 (CPUPPCState *env)
3726 {
3727     /* Time base */
3728     gen_tbl(env);
3729     gen_spr_BookE(env, 0x000000000000FFFFULL);
3730     gen_spr_440(env);
3731     gen_spr_usprgh(env);
3732     /* Processor identification */
3733     spr_register(env, SPR_BOOKE_PIR, "PIR",
3734                  SPR_NOACCESS, SPR_NOACCESS,
3735                  &spr_read_generic, &spr_write_pir,
3736                  0x00000000);
3737     /* XXX : not implemented */
3738     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3739                  SPR_NOACCESS, SPR_NOACCESS,
3740                  &spr_read_generic, &spr_write_generic,
3741                  0x00000000);
3742     /* XXX : not implemented */
3743     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3744                  SPR_NOACCESS, SPR_NOACCESS,
3745                  &spr_read_generic, &spr_write_generic,
3746                  0x00000000);
3747     /* XXX : not implemented */
3748     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3749                  SPR_NOACCESS, SPR_NOACCESS,
3750                  &spr_read_generic, &spr_write_generic,
3751                  0x00000000);
3752     /* XXX : not implemented */
3753     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3754                  SPR_NOACCESS, SPR_NOACCESS,
3755                  &spr_read_generic, &spr_write_generic,
3756                  0x00000000);
3757     /* XXX : not implemented */
3758     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3759                  SPR_NOACCESS, SPR_NOACCESS,
3760                  &spr_read_generic, &spr_write_generic,
3761                  0x00000000);
3762     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3763                  SPR_NOACCESS, SPR_NOACCESS,
3764                  &spr_read_generic, &spr_write_generic,
3765                  0x00000000);
3766     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3767                  SPR_NOACCESS, SPR_NOACCESS,
3768                  &spr_read_generic, &spr_write_generic,
3769                  0x00000000);
3770     /* XXX : not implemented */
3771     spr_register(env, SPR_440_CCR1, "CCR1",
3772                  SPR_NOACCESS, SPR_NOACCESS,
3773                  &spr_read_generic, &spr_write_generic,
3774                  0x00000000);
3775     /* XXX : not implemented */
3776     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3777                  &spr_read_generic, &spr_write_generic,
3778                  &spr_read_generic, &spr_write_generic,
3779                  0x00000000);
3780     /* Memory management */
3781 #if !defined(CONFIG_USER_ONLY)
3782     env->nb_tlb = 64;
3783     env->nb_ways = 1;
3784     env->id_tlbs = 0;
3785 #endif
3786     init_excp_BookE(env);
3787     env->dcache_line_size = 32;
3788     env->icache_line_size = 32;
3789     /* XXX: TODO: allocate internal IRQ controller */
3790 }
3791
3792 /* PowerPC 460F (guessed)                                                    */
3793 #define POWERPC_INSNS_460F   (PPC_INSNS_BASE | PPC_STRING |                   \
3794                               PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |   \
3795                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
3796                               PPC_FLOAT_STFIWX | PPC_MFTB |                   \
3797                               PPC_DCR | PPC_DCRX | PPC_DCRUX |                \
3798                               PPC_WRTEE | PPC_MFAPIDI |                       \
3799                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3800                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3801                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3802                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3803                               PPC_440_SPEC)
3804 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3805 #define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3806 #define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3807 #define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3808 #define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3809 #define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3810                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3811 #define check_pow_460F       check_pow_nocheck
3812
3813 __attribute__ (( unused ))
3814 static void init_proc_460F (CPUPPCState *env)
3815 {
3816     /* Time base */
3817     gen_tbl(env);
3818     gen_spr_BookE(env, 0x000000000000FFFFULL);
3819     gen_spr_440(env);
3820     gen_spr_usprgh(env);
3821     /* Processor identification */
3822     spr_register(env, SPR_BOOKE_PIR, "PIR",
3823                  SPR_NOACCESS, SPR_NOACCESS,
3824                  &spr_read_generic, &spr_write_pir,
3825                  0x00000000);
3826     /* XXX : not implemented */
3827     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3828                  SPR_NOACCESS, SPR_NOACCESS,
3829                  &spr_read_generic, &spr_write_generic,
3830                  0x00000000);
3831     /* XXX : not implemented */
3832     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3833                  SPR_NOACCESS, SPR_NOACCESS,
3834                  &spr_read_generic, &spr_write_generic,
3835                  0x00000000);
3836     /* XXX : not implemented */
3837     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3838                  SPR_NOACCESS, SPR_NOACCESS,
3839                  &spr_read_generic, &spr_write_generic,
3840                  0x00000000);
3841     /* XXX : not implemented */
3842     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3843                  SPR_NOACCESS, SPR_NOACCESS,
3844                  &spr_read_generic, &spr_write_generic,
3845                  0x00000000);
3846     /* XXX : not implemented */
3847     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3848                  SPR_NOACCESS, SPR_NOACCESS,
3849                  &spr_read_generic, &spr_write_generic,
3850                  0x00000000);
3851     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3852                  SPR_NOACCESS, SPR_NOACCESS,
3853                  &spr_read_generic, &spr_write_generic,
3854                  0x00000000);
3855     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3856                  SPR_NOACCESS, SPR_NOACCESS,
3857                  &spr_read_generic, &spr_write_generic,
3858                  0x00000000);
3859     /* XXX : not implemented */
3860     spr_register(env, SPR_440_CCR1, "CCR1",
3861                  SPR_NOACCESS, SPR_NOACCESS,
3862                  &spr_read_generic, &spr_write_generic,
3863                  0x00000000);
3864     /* XXX : not implemented */
3865     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3866                  &spr_read_generic, &spr_write_generic,
3867                  &spr_read_generic, &spr_write_generic,
3868                  0x00000000);
3869     /* Memory management */
3870 #if !defined(CONFIG_USER_ONLY)
3871     env->nb_tlb = 64;
3872     env->nb_ways = 1;
3873     env->id_tlbs = 0;
3874 #endif
3875     init_excp_BookE(env);
3876     env->dcache_line_size = 32;
3877     env->icache_line_size = 32;
3878     /* XXX: TODO: allocate internal IRQ controller */
3879 }
3880
3881 /* Freescale 5xx cores (aka RCPU) */
3882 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING |                   \
3883                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3884                               PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3885                               PPC_MFTB)
3886 #define POWERPC_MSRM_MPC5xx  (0x000000000001FF43ULL)
3887 #define POWERPC_MMU_MPC5xx   (POWERPC_MMU_REAL)
3888 #define POWERPC_EXCP_MPC5xx  (POWERPC_EXCP_603)
3889 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3890 #define POWERPC_BFDM_MPC5xx  (bfd_mach_ppc_505)
3891 #define POWERPC_FLAG_MPC5xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3892                               POWERPC_FLAG_BUS_CLK)
3893 #define check_pow_MPC5xx     check_pow_none
3894
3895 __attribute__ (( unused ))
3896 static void init_proc_MPC5xx (CPUPPCState *env)
3897 {
3898     /* Time base */
3899     gen_tbl(env);
3900     gen_spr_5xx_8xx(env);
3901     gen_spr_5xx(env);
3902     init_excp_MPC5xx(env);
3903     env->dcache_line_size = 32;
3904     env->icache_line_size = 32;
3905     /* XXX: TODO: allocate internal IRQ controller */
3906 }
3907
3908 /* Freescale 8xx cores (aka PowerQUICC) */
3909 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING  |                  \
3910                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3911                               PPC_CACHE_ICBI | PPC_MFTB)
3912 #define POWERPC_MSRM_MPC8xx  (0x000000000001F673ULL)
3913 #define POWERPC_MMU_MPC8xx   (POWERPC_MMU_MPC8xx)
3914 #define POWERPC_EXCP_MPC8xx  (POWERPC_EXCP_603)
3915 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3916 #define POWERPC_BFDM_MPC8xx  (bfd_mach_ppc_860)
3917 #define POWERPC_FLAG_MPC8xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3918                               POWERPC_FLAG_BUS_CLK)
3919 #define check_pow_MPC8xx     check_pow_none
3920
3921 __attribute__ (( unused ))
3922 static void init_proc_MPC8xx (CPUPPCState *env)
3923 {
3924     /* Time base */
3925     gen_tbl(env);
3926     gen_spr_5xx_8xx(env);
3927     gen_spr_8xx(env);
3928     init_excp_MPC8xx(env);
3929     env->dcache_line_size = 32;
3930     env->icache_line_size = 32;
3931     /* XXX: TODO: allocate internal IRQ controller */
3932 }
3933
3934 /* Freescale 82xx cores (aka PowerQUICC-II)                                  */
3935 /* PowerPC G2                                                                */
3936 #define POWERPC_INSNS_G2     (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3937                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3938                               PPC_FLOAT_STFIWX |                              \
3939                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3940                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3941                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3942                               PPC_SEGMENT | PPC_EXTERN)
3943 #define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3944 #define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3945 //#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3946 #define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3947 #define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3948 #define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3949                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3950 #define check_pow_G2         check_pow_hid0
3951
3952 static void init_proc_G2 (CPUPPCState *env)
3953 {
3954     gen_spr_ne_601(env);
3955     gen_spr_G2_755(env);
3956     gen_spr_G2(env);
3957     /* Time base */
3958     gen_tbl(env);
3959     /* External access control */
3960     /* XXX : not implemented */
3961     spr_register(env, SPR_EAR, "EAR",
3962                  SPR_NOACCESS, SPR_NOACCESS,
3963                  &spr_read_generic, &spr_write_generic,
3964                  0x00000000);
3965     /* Hardware implementation register */
3966     /* XXX : not implemented */
3967     spr_register(env, SPR_HID0, "HID0",
3968                  SPR_NOACCESS, SPR_NOACCESS,
3969                  &spr_read_generic, &spr_write_generic,
3970                  0x00000000);
3971     /* XXX : not implemented */
3972     spr_register(env, SPR_HID1, "HID1",
3973                  SPR_NOACCESS, SPR_NOACCESS,
3974                  &spr_read_generic, &spr_write_generic,
3975                  0x00000000);
3976     /* XXX : not implemented */
3977     spr_register(env, SPR_HID2, "HID2",
3978                  SPR_NOACCESS, SPR_NOACCESS,
3979                  &spr_read_generic, &spr_write_generic,
3980                  0x00000000);
3981     /* Memory management */
3982     gen_low_BATs(env);
3983     gen_high_BATs(env);
3984     gen_6xx_7xx_soft_tlb(env, 64, 2);
3985     init_excp_G2(env);
3986     env->dcache_line_size = 32;
3987     env->icache_line_size = 32;
3988     /* Allocate hardware IRQ controller */
3989     ppc6xx_irq_init(env);
3990 }
3991
3992 /* PowerPC G2LE                                                              */
3993 #define POWERPC_INSNS_G2LE   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3994                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3995                               PPC_FLOAT_STFIWX |                              \
3996                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3997                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3998                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3999                               PPC_SEGMENT | PPC_EXTERN)
4000 #define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
4001 #define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
4002 #define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
4003 #define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
4004 #define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
4005 #define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4006                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4007 #define check_pow_G2LE       check_pow_hid0
4008
4009 static void init_proc_G2LE (CPUPPCState *env)
4010 {
4011     gen_spr_ne_601(env);
4012     gen_spr_G2_755(env);
4013     gen_spr_G2(env);
4014     /* Time base */
4015     gen_tbl(env);
4016     /* External access control */
4017     /* XXX : not implemented */
4018     spr_register(env, SPR_EAR, "EAR",
4019                  SPR_NOACCESS, SPR_NOACCESS,
4020                  &spr_read_generic, &spr_write_generic,
4021                  0x00000000);
4022     /* Hardware implementation register */
4023     /* XXX : not implemented */
4024     spr_register(env, SPR_HID0, "HID0",
4025                  SPR_NOACCESS, SPR_NOACCESS,
4026                  &spr_read_generic, &spr_write_generic,
4027                  0x00000000);
4028     /* XXX : not implemented */
4029     spr_register(env, SPR_HID1, "HID1",
4030                  SPR_NOACCESS, SPR_NOACCESS,
4031                  &spr_read_generic, &spr_write_generic,
4032                  0x00000000);
4033     /* XXX : not implemented */
4034     spr_register(env, SPR_HID2, "HID2",
4035                  SPR_NOACCESS, SPR_NOACCESS,
4036                  &spr_read_generic, &spr_write_generic,
4037                  0x00000000);
4038     /* Memory management */
4039     gen_low_BATs(env);
4040     gen_high_BATs(env);
4041     gen_6xx_7xx_soft_tlb(env, 64, 2);
4042     init_excp_G2(env);
4043     env->dcache_line_size = 32;
4044     env->icache_line_size = 32;
4045     /* Allocate hardware IRQ controller */
4046     ppc6xx_irq_init(env);
4047 }
4048
4049 /* e200 core                                                                 */
4050 /* XXX: unimplemented instructions:
4051  * dcblc
4052  * dcbtlst
4053  * dcbtstls
4054  * icblc
4055  * icbtls
4056  * tlbivax
4057  * all SPE multiply-accumulate instructions
4058  */
4059 #define POWERPC_INSNS_e200   (PPC_INSNS_BASE | PPC_ISEL |                     \
4060                               PPC_SPE | PPC_SPE_SINGLE |                      \
4061                               PPC_WRTEE | PPC_RFDI |                          \
4062                               PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |   \
4063                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
4064                               PPC_MEM_TLBSYNC | PPC_TLBIVAX |                 \
4065                               PPC_BOOKE)
4066 #define POWERPC_MSRM_e200    (0x000000000606FF30ULL)
4067 #define POWERPC_MMU_e200     (POWERPC_MMU_BOOKE_FSL)
4068 #define POWERPC_EXCP_e200    (POWERPC_EXCP_BOOKE)
4069 #define POWERPC_INPUT_e200   (PPC_FLAGS_INPUT_BookE)
4070 #define POWERPC_BFDM_e200    (bfd_mach_ppc_860)
4071 #define POWERPC_FLAG_e200    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
4072                               POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
4073                               POWERPC_FLAG_BUS_CLK)
4074 #define check_pow_e200       check_pow_hid0
4075
4076 __attribute__ (( unused ))
4077 static void init_proc_e200 (CPUPPCState *env)
4078 {
4079     /* Time base */
4080     gen_tbl(env);
4081     gen_spr_BookE(env, 0x000000070000FFFFULL);
4082     /* XXX : not implemented */
4083     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4084                  &spr_read_spefscr, &spr_write_spefscr,
4085                  &spr_read_spefscr, &spr_write_spefscr,
4086                  0x00000000);
4087     /* Memory management */
4088     gen_spr_BookE_FSL(env, 0x0000005D);
4089     /* XXX : not implemented */
4090     spr_register(env, SPR_HID0, "HID0",
4091                  SPR_NOACCESS, SPR_NOACCESS,
4092                  &spr_read_generic, &spr_write_generic,
4093                  0x00000000);
4094     /* XXX : not implemented */
4095     spr_register(env, SPR_HID1, "HID1",
4096                  SPR_NOACCESS, SPR_NOACCESS,
4097                  &spr_read_generic, &spr_write_generic,
4098                  0x00000000);
4099     /* XXX : not implemented */
4100     spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4101                  SPR_NOACCESS, SPR_NOACCESS,
4102                  &spr_read_generic, &spr_write_generic,
4103                  0x00000000);
4104     /* XXX : not implemented */
4105     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4106                  SPR_NOACCESS, SPR_NOACCESS,
4107                  &spr_read_generic, &spr_write_generic,
4108                  0x00000000);
4109     /* XXX : not implemented */
4110     spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4111                  SPR_NOACCESS, SPR_NOACCESS,
4112                  &spr_read_generic, &spr_write_generic,
4113                  0x00000000);
4114     /* XXX : not implemented */
4115     spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4116                  SPR_NOACCESS, SPR_NOACCESS,
4117                  &spr_read_generic, &spr_write_generic,
4118                  0x00000000);
4119     /* XXX : not implemented */
4120     spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4121                  SPR_NOACCESS, SPR_NOACCESS,
4122                  &spr_read_generic, &spr_write_generic,
4123                  0x00000000);
4124     /* XXX : not implemented */
4125     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4126                  SPR_NOACCESS, SPR_NOACCESS,
4127                  &spr_read_generic, &spr_write_generic,
4128                  0x00000000);
4129     /* XXX : not implemented */
4130     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4131                  SPR_NOACCESS, SPR_NOACCESS,
4132                  &spr_read_generic, &spr_write_generic,
4133                  0x00000000);
4134     /* XXX : not implemented */
4135     spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4136                  SPR_NOACCESS, SPR_NOACCESS,
4137                  &spr_read_generic, &spr_write_generic,
4138                  0x00000000);
4139     /* XXX : not implemented */
4140     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4141                  SPR_NOACCESS, SPR_NOACCESS,
4142                  &spr_read_generic, &spr_write_generic,
4143                  0x00000000);
4144     /* XXX : not implemented */
4145     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4146                  SPR_NOACCESS, SPR_NOACCESS,
4147                  &spr_read_generic, &spr_write_generic,
4148                  0x00000000);
4149     /* XXX : not implemented */
4150     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4151                  SPR_NOACCESS, SPR_NOACCESS,
4152                  &spr_read_generic, &spr_write_generic,
4153                  0x00000000);
4154     /* XXX : not implemented */
4155     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4156                  SPR_NOACCESS, SPR_NOACCESS,
4157                  &spr_read_generic, &spr_write_generic,
4158                  0x00000000);
4159     spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4160                  SPR_NOACCESS, SPR_NOACCESS,
4161                  &spr_read_generic, &spr_write_generic,
4162                  0x00000000);
4163     spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4164                  SPR_NOACCESS, SPR_NOACCESS,
4165                  &spr_read_generic, &spr_write_generic,
4166                  0x00000000);
4167 #if !defined(CONFIG_USER_ONLY)
4168     env->nb_tlb = 64;
4169     env->nb_ways = 1;
4170     env->id_tlbs = 0;
4171 #endif
4172     init_excp_e200(env);
4173     env->dcache_line_size = 32;
4174     env->icache_line_size = 32;
4175     /* XXX: TODO: allocate internal IRQ controller */
4176 }
4177
4178 /* e300 core                                                                 */
4179 #define POWERPC_INSNS_e300   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4180                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4181                               PPC_FLOAT_STFIWX |                              \
4182                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4183                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4184                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4185                               PPC_SEGMENT | PPC_EXTERN)
4186 #define POWERPC_MSRM_e300    (0x000000000007FFF3ULL)
4187 #define POWERPC_MMU_e300     (POWERPC_MMU_SOFT_6xx)
4188 #define POWERPC_EXCP_e300    (POWERPC_EXCP_603)
4189 #define POWERPC_INPUT_e300   (PPC_FLAGS_INPUT_6xx)
4190 #define POWERPC_BFDM_e300    (bfd_mach_ppc_603)
4191 #define POWERPC_FLAG_e300    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4192                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4193 #define check_pow_e300       check_pow_hid0
4194
4195 __attribute__ (( unused ))
4196 static void init_proc_e300 (CPUPPCState *env)
4197 {
4198     gen_spr_ne_601(env);
4199     gen_spr_603(env);
4200     /* Time base */
4201     gen_tbl(env);
4202     /* hardware implementation registers */
4203     /* XXX : not implemented */
4204     spr_register(env, SPR_HID0, "HID0",
4205                  SPR_NOACCESS, SPR_NOACCESS,
4206                  &spr_read_generic, &spr_write_generic,
4207                  0x00000000);
4208     /* XXX : not implemented */
4209     spr_register(env, SPR_HID1, "HID1",
4210                  SPR_NOACCESS, SPR_NOACCESS,
4211                  &spr_read_generic, &spr_write_generic,
4212                  0x00000000);
4213     /* XXX : not implemented */
4214     spr_register(env, SPR_HID2, "HID2",
4215                  SPR_NOACCESS, SPR_NOACCESS,
4216                  &spr_read_generic, &spr_write_generic,
4217                  0x00000000);
4218     /* Memory management */
4219     gen_low_BATs(env);
4220     gen_high_BATs(env);
4221     gen_6xx_7xx_soft_tlb(env, 64, 2);
4222     init_excp_603(env);
4223     env->dcache_line_size = 32;
4224     env->icache_line_size = 32;
4225     /* Allocate hardware IRQ controller */
4226     ppc6xx_irq_init(env);
4227 }
4228
4229 /* e500v1 core                                                               */
4230 #define POWERPC_INSNS_e500v1   (PPC_INSNS_BASE | PPC_ISEL |             \
4231                                 PPC_SPE | PPC_SPE_SINGLE |              \
4232                                 PPC_WRTEE | PPC_RFDI |                  \
4233                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4234                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4235                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4236                                 PPC_BOOKE)
4237 #define POWERPC_MSRM_e500v1    (0x000000000606FF30ULL)
4238 #define POWERPC_MMU_e500v1     (POWERPC_MMU_BOOKE_FSL)
4239 #define POWERPC_EXCP_e500v1    (POWERPC_EXCP_BOOKE)
4240 #define POWERPC_INPUT_e500v1   (PPC_FLAGS_INPUT_BookE)
4241 #define POWERPC_BFDM_e500v1    (bfd_mach_ppc_860)
4242 #define POWERPC_FLAG_e500v1    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4243                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4244                                 POWERPC_FLAG_BUS_CLK)
4245 #define check_pow_e500v1       check_pow_hid0
4246 #define init_proc_e500v1       init_proc_e500
4247
4248 /* e500v2 core                                                               */
4249 #define POWERPC_INSNS_e500v2   (PPC_INSNS_BASE | PPC_ISEL |             \
4250                                 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |   \
4251                                 PPC_WRTEE | PPC_RFDI |                  \
4252                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4253                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4254                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4255                                 PPC_BOOKE)
4256 #define POWERPC_MSRM_e500v2    (0x000000000606FF30ULL)
4257 #define POWERPC_MMU_e500v2     (POWERPC_MMU_BOOKE_FSL)
4258 #define POWERPC_EXCP_e500v2    (POWERPC_EXCP_BOOKE)
4259 #define POWERPC_INPUT_e500v2   (PPC_FLAGS_INPUT_BookE)
4260 #define POWERPC_BFDM_e500v2    (bfd_mach_ppc_860)
4261 #define POWERPC_FLAG_e500v2    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4262                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4263                                 POWERPC_FLAG_BUS_CLK)
4264 #define check_pow_e500v2       check_pow_hid0
4265 #define init_proc_e500v2       init_proc_e500
4266
4267 static void init_proc_e500 (CPUPPCState *env)
4268 {
4269     /* Time base */
4270     gen_tbl(env);
4271     gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4272     /* Processor identification */
4273     spr_register(env, SPR_BOOKE_PIR, "PIR",
4274                  SPR_NOACCESS, SPR_NOACCESS,
4275                  &spr_read_generic, &spr_write_pir,
4276                  0x00000000);
4277     /* XXX : not implemented */
4278     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4279                  &spr_read_spefscr, &spr_write_spefscr,
4280                  &spr_read_spefscr, &spr_write_spefscr,
4281                  0x00000000);
4282     /* Memory management */
4283 #if !defined(CONFIG_USER_ONLY)
4284     env->nb_pids = 3;
4285 #endif
4286     gen_spr_BookE_FSL(env, 0x0000005F);
4287     /* XXX : not implemented */
4288     spr_register(env, SPR_HID0, "HID0",
4289                  SPR_NOACCESS, SPR_NOACCESS,
4290                  &spr_read_generic, &spr_write_generic,
4291                  0x00000000);
4292     /* XXX : not implemented */
4293     spr_register(env, SPR_HID1, "HID1",
4294                  SPR_NOACCESS, SPR_NOACCESS,
4295                  &spr_read_generic, &spr_write_generic,
4296                  0x00000000);
4297     /* XXX : not implemented */
4298     spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4299                  SPR_NOACCESS, SPR_NOACCESS,
4300                  &spr_read_generic, &spr_write_generic,
4301                  0x00000000);
4302     /* XXX : not implemented */
4303     spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4304                  SPR_NOACCESS, SPR_NOACCESS,
4305                  &spr_read_generic, &spr_write_generic,
4306                  0x00000000);
4307     /* XXX : not implemented */
4308     spr_register(env, SPR_Exxx_MCAR, "MCAR",
4309                  SPR_NOACCESS, SPR_NOACCESS,
4310                  &spr_read_generic, &spr_write_generic,
4311                  0x00000000);
4312     /* XXX : not implemented */
4313     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4314                  SPR_NOACCESS, SPR_NOACCESS,
4315                  &spr_read_generic, &spr_write_generic,
4316                  0x00000000);
4317     /* XXX : not implemented */
4318     spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4319                  SPR_NOACCESS, SPR_NOACCESS,
4320                  &spr_read_generic, &spr_write_generic,
4321                  0x00000000);
4322     /* XXX : not implemented */
4323     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4324                  SPR_NOACCESS, SPR_NOACCESS,
4325                  &spr_read_generic, &spr_write_generic,
4326                  0x00000000);
4327     /* XXX : not implemented */
4328     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4329                  SPR_NOACCESS, SPR_NOACCESS,
4330                  &spr_read_generic, &spr_write_generic,
4331                  0x00000000);
4332     /* XXX : not implemented */
4333     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4334                  SPR_NOACCESS, SPR_NOACCESS,
4335                  &spr_read_generic, &spr_write_generic,
4336                  0x00000000);
4337     /* XXX : not implemented */
4338     spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4339                  SPR_NOACCESS, SPR_NOACCESS,
4340                  &spr_read_generic, &spr_write_generic,
4341                  0x00000000);
4342     /* XXX : not implemented */
4343     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4344                  SPR_NOACCESS, SPR_NOACCESS,
4345                  &spr_read_generic, &spr_write_generic,
4346                  0x00000000);
4347     /* XXX : not implemented */
4348     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4349                  SPR_NOACCESS, SPR_NOACCESS,
4350                  &spr_read_generic, &spr_write_generic,
4351                  0x00000000);
4352     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4353                  SPR_NOACCESS, SPR_NOACCESS,
4354                  &spr_read_generic, &spr_write_generic,
4355                  0x00000000);
4356     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4357                  SPR_NOACCESS, SPR_NOACCESS,
4358                  &spr_read_generic, &spr_write_generic,
4359                  0x00000000);
4360 #if !defined(CONFIG_USER_ONLY)
4361     env->nb_tlb = 64;
4362     env->nb_ways = 1;
4363     env->id_tlbs = 0;
4364 #endif
4365     init_excp_e200(env);
4366     env->dcache_line_size = 32;
4367     env->icache_line_size = 32;
4368     /* Allocate hardware IRQ controller */
4369     ppce500_irq_init(env);
4370 }
4371
4372 /* Non-embedded PowerPC                                                      */
4373
4374 /* POWER : same as 601, without mfmsr, mfsr                                  */
4375 #if defined(TODO)
4376 #define POWERPC_INSNS_POWER  (XXX_TODO)
4377 /* POWER RSC (from RAD6000) */
4378 #define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
4379 #endif /* TODO */
4380
4381 /* PowerPC 601                                                               */
4382 #define POWERPC_INSNS_601    (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4383                               PPC_FLOAT |                                     \
4384                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4385                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4386                               PPC_SEGMENT | PPC_EXTERN)
4387 #define POWERPC_MSRM_601     (0x000000000000FD70ULL)
4388 #define POWERPC_MSRR_601     (0x0000000000001040ULL)
4389 //#define POWERPC_MMU_601      (POWERPC_MMU_601)
4390 //#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
4391 #define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
4392 #define POWERPC_BFDM_601     (bfd_mach_ppc_601)
4393 #define POWERPC_FLAG_601     (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4394 #define check_pow_601        check_pow_none
4395
4396 static void init_proc_601 (CPUPPCState *env)
4397 {
4398     gen_spr_ne_601(env);
4399     gen_spr_601(env);
4400     /* Hardware implementation registers */
4401     /* XXX : not implemented */
4402     spr_register(env, SPR_HID0, "HID0",
4403                  SPR_NOACCESS, SPR_NOACCESS,
4404                  &spr_read_generic, &spr_write_hid0_601,
4405                  0x80010080);
4406     /* XXX : not implemented */
4407     spr_register(env, SPR_HID1, "HID1",
4408                  SPR_NOACCESS, SPR_NOACCESS,
4409                  &spr_read_generic, &spr_write_generic,
4410                  0x00000000);
4411     /* XXX : not implemented */
4412     spr_register(env, SPR_601_HID2, "HID2",
4413                  SPR_NOACCESS, SPR_NOACCESS,
4414                  &spr_read_generic, &spr_write_generic,
4415                  0x00000000);
4416     /* XXX : not implemented */
4417     spr_register(env, SPR_601_HID5, "HID5",
4418                  SPR_NOACCESS, SPR_NOACCESS,
4419                  &spr_read_generic, &spr_write_generic,
4420                  0x00000000);
4421     /* Memory management */
4422     init_excp_601(env);
4423     /* XXX: beware that dcache line size is 64
4424      *      but dcbz uses 32 bytes "sectors"
4425      * XXX: this breaks clcs instruction !
4426      */
4427     env->dcache_line_size = 32;
4428     env->icache_line_size = 64;
4429     /* Allocate hardware IRQ controller */
4430     ppc6xx_irq_init(env);
4431 }
4432
4433 /* PowerPC 601v                                                              */
4434 #define POWERPC_INSNS_601v   (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4435                               PPC_FLOAT |                                     \
4436                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4437                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4438                               PPC_SEGMENT | PPC_EXTERN)
4439 #define POWERPC_MSRM_601v    (0x000000000000FD70ULL)
4440 #define POWERPC_MSRR_601v    (0x0000000000001040ULL)
4441 #define POWERPC_MMU_601v     (POWERPC_MMU_601)
4442 #define POWERPC_EXCP_601v    (POWERPC_EXCP_601)
4443 #define POWERPC_INPUT_601v   (PPC_FLAGS_INPUT_6xx)
4444 #define POWERPC_BFDM_601v    (bfd_mach_ppc_601)
4445 #define POWERPC_FLAG_601v    (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4446 #define check_pow_601v       check_pow_none
4447
4448 static void init_proc_601v (CPUPPCState *env)
4449 {
4450     init_proc_601(env);
4451     /* XXX : not implemented */
4452     spr_register(env, SPR_601_HID15, "HID15",
4453                  SPR_NOACCESS, SPR_NOACCESS,
4454                  &spr_read_generic, &spr_write_generic,
4455                  0x00000000);
4456 }
4457
4458 /* PowerPC 602                                                               */
4459 #define POWERPC_INSNS_602    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4460                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4461                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4462                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4463                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4464                               PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4465                               PPC_SEGMENT | PPC_602_SPEC)
4466 #define POWERPC_MSRM_602     (0x0000000000C7FF73ULL)
4467 /* XXX: 602 MMU is quite specific. Should add a special case */
4468 #define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
4469 //#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
4470 #define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
4471 #define POWERPC_BFDM_602     (bfd_mach_ppc_602)
4472 #define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4473                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4474 #define check_pow_602        check_pow_hid0
4475
4476 static void init_proc_602 (CPUPPCState *env)
4477 {
4478     gen_spr_ne_601(env);
4479     gen_spr_602(env);
4480     /* Time base */
4481     gen_tbl(env);
4482     /* hardware implementation registers */
4483     /* XXX : not implemented */
4484     spr_register(env, SPR_HID0, "HID0",
4485                  SPR_NOACCESS, SPR_NOACCESS,
4486                  &spr_read_generic, &spr_write_generic,
4487                  0x00000000);
4488     /* XXX : not implemented */
4489     spr_register(env, SPR_HID1, "HID1",
4490                  SPR_NOACCESS, SPR_NOACCESS,
4491                  &spr_read_generic, &spr_write_generic,
4492                  0x00000000);
4493     /* Memory management */
4494     gen_low_BATs(env);
4495     gen_6xx_7xx_soft_tlb(env, 64, 2);
4496     init_excp_602(env);
4497     env->dcache_line_size = 32;
4498     env->icache_line_size = 32;
4499     /* Allocate hardware IRQ controller */
4500     ppc6xx_irq_init(env);
4501 }
4502
4503 /* PowerPC 603                                                               */
4504 #define POWERPC_INSNS_603    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4505                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4506                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4507                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4508                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4509                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4510                               PPC_SEGMENT | PPC_EXTERN)
4511 #define POWERPC_MSRM_603     (0x000000000007FF73ULL)
4512 #define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
4513 //#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
4514 #define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
4515 #define POWERPC_BFDM_603     (bfd_mach_ppc_603)
4516 #define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4517                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4518 #define check_pow_603        check_pow_hid0
4519
4520 static void init_proc_603 (CPUPPCState *env)
4521 {
4522     gen_spr_ne_601(env);
4523     gen_spr_603(env);
4524     /* Time base */
4525     gen_tbl(env);
4526     /* hardware implementation registers */
4527     /* XXX : not implemented */
4528     spr_register(env, SPR_HID0, "HID0",
4529                  SPR_NOACCESS, SPR_NOACCESS,
4530                  &spr_read_generic, &spr_write_generic,
4531                  0x00000000);
4532     /* XXX : not implemented */
4533     spr_register(env, SPR_HID1, "HID1",
4534                  SPR_NOACCESS, SPR_NOACCESS,
4535                  &spr_read_generic, &spr_write_generic,
4536                  0x00000000);
4537     /* Memory management */
4538     gen_low_BATs(env);
4539     gen_6xx_7xx_soft_tlb(env, 64, 2);
4540     init_excp_603(env);
4541     env->dcache_line_size = 32;
4542     env->icache_line_size = 32;
4543     /* Allocate hardware IRQ controller */
4544     ppc6xx_irq_init(env);
4545 }
4546
4547 /* PowerPC 603e                                                              */
4548 #define POWERPC_INSNS_603E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4549                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4550                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4551                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4552                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4553                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4554                               PPC_SEGMENT | PPC_EXTERN)
4555 #define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
4556 #define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
4557 //#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
4558 #define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
4559 #define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
4560 #define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4561                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4562 #define check_pow_603E       check_pow_hid0
4563
4564 static void init_proc_603E (CPUPPCState *env)
4565 {
4566     gen_spr_ne_601(env);
4567     gen_spr_603(env);
4568     /* Time base */
4569     gen_tbl(env);
4570     /* hardware implementation registers */
4571     /* XXX : not implemented */
4572     spr_register(env, SPR_HID0, "HID0",
4573                  SPR_NOACCESS, SPR_NOACCESS,
4574                  &spr_read_generic, &spr_write_generic,
4575                  0x00000000);
4576     /* XXX : not implemented */
4577     spr_register(env, SPR_HID1, "HID1",
4578                  SPR_NOACCESS, SPR_NOACCESS,
4579                  &spr_read_generic, &spr_write_generic,
4580                  0x00000000);
4581     /* XXX : not implemented */
4582     spr_register(env, SPR_IABR, "IABR",
4583                  SPR_NOACCESS, SPR_NOACCESS,
4584                  &spr_read_generic, &spr_write_generic,
4585                  0x00000000);
4586     /* Memory management */
4587     gen_low_BATs(env);
4588     gen_6xx_7xx_soft_tlb(env, 64, 2);
4589     init_excp_603(env);
4590     env->dcache_line_size = 32;
4591     env->icache_line_size = 32;
4592     /* Allocate hardware IRQ controller */
4593     ppc6xx_irq_init(env);
4594 }
4595
4596 /* PowerPC 604                                                               */
4597 #define POWERPC_INSNS_604    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4598                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4599                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4600                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4601                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4602                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4603                               PPC_SEGMENT | PPC_EXTERN)
4604 #define POWERPC_MSRM_604     (0x000000000005FF77ULL)
4605 #define POWERPC_MMU_604      (POWERPC_MMU_32B)
4606 //#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
4607 #define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
4608 #define POWERPC_BFDM_604     (bfd_mach_ppc_604)
4609 #define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4610                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4611 #define check_pow_604        check_pow_nocheck
4612
4613 static void init_proc_604 (CPUPPCState *env)
4614 {
4615     gen_spr_ne_601(env);
4616     gen_spr_604(env);
4617     /* Time base */
4618     gen_tbl(env);
4619     /* Hardware implementation registers */
4620     /* XXX : not implemented */
4621     spr_register(env, SPR_HID0, "HID0",
4622                  SPR_NOACCESS, SPR_NOACCESS,
4623                  &spr_read_generic, &spr_write_generic,
4624                  0x00000000);
4625     /* Memory management */
4626     gen_low_BATs(env);
4627     init_excp_604(env);
4628     env->dcache_line_size = 32;
4629     env->icache_line_size = 32;
4630     /* Allocate hardware IRQ controller */
4631     ppc6xx_irq_init(env);
4632 }
4633
4634 /* PowerPC 604E                                                              */
4635 #define POWERPC_INSNS_604E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4636                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4637                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4638                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4639                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4640                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4641                               PPC_SEGMENT | PPC_EXTERN)
4642 #define POWERPC_MSRM_604E    (0x000000000005FF77ULL)
4643 #define POWERPC_MMU_604E     (POWERPC_MMU_32B)
4644 #define POWERPC_EXCP_604E    (POWERPC_EXCP_604)
4645 #define POWERPC_INPUT_604E   (PPC_FLAGS_INPUT_6xx)
4646 #define POWERPC_BFDM_604E    (bfd_mach_ppc_604)
4647 #define POWERPC_FLAG_604E    (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4648                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4649 #define check_pow_604E       check_pow_nocheck
4650
4651 static void init_proc_604E (CPUPPCState *env)
4652 {
4653     gen_spr_ne_601(env);
4654     gen_spr_604(env);
4655     /* XXX : not implemented */
4656     spr_register(env, SPR_MMCR1, "MMCR1",
4657                  SPR_NOACCESS, SPR_NOACCESS,
4658                  &spr_read_generic, &spr_write_generic,
4659                  0x00000000);
4660     /* XXX : not implemented */
4661     spr_register(env, SPR_PMC3, "PMC3",
4662                  SPR_NOACCESS, SPR_NOACCESS,
4663                  &spr_read_generic, &spr_write_generic,
4664                  0x00000000);
4665     /* XXX : not implemented */
4666     spr_register(env, SPR_PMC4, "PMC4",
4667                  SPR_NOACCESS, SPR_NOACCESS,
4668                  &spr_read_generic, &spr_write_generic,
4669                  0x00000000);
4670     /* Time base */
4671     gen_tbl(env);
4672     /* Hardware implementation registers */
4673     /* XXX : not implemented */
4674     spr_register(env, SPR_HID0, "HID0",
4675                  SPR_NOACCESS, SPR_NOACCESS,
4676                  &spr_read_generic, &spr_write_generic,
4677                  0x00000000);
4678     /* XXX : not implemented */
4679     spr_register(env, SPR_HID1, "HID1",
4680                  SPR_NOACCESS, SPR_NOACCESS,
4681                  &spr_read_generic, &spr_write_generic,
4682                  0x00000000);
4683     /* Memory management */
4684     gen_low_BATs(env);
4685     init_excp_604(env);
4686     env->dcache_line_size = 32;
4687     env->icache_line_size = 32;
4688     /* Allocate hardware IRQ controller */
4689     ppc6xx_irq_init(env);
4690 }
4691
4692 /* PowerPC 740                                                               */
4693 #define POWERPC_INSNS_740    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4694                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4695                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4696                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4697                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4698                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4699                               PPC_SEGMENT | PPC_EXTERN)
4700 #define POWERPC_MSRM_740     (0x000000000005FF77ULL)
4701 #define POWERPC_MMU_740      (POWERPC_MMU_32B)
4702 #define POWERPC_EXCP_740     (POWERPC_EXCP_7x0)
4703 #define POWERPC_INPUT_740    (PPC_FLAGS_INPUT_6xx)
4704 #define POWERPC_BFDM_740     (bfd_mach_ppc_750)
4705 #define POWERPC_FLAG_740     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4706                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4707 #define check_pow_740        check_pow_hid0
4708
4709 static void init_proc_740 (CPUPPCState *env)
4710 {
4711     gen_spr_ne_601(env);
4712     gen_spr_7xx(env);
4713     /* Time base */
4714     gen_tbl(env);
4715     /* Thermal management */
4716     gen_spr_thrm(env);
4717     /* Hardware implementation registers */
4718     /* XXX : not implemented */
4719     spr_register(env, SPR_HID0, "HID0",
4720                  SPR_NOACCESS, SPR_NOACCESS,
4721                  &spr_read_generic, &spr_write_generic,
4722                  0x00000000);
4723     /* XXX : not implemented */
4724     spr_register(env, SPR_HID1, "HID1",
4725                  SPR_NOACCESS, SPR_NOACCESS,
4726                  &spr_read_generic, &spr_write_generic,
4727                  0x00000000);
4728     /* Memory management */
4729     gen_low_BATs(env);
4730     init_excp_7x0(env);
4731     env->dcache_line_size = 32;
4732     env->icache_line_size = 32;
4733     /* Allocate hardware IRQ controller */
4734     ppc6xx_irq_init(env);
4735 }
4736
4737 /* PowerPC 750                                                               */
4738 #define POWERPC_INSNS_750    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4739                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4740                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4741                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4742                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4743                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4744                               PPC_SEGMENT | PPC_EXTERN)
4745 #define POWERPC_MSRM_750     (0x000000000005FF77ULL)
4746 #define POWERPC_MMU_750      (POWERPC_MMU_32B)
4747 #define POWERPC_EXCP_750     (POWERPC_EXCP_7x0)
4748 #define POWERPC_INPUT_750    (PPC_FLAGS_INPUT_6xx)
4749 #define POWERPC_BFDM_750     (bfd_mach_ppc_750)
4750 #define POWERPC_FLAG_750     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4751                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4752 #define check_pow_750        check_pow_hid0
4753
4754 static void init_proc_750 (CPUPPCState *env)
4755 {
4756     gen_spr_ne_601(env);
4757     gen_spr_7xx(env);
4758     /* XXX : not implemented */
4759     spr_register(env, SPR_L2CR, "L2CR",
4760                  SPR_NOACCESS, SPR_NOACCESS,
4761                  &spr_read_generic, &spr_write_generic,
4762                  0x00000000);
4763     /* Time base */
4764     gen_tbl(env);
4765     /* Thermal management */
4766     gen_spr_thrm(env);
4767     /* Hardware implementation registers */
4768     /* XXX : not implemented */
4769     spr_register(env, SPR_HID0, "HID0",
4770                  SPR_NOACCESS, SPR_NOACCESS,
4771                  &spr_read_generic, &spr_write_generic,
4772                  0x00000000);
4773     /* XXX : not implemented */
4774     spr_register(env, SPR_HID1, "HID1",
4775                  SPR_NOACCESS, SPR_NOACCESS,
4776                  &spr_read_generic, &spr_write_generic,
4777                  0x00000000);
4778     /* Memory management */
4779     gen_low_BATs(env);
4780     /* XXX: high BATs are also present but are known to be bugged on
4781      *      die version 1.x
4782      */
4783     init_excp_7x0(env);
4784     env->dcache_line_size = 32;
4785     env->icache_line_size = 32;
4786     /* Allocate hardware IRQ controller */
4787     ppc6xx_irq_init(env);
4788 }
4789
4790 /* PowerPC 750 CL                                                            */
4791 /* XXX: not implemented:
4792  * cache lock instructions:
4793  * dcbz_l
4794  * floating point paired instructions
4795  * psq_lux
4796  * psq_lx
4797  * psq_stux
4798  * psq_stx
4799  * ps_abs
4800  * ps_add
4801  * ps_cmpo0
4802  * ps_cmpo1
4803  * ps_cmpu0
4804  * ps_cmpu1
4805  * ps_div
4806  * ps_madd
4807  * ps_madds0
4808  * ps_madds1
4809  * ps_merge00
4810  * ps_merge01
4811  * ps_merge10
4812  * ps_merge11
4813  * ps_mr
4814  * ps_msub
4815  * ps_mul
4816  * ps_muls0
4817  * ps_muls1
4818  * ps_nabs
4819  * ps_neg
4820  * ps_nmadd
4821  * ps_nmsub
4822  * ps_res
4823  * ps_rsqrte
4824  * ps_sel
4825  * ps_sub
4826  * ps_sum0
4827  * ps_sum1
4828  */
4829 #define POWERPC_INSNS_750cl  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4830                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4831                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4832                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4833                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4834                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4835                               PPC_SEGMENT | PPC_EXTERN)
4836 #define POWERPC_MSRM_750cl   (0x000000000005FF77ULL)
4837 #define POWERPC_MMU_750cl    (POWERPC_MMU_32B)
4838 #define POWERPC_EXCP_750cl   (POWERPC_EXCP_7x0)
4839 #define POWERPC_INPUT_750cl  (PPC_FLAGS_INPUT_6xx)
4840 #define POWERPC_BFDM_750cl   (bfd_mach_ppc_750)
4841 #define POWERPC_FLAG_750cl   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4842                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4843 #define check_pow_750cl      check_pow_hid0
4844
4845 static void init_proc_750cl (CPUPPCState *env)
4846 {
4847     gen_spr_ne_601(env);
4848     gen_spr_7xx(env);
4849     /* XXX : not implemented */
4850     spr_register(env, SPR_L2CR, "L2CR",
4851                  SPR_NOACCESS, SPR_NOACCESS,
4852                  &spr_read_generic, &spr_write_generic,
4853                  0x00000000);
4854     /* Time base */
4855     gen_tbl(env);
4856     /* Thermal management */
4857     /* Those registers are fake on 750CL */
4858     spr_register(env, SPR_THRM1, "THRM1",
4859                  SPR_NOACCESS, SPR_NOACCESS,
4860                  &spr_read_generic, &spr_write_generic,
4861                  0x00000000);
4862     spr_register(env, SPR_THRM2, "THRM2",
4863                  SPR_NOACCESS, SPR_NOACCESS,
4864                  &spr_read_generic, &spr_write_generic,
4865                  0x00000000);
4866     spr_register(env, SPR_THRM3, "THRM3",
4867                  SPR_NOACCESS, SPR_NOACCESS,
4868                  &spr_read_generic, &spr_write_generic,
4869                  0x00000000);
4870     /* XXX: not implemented */
4871     spr_register(env, SPR_750_TDCL, "TDCL",
4872                  SPR_NOACCESS, SPR_NOACCESS,
4873                  &spr_read_generic, &spr_write_generic,
4874                  0x00000000);
4875     spr_register(env, SPR_750_TDCH, "TDCH",
4876                  SPR_NOACCESS, SPR_NOACCESS,
4877                  &spr_read_generic, &spr_write_generic,
4878                  0x00000000);
4879     /* DMA */
4880     /* XXX : not implemented */
4881     spr_register(env, SPR_750_WPAR, "WPAR",
4882                  SPR_NOACCESS, SPR_NOACCESS,
4883                  &spr_read_generic, &spr_write_generic,
4884                  0x00000000);
4885     spr_register(env, SPR_750_DMAL, "DMAL",
4886                  SPR_NOACCESS, SPR_NOACCESS,
4887                  &spr_read_generic, &spr_write_generic,
4888                  0x00000000);
4889     spr_register(env, SPR_750_DMAU, "DMAU",
4890                  SPR_NOACCESS, SPR_NOACCESS,
4891                  &spr_read_generic, &spr_write_generic,
4892                  0x00000000);
4893     /* Hardware implementation registers */
4894     /* XXX : not implemented */
4895     spr_register(env, SPR_HID0, "HID0",
4896                  SPR_NOACCESS, SPR_NOACCESS,
4897                  &spr_read_generic, &spr_write_generic,
4898                  0x00000000);
4899     /* XXX : not implemented */
4900     spr_register(env, SPR_HID1, "HID1",
4901                  SPR_NOACCESS, SPR_NOACCESS,
4902                  &spr_read_generic, &spr_write_generic,
4903                  0x00000000);
4904     /* XXX : not implemented */
4905     spr_register(env, SPR_750CL_HID2, "HID2",
4906                  SPR_NOACCESS, SPR_NOACCESS,
4907                  &spr_read_generic, &spr_write_generic,
4908                  0x00000000);
4909     /* XXX : not implemented */
4910     spr_register(env, SPR_750CL_HID4, "HID4",
4911                  SPR_NOACCESS, SPR_NOACCESS,
4912                  &spr_read_generic, &spr_write_generic,
4913                  0x00000000);
4914     /* Quantization registers */
4915     /* XXX : not implemented */
4916     spr_register(env, SPR_750_GQR0, "GQR0",
4917                  SPR_NOACCESS, SPR_NOACCESS,
4918                  &spr_read_generic, &spr_write_generic,
4919                  0x00000000);
4920     /* XXX : not implemented */
4921     spr_register(env, SPR_750_GQR1, "GQR1",
4922                  SPR_NOACCESS, SPR_NOACCESS,
4923                  &spr_read_generic, &spr_write_generic,
4924                  0x00000000);
4925     /* XXX : not implemented */
4926     spr_register(env, SPR_750_GQR2, "GQR2",
4927                  SPR_NOACCESS, SPR_NOACCESS,
4928                  &spr_read_generic, &spr_write_generic,
4929                  0x00000000);
4930     /* XXX : not implemented */
4931     spr_register(env, SPR_750_GQR3, "GQR3",
4932                  SPR_NOACCESS, SPR_NOACCESS,
4933                  &spr_read_generic, &spr_write_generic,
4934                  0x00000000);
4935     /* XXX : not implemented */
4936     spr_register(env, SPR_750_GQR4, "GQR4",
4937                  SPR_NOACCESS, SPR_NOACCESS,
4938                  &spr_read_generic, &spr_write_generic,
4939                  0x00000000);
4940     /* XXX : not implemented */
4941     spr_register(env, SPR_750_GQR5, "GQR5",
4942                  SPR_NOACCESS, SPR_NOACCESS,
4943                  &spr_read_generic, &spr_write_generic,
4944                  0x00000000);
4945     /* XXX : not implemented */
4946     spr_register(env, SPR_750_GQR6, "GQR6",
4947                  SPR_NOACCESS, SPR_NOACCESS,
4948                  &spr_read_generic, &spr_write_generic,
4949                  0x00000000);
4950     /* XXX : not implemented */
4951     spr_register(env, SPR_750_GQR7, "GQR7",
4952                  SPR_NOACCESS, SPR_NOACCESS,
4953                  &spr_read_generic, &spr_write_generic,
4954                  0x00000000);
4955     /* Memory management */
4956     gen_low_BATs(env);
4957     /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4958     gen_high_BATs(env);
4959     init_excp_750cl(env);
4960     env->dcache_line_size = 32;
4961     env->icache_line_size = 32;
4962     /* Allocate hardware IRQ controller */
4963     ppc6xx_irq_init(env);
4964 }
4965
4966 /* PowerPC 750CX                                                             */
4967 #define POWERPC_INSNS_750cx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4968                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4969                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4970                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4971                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4972                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4973                               PPC_SEGMENT | PPC_EXTERN)
4974 #define POWERPC_MSRM_750cx   (0x000000000005FF77ULL)
4975 #define POWERPC_MMU_750cx    (POWERPC_MMU_32B)
4976 #define POWERPC_EXCP_750cx   (POWERPC_EXCP_7x0)
4977 #define POWERPC_INPUT_750cx  (PPC_FLAGS_INPUT_6xx)
4978 #define POWERPC_BFDM_750cx   (bfd_mach_ppc_750)
4979 #define POWERPC_FLAG_750cx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4980                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4981 #define check_pow_750cx      check_pow_hid0
4982
4983 static void init_proc_750cx (CPUPPCState *env)
4984 {
4985     gen_spr_ne_601(env);
4986     gen_spr_7xx(env);
4987     /* XXX : not implemented */
4988     spr_register(env, SPR_L2CR, "L2CR",
4989                  SPR_NOACCESS, SPR_NOACCESS,
4990                  &spr_read_generic, &spr_write_generic,
4991                  0x00000000);
4992     /* Time base */
4993     gen_tbl(env);
4994     /* Thermal management */
4995     gen_spr_thrm(env);
4996     /* This register is not implemented but is present for compatibility */
4997     spr_register(env, SPR_SDA, "SDA",
4998                  SPR_NOACCESS, SPR_NOACCESS,
4999                  &spr_read_generic, &spr_write_generic,
5000                  0x00000000);
5001     /* Hardware implementation registers */
5002     /* XXX : not implemented */
5003     spr_register(env, SPR_HID0, "HID0",
5004                  SPR_NOACCESS, SPR_NOACCESS,
5005                  &spr_read_generic, &spr_write_generic,
5006                  0x00000000);
5007     /* XXX : not implemented */
5008     spr_register(env, SPR_HID1, "HID1",
5009                  SPR_NOACCESS, SPR_NOACCESS,
5010                  &spr_read_generic, &spr_write_generic,
5011                  0x00000000);
5012     /* Memory management */
5013     gen_low_BATs(env);
5014     /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5015     gen_high_BATs(env);
5016     init_excp_750cx(env);
5017     env->dcache_line_size = 32;
5018     env->icache_line_size = 32;
5019     /* Allocate hardware IRQ controller */
5020     ppc6xx_irq_init(env);
5021 }
5022
5023 /* PowerPC 750FX                                                             */
5024 #define POWERPC_INSNS_750fx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5025                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5026                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5027                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5028                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5029                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5030                               PPC_SEGMENT  | PPC_EXTERN)
5031 #define POWERPC_MSRM_750fx   (0x000000000005FF77ULL)
5032 #define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
5033 #define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
5034 #define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
5035 #define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
5036 #define POWERPC_FLAG_750fx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5037                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5038 #define check_pow_750fx      check_pow_hid0
5039
5040 static void init_proc_750fx (CPUPPCState *env)
5041 {
5042     gen_spr_ne_601(env);
5043     gen_spr_7xx(env);
5044     /* XXX : not implemented */
5045     spr_register(env, SPR_L2CR, "L2CR",
5046                  SPR_NOACCESS, SPR_NOACCESS,
5047                  &spr_read_generic, &spr_write_generic,
5048                  0x00000000);
5049     /* Time base */
5050     gen_tbl(env);
5051     /* Thermal management */
5052     gen_spr_thrm(env);
5053     /* XXX : not implemented */
5054     spr_register(env, SPR_750_THRM4, "THRM4",
5055                  SPR_NOACCESS, SPR_NOACCESS,
5056                  &spr_read_generic, &spr_write_generic,
5057                  0x00000000);
5058     /* Hardware implementation registers */
5059     /* XXX : not implemented */
5060     spr_register(env, SPR_HID0, "HID0",
5061                  SPR_NOACCESS, SPR_NOACCESS,
5062                  &spr_read_generic, &spr_write_generic,
5063                  0x00000000);
5064     /* XXX : not implemented */
5065     spr_register(env, SPR_HID1, "HID1",
5066                  SPR_NOACCESS, SPR_NOACCESS,
5067                  &spr_read_generic, &spr_write_generic,
5068                  0x00000000);
5069     /* XXX : not implemented */
5070     spr_register(env, SPR_750FX_HID2, "HID2",
5071                  SPR_NOACCESS, SPR_NOACCESS,
5072                  &spr_read_generic, &spr_write_generic,
5073                  0x00000000);
5074     /* Memory management */
5075     gen_low_BATs(env);
5076     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5077     gen_high_BATs(env);
5078     init_excp_7x0(env);
5079     env->dcache_line_size = 32;
5080     env->icache_line_size = 32;
5081     /* Allocate hardware IRQ controller */
5082     ppc6xx_irq_init(env);
5083 }
5084
5085 /* PowerPC 750GX                                                             */
5086 #define POWERPC_INSNS_750gx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5087                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5088                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5089                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5090                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5091                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5092                               PPC_SEGMENT  | PPC_EXTERN)
5093 #define POWERPC_MSRM_750gx   (0x000000000005FF77ULL)
5094 #define POWERPC_MMU_750gx    (POWERPC_MMU_32B)
5095 #define POWERPC_EXCP_750gx   (POWERPC_EXCP_7x0)
5096 #define POWERPC_INPUT_750gx  (PPC_FLAGS_INPUT_6xx)
5097 #define POWERPC_BFDM_750gx   (bfd_mach_ppc_750)
5098 #define POWERPC_FLAG_750gx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5099                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5100 #define check_pow_750gx      check_pow_hid0
5101
5102 static void init_proc_750gx (CPUPPCState *env)
5103 {
5104     gen_spr_ne_601(env);
5105     gen_spr_7xx(env);
5106     /* XXX : not implemented (XXX: different from 750fx) */
5107     spr_register(env, SPR_L2CR, "L2CR",
5108                  SPR_NOACCESS, SPR_NOACCESS,
5109                  &spr_read_generic, &spr_write_generic,
5110                  0x00000000);
5111     /* Time base */
5112     gen_tbl(env);
5113     /* Thermal management */
5114     gen_spr_thrm(env);
5115     /* XXX : not implemented */
5116     spr_register(env, SPR_750_THRM4, "THRM4",
5117                  SPR_NOACCESS, SPR_NOACCESS,
5118                  &spr_read_generic, &spr_write_generic,
5119                  0x00000000);
5120     /* Hardware implementation registers */
5121     /* XXX : not implemented (XXX: different from 750fx) */
5122     spr_register(env, SPR_HID0, "HID0",
5123                  SPR_NOACCESS, SPR_NOACCESS,
5124                  &spr_read_generic, &spr_write_generic,
5125                  0x00000000);
5126     /* XXX : not implemented */
5127     spr_register(env, SPR_HID1, "HID1",
5128                  SPR_NOACCESS, SPR_NOACCESS,
5129                  &spr_read_generic, &spr_write_generic,
5130                  0x00000000);
5131     /* XXX : not implemented (XXX: different from 750fx) */
5132     spr_register(env, SPR_750FX_HID2, "HID2",
5133                  SPR_NOACCESS, SPR_NOACCESS,
5134                  &spr_read_generic, &spr_write_generic,
5135                  0x00000000);
5136     /* Memory management */
5137     gen_low_BATs(env);
5138     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5139     gen_high_BATs(env);
5140     init_excp_7x0(env);
5141     env->dcache_line_size = 32;
5142     env->icache_line_size = 32;
5143     /* Allocate hardware IRQ controller */
5144     ppc6xx_irq_init(env);
5145 }
5146
5147 /* PowerPC 745                                                               */
5148 #define POWERPC_INSNS_745    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5149                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5150                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5151                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5152                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5153                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5154                               PPC_SEGMENT | PPC_EXTERN)
5155 #define POWERPC_MSRM_745     (0x000000000005FF77ULL)
5156 #define POWERPC_MMU_745      (POWERPC_MMU_SOFT_6xx)
5157 #define POWERPC_EXCP_745     (POWERPC_EXCP_7x5)
5158 #define POWERPC_INPUT_745    (PPC_FLAGS_INPUT_6xx)
5159 #define POWERPC_BFDM_745     (bfd_mach_ppc_750)
5160 #define POWERPC_FLAG_745     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5161                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5162 #define check_pow_745        check_pow_hid0
5163
5164 static void init_proc_745 (CPUPPCState *env)
5165 {
5166     gen_spr_ne_601(env);
5167     gen_spr_7xx(env);
5168     gen_spr_G2_755(env);
5169     /* Time base */
5170     gen_tbl(env);
5171     /* Thermal management */
5172     gen_spr_thrm(env);
5173     /* Hardware implementation registers */
5174     /* XXX : not implemented */
5175     spr_register(env, SPR_HID0, "HID0",
5176                  SPR_NOACCESS, SPR_NOACCESS,
5177                  &spr_read_generic, &spr_write_generic,
5178                  0x00000000);
5179     /* XXX : not implemented */
5180     spr_register(env, SPR_HID1, "HID1",
5181                  SPR_NOACCESS, SPR_NOACCESS,
5182                  &spr_read_generic, &spr_write_generic,
5183                  0x00000000);
5184     /* XXX : not implemented */
5185     spr_register(env, SPR_HID2, "HID2",
5186                  SPR_NOACCESS, SPR_NOACCESS,
5187                  &spr_read_generic, &spr_write_generic,
5188                  0x00000000);
5189     /* Memory management */
5190     gen_low_BATs(env);
5191     gen_high_BATs(env);
5192     gen_6xx_7xx_soft_tlb(env, 64, 2);
5193     init_excp_7x5(env);
5194     env->dcache_line_size = 32;
5195     env->icache_line_size = 32;
5196     /* Allocate hardware IRQ controller */
5197     ppc6xx_irq_init(env);
5198 }
5199
5200 /* PowerPC 755                                                               */
5201 #define POWERPC_INSNS_755    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5202                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5203                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5204                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5205                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5206                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5207                               PPC_SEGMENT | PPC_EXTERN)
5208 #define POWERPC_MSRM_755     (0x000000000005FF77ULL)
5209 #define POWERPC_MMU_755      (POWERPC_MMU_SOFT_6xx)
5210 #define POWERPC_EXCP_755     (POWERPC_EXCP_7x5)
5211 #define POWERPC_INPUT_755    (PPC_FLAGS_INPUT_6xx)
5212 #define POWERPC_BFDM_755     (bfd_mach_ppc_750)
5213 #define POWERPC_FLAG_755     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5214                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5215 #define check_pow_755        check_pow_hid0
5216
5217 static void init_proc_755 (CPUPPCState *env)
5218 {
5219     gen_spr_ne_601(env);
5220     gen_spr_7xx(env);
5221     gen_spr_G2_755(env);
5222     /* Time base */
5223     gen_tbl(env);
5224     /* L2 cache control */
5225     /* XXX : not implemented */
5226     spr_register(env, SPR_L2CR, "L2CR",
5227                  SPR_NOACCESS, SPR_NOACCESS,
5228                  &spr_read_generic, &spr_write_generic,
5229                  0x00000000);
5230     /* XXX : not implemented */
5231     spr_register(env, SPR_L2PMCR, "L2PMCR",
5232                  SPR_NOACCESS, SPR_NOACCESS,
5233                  &spr_read_generic, &spr_write_generic,
5234                  0x00000000);
5235     /* Thermal management */
5236     gen_spr_thrm(env);
5237     /* Hardware implementation registers */
5238     /* XXX : not implemented */
5239     spr_register(env, SPR_HID0, "HID0",
5240                  SPR_NOACCESS, SPR_NOACCESS,
5241                  &spr_read_generic, &spr_write_generic,
5242                  0x00000000);
5243     /* XXX : not implemented */
5244     spr_register(env, SPR_HID1, "HID1",
5245                  SPR_NOACCESS, SPR_NOACCESS,
5246                  &spr_read_generic, &spr_write_generic,
5247                  0x00000000);
5248     /* XXX : not implemented */
5249     spr_register(env, SPR_HID2, "HID2",
5250                  SPR_NOACCESS, SPR_NOACCESS,
5251                  &spr_read_generic, &spr_write_generic,
5252                  0x00000000);
5253     /* Memory management */
5254     gen_low_BATs(env);
5255     gen_high_BATs(env);
5256     gen_6xx_7xx_soft_tlb(env, 64, 2);
5257     init_excp_7x5(env);
5258     env->dcache_line_size = 32;
5259     env->icache_line_size = 32;
5260     /* Allocate hardware IRQ controller */
5261     ppc6xx_irq_init(env);
5262 }
5263
5264 /* PowerPC 7400 (aka G4)                                                     */
5265 #define POWERPC_INSNS_7400   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5266                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5267                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5268                               PPC_FLOAT_STFIWX |                              \
5269                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5270                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5271                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5272                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5273                               PPC_MEM_TLBIA |                                 \
5274                               PPC_SEGMENT | PPC_EXTERN |                      \
5275                               PPC_ALTIVEC)
5276 #define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
5277 #define POWERPC_MMU_7400     (POWERPC_MMU_32B)
5278 #define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
5279 #define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
5280 #define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
5281 #define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5282                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5283                               POWERPC_FLAG_BUS_CLK)
5284 #define check_pow_7400       check_pow_hid0
5285
5286 static void init_proc_7400 (CPUPPCState *env)
5287 {
5288     gen_spr_ne_601(env);
5289     gen_spr_7xx(env);
5290     /* Time base */
5291     gen_tbl(env);
5292     /* 74xx specific SPR */
5293     gen_spr_74xx(env);
5294     /* XXX : not implemented */
5295     spr_register(env, SPR_UBAMR, "UBAMR",
5296                  &spr_read_ureg, SPR_NOACCESS,
5297                  &spr_read_ureg, SPR_NOACCESS,
5298                  0x00000000);
5299     /* XXX: this seems not implemented on all revisions. */
5300     /* XXX : not implemented */
5301     spr_register(env, SPR_MSSCR1, "MSSCR1",
5302                  SPR_NOACCESS, SPR_NOACCESS,
5303                  &spr_read_generic, &spr_write_generic,
5304                  0x00000000);
5305     /* Thermal management */
5306     gen_spr_thrm(env);
5307     /* Memory management */
5308     gen_low_BATs(env);
5309     init_excp_7400(env);
5310     env->dcache_line_size = 32;
5311     env->icache_line_size = 32;
5312     /* Allocate hardware IRQ controller */
5313     ppc6xx_irq_init(env);
5314 }
5315
5316 /* PowerPC 7410 (aka G4)                                                     */
5317 #define POWERPC_INSNS_7410   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5318                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5319                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5320                               PPC_FLOAT_STFIWX |                              \
5321                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5322                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5323                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5324                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5325                               PPC_MEM_TLBIA |                                 \
5326                               PPC_SEGMENT | PPC_EXTERN |                      \
5327                               PPC_ALTIVEC)
5328 #define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
5329 #define POWERPC_MMU_7410     (POWERPC_MMU_32B)
5330 #define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
5331 #define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
5332 #define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
5333 #define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5334                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5335                               POWERPC_FLAG_BUS_CLK)
5336 #define check_pow_7410       check_pow_hid0
5337
5338 static void init_proc_7410 (CPUPPCState *env)
5339 {
5340     gen_spr_ne_601(env);
5341     gen_spr_7xx(env);
5342     /* Time base */
5343     gen_tbl(env);
5344     /* 74xx specific SPR */
5345     gen_spr_74xx(env);
5346     /* XXX : not implemented */
5347     spr_register(env, SPR_UBAMR, "UBAMR",
5348                  &spr_read_ureg, SPR_NOACCESS,
5349                  &spr_read_ureg, SPR_NOACCESS,
5350                  0x00000000);
5351     /* Thermal management */
5352     gen_spr_thrm(env);
5353     /* L2PMCR */
5354     /* XXX : not implemented */
5355     spr_register(env, SPR_L2PMCR, "L2PMCR",
5356                  SPR_NOACCESS, SPR_NOACCESS,
5357                  &spr_read_generic, &spr_write_generic,
5358                  0x00000000);
5359     /* LDSTDB */
5360     /* XXX : not implemented */
5361     spr_register(env, SPR_LDSTDB, "LDSTDB",
5362                  SPR_NOACCESS, SPR_NOACCESS,
5363                  &spr_read_generic, &spr_write_generic,
5364                  0x00000000);
5365     /* Memory management */
5366     gen_low_BATs(env);
5367     init_excp_7400(env);
5368     env->dcache_line_size = 32;
5369     env->icache_line_size = 32;
5370     /* Allocate hardware IRQ controller */
5371     ppc6xx_irq_init(env);
5372 }
5373
5374 /* PowerPC 7440 (aka G4)                                                     */
5375 #define POWERPC_INSNS_7440   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5376                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5377                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5378                               PPC_FLOAT_STFIWX |                              \
5379                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5380                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5381                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5382                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5383                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5384                               PPC_SEGMENT | PPC_EXTERN |                      \
5385                               PPC_ALTIVEC)
5386 #define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
5387 #define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
5388 #define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
5389 #define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
5390 #define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
5391 #define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5392                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5393                               POWERPC_FLAG_BUS_CLK)
5394 #define check_pow_7440       check_pow_hid0_74xx
5395
5396 __attribute__ (( unused ))
5397 static void init_proc_7440 (CPUPPCState *env)
5398 {
5399     gen_spr_ne_601(env);
5400     gen_spr_7xx(env);
5401     /* Time base */
5402     gen_tbl(env);
5403     /* 74xx specific SPR */
5404     gen_spr_74xx(env);
5405     /* XXX : not implemented */
5406     spr_register(env, SPR_UBAMR, "UBAMR",
5407                  &spr_read_ureg, SPR_NOACCESS,
5408                  &spr_read_ureg, SPR_NOACCESS,
5409                  0x00000000);
5410     /* LDSTCR */
5411     /* XXX : not implemented */
5412     spr_register(env, SPR_LDSTCR, "LDSTCR",
5413                  SPR_NOACCESS, SPR_NOACCESS,
5414                  &spr_read_generic, &spr_write_generic,
5415                  0x00000000);
5416     /* ICTRL */
5417     /* XXX : not implemented */
5418     spr_register(env, SPR_ICTRL, "ICTRL",
5419                  SPR_NOACCESS, SPR_NOACCESS,
5420                  &spr_read_generic, &spr_write_generic,
5421                  0x00000000);
5422     /* MSSSR0 */
5423     /* XXX : not implemented */
5424     spr_register(env, SPR_MSSSR0, "MSSSR0",
5425                  SPR_NOACCESS, SPR_NOACCESS,
5426                  &spr_read_generic, &spr_write_generic,
5427                  0x00000000);
5428     /* PMC */
5429     /* XXX : not implemented */
5430     spr_register(env, SPR_PMC5, "PMC5",
5431                  SPR_NOACCESS, SPR_NOACCESS,
5432                  &spr_read_generic, &spr_write_generic,
5433                  0x00000000);
5434     /* XXX : not implemented */
5435     spr_register(env, SPR_UPMC5, "UPMC5",
5436                  &spr_read_ureg, SPR_NOACCESS,
5437                  &spr_read_ureg, SPR_NOACCESS,
5438                  0x00000000);
5439     /* XXX : not implemented */
5440     spr_register(env, SPR_PMC6, "PMC6",
5441                  SPR_NOACCESS, SPR_NOACCESS,
5442                  &spr_read_generic, &spr_write_generic,
5443                  0x00000000);
5444     /* XXX : not implemented */
5445     spr_register(env, SPR_UPMC6, "UPMC6",
5446                  &spr_read_ureg, SPR_NOACCESS,
5447                  &spr_read_ureg, SPR_NOACCESS,
5448                  0x00000000);
5449     /* Memory management */
5450     gen_low_BATs(env);
5451     gen_74xx_soft_tlb(env, 128, 2);
5452     init_excp_7450(env);
5453     env->dcache_line_size = 32;
5454     env->icache_line_size = 32;
5455     /* Allocate hardware IRQ controller */
5456     ppc6xx_irq_init(env);
5457 }
5458
5459 /* PowerPC 7450 (aka G4)                                                     */
5460 #define POWERPC_INSNS_7450   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5461                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5462                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5463                               PPC_FLOAT_STFIWX |                              \
5464                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5465                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5466                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5467                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5468                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5469                               PPC_SEGMENT | PPC_EXTERN |                      \
5470                               PPC_ALTIVEC)
5471 #define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
5472 #define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
5473 #define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
5474 #define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
5475 #define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
5476 #define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5477                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5478                               POWERPC_FLAG_BUS_CLK)
5479 #define check_pow_7450       check_pow_hid0_74xx
5480
5481 __attribute__ (( unused ))
5482 static void init_proc_7450 (CPUPPCState *env)
5483 {
5484     gen_spr_ne_601(env);
5485     gen_spr_7xx(env);
5486     /* Time base */
5487     gen_tbl(env);
5488     /* 74xx specific SPR */
5489     gen_spr_74xx(env);
5490     /* Level 3 cache control */
5491     gen_l3_ctrl(env);
5492     /* L3ITCR1 */
5493     /* XXX : not implemented */
5494     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5495                  SPR_NOACCESS, SPR_NOACCESS,
5496                  &spr_read_generic, &spr_write_generic,
5497                  0x00000000);
5498     /* L3ITCR2 */
5499     /* XXX : not implemented */
5500     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5501                  SPR_NOACCESS, SPR_NOACCESS,
5502                  &spr_read_generic, &spr_write_generic,
5503                  0x00000000);
5504     /* L3ITCR3 */
5505     /* XXX : not implemented */
5506     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5507                  SPR_NOACCESS, SPR_NOACCESS,
5508                  &spr_read_generic, &spr_write_generic,
5509                  0x00000000);
5510     /* L3OHCR */
5511     /* XXX : not implemented */
5512     spr_register(env, SPR_L3OHCR, "L3OHCR",
5513                  SPR_NOACCESS, SPR_NOACCESS,
5514                  &spr_read_generic, &spr_write_generic,
5515                  0x00000000);
5516     /* XXX : not implemented */
5517     spr_register(env, SPR_UBAMR, "UBAMR",
5518                  &spr_read_ureg, SPR_NOACCESS,
5519                  &spr_read_ureg, SPR_NOACCESS,
5520                  0x00000000);
5521     /* LDSTCR */
5522     /* XXX : not implemented */
5523     spr_register(env, SPR_LDSTCR, "LDSTCR",
5524                  SPR_NOACCESS, SPR_NOACCESS,
5525                  &spr_read_generic, &spr_write_generic,
5526                  0x00000000);
5527     /* ICTRL */
5528     /* XXX : not implemented */
5529     spr_register(env, SPR_ICTRL, "ICTRL",
5530                  SPR_NOACCESS, SPR_NOACCESS,
5531                  &spr_read_generic, &spr_write_generic,
5532                  0x00000000);
5533     /* MSSSR0 */
5534     /* XXX : not implemented */
5535     spr_register(env, SPR_MSSSR0, "MSSSR0",
5536                  SPR_NOACCESS, SPR_NOACCESS,
5537                  &spr_read_generic, &spr_write_generic,
5538                  0x00000000);
5539     /* PMC */
5540     /* XXX : not implemented */
5541     spr_register(env, SPR_PMC5, "PMC5",
5542                  SPR_NOACCESS, SPR_NOACCESS,
5543                  &spr_read_generic, &spr_write_generic,
5544                  0x00000000);
5545     /* XXX : not implemented */
5546     spr_register(env, SPR_UPMC5, "UPMC5",
5547                  &spr_read_ureg, SPR_NOACCESS,
5548                  &spr_read_ureg, SPR_NOACCESS,
5549                  0x00000000);
5550     /* XXX : not implemented */
5551     spr_register(env, SPR_PMC6, "PMC6",
5552                  SPR_NOACCESS, SPR_NOACCESS,
5553                  &spr_read_generic, &spr_write_generic,
5554                  0x00000000);
5555     /* XXX : not implemented */
5556     spr_register(env, SPR_UPMC6, "UPMC6",
5557                  &spr_read_ureg, SPR_NOACCESS,
5558                  &spr_read_ureg, SPR_NOACCESS,
5559                  0x00000000);
5560     /* Memory management */
5561     gen_low_BATs(env);
5562     gen_74xx_soft_tlb(env, 128, 2);
5563     init_excp_7450(env);
5564     env->dcache_line_size = 32;
5565     env->icache_line_size = 32;
5566     /* Allocate hardware IRQ controller */
5567     ppc6xx_irq_init(env);
5568 }
5569
5570 /* PowerPC 7445 (aka G4)                                                     */
5571 #define POWERPC_INSNS_7445   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5572                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5573                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5574                               PPC_FLOAT_STFIWX |                              \
5575                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5576                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5577                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5578                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5579                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5580                               PPC_SEGMENT | PPC_EXTERN |                      \
5581                               PPC_ALTIVEC)
5582 #define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
5583 #define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
5584 #define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
5585 #define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
5586 #define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
5587 #define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5588                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5589                               POWERPC_FLAG_BUS_CLK)
5590 #define check_pow_7445       check_pow_hid0_74xx
5591
5592 __attribute__ (( unused ))
5593 static void init_proc_7445 (CPUPPCState *env)
5594 {
5595     gen_spr_ne_601(env);
5596     gen_spr_7xx(env);
5597     /* Time base */
5598     gen_tbl(env);
5599     /* 74xx specific SPR */
5600     gen_spr_74xx(env);
5601     /* LDSTCR */
5602     /* XXX : not implemented */
5603     spr_register(env, SPR_LDSTCR, "LDSTCR",
5604                  SPR_NOACCESS, SPR_NOACCESS,
5605                  &spr_read_generic, &spr_write_generic,
5606                  0x00000000);
5607     /* ICTRL */
5608     /* XXX : not implemented */
5609     spr_register(env, SPR_ICTRL, "ICTRL",
5610                  SPR_NOACCESS, SPR_NOACCESS,
5611                  &spr_read_generic, &spr_write_generic,
5612                  0x00000000);
5613     /* MSSSR0 */
5614     /* XXX : not implemented */
5615     spr_register(env, SPR_MSSSR0, "MSSSR0",
5616                  SPR_NOACCESS, SPR_NOACCESS,
5617                  &spr_read_generic, &spr_write_generic,
5618                  0x00000000);
5619     /* PMC */
5620     /* XXX : not implemented */
5621     spr_register(env, SPR_PMC5, "PMC5",
5622                  SPR_NOACCESS, SPR_NOACCESS,
5623                  &spr_read_generic, &spr_write_generic,
5624                  0x00000000);
5625     /* XXX : not implemented */
5626     spr_register(env, SPR_UPMC5, "UPMC5",
5627                  &spr_read_ureg, SPR_NOACCESS,
5628                  &spr_read_ureg, SPR_NOACCESS,
5629                  0x00000000);
5630     /* XXX : not implemented */
5631     spr_register(env, SPR_PMC6, "PMC6",
5632                  SPR_NOACCESS, SPR_NOACCESS,
5633                  &spr_read_generic, &spr_write_generic,
5634                  0x00000000);
5635     /* XXX : not implemented */
5636     spr_register(env, SPR_UPMC6, "UPMC6",
5637                  &spr_read_ureg, SPR_NOACCESS,
5638                  &spr_read_ureg, SPR_NOACCESS,
5639                  0x00000000);
5640     /* SPRGs */
5641     spr_register(env, SPR_SPRG4, "SPRG4",
5642                  SPR_NOACCESS, SPR_NOACCESS,
5643                  &spr_read_generic, &spr_write_generic,
5644                  0x00000000);
5645     spr_register(env, SPR_USPRG4, "USPRG4",
5646                  &spr_read_ureg, SPR_NOACCESS,
5647                  &spr_read_ureg, SPR_NOACCESS,
5648                  0x00000000);
5649     spr_register(env, SPR_SPRG5, "SPRG5",
5650                  SPR_NOACCESS, SPR_NOACCESS,
5651                  &spr_read_generic, &spr_write_generic,
5652                  0x00000000);
5653     spr_register(env, SPR_USPRG5, "USPRG5",
5654                  &spr_read_ureg, SPR_NOACCESS,
5655                  &spr_read_ureg, SPR_NOACCESS,
5656                  0x00000000);
5657     spr_register(env, SPR_SPRG6, "SPRG6",
5658                  SPR_NOACCESS, SPR_NOACCESS,
5659                  &spr_read_generic, &spr_write_generic,
5660                  0x00000000);
5661     spr_register(env, SPR_USPRG6, "USPRG6",
5662                  &spr_read_ureg, SPR_NOACCESS,
5663                  &spr_read_ureg, SPR_NOACCESS,
5664                  0x00000000);
5665     spr_register(env, SPR_SPRG7, "SPRG7",
5666                  SPR_NOACCESS, SPR_NOACCESS,
5667                  &spr_read_generic, &spr_write_generic,
5668                  0x00000000);
5669     spr_register(env, SPR_USPRG7, "USPRG7",
5670                  &spr_read_ureg, SPR_NOACCESS,
5671                  &spr_read_ureg, SPR_NOACCESS,
5672                  0x00000000);
5673     /* Memory management */
5674     gen_low_BATs(env);
5675     gen_high_BATs(env);
5676     gen_74xx_soft_tlb(env, 128, 2);
5677     init_excp_7450(env);
5678     env->dcache_line_size = 32;
5679     env->icache_line_size = 32;
5680     /* Allocate hardware IRQ controller */
5681     ppc6xx_irq_init(env);
5682 }
5683
5684 /* PowerPC 7455 (aka G4)                                                     */
5685 #define POWERPC_INSNS_7455   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5686                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5687                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5688                               PPC_FLOAT_STFIWX |                              \
5689                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5690                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5691                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5692                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5693                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5694                               PPC_SEGMENT | PPC_EXTERN |                      \
5695                               PPC_ALTIVEC)
5696 #define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
5697 #define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
5698 #define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
5699 #define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
5700 #define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
5701 #define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5702                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5703                               POWERPC_FLAG_BUS_CLK)
5704 #define check_pow_7455       check_pow_hid0_74xx
5705
5706 __attribute__ (( unused ))
5707 static void init_proc_7455 (CPUPPCState *env)
5708 {
5709     gen_spr_ne_601(env);
5710     gen_spr_7xx(env);
5711     /* Time base */
5712     gen_tbl(env);
5713     /* 74xx specific SPR */
5714     gen_spr_74xx(env);
5715     /* Level 3 cache control */
5716     gen_l3_ctrl(env);
5717     /* LDSTCR */
5718     /* XXX : not implemented */
5719     spr_register(env, SPR_LDSTCR, "LDSTCR",
5720                  SPR_NOACCESS, SPR_NOACCESS,
5721                  &spr_read_generic, &spr_write_generic,
5722                  0x00000000);
5723     /* ICTRL */
5724     /* XXX : not implemented */
5725     spr_register(env, SPR_ICTRL, "ICTRL",
5726                  SPR_NOACCESS, SPR_NOACCESS,
5727                  &spr_read_generic, &spr_write_generic,
5728                  0x00000000);
5729     /* MSSSR0 */
5730     /* XXX : not implemented */
5731     spr_register(env, SPR_MSSSR0, "MSSSR0",
5732                  SPR_NOACCESS, SPR_NOACCESS,
5733                  &spr_read_generic, &spr_write_generic,
5734                  0x00000000);
5735     /* PMC */
5736     /* XXX : not implemented */
5737     spr_register(env, SPR_PMC5, "PMC5",
5738                  SPR_NOACCESS, SPR_NOACCESS,
5739                  &spr_read_generic, &spr_write_generic,
5740                  0x00000000);
5741     /* XXX : not implemented */
5742     spr_register(env, SPR_UPMC5, "UPMC5",
5743                  &spr_read_ureg, SPR_NOACCESS,
5744                  &spr_read_ureg, SPR_NOACCESS,
5745                  0x00000000);
5746     /* XXX : not implemented */
5747     spr_register(env, SPR_PMC6, "PMC6",
5748                  SPR_NOACCESS, SPR_NOACCESS,
5749                  &spr_read_generic, &spr_write_generic,
5750                  0x00000000);
5751     /* XXX : not implemented */
5752     spr_register(env, SPR_UPMC6, "UPMC6",
5753                  &spr_read_ureg, SPR_NOACCESS,
5754                  &spr_read_ureg, SPR_NOACCESS,
5755                  0x00000000);
5756     /* SPRGs */
5757     spr_register(env, SPR_SPRG4, "SPRG4",
5758                  SPR_NOACCESS, SPR_NOACCESS,
5759                  &spr_read_generic, &spr_write_generic,
5760                  0x00000000);
5761     spr_register(env, SPR_USPRG4, "USPRG4",
5762                  &spr_read_ureg, SPR_NOACCESS,
5763                  &spr_read_ureg, SPR_NOACCESS,
5764                  0x00000000);
5765     spr_register(env, SPR_SPRG5, "SPRG5",
5766                  SPR_NOACCESS, SPR_NOACCESS,
5767                  &spr_read_generic, &spr_write_generic,
5768                  0x00000000);
5769     spr_register(env, SPR_USPRG5, "USPRG5",
5770                  &spr_read_ureg, SPR_NOACCESS,
5771                  &spr_read_ureg, SPR_NOACCESS,
5772                  0x00000000);
5773     spr_register(env, SPR_SPRG6, "SPRG6",
5774                  SPR_NOACCESS, SPR_NOACCESS,
5775                  &spr_read_generic, &spr_write_generic,
5776                  0x00000000);
5777     spr_register(env, SPR_USPRG6, "USPRG6",
5778                  &spr_read_ureg, SPR_NOACCESS,
5779                  &spr_read_ureg, SPR_NOACCESS,
5780                  0x00000000);
5781     spr_register(env, SPR_SPRG7, "SPRG7",
5782                  SPR_NOACCESS, SPR_NOACCESS,
5783                  &spr_read_generic, &spr_write_generic,
5784                  0x00000000);
5785     spr_register(env, SPR_USPRG7, "USPRG7",
5786                  &spr_read_ureg, SPR_NOACCESS,
5787                  &spr_read_ureg, SPR_NOACCESS,
5788                  0x00000000);
5789     /* Memory management */
5790     gen_low_BATs(env);
5791     gen_high_BATs(env);
5792     gen_74xx_soft_tlb(env, 128, 2);
5793     init_excp_7450(env);
5794     env->dcache_line_size = 32;
5795     env->icache_line_size = 32;
5796     /* Allocate hardware IRQ controller */
5797     ppc6xx_irq_init(env);
5798 }
5799
5800 /* PowerPC 7457 (aka G4)                                                     */
5801 #define POWERPC_INSNS_7457   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5802                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5803                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5804                               PPC_FLOAT_STFIWX |                              \
5805                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5806                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5807                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5808                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5809                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5810                               PPC_SEGMENT | PPC_EXTERN |                      \
5811                               PPC_ALTIVEC)
5812 #define POWERPC_MSRM_7457    (0x000000000205FF77ULL)
5813 #define POWERPC_MMU_7457     (POWERPC_MMU_SOFT_74xx)
5814 #define POWERPC_EXCP_7457    (POWERPC_EXCP_74xx)
5815 #define POWERPC_INPUT_7457   (PPC_FLAGS_INPUT_6xx)
5816 #define POWERPC_BFDM_7457    (bfd_mach_ppc_7400)
5817 #define POWERPC_FLAG_7457    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5818                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5819                               POWERPC_FLAG_BUS_CLK)
5820 #define check_pow_7457       check_pow_hid0_74xx
5821
5822 __attribute__ (( unused ))
5823 static void init_proc_7457 (CPUPPCState *env)
5824 {
5825     gen_spr_ne_601(env);
5826     gen_spr_7xx(env);
5827     /* Time base */
5828     gen_tbl(env);
5829     /* 74xx specific SPR */
5830     gen_spr_74xx(env);
5831     /* Level 3 cache control */
5832     gen_l3_ctrl(env);
5833     /* L3ITCR1 */
5834     /* XXX : not implemented */
5835     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5836                  SPR_NOACCESS, SPR_NOACCESS,
5837                  &spr_read_generic, &spr_write_generic,
5838                  0x00000000);
5839     /* L3ITCR2 */
5840     /* XXX : not implemented */
5841     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5842                  SPR_NOACCESS, SPR_NOACCESS,
5843                  &spr_read_generic, &spr_write_generic,
5844                  0x00000000);
5845     /* L3ITCR3 */
5846     /* XXX : not implemented */
5847     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5848                  SPR_NOACCESS, SPR_NOACCESS,
5849                  &spr_read_generic, &spr_write_generic,
5850                  0x00000000);
5851     /* L3OHCR */
5852     /* XXX : not implemented */
5853     spr_register(env, SPR_L3OHCR, "L3OHCR",
5854                  SPR_NOACCESS, SPR_NOACCESS,
5855                  &spr_read_generic, &spr_write_generic,
5856                  0x00000000);
5857     /* LDSTCR */
5858     /* XXX : not implemented */
5859     spr_register(env, SPR_LDSTCR, "LDSTCR",
5860                  SPR_NOACCESS, SPR_NOACCESS,
5861                  &spr_read_generic, &spr_write_generic,
5862                  0x00000000);
5863     /* ICTRL */
5864     /* XXX : not implemented */
5865     spr_register(env, SPR_ICTRL, "ICTRL",
5866                  SPR_NOACCESS, SPR_NOACCESS,
5867                  &spr_read_generic, &spr_write_generic,
5868                  0x00000000);
5869     /* MSSSR0 */
5870     /* XXX : not implemented */
5871     spr_register(env, SPR_MSSSR0, "MSSSR0",
5872                  SPR_NOACCESS, SPR_NOACCESS,
5873                  &spr_read_generic, &spr_write_generic,
5874                  0x00000000);
5875     /* PMC */
5876     /* XXX : not implemented */
5877     spr_register(env, SPR_PMC5, "PMC5",
5878                  SPR_NOACCESS, SPR_NOACCESS,
5879                  &spr_read_generic, &spr_write_generic,
5880                  0x00000000);
5881     /* XXX : not implemented */
5882     spr_register(env, SPR_UPMC5, "UPMC5",
5883                  &spr_read_ureg, SPR_NOACCESS,
5884                  &spr_read_ureg, SPR_NOACCESS,
5885                  0x00000000);
5886     /* XXX : not implemented */
5887     spr_register(env, SPR_PMC6, "PMC6",
5888                  SPR_NOACCESS, SPR_NOACCESS,
5889                  &spr_read_generic, &spr_write_generic,
5890                  0x00000000);
5891     /* XXX : not implemented */
5892     spr_register(env, SPR_UPMC6, "UPMC6",
5893                  &spr_read_ureg, SPR_NOACCESS,
5894                  &spr_read_ureg, SPR_NOACCESS,
5895                  0x00000000);
5896     /* SPRGs */
5897     spr_register(env, SPR_SPRG4, "SPRG4",
5898                  SPR_NOACCESS, SPR_NOACCESS,
5899                  &spr_read_generic, &spr_write_generic,
5900                  0x00000000);
5901     spr_register(env, SPR_USPRG4, "USPRG4",
5902                  &spr_read_ureg, SPR_NOACCESS,
5903                  &spr_read_ureg, SPR_NOACCESS,
5904                  0x00000000);
5905     spr_register(env, SPR_SPRG5, "SPRG5",
5906                  SPR_NOACCESS, SPR_NOACCESS,
5907                  &spr_read_generic, &spr_write_generic,
5908                  0x00000000);
5909     spr_register(env, SPR_USPRG5, "USPRG5",
5910                  &spr_read_ureg, SPR_NOACCESS,
5911                  &spr_read_ureg, SPR_NOACCESS,
5912                  0x00000000);
5913     spr_register(env, SPR_SPRG6, "SPRG6",
5914                  SPR_NOACCESS, SPR_NOACCESS,
5915                  &spr_read_generic, &spr_write_generic,
5916                  0x00000000);
5917     spr_register(env, SPR_USPRG6, "USPRG6",
5918                  &spr_read_ureg, SPR_NOACCESS,
5919                  &spr_read_ureg, SPR_NOACCESS,
5920                  0x00000000);
5921     spr_register(env, SPR_SPRG7, "SPRG7",
5922                  SPR_NOACCESS, SPR_NOACCESS,
5923                  &spr_read_generic, &spr_write_generic,
5924                  0x00000000);
5925     spr_register(env, SPR_USPRG7, "USPRG7",
5926                  &spr_read_ureg, SPR_NOACCESS,
5927                  &spr_read_ureg, SPR_NOACCESS,
5928                  0x00000000);
5929     /* Memory management */
5930     gen_low_BATs(env);
5931     gen_high_BATs(env);
5932     gen_74xx_soft_tlb(env, 128, 2);
5933     init_excp_7450(env);
5934     env->dcache_line_size = 32;
5935     env->icache_line_size = 32;
5936     /* Allocate hardware IRQ controller */
5937     ppc6xx_irq_init(env);
5938 }
5939
5940 #if defined (TARGET_PPC64)
5941 /* PowerPC 970                                                               */
5942 #define POWERPC_INSNS_970    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5943                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5944                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5945                               PPC_FLOAT_STFIWX |                              \
5946                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
5947                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5948                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5949                               PPC_64B | PPC_ALTIVEC |                         \
5950                               PPC_SEGMENT_64B | PPC_SLBI)
5951 #define POWERPC_MSRM_970     (0x900000000204FF36ULL)
5952 #define POWERPC_MMU_970      (POWERPC_MMU_64B)
5953 //#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
5954 #define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
5955 #define POWERPC_BFDM_970     (bfd_mach_ppc64)
5956 #define POWERPC_FLAG_970     (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5957                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5958                               POWERPC_FLAG_BUS_CLK)
5959
5960 #if defined(CONFIG_USER_ONLY)
5961 #define POWERPC970_HID5_INIT 0x00000080
5962 #else
5963 #define POWERPC970_HID5_INIT 0x00000000
5964 #endif
5965
5966 static int check_pow_970 (CPUPPCState *env)
5967 {
5968     if (env->spr[SPR_HID0] & 0x00600000)
5969         return 1;
5970
5971     return 0;
5972 }
5973
5974 static void init_proc_970 (CPUPPCState *env)
5975 {
5976     gen_spr_ne_601(env);
5977     gen_spr_7xx(env);
5978     /* Time base */
5979     gen_tbl(env);
5980     /* Hardware implementation registers */
5981     /* XXX : not implemented */
5982     spr_register(env, SPR_HID0, "HID0",
5983                  SPR_NOACCESS, SPR_NOACCESS,
5984                  &spr_read_generic, &spr_write_clear,
5985                  0x60000000);
5986     /* XXX : not implemented */
5987     spr_register(env, SPR_HID1, "HID1",
5988                  SPR_NOACCESS, SPR_NOACCESS,
5989                  &spr_read_generic, &spr_write_generic,
5990                  0x00000000);
5991     /* XXX : not implemented */
5992     spr_register(env, SPR_750FX_HID2, "HID2",
5993                  SPR_NOACCESS, SPR_NOACCESS,
5994                  &spr_read_generic, &spr_write_generic,
5995                  0x00000000);
5996     /* XXX : not implemented */
5997     spr_register(env, SPR_970_HID5, "HID5",
5998                  SPR_NOACCESS, SPR_NOACCESS,
5999                  &spr_read_generic, &spr_write_generic,
6000                  POWERPC970_HID5_INIT);
6001     /* XXX : not implemented */
6002     spr_register(env, SPR_L2CR, "L2CR",
6003                  SPR_NOACCESS, SPR_NOACCESS,
6004                  &spr_read_generic, &spr_write_generic,
6005                  0x00000000);
6006     /* Memory management */
6007     /* XXX: not correct */
6008     gen_low_BATs(env);
6009     /* XXX : not implemented */
6010     spr_register(env, SPR_MMUCFG, "MMUCFG",
6011                  SPR_NOACCESS, SPR_NOACCESS,
6012                  &spr_read_generic, SPR_NOACCESS,
6013                  0x00000000); /* TOFIX */
6014     /* XXX : not implemented */
6015     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6016                  SPR_NOACCESS, SPR_NOACCESS,
6017                  &spr_read_generic, &spr_write_generic,
6018                  0x00000000); /* TOFIX */
6019     spr_register(env, SPR_HIOR, "SPR_HIOR",
6020                  SPR_NOACCESS, SPR_NOACCESS,
6021                  &spr_read_hior, &spr_write_hior,
6022                  0x00000000);
6023 #if !defined(CONFIG_USER_ONLY)
6024     env->slb_nr = 32;
6025 #endif
6026     init_excp_970(env);
6027     env->dcache_line_size = 128;
6028     env->icache_line_size = 128;
6029     /* Allocate hardware IRQ controller */
6030     ppc970_irq_init(env);
6031     /* Can't find information on what this should be on reset.  This
6032      * value is the one used by 74xx processors. */
6033     vscr_init(env, 0x00010000);
6034 }
6035
6036 /* PowerPC 970FX (aka G5)                                                    */
6037 #define POWERPC_INSNS_970FX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6038                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6039                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6040                               PPC_FLOAT_STFIWX |                              \
6041                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6042                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6043                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6044                               PPC_64B | PPC_ALTIVEC |                         \
6045                               PPC_SEGMENT_64B | PPC_SLBI)
6046 #define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
6047 #define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
6048 #define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
6049 #define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
6050 #define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
6051 #define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6052                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6053                               POWERPC_FLAG_BUS_CLK)
6054
6055 static int check_pow_970FX (CPUPPCState *env)
6056 {
6057     if (env->spr[SPR_HID0] & 0x00600000)
6058         return 1;
6059
6060     return 0;
6061 }
6062
6063 static void init_proc_970FX (CPUPPCState *env)
6064 {
6065     gen_spr_ne_601(env);
6066     gen_spr_7xx(env);
6067     /* Time base */
6068     gen_tbl(env);
6069     /* Hardware implementation registers */
6070     /* XXX : not implemented */
6071     spr_register(env, SPR_HID0, "HID0",
6072                  SPR_NOACCESS, SPR_NOACCESS,
6073                  &spr_read_generic, &spr_write_clear,
6074                  0x60000000);
6075     /* XXX : not implemented */
6076     spr_register(env, SPR_HID1, "HID1",
6077                  SPR_NOACCESS, SPR_NOACCESS,
6078                  &spr_read_generic, &spr_write_generic,
6079                  0x00000000);
6080     /* XXX : not implemented */
6081     spr_register(env, SPR_750FX_HID2, "HID2",
6082                  SPR_NOACCESS, SPR_NOACCESS,
6083                  &spr_read_generic, &spr_write_generic,
6084                  0x00000000);
6085     /* XXX : not implemented */
6086     spr_register(env, SPR_970_HID5, "HID5",
6087                  SPR_NOACCESS, SPR_NOACCESS,
6088                  &spr_read_generic, &spr_write_generic,
6089                  POWERPC970_HID5_INIT);
6090     /* XXX : not implemented */
6091     spr_register(env, SPR_L2CR, "L2CR",
6092                  SPR_NOACCESS, SPR_NOACCESS,
6093                  &spr_read_generic, &spr_write_generic,
6094                  0x00000000);
6095     /* Memory management */
6096     /* XXX: not correct */
6097     gen_low_BATs(env);
6098     /* XXX : not implemented */
6099     spr_register(env, SPR_MMUCFG, "MMUCFG",
6100                  SPR_NOACCESS, SPR_NOACCESS,
6101                  &spr_read_generic, SPR_NOACCESS,
6102                  0x00000000); /* TOFIX */
6103     /* XXX : not implemented */
6104     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6105                  SPR_NOACCESS, SPR_NOACCESS,
6106                  &spr_read_generic, &spr_write_generic,
6107                  0x00000000); /* TOFIX */
6108     spr_register(env, SPR_HIOR, "SPR_HIOR",
6109                  SPR_NOACCESS, SPR_NOACCESS,
6110                  &spr_read_hior, &spr_write_hior,
6111                  0x00000000);
6112     spr_register(env, SPR_CTRL, "SPR_CTRL",
6113                  SPR_NOACCESS, SPR_NOACCESS,
6114                  &spr_read_generic, &spr_write_generic,
6115                  0x00000000);
6116     spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6117                  SPR_NOACCESS, SPR_NOACCESS,
6118                  &spr_read_generic, &spr_write_generic,
6119                  0x00000000);
6120     spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6121                  &spr_read_generic, &spr_write_generic,
6122                  &spr_read_generic, &spr_write_generic,
6123                  0x00000000);
6124 #if !defined(CONFIG_USER_ONLY)
6125     env->slb_nr = 64;
6126 #endif
6127     init_excp_970(env);
6128     env->dcache_line_size = 128;
6129     env->icache_line_size = 128;
6130     /* Allocate hardware IRQ controller */
6131     ppc970_irq_init(env);
6132     /* Can't find information on what this should be on reset.  This
6133      * value is the one used by 74xx processors. */
6134     vscr_init(env, 0x00010000);
6135 }
6136
6137 /* PowerPC 970 GX                                                            */
6138 #define POWERPC_INSNS_970GX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6139                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6140                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6141                               PPC_FLOAT_STFIWX |                              \
6142                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6143                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6144                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6145                               PPC_64B | PPC_ALTIVEC |                         \
6146                               PPC_SEGMENT_64B | PPC_SLBI)
6147 #define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
6148 #define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
6149 #define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
6150 #define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
6151 #define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
6152 #define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6153                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6154                               POWERPC_FLAG_BUS_CLK)
6155
6156 static int check_pow_970GX (CPUPPCState *env)
6157 {
6158     if (env->spr[SPR_HID0] & 0x00600000)
6159         return 1;
6160
6161     return 0;
6162 }
6163
6164 static void init_proc_970GX (CPUPPCState *env)
6165 {
6166     gen_spr_ne_601(env);
6167     gen_spr_7xx(env);
6168     /* Time base */
6169     gen_tbl(env);
6170     /* Hardware implementation registers */
6171     /* XXX : not implemented */
6172     spr_register(env, SPR_HID0, "HID0",
6173                  SPR_NOACCESS, SPR_NOACCESS,
6174                  &spr_read_generic, &spr_write_clear,
6175                  0x60000000);
6176     /* XXX : not implemented */
6177     spr_register(env, SPR_HID1, "HID1",
6178                  SPR_NOACCESS, SPR_NOACCESS,
6179                  &spr_read_generic, &spr_write_generic,
6180                  0x00000000);
6181     /* XXX : not implemented */
6182     spr_register(env, SPR_750FX_HID2, "HID2",
6183                  SPR_NOACCESS, SPR_NOACCESS,
6184                  &spr_read_generic, &spr_write_generic,
6185                  0x00000000);
6186     /* XXX : not implemented */
6187     spr_register(env, SPR_970_HID5, "HID5",
6188                  SPR_NOACCESS, SPR_NOACCESS,
6189                  &spr_read_generic, &spr_write_generic,
6190                  POWERPC970_HID5_INIT);
6191     /* XXX : not implemented */
6192     spr_register(env, SPR_L2CR, "L2CR",
6193                  SPR_NOACCESS, SPR_NOACCESS,
6194                  &spr_read_generic, &spr_write_generic,
6195                  0x00000000);
6196     /* Memory management */
6197     /* XXX: not correct */
6198     gen_low_BATs(env);
6199     /* XXX : not implemented */
6200     spr_register(env, SPR_MMUCFG, "MMUCFG",
6201                  SPR_NOACCESS, SPR_NOACCESS,
6202                  &spr_read_generic, SPR_NOACCESS,
6203                  0x00000000); /* TOFIX */
6204     /* XXX : not implemented */
6205     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6206                  SPR_NOACCESS, SPR_NOACCESS,
6207                  &spr_read_generic, &spr_write_generic,
6208                  0x00000000); /* TOFIX */
6209     spr_register(env, SPR_HIOR, "SPR_HIOR",
6210                  SPR_NOACCESS, SPR_NOACCESS,
6211                  &spr_read_hior, &spr_write_hior,
6212                  0x00000000);
6213 #if !defined(CONFIG_USER_ONLY)
6214     env->slb_nr = 32;
6215 #endif
6216     init_excp_970(env);
6217     env->dcache_line_size = 128;
6218     env->icache_line_size = 128;
6219     /* Allocate hardware IRQ controller */
6220     ppc970_irq_init(env);
6221     /* Can't find information on what this should be on reset.  This
6222      * value is the one used by 74xx processors. */
6223     vscr_init(env, 0x00010000);
6224 }
6225
6226 /* PowerPC 970 MP                                                            */
6227 #define POWERPC_INSNS_970MP  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6228                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6229                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6230                               PPC_FLOAT_STFIWX |                              \
6231                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6232                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6233                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6234                               PPC_64B | PPC_ALTIVEC |                         \
6235                               PPC_SEGMENT_64B | PPC_SLBI)
6236 #define POWERPC_MSRM_970MP   (0x900000000204FF36ULL)
6237 #define POWERPC_MMU_970MP    (POWERPC_MMU_64B)
6238 #define POWERPC_EXCP_970MP   (POWERPC_EXCP_970)
6239 #define POWERPC_INPUT_970MP  (PPC_FLAGS_INPUT_970)
6240 #define POWERPC_BFDM_970MP   (bfd_mach_ppc64)
6241 #define POWERPC_FLAG_970MP   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6242                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6243                               POWERPC_FLAG_BUS_CLK)
6244
6245 static int check_pow_970MP (CPUPPCState *env)
6246 {
6247     if (env->spr[SPR_HID0] & 0x01C00000)
6248         return 1;
6249
6250     return 0;
6251 }
6252
6253 static void init_proc_970MP (CPUPPCState *env)
6254 {
6255     gen_spr_ne_601(env);
6256     gen_spr_7xx(env);
6257     /* Time base */
6258     gen_tbl(env);
6259     /* Hardware implementation registers */
6260     /* XXX : not implemented */
6261     spr_register(env, SPR_HID0, "HID0",
6262                  SPR_NOACCESS, SPR_NOACCESS,
6263                  &spr_read_generic, &spr_write_clear,
6264                  0x60000000);
6265     /* XXX : not implemented */
6266     spr_register(env, SPR_HID1, "HID1",
6267                  SPR_NOACCESS, SPR_NOACCESS,
6268                  &spr_read_generic, &spr_write_generic,
6269                  0x00000000);
6270     /* XXX : not implemented */
6271     spr_register(env, SPR_750FX_HID2, "HID2",
6272                  SPR_NOACCESS, SPR_NOACCESS,
6273                  &spr_read_generic, &spr_write_generic,
6274                  0x00000000);
6275     /* XXX : not implemented */
6276     spr_register(env, SPR_970_HID5, "HID5",
6277                  SPR_NOACCESS, SPR_NOACCESS,
6278                  &spr_read_generic, &spr_write_generic,
6279                  POWERPC970_HID5_INIT);
6280     /* XXX : not implemented */
6281     spr_register(env, SPR_L2CR, "L2CR",
6282                  SPR_NOACCESS, SPR_NOACCESS,
6283                  &spr_read_generic, &spr_write_generic,
6284                  0x00000000);
6285     /* Memory management */
6286     /* XXX: not correct */
6287     gen_low_BATs(env);
6288     /* XXX : not implemented */
6289     spr_register(env, SPR_MMUCFG, "MMUCFG",
6290                  SPR_NOACCESS, SPR_NOACCESS,
6291                  &spr_read_generic, SPR_NOACCESS,
6292                  0x00000000); /* TOFIX */
6293     /* XXX : not implemented */
6294     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6295                  SPR_NOACCESS, SPR_NOACCESS,
6296                  &spr_read_generic, &spr_write_generic,
6297                  0x00000000); /* TOFIX */
6298     spr_register(env, SPR_HIOR, "SPR_HIOR",
6299                  SPR_NOACCESS, SPR_NOACCESS,
6300                  &spr_read_hior, &spr_write_hior,
6301                  0x00000000);
6302 #if !defined(CONFIG_USER_ONLY)
6303     env->slb_nr = 32;
6304 #endif
6305     init_excp_970(env);
6306     env->dcache_line_size = 128;
6307     env->icache_line_size = 128;
6308     /* Allocate hardware IRQ controller */
6309     ppc970_irq_init(env);
6310     /* Can't find information on what this should be on reset.  This
6311      * value is the one used by 74xx processors. */
6312     vscr_init(env, 0x00010000);
6313 }
6314
6315 /* PowerPC 620                                                               */
6316 #define POWERPC_INSNS_620    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6317                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6318                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6319                               PPC_FLOAT_STFIWX |                              \
6320                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
6321                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6322                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6323                               PPC_SEGMENT | PPC_EXTERN |                      \
6324                               PPC_64B | PPC_SLBI)
6325 #define POWERPC_MSRM_620     (0x800000000005FF77ULL)
6326 //#define POWERPC_MMU_620      (POWERPC_MMU_620)
6327 #define POWERPC_EXCP_620     (POWERPC_EXCP_970)
6328 #define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_6xx)
6329 #define POWERPC_BFDM_620     (bfd_mach_ppc64)
6330 #define POWERPC_FLAG_620     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |            \
6331                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6332 #define check_pow_620        check_pow_nocheck /* Check this */
6333
6334 __attribute__ (( unused ))
6335 static void init_proc_620 (CPUPPCState *env)
6336 {
6337     gen_spr_ne_601(env);
6338     gen_spr_620(env);
6339     /* Time base */
6340     gen_tbl(env);
6341     /* Hardware implementation registers */
6342     /* XXX : not implemented */
6343     spr_register(env, SPR_HID0, "HID0",
6344                  SPR_NOACCESS, SPR_NOACCESS,
6345                  &spr_read_generic, &spr_write_generic,
6346                  0x00000000);
6347     /* Memory management */
6348     gen_low_BATs(env);
6349     init_excp_620(env);
6350     env->dcache_line_size = 64;
6351     env->icache_line_size = 64;
6352     /* Allocate hardware IRQ controller */
6353     ppc6xx_irq_init(env);
6354 }
6355 #endif /* defined (TARGET_PPC64) */
6356
6357 /* Default 32 bits PowerPC target will be 604 */
6358 #define CPU_POWERPC_PPC32     CPU_POWERPC_604
6359 #define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
6360 #define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
6361 #define POWERPC_MMU_PPC32     POWERPC_MMU_604
6362 #define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
6363 #define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
6364 #define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
6365 #define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
6366 #define check_pow_PPC32       check_pow_604
6367 #define init_proc_PPC32       init_proc_604
6368
6369 /* Default 64 bits PowerPC target will be 970 FX */
6370 #define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
6371 #define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
6372 #define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
6373 #define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
6374 #define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
6375 #define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
6376 #define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
6377 #define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
6378 #define check_pow_PPC64       check_pow_970FX
6379 #define init_proc_PPC64       init_proc_970FX
6380
6381 /* Default PowerPC target will be PowerPC 32 */
6382 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6383 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
6384 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6385 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
6386 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
6387 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
6388 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6389 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
6390 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
6391 #define check_pow_DEFAULT     check_pow_PPC64
6392 #define init_proc_DEFAULT     init_proc_PPC64
6393 #else
6394 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
6395 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6396 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
6397 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
6398 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
6399 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6400 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
6401 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
6402 #define check_pow_DEFAULT     check_pow_PPC32
6403 #define init_proc_DEFAULT     init_proc_PPC32
6404 #endif
6405
6406 /*****************************************************************************/
6407 /* PVR definitions for most known PowerPC                                    */
6408 enum {
6409     /* PowerPC 401 family */
6410     /* Generic PowerPC 401 */
6411 #define CPU_POWERPC_401              CPU_POWERPC_401G2
6412     /* PowerPC 401 cores */
6413     CPU_POWERPC_401A1              = 0x00210000,
6414     CPU_POWERPC_401B2              = 0x00220000,
6415 #if 0
6416     CPU_POWERPC_401B3              = xxx,
6417 #endif
6418     CPU_POWERPC_401C2              = 0x00230000,
6419     CPU_POWERPC_401D2              = 0x00240000,
6420     CPU_POWERPC_401E2              = 0x00250000,
6421     CPU_POWERPC_401F2              = 0x00260000,
6422     CPU_POWERPC_401G2              = 0x00270000,
6423     /* PowerPC 401 microcontrolers */
6424 #if 0
6425     CPU_POWERPC_401GF              = xxx,
6426 #endif
6427 #define CPU_POWERPC_IOP480           CPU_POWERPC_401B2
6428     /* IBM Processor for Network Resources */
6429     CPU_POWERPC_COBRA              = 0x10100000, /* XXX: 405 ? */
6430 #if 0
6431     CPU_POWERPC_XIPCHIP            = xxx,
6432 #endif
6433     /* PowerPC 403 family */
6434     /* Generic PowerPC 403 */
6435 #define CPU_POWERPC_403              CPU_POWERPC_403GC
6436     /* PowerPC 403 microcontrollers */
6437     CPU_POWERPC_403GA              = 0x00200011,
6438     CPU_POWERPC_403GB              = 0x00200100,
6439     CPU_POWERPC_403GC              = 0x00200200,
6440     CPU_POWERPC_403GCX             = 0x00201400,
6441 #if 0
6442     CPU_POWERPC_403GP              = xxx,
6443 #endif
6444     /* PowerPC 405 family */
6445     /* Generic PowerPC 405 */
6446 #define CPU_POWERPC_405              CPU_POWERPC_405D4
6447     /* PowerPC 405 cores */
6448 #if 0
6449     CPU_POWERPC_405A3              = xxx,
6450 #endif
6451 #if 0
6452     CPU_POWERPC_405A4              = xxx,
6453 #endif
6454 #if 0
6455     CPU_POWERPC_405B3              = xxx,
6456 #endif
6457 #if 0
6458     CPU_POWERPC_405B4              = xxx,
6459 #endif
6460 #if 0
6461     CPU_POWERPC_405C3              = xxx,
6462 #endif
6463 #if 0
6464     CPU_POWERPC_405C4              = xxx,
6465 #endif
6466     CPU_POWERPC_405D2              = 0x20010000,
6467 #if 0
6468     CPU_POWERPC_405D3              = xxx,
6469 #endif
6470     CPU_POWERPC_405D4              = 0x41810000,
6471 #if 0
6472     CPU_POWERPC_405D5              = xxx,
6473 #endif
6474 #if 0
6475     CPU_POWERPC_405E4              = xxx,
6476 #endif
6477 #if 0
6478     CPU_POWERPC_405F4              = xxx,
6479 #endif
6480 #if 0
6481     CPU_POWERPC_405F5              = xxx,
6482 #endif
6483 #if 0
6484     CPU_POWERPC_405F6              = xxx,
6485 #endif
6486     /* PowerPC 405 microcontrolers */
6487     /* XXX: missing 0x200108a0 */
6488 #define CPU_POWERPC_405CR            CPU_POWERPC_405CRc
6489     CPU_POWERPC_405CRa             = 0x40110041,
6490     CPU_POWERPC_405CRb             = 0x401100C5,
6491     CPU_POWERPC_405CRc             = 0x40110145,
6492     CPU_POWERPC_405EP              = 0x51210950,
6493 #if 0
6494     CPU_POWERPC_405EXr             = xxx,
6495 #endif
6496     CPU_POWERPC_405EZ              = 0x41511460, /* 0x51210950 ? */
6497 #if 0
6498     CPU_POWERPC_405FX              = xxx,
6499 #endif
6500 #define CPU_POWERPC_405GP            CPU_POWERPC_405GPd
6501     CPU_POWERPC_405GPa             = 0x40110000,
6502     CPU_POWERPC_405GPb             = 0x40110040,
6503     CPU_POWERPC_405GPc             = 0x40110082,
6504     CPU_POWERPC_405GPd             = 0x401100C4,
6505 #define CPU_POWERPC_405GPe           CPU_POWERPC_405CRc
6506     CPU_POWERPC_405GPR             = 0x50910951,
6507 #if 0
6508     CPU_POWERPC_405H               = xxx,
6509 #endif
6510 #if 0
6511     CPU_POWERPC_405L               = xxx,
6512 #endif
6513     CPU_POWERPC_405LP              = 0x41F10000,
6514 #if 0
6515     CPU_POWERPC_405PM              = xxx,
6516 #endif
6517 #if 0
6518     CPU_POWERPC_405PS              = xxx,
6519 #endif
6520 #if 0
6521     CPU_POWERPC_405S               = xxx,
6522 #endif
6523     /* IBM network processors */
6524     CPU_POWERPC_NPE405H            = 0x414100C0,
6525     CPU_POWERPC_NPE405H2           = 0x41410140,
6526     CPU_POWERPC_NPE405L            = 0x416100C0,
6527     CPU_POWERPC_NPE4GS3            = 0x40B10000,
6528 #if 0
6529     CPU_POWERPC_NPCxx1             = xxx,
6530 #endif
6531 #if 0
6532     CPU_POWERPC_NPR161             = xxx,
6533 #endif
6534 #if 0
6535     CPU_POWERPC_LC77700            = xxx,
6536 #endif
6537     /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6538 #if 0
6539     CPU_POWERPC_STB01000           = xxx,
6540 #endif
6541 #if 0
6542     CPU_POWERPC_STB01010           = xxx,
6543 #endif
6544 #if 0
6545     CPU_POWERPC_STB0210            = xxx, /* 401B3 */
6546 #endif
6547     CPU_POWERPC_STB03              = 0x40310000, /* 0x40130000 ? */
6548 #if 0
6549     CPU_POWERPC_STB043             = xxx,
6550 #endif
6551 #if 0
6552     CPU_POWERPC_STB045             = xxx,
6553 #endif
6554     CPU_POWERPC_STB04              = 0x41810000,
6555     CPU_POWERPC_STB25              = 0x51510950,
6556 #if 0
6557     CPU_POWERPC_STB130             = xxx,
6558 #endif
6559     /* Xilinx cores */
6560     CPU_POWERPC_X2VP4              = 0x20010820,
6561 #define CPU_POWERPC_X2VP7            CPU_POWERPC_X2VP4
6562     CPU_POWERPC_X2VP20             = 0x20010860,
6563 #define CPU_POWERPC_X2VP50           CPU_POWERPC_X2VP20
6564 #if 0
6565     CPU_POWERPC_ZL10310            = xxx,
6566 #endif
6567 #if 0
6568     CPU_POWERPC_ZL10311            = xxx,
6569 #endif
6570 #if 0
6571     CPU_POWERPC_ZL10320            = xxx,
6572 #endif
6573 #if 0
6574     CPU_POWERPC_ZL10321            = xxx,
6575 #endif
6576     /* PowerPC 440 family */
6577     /* Generic PowerPC 440 */
6578 #define CPU_POWERPC_440              CPU_POWERPC_440GXf
6579     /* PowerPC 440 cores */
6580 #if 0
6581     CPU_POWERPC_440A4              = xxx,
6582 #endif
6583     CPU_POWERPC_440_XILINX         = 0x7ff21910,
6584 #if 0
6585     CPU_POWERPC_440A5              = xxx,
6586 #endif
6587 #if 0
6588     CPU_POWERPC_440B4              = xxx,
6589 #endif
6590 #if 0
6591     CPU_POWERPC_440F5              = xxx,
6592 #endif
6593 #if 0
6594     CPU_POWERPC_440G5              = xxx,
6595 #endif
6596 #if 0
6597     CPU_POWERPC_440H4              = xxx,
6598 #endif
6599 #if 0
6600     CPU_POWERPC_440H6              = xxx,
6601 #endif
6602     /* PowerPC 440 microcontrolers */
6603 #define CPU_POWERPC_440EP            CPU_POWERPC_440EPb
6604     CPU_POWERPC_440EPa             = 0x42221850,
6605     CPU_POWERPC_440EPb             = 0x422218D3,
6606 #define CPU_POWERPC_440GP            CPU_POWERPC_440GPc
6607     CPU_POWERPC_440GPb             = 0x40120440,
6608     CPU_POWERPC_440GPc             = 0x40120481,
6609 #define CPU_POWERPC_440GR            CPU_POWERPC_440GRa
6610 #define CPU_POWERPC_440GRa           CPU_POWERPC_440EPb
6611     CPU_POWERPC_440GRX             = 0x200008D0,
6612 #define CPU_POWERPC_440EPX           CPU_POWERPC_440GRX
6613 #define CPU_POWERPC_440GX            CPU_POWERPC_440GXf
6614     CPU_POWERPC_440GXa             = 0x51B21850,
6615     CPU_POWERPC_440GXb             = 0x51B21851,
6616     CPU_POWERPC_440GXc             = 0x51B21892,
6617     CPU_POWERPC_440GXf             = 0x51B21894,
6618 #if 0
6619     CPU_POWERPC_440S               = xxx,
6620 #endif
6621     CPU_POWERPC_440SP              = 0x53221850,
6622     CPU_POWERPC_440SP2             = 0x53221891,
6623     CPU_POWERPC_440SPE             = 0x53421890,
6624     /* PowerPC 460 family */
6625 #if 0
6626     /* Generic PowerPC 464 */
6627 #define CPU_POWERPC_464              CPU_POWERPC_464H90
6628 #endif
6629     /* PowerPC 464 microcontrolers */
6630 #if 0
6631     CPU_POWERPC_464H90             = xxx,
6632 #endif
6633 #if 0
6634     CPU_POWERPC_464H90FP           = xxx,
6635 #endif
6636     /* Freescale embedded PowerPC cores */
6637     /* PowerPC MPC 5xx cores (aka RCPU) */
6638     CPU_POWERPC_MPC5xx             = 0x00020020,
6639 #define CPU_POWERPC_MGT560           CPU_POWERPC_MPC5xx
6640 #define CPU_POWERPC_MPC509           CPU_POWERPC_MPC5xx
6641 #define CPU_POWERPC_MPC533           CPU_POWERPC_MPC5xx
6642 #define CPU_POWERPC_MPC534           CPU_POWERPC_MPC5xx
6643 #define CPU_POWERPC_MPC555           CPU_POWERPC_MPC5xx
6644 #define CPU_POWERPC_MPC556           CPU_POWERPC_MPC5xx
6645 #define CPU_POWERPC_MPC560           CPU_POWERPC_MPC5xx
6646 #define CPU_POWERPC_MPC561           CPU_POWERPC_MPC5xx
6647 #define CPU_POWERPC_MPC562           CPU_POWERPC_MPC5xx
6648 #define CPU_POWERPC_MPC563           CPU_POWERPC_MPC5xx
6649 #define CPU_POWERPC_MPC564           CPU_POWERPC_MPC5xx
6650 #define CPU_POWERPC_MPC565           CPU_POWERPC_MPC5xx
6651 #define CPU_POWERPC_MPC566           CPU_POWERPC_MPC5xx
6652     /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6653     CPU_POWERPC_MPC8xx             = 0x00500000,
6654 #define CPU_POWERPC_MGT823           CPU_POWERPC_MPC8xx
6655 #define CPU_POWERPC_MPC821           CPU_POWERPC_MPC8xx
6656 #define CPU_POWERPC_MPC823           CPU_POWERPC_MPC8xx
6657 #define CPU_POWERPC_MPC850           CPU_POWERPC_MPC8xx
6658 #define CPU_POWERPC_MPC852T          CPU_POWERPC_MPC8xx
6659 #define CPU_POWERPC_MPC855T          CPU_POWERPC_MPC8xx
6660 #define CPU_POWERPC_MPC857           CPU_POWERPC_MPC8xx
6661 #define CPU_POWERPC_MPC859           CPU_POWERPC_MPC8xx
6662 #define CPU_POWERPC_MPC860           CPU_POWERPC_MPC8xx
6663 #define CPU_POWERPC_MPC862           CPU_POWERPC_MPC8xx
6664 #define CPU_POWERPC_MPC866           CPU_POWERPC_MPC8xx
6665 #define CPU_POWERPC_MPC870           CPU_POWERPC_MPC8xx
6666 #define CPU_POWERPC_MPC875           CPU_POWERPC_MPC8xx
6667 #define CPU_POWERPC_MPC880           CPU_POWERPC_MPC8xx
6668 #define CPU_POWERPC_MPC885           CPU_POWERPC_MPC8xx
6669     /* G2 cores (aka PowerQUICC-II) */
6670     CPU_POWERPC_G2                 = 0x00810011,
6671     CPU_POWERPC_G2H4               = 0x80811010,
6672     CPU_POWERPC_G2gp               = 0x80821010,
6673     CPU_POWERPC_G2ls               = 0x90810010,
6674     CPU_POWERPC_MPC603             = 0x00810100,
6675     CPU_POWERPC_G2_HIP3            = 0x00810101,
6676     CPU_POWERPC_G2_HIP4            = 0x80811014,
6677     /*   G2_LE core (aka PowerQUICC-II) */
6678     CPU_POWERPC_G2LE               = 0x80820010,
6679     CPU_POWERPC_G2LEgp             = 0x80822010,
6680     CPU_POWERPC_G2LEls             = 0xA0822010,
6681     CPU_POWERPC_G2LEgp1            = 0x80822011,
6682     CPU_POWERPC_G2LEgp3            = 0x80822013,
6683     /* MPC52xx microcontrollers  */
6684     /* XXX: MPC 5121 ? */
6685 #define CPU_POWERPC_MPC52xx          CPU_POWERPC_MPC5200
6686 #define CPU_POWERPC_MPC5200          CPU_POWERPC_MPC5200_v12
6687 #define CPU_POWERPC_MPC5200_v10      CPU_POWERPC_G2LEgp1
6688 #define CPU_POWERPC_MPC5200_v11      CPU_POWERPC_G2LEgp1
6689 #define CPU_POWERPC_MPC5200_v12      CPU_POWERPC_G2LEgp1
6690 #define CPU_POWERPC_MPC5200B         CPU_POWERPC_MPC5200B_v21
6691 #define CPU_POWERPC_MPC5200B_v20     CPU_POWERPC_G2LEgp1
6692 #define CPU_POWERPC_MPC5200B_v21     CPU_POWERPC_G2LEgp1
6693     /* MPC82xx microcontrollers */
6694 #define CPU_POWERPC_MPC82xx          CPU_POWERPC_MPC8280
6695 #define CPU_POWERPC_MPC8240          CPU_POWERPC_MPC603
6696 #define CPU_POWERPC_MPC8241          CPU_POWERPC_G2_HIP4
6697 #define CPU_POWERPC_MPC8245          CPU_POWERPC_G2_HIP4
6698 #define CPU_POWERPC_MPC8247          CPU_POWERPC_G2LEgp3
6699 #define CPU_POWERPC_MPC8248          CPU_POWERPC_G2LEgp3
6700 #define CPU_POWERPC_MPC8250          CPU_POWERPC_MPC8250_HiP4
6701 #define CPU_POWERPC_MPC8250_HiP3     CPU_POWERPC_G2_HIP3
6702 #define CPU_POWERPC_MPC8250_HiP4     CPU_POWERPC_G2_HIP4
6703 #define CPU_POWERPC_MPC8255          CPU_POWERPC_MPC8255_HiP4
6704 #define CPU_POWERPC_MPC8255_HiP3     CPU_POWERPC_G2_HIP3
6705 #define CPU_POWERPC_MPC8255_HiP4     CPU_POWERPC_G2_HIP4
6706 #define CPU_POWERPC_MPC8260          CPU_POWERPC_MPC8260_HiP4
6707 #define CPU_POWERPC_MPC8260_HiP3     CPU_POWERPC_G2_HIP3
6708 #define CPU_POWERPC_MPC8260_HiP4     CPU_POWERPC_G2_HIP4
6709 #define CPU_POWERPC_MPC8264          CPU_POWERPC_MPC8264_HiP4
6710 #define CPU_POWERPC_MPC8264_HiP3     CPU_POWERPC_G2_HIP3
6711 #define CPU_POWERPC_MPC8264_HiP4     CPU_POWERPC_G2_HIP4
6712 #define CPU_POWERPC_MPC8265          CPU_POWERPC_MPC8265_HiP4
6713 #define CPU_POWERPC_MPC8265_HiP3     CPU_POWERPC_G2_HIP3
6714 #define CPU_POWERPC_MPC8265_HiP4     CPU_POWERPC_G2_HIP4
6715 #define CPU_POWERPC_MPC8266          CPU_POWERPC_MPC8266_HiP4
6716 #define CPU_POWERPC_MPC8266_HiP3     CPU_POWERPC_G2_HIP3
6717 #define CPU_POWERPC_MPC8266_HiP4     CPU_POWERPC_G2_HIP4
6718 #define CPU_POWERPC_MPC8270          CPU_POWERPC_G2LEgp3
6719 #define CPU_POWERPC_MPC8271          CPU_POWERPC_G2LEgp3
6720 #define CPU_POWERPC_MPC8272          CPU_POWERPC_G2LEgp3
6721 #define CPU_POWERPC_MPC8275          CPU_POWERPC_G2LEgp3
6722 #define CPU_POWERPC_MPC8280          CPU_POWERPC_G2LEgp3
6723     /* e200 family */
6724     /* e200 cores */
6725 #define CPU_POWERPC_e200             CPU_POWERPC_e200z6
6726 #if 0
6727     CPU_POWERPC_e200z0             = xxx,
6728 #endif
6729 #if 0
6730     CPU_POWERPC_e200z1             = xxx,
6731 #endif
6732 #if 0 /* ? */
6733     CPU_POWERPC_e200z3             = 0x81120000,
6734 #endif
6735     CPU_POWERPC_e200z5             = 0x81000000,
6736     CPU_POWERPC_e200z6             = 0x81120000,
6737     /* MPC55xx microcontrollers */
6738 #define CPU_POWERPC_MPC55xx          CPU_POWERPC_MPC5567
6739 #if 0
6740 #define CPU_POWERPC_MPC5514E         CPU_POWERPC_MPC5514E_v1
6741 #define CPU_POWERPC_MPC5514E_v0      CPU_POWERPC_e200z0
6742 #define CPU_POWERPC_MPC5514E_v1      CPU_POWERPC_e200z1
6743 #define CPU_POWERPC_MPC5514G         CPU_POWERPC_MPC5514G_v1
6744 #define CPU_POWERPC_MPC5514G_v0      CPU_POWERPC_e200z0
6745 #define CPU_POWERPC_MPC5514G_v1      CPU_POWERPC_e200z1
6746 #define CPU_POWERPC_MPC5515S         CPU_POWERPC_e200z1
6747 #define CPU_POWERPC_MPC5516E         CPU_POWERPC_MPC5516E_v1
6748 #define CPU_POWERPC_MPC5516E_v0      CPU_POWERPC_e200z0
6749 #define CPU_POWERPC_MPC5516E_v1      CPU_POWERPC_e200z1
6750 #define CPU_POWERPC_MPC5516G         CPU_POWERPC_MPC5516G_v1
6751 #define CPU_POWERPC_MPC5516G_v0      CPU_POWERPC_e200z0
6752 #define CPU_POWERPC_MPC5516G_v1      CPU_POWERPC_e200z1
6753 #define CPU_POWERPC_MPC5516S         CPU_POWERPC_e200z1
6754 #endif
6755 #if 0
6756 #define CPU_POWERPC_MPC5533          CPU_POWERPC_e200z3
6757 #define CPU_POWERPC_MPC5534          CPU_POWERPC_e200z3
6758 #endif
6759 #define CPU_POWERPC_MPC5553          CPU_POWERPC_e200z6
6760 #define CPU_POWERPC_MPC5554          CPU_POWERPC_e200z6
6761 #define CPU_POWERPC_MPC5561          CPU_POWERPC_e200z6
6762 #define CPU_POWERPC_MPC5565          CPU_POWERPC_e200z6
6763 #define CPU_POWERPC_MPC5566          CPU_POWERPC_e200z6
6764 #define CPU_POWERPC_MPC5567          CPU_POWERPC_e200z6
6765     /* e300 family */
6766     /* e300 cores */
6767 #define CPU_POWERPC_e300             CPU_POWERPC_e300c3
6768     CPU_POWERPC_e300c1             = 0x00830010,
6769     CPU_POWERPC_e300c2             = 0x00840010,
6770     CPU_POWERPC_e300c3             = 0x00850010,
6771     CPU_POWERPC_e300c4             = 0x00860010,
6772     /* MPC83xx microcontrollers */
6773 #define CPU_POWERPC_MPC831x          CPU_POWERPC_e300c3
6774 #define CPU_POWERPC_MPC832x          CPU_POWERPC_e300c2
6775 #define CPU_POWERPC_MPC834x          CPU_POWERPC_e300c1
6776 #define CPU_POWERPC_MPC835x          CPU_POWERPC_e300c1
6777 #define CPU_POWERPC_MPC836x          CPU_POWERPC_e300c1
6778 #define CPU_POWERPC_MPC837x          CPU_POWERPC_e300c4
6779     /* e500 family */
6780     /* e500 cores  */
6781 #define CPU_POWERPC_e500             CPU_POWERPC_e500v2_v22
6782 #define CPU_POWERPC_e500v1           CPU_POWERPC_e500v1_v20
6783 #define CPU_POWERPC_e500v2           CPU_POWERPC_e500v2_v22
6784     CPU_POWERPC_e500v1_v10         = 0x80200010,
6785     CPU_POWERPC_e500v1_v20         = 0x80200020,
6786     CPU_POWERPC_e500v2_v10         = 0x80210010,
6787     CPU_POWERPC_e500v2_v11         = 0x80210011,
6788     CPU_POWERPC_e500v2_v20         = 0x80210020,
6789     CPU_POWERPC_e500v2_v21         = 0x80210021,
6790     CPU_POWERPC_e500v2_v22         = 0x80210022,
6791     CPU_POWERPC_e500v2_v30         = 0x80210030,
6792     /* MPC85xx microcontrollers */
6793 #define CPU_POWERPC_MPC8533          CPU_POWERPC_MPC8533_v11
6794 #define CPU_POWERPC_MPC8533_v10      CPU_POWERPC_e500v2_v21
6795 #define CPU_POWERPC_MPC8533_v11      CPU_POWERPC_e500v2_v22
6796 #define CPU_POWERPC_MPC8533E         CPU_POWERPC_MPC8533E_v11
6797 #define CPU_POWERPC_MPC8533E_v10     CPU_POWERPC_e500v2_v21
6798 #define CPU_POWERPC_MPC8533E_v11     CPU_POWERPC_e500v2_v22
6799 #define CPU_POWERPC_MPC8540          CPU_POWERPC_MPC8540_v21
6800 #define CPU_POWERPC_MPC8540_v10      CPU_POWERPC_e500v1_v10
6801 #define CPU_POWERPC_MPC8540_v20      CPU_POWERPC_e500v1_v20
6802 #define CPU_POWERPC_MPC8540_v21      CPU_POWERPC_e500v1_v20
6803 #define CPU_POWERPC_MPC8541          CPU_POWERPC_MPC8541_v11
6804 #define CPU_POWERPC_MPC8541_v10      CPU_POWERPC_e500v1_v20
6805 #define CPU_POWERPC_MPC8541_v11      CPU_POWERPC_e500v1_v20
6806 #define CPU_POWERPC_MPC8541E         CPU_POWERPC_MPC8541E_v11
6807 #define CPU_POWERPC_MPC8541E_v10     CPU_POWERPC_e500v1_v20
6808 #define CPU_POWERPC_MPC8541E_v11     CPU_POWERPC_e500v1_v20
6809 #define CPU_POWERPC_MPC8543          CPU_POWERPC_MPC8543_v21
6810 #define CPU_POWERPC_MPC8543_v10      CPU_POWERPC_e500v2_v10
6811 #define CPU_POWERPC_MPC8543_v11      CPU_POWERPC_e500v2_v11
6812 #define CPU_POWERPC_MPC8543_v20      CPU_POWERPC_e500v2_v20
6813 #define CPU_POWERPC_MPC8543_v21      CPU_POWERPC_e500v2_v21
6814 #define CPU_POWERPC_MPC8543E         CPU_POWERPC_MPC8543E_v21
6815 #define CPU_POWERPC_MPC8543E_v10     CPU_POWERPC_e500v2_v10
6816 #define CPU_POWERPC_MPC8543E_v11     CPU_POWERPC_e500v2_v11
6817 #define CPU_POWERPC_MPC8543E_v20     CPU_POWERPC_e500v2_v20
6818 #define CPU_POWERPC_MPC8543E_v21     CPU_POWERPC_e500v2_v21
6819 #define CPU_POWERPC_MPC8544          CPU_POWERPC_MPC8544_v11
6820 #define CPU_POWERPC_MPC8544_v10      CPU_POWERPC_e500v2_v21
6821 #define CPU_POWERPC_MPC8544_v11      CPU_POWERPC_e500v2_v22
6822 #define CPU_POWERPC_MPC8544E_v11     CPU_POWERPC_e500v2_v22
6823 #define CPU_POWERPC_MPC8544E         CPU_POWERPC_MPC8544E_v11
6824 #define CPU_POWERPC_MPC8544E_v10     CPU_POWERPC_e500v2_v21
6825 #define CPU_POWERPC_MPC8545          CPU_POWERPC_MPC8545_v21
6826 #define CPU_POWERPC_MPC8545_v10      CPU_POWERPC_e500v2_v10
6827 #define CPU_POWERPC_MPC8545_v20      CPU_POWERPC_e500v2_v20
6828 #define CPU_POWERPC_MPC8545_v21      CPU_POWERPC_e500v2_v21
6829 #define CPU_POWERPC_MPC8545E         CPU_POWERPC_MPC8545E_v21
6830 #define CPU_POWERPC_MPC8545E_v10     CPU_POWERPC_e500v2_v10
6831 #define CPU_POWERPC_MPC8545E_v20     CPU_POWERPC_e500v2_v20
6832 #define CPU_POWERPC_MPC8545E_v21     CPU_POWERPC_e500v2_v21
6833 #define CPU_POWERPC_MPC8547E         CPU_POWERPC_MPC8545E_v21
6834 #define CPU_POWERPC_MPC8547E_v10     CPU_POWERPC_e500v2_v10
6835 #define CPU_POWERPC_MPC8547E_v20     CPU_POWERPC_e500v2_v20
6836 #define CPU_POWERPC_MPC8547E_v21     CPU_POWERPC_e500v2_v21
6837 #define CPU_POWERPC_MPC8548          CPU_POWERPC_MPC8548_v21
6838 #define CPU_POWERPC_MPC8548_v10      CPU_POWERPC_e500v2_v10
6839 #define CPU_POWERPC_MPC8548_v11      CPU_POWERPC_e500v2_v11
6840 #define CPU_POWERPC_MPC8548_v20      CPU_POWERPC_e500v2_v20
6841 #define CPU_POWERPC_MPC8548_v21      CPU_POWERPC_e500v2_v21
6842 #define CPU_POWERPC_MPC8548E         CPU_POWERPC_MPC8548E_v21
6843 #define CPU_POWERPC_MPC8548E_v10     CPU_POWERPC_e500v2_v10
6844 #define CPU_POWERPC_MPC8548E_v11     CPU_POWERPC_e500v2_v11
6845 #define CPU_POWERPC_MPC8548E_v20     CPU_POWERPC_e500v2_v20
6846 #define CPU_POWERPC_MPC8548E_v21     CPU_POWERPC_e500v2_v21
6847 #define CPU_POWERPC_MPC8555          CPU_POWERPC_MPC8555_v11
6848 #define CPU_POWERPC_MPC8555_v10      CPU_POWERPC_e500v2_v10
6849 #define CPU_POWERPC_MPC8555_v11      CPU_POWERPC_e500v2_v11
6850 #define CPU_POWERPC_MPC8555E         CPU_POWERPC_MPC8555E_v11
6851 #define CPU_POWERPC_MPC8555E_v10     CPU_POWERPC_e500v2_v10
6852 #define CPU_POWERPC_MPC8555E_v11     CPU_POWERPC_e500v2_v11
6853 #define CPU_POWERPC_MPC8560          CPU_POWERPC_MPC8560_v21
6854 #define CPU_POWERPC_MPC8560_v10      CPU_POWERPC_e500v2_v10
6855 #define CPU_POWERPC_MPC8560_v20      CPU_POWERPC_e500v2_v20
6856 #define CPU_POWERPC_MPC8560_v21      CPU_POWERPC_e500v2_v21
6857 #define CPU_POWERPC_MPC8567          CPU_POWERPC_e500v2_v22
6858 #define CPU_POWERPC_MPC8567E         CPU_POWERPC_e500v2_v22
6859 #define CPU_POWERPC_MPC8568          CPU_POWERPC_e500v2_v22
6860 #define CPU_POWERPC_MPC8568E         CPU_POWERPC_e500v2_v22
6861 #define CPU_POWERPC_MPC8572          CPU_POWERPC_e500v2_v30
6862 #define CPU_POWERPC_MPC8572E         CPU_POWERPC_e500v2_v30
6863     /* e600 family */
6864     /* e600 cores */
6865     CPU_POWERPC_e600               = 0x80040010,
6866     /* MPC86xx microcontrollers */
6867 #define CPU_POWERPC_MPC8610          CPU_POWERPC_e600
6868 #define CPU_POWERPC_MPC8641          CPU_POWERPC_e600
6869 #define CPU_POWERPC_MPC8641D         CPU_POWERPC_e600
6870     /* PowerPC 6xx cores */
6871 #define CPU_POWERPC_601              CPU_POWERPC_601_v2
6872     CPU_POWERPC_601_v0             = 0x00010001,
6873     CPU_POWERPC_601_v1             = 0x00010001,
6874 #define CPU_POWERPC_601v             CPU_POWERPC_601_v2
6875     CPU_POWERPC_601_v2             = 0x00010002,
6876     CPU_POWERPC_602                = 0x00050100,
6877     CPU_POWERPC_603                = 0x00030100,
6878 #define CPU_POWERPC_603E             CPU_POWERPC_603E_v41
6879     CPU_POWERPC_603E_v11           = 0x00060101,
6880     CPU_POWERPC_603E_v12           = 0x00060102,
6881     CPU_POWERPC_603E_v13           = 0x00060103,
6882     CPU_POWERPC_603E_v14           = 0x00060104,
6883     CPU_POWERPC_603E_v22           = 0x00060202,
6884     CPU_POWERPC_603E_v3            = 0x00060300,
6885     CPU_POWERPC_603E_v4            = 0x00060400,
6886     CPU_POWERPC_603E_v41           = 0x00060401,
6887     CPU_POWERPC_603E7t             = 0x00071201,
6888     CPU_POWERPC_603E7v             = 0x00070100,
6889     CPU_POWERPC_603E7v1            = 0x00070101,
6890     CPU_POWERPC_603E7v2            = 0x00070201,
6891     CPU_POWERPC_603E7              = 0x00070200,
6892     CPU_POWERPC_603P               = 0x00070000,
6893 #define CPU_POWERPC_603R             CPU_POWERPC_603E7t
6894     /* XXX: missing 0x00040303 (604) */
6895     CPU_POWERPC_604                = 0x00040103,
6896 #define CPU_POWERPC_604E             CPU_POWERPC_604E_v24
6897     /* XXX: missing 0x00091203 */
6898     /* XXX: missing 0x00092110 */
6899     /* XXX: missing 0x00092120 */
6900     CPU_POWERPC_604E_v10           = 0x00090100,
6901     CPU_POWERPC_604E_v22           = 0x00090202,
6902     CPU_POWERPC_604E_v24           = 0x00090204,
6903     /* XXX: missing 0x000a0100 */
6904     /* XXX: missing 0x00093102 */
6905     CPU_POWERPC_604R               = 0x000a0101,
6906 #if 0
6907     CPU_POWERPC_604EV              = xxx, /* XXX: same as 604R ? */
6908 #endif
6909     /* PowerPC 740/750 cores (aka G3) */
6910     /* XXX: missing 0x00084202 */
6911 #define CPU_POWERPC_7x0              CPU_POWERPC_7x0_v31
6912     CPU_POWERPC_7x0_v10            = 0x00080100,
6913     CPU_POWERPC_7x0_v20            = 0x00080200,
6914     CPU_POWERPC_7x0_v21            = 0x00080201,
6915     CPU_POWERPC_7x0_v22            = 0x00080202,
6916     CPU_POWERPC_7x0_v30            = 0x00080300,
6917     CPU_POWERPC_7x0_v31            = 0x00080301,
6918     CPU_POWERPC_740E               = 0x00080100,
6919     CPU_POWERPC_750E               = 0x00080200,
6920     CPU_POWERPC_7x0P               = 0x10080000,
6921     /* XXX: missing 0x00087010 (CL ?) */
6922 #define CPU_POWERPC_750CL            CPU_POWERPC_750CL_v20
6923     CPU_POWERPC_750CL_v10          = 0x00087200,
6924     CPU_POWERPC_750CL_v20          = 0x00087210, /* aka rev E */
6925 #define CPU_POWERPC_750CX            CPU_POWERPC_750CX_v22
6926     CPU_POWERPC_750CX_v10          = 0x00082100,
6927     CPU_POWERPC_750CX_v20          = 0x00082200,
6928     CPU_POWERPC_750CX_v21          = 0x00082201,
6929     CPU_POWERPC_750CX_v22          = 0x00082202,
6930 #define CPU_POWERPC_750CXE           CPU_POWERPC_750CXE_v31b
6931     CPU_POWERPC_750CXE_v21         = 0x00082211,
6932     CPU_POWERPC_750CXE_v22         = 0x00082212,
6933     CPU_POWERPC_750CXE_v23         = 0x00082213,
6934     CPU_POWERPC_750CXE_v24         = 0x00082214,
6935     CPU_POWERPC_750CXE_v24b        = 0x00083214,
6936     CPU_POWERPC_750CXE_v30         = 0x00082310,
6937     CPU_POWERPC_750CXE_v31         = 0x00082311,
6938     CPU_POWERPC_750CXE_v31b        = 0x00083311,
6939     CPU_POWERPC_750CXR             = 0x00083410,
6940     CPU_POWERPC_750FL              = 0x70000203,
6941 #define CPU_POWERPC_750FX            CPU_POWERPC_750FX_v23
6942     CPU_POWERPC_750FX_v10          = 0x70000100,
6943     CPU_POWERPC_750FX_v20          = 0x70000200,
6944     CPU_POWERPC_750FX_v21          = 0x70000201,
6945     CPU_POWERPC_750FX_v22          = 0x70000202,
6946     CPU_POWERPC_750FX_v23          = 0x70000203,
6947     CPU_POWERPC_750GL              = 0x70020102,
6948 #define CPU_POWERPC_750GX            CPU_POWERPC_750GX_v12
6949     CPU_POWERPC_750GX_v10          = 0x70020100,
6950     CPU_POWERPC_750GX_v11          = 0x70020101,
6951     CPU_POWERPC_750GX_v12          = 0x70020102,
6952 #define CPU_POWERPC_750L             CPU_POWERPC_750L_v32 /* Aka LoneStar */
6953     CPU_POWERPC_750L_v20           = 0x00088200,
6954     CPU_POWERPC_750L_v21           = 0x00088201,
6955     CPU_POWERPC_750L_v22           = 0x00088202,
6956     CPU_POWERPC_750L_v30           = 0x00088300,
6957     CPU_POWERPC_750L_v32           = 0x00088302,
6958     /* PowerPC 745/755 cores */
6959 #define CPU_POWERPC_7x5              CPU_POWERPC_7x5_v28
6960     CPU_POWERPC_7x5_v10            = 0x00083100,
6961     CPU_POWERPC_7x5_v11            = 0x00083101,
6962     CPU_POWERPC_7x5_v20            = 0x00083200,
6963     CPU_POWERPC_7x5_v21            = 0x00083201,
6964     CPU_POWERPC_7x5_v22            = 0x00083202, /* aka D */
6965     CPU_POWERPC_7x5_v23            = 0x00083203, /* aka E */
6966     CPU_POWERPC_7x5_v24            = 0x00083204,
6967     CPU_POWERPC_7x5_v25            = 0x00083205,
6968     CPU_POWERPC_7x5_v26            = 0x00083206,
6969     CPU_POWERPC_7x5_v27            = 0x00083207,
6970     CPU_POWERPC_7x5_v28            = 0x00083208,
6971 #if 0
6972     CPU_POWERPC_7x5P               = xxx,
6973 #endif
6974     /* PowerPC 74xx cores (aka G4) */
6975     /* XXX: missing 0x000C1101 */
6976 #define CPU_POWERPC_7400             CPU_POWERPC_7400_v29
6977     CPU_POWERPC_7400_v10           = 0x000C0100,
6978     CPU_POWERPC_7400_v11           = 0x000C0101,
6979     CPU_POWERPC_7400_v20           = 0x000C0200,
6980     CPU_POWERPC_7400_v21           = 0x000C0201,
6981     CPU_POWERPC_7400_v22           = 0x000C0202,
6982     CPU_POWERPC_7400_v26           = 0x000C0206,
6983     CPU_POWERPC_7400_v27           = 0x000C0207,
6984     CPU_POWERPC_7400_v28           = 0x000C0208,
6985     CPU_POWERPC_7400_v29           = 0x000C0209,
6986 #define CPU_POWERPC_7410             CPU_POWERPC_7410_v14
6987     CPU_POWERPC_7410_v10           = 0x800C1100,
6988     CPU_POWERPC_7410_v11           = 0x800C1101,
6989     CPU_POWERPC_7410_v12           = 0x800C1102, /* aka C */
6990     CPU_POWERPC_7410_v13           = 0x800C1103, /* aka D */
6991     CPU_POWERPC_7410_v14           = 0x800C1104, /* aka E */
6992 #define CPU_POWERPC_7448             CPU_POWERPC_7448_v21
6993     CPU_POWERPC_7448_v10           = 0x80040100,
6994     CPU_POWERPC_7448_v11           = 0x80040101,
6995     CPU_POWERPC_7448_v20           = 0x80040200,
6996     CPU_POWERPC_7448_v21           = 0x80040201,
6997 #define CPU_POWERPC_7450             CPU_POWERPC_7450_v21
6998     CPU_POWERPC_7450_v10           = 0x80000100,
6999     CPU_POWERPC_7450_v11           = 0x80000101,
7000     CPU_POWERPC_7450_v12           = 0x80000102,
7001     CPU_POWERPC_7450_v20           = 0x80000200, /* aka A, B, C, D: 2.04 */
7002     CPU_POWERPC_7450_v21           = 0x80000201, /* aka E */
7003 #define CPU_POWERPC_74x1             CPU_POWERPC_74x1_v23
7004     CPU_POWERPC_74x1_v23           = 0x80000203, /* aka G: 2.3 */
7005     /* XXX: this entry might be a bug in some documentation */
7006     CPU_POWERPC_74x1_v210          = 0x80000210, /* aka G: 2.3 ? */
7007 #define CPU_POWERPC_74x5             CPU_POWERPC_74x5_v32
7008     CPU_POWERPC_74x5_v10           = 0x80010100,
7009     /* XXX: missing 0x80010200 */
7010     CPU_POWERPC_74x5_v21           = 0x80010201, /* aka C: 2.1 */
7011     CPU_POWERPC_74x5_v32           = 0x80010302,
7012     CPU_POWERPC_74x5_v33           = 0x80010303, /* aka F: 3.3 */
7013     CPU_POWERPC_74x5_v34           = 0x80010304, /* aka G: 3.4 */
7014 #define CPU_POWERPC_74x7             CPU_POWERPC_74x7_v12
7015     CPU_POWERPC_74x7_v10           = 0x80020100, /* aka A: 1.0 */
7016     CPU_POWERPC_74x7_v11           = 0x80020101, /* aka B: 1.1 */
7017     CPU_POWERPC_74x7_v12           = 0x80020102, /* aka C: 1.2 */
7018 #define CPU_POWERPC_74x7A            CPU_POWERPC_74x7A_v12
7019     CPU_POWERPC_74x7A_v10          = 0x80030100, /* aka A: 1.0 */
7020     CPU_POWERPC_74x7A_v11          = 0x80030101, /* aka B: 1.1 */
7021     CPU_POWERPC_74x7A_v12          = 0x80030102, /* aka C: 1.2 */
7022     /* 64 bits PowerPC */
7023 #if defined(TARGET_PPC64)
7024     CPU_POWERPC_620                = 0x00140000,
7025     CPU_POWERPC_630                = 0x00400000,
7026     CPU_POWERPC_631                = 0x00410104,
7027     CPU_POWERPC_POWER4             = 0x00350000,
7028     CPU_POWERPC_POWER4P            = 0x00380000,
7029      /* XXX: missing 0x003A0201 */
7030     CPU_POWERPC_POWER5             = 0x003A0203,
7031 #define CPU_POWERPC_POWER5GR         CPU_POWERPC_POWER5
7032     CPU_POWERPC_POWER5P            = 0x003B0000,
7033 #define CPU_POWERPC_POWER5GS         CPU_POWERPC_POWER5P
7034     CPU_POWERPC_POWER6             = 0x003E0000,
7035     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
7036     CPU_POWERPC_POWER6A            = 0x0F000002,
7037     CPU_POWERPC_970                = 0x00390202,
7038 #define CPU_POWERPC_970FX            CPU_POWERPC_970FX_v31
7039     CPU_POWERPC_970FX_v10          = 0x00391100,
7040     CPU_POWERPC_970FX_v20          = 0x003C0200,
7041     CPU_POWERPC_970FX_v21          = 0x003C0201,
7042     CPU_POWERPC_970FX_v30          = 0x003C0300,
7043     CPU_POWERPC_970FX_v31          = 0x003C0301,
7044     CPU_POWERPC_970GX              = 0x00450000,
7045 #define CPU_POWERPC_970MP            CPU_POWERPC_970MP_v11
7046     CPU_POWERPC_970MP_v10          = 0x00440100,
7047     CPU_POWERPC_970MP_v11          = 0x00440101,
7048 #define CPU_POWERPC_CELL             CPU_POWERPC_CELL_v32
7049     CPU_POWERPC_CELL_v10           = 0x00700100,
7050     CPU_POWERPC_CELL_v20           = 0x00700400,
7051     CPU_POWERPC_CELL_v30           = 0x00700500,
7052     CPU_POWERPC_CELL_v31           = 0x00700501,
7053 #define CPU_POWERPC_CELL_v32         CPU_POWERPC_CELL_v31
7054     CPU_POWERPC_RS64               = 0x00330000,
7055     CPU_POWERPC_RS64II             = 0x00340000,
7056     CPU_POWERPC_RS64III            = 0x00360000,
7057     CPU_POWERPC_RS64IV             = 0x00370000,
7058 #endif /* defined(TARGET_PPC64) */
7059     /* Original POWER */
7060     /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7061      * POWER2 (RIOS2) & RSC2 (P2SC) here
7062      */
7063 #if 0
7064     CPU_POWER                      = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7065 #endif
7066 #if 0
7067     CPU_POWER2                     = xxx, /* 0x40000 ? */
7068 #endif
7069     /* PA Semi core */
7070     CPU_POWERPC_PA6T               = 0x00900000,
7071 };
7072
7073 /* System version register (used on MPC 8xxx)                                */
7074 enum {
7075     POWERPC_SVR_NONE               = 0x00000000,
7076 #define POWERPC_SVR_52xx             POWERPC_SVR_5200
7077 #define POWERPC_SVR_5200             POWERPC_SVR_5200_v12
7078     POWERPC_SVR_5200_v10           = 0x80110010,
7079     POWERPC_SVR_5200_v11           = 0x80110011,
7080     POWERPC_SVR_5200_v12           = 0x80110012,
7081 #define POWERPC_SVR_5200B            POWERPC_SVR_5200B_v21
7082     POWERPC_SVR_5200B_v20          = 0x80110020,
7083     POWERPC_SVR_5200B_v21          = 0x80110021,
7084 #define POWERPC_SVR_55xx             POWERPC_SVR_5567
7085 #if 0
7086     POWERPC_SVR_5533               = xxx,
7087 #endif
7088 #if 0
7089     POWERPC_SVR_5534               = xxx,
7090 #endif
7091 #if 0
7092     POWERPC_SVR_5553               = xxx,
7093 #endif
7094 #if 0
7095     POWERPC_SVR_5554               = xxx,
7096 #endif
7097 #if 0
7098     POWERPC_SVR_5561               = xxx,
7099 #endif
7100 #if 0
7101     POWERPC_SVR_5565               = xxx,
7102 #endif
7103 #if 0
7104     POWERPC_SVR_5566               = xxx,
7105 #endif
7106 #if 0
7107     POWERPC_SVR_5567               = xxx,
7108 #endif
7109 #if 0
7110     POWERPC_SVR_8313               = xxx,
7111 #endif
7112 #if 0
7113     POWERPC_SVR_8313E              = xxx,
7114 #endif
7115 #if 0
7116     POWERPC_SVR_8314               = xxx,
7117 #endif
7118 #if 0
7119     POWERPC_SVR_8314E              = xxx,
7120 #endif
7121 #if 0
7122     POWERPC_SVR_8315               = xxx,
7123 #endif
7124 #if 0
7125     POWERPC_SVR_8315E              = xxx,
7126 #endif
7127 #if 0
7128     POWERPC_SVR_8321               = xxx,
7129 #endif
7130 #if 0
7131     POWERPC_SVR_8321E              = xxx,
7132 #endif
7133 #if 0
7134     POWERPC_SVR_8323               = xxx,
7135 #endif
7136 #if 0
7137     POWERPC_SVR_8323E              = xxx,
7138 #endif
7139     POWERPC_SVR_8343               = 0x80570010,
7140     POWERPC_SVR_8343A              = 0x80570030,
7141     POWERPC_SVR_8343E              = 0x80560010,
7142     POWERPC_SVR_8343EA             = 0x80560030,
7143 #define POWERPC_SVR_8347             POWERPC_SVR_8347T
7144     POWERPC_SVR_8347P              = 0x80550010, /* PBGA package */
7145     POWERPC_SVR_8347T              = 0x80530010, /* TBGA package */
7146 #define POWERPC_SVR_8347A            POWERPC_SVR_8347AT
7147     POWERPC_SVR_8347AP             = 0x80550030, /* PBGA package */
7148     POWERPC_SVR_8347AT             = 0x80530030, /* TBGA package */
7149 #define POWERPC_SVR_8347E            POWERPC_SVR_8347ET
7150     POWERPC_SVR_8347EP             = 0x80540010, /* PBGA package */
7151     POWERPC_SVR_8347ET             = 0x80520010, /* TBGA package */
7152 #define POWERPC_SVR_8347EA            POWERPC_SVR_8347EAT
7153     POWERPC_SVR_8347EAP            = 0x80540030, /* PBGA package */
7154     POWERPC_SVR_8347EAT            = 0x80520030, /* TBGA package */
7155     POWERPC_SVR_8349               = 0x80510010,
7156     POWERPC_SVR_8349A              = 0x80510030,
7157     POWERPC_SVR_8349E              = 0x80500010,
7158     POWERPC_SVR_8349EA             = 0x80500030,
7159 #if 0
7160     POWERPC_SVR_8358E              = xxx,
7161 #endif
7162 #if 0
7163     POWERPC_SVR_8360E              = xxx,
7164 #endif
7165 #define POWERPC_SVR_E500             0x40000000
7166     POWERPC_SVR_8377               = 0x80C70010 | POWERPC_SVR_E500,
7167     POWERPC_SVR_8377E              = 0x80C60010 | POWERPC_SVR_E500,
7168     POWERPC_SVR_8378               = 0x80C50010 | POWERPC_SVR_E500,
7169     POWERPC_SVR_8378E              = 0x80C40010 | POWERPC_SVR_E500,
7170     POWERPC_SVR_8379               = 0x80C30010 | POWERPC_SVR_E500,
7171     POWERPC_SVR_8379E              = 0x80C00010 | POWERPC_SVR_E500,
7172 #define POWERPC_SVR_8533             POWERPC_SVR_8533_v11
7173     POWERPC_SVR_8533_v10           = 0x80340010 | POWERPC_SVR_E500,
7174     POWERPC_SVR_8533_v11           = 0x80340011 | POWERPC_SVR_E500,
7175 #define POWERPC_SVR_8533E            POWERPC_SVR_8533E_v11
7176     POWERPC_SVR_8533E_v10          = 0x803C0010 | POWERPC_SVR_E500,
7177     POWERPC_SVR_8533E_v11          = 0x803C0011 | POWERPC_SVR_E500,
7178 #define POWERPC_SVR_8540             POWERPC_SVR_8540_v21
7179     POWERPC_SVR_8540_v10           = 0x80300010 | POWERPC_SVR_E500,
7180     POWERPC_SVR_8540_v20           = 0x80300020 | POWERPC_SVR_E500,
7181     POWERPC_SVR_8540_v21           = 0x80300021 | POWERPC_SVR_E500,
7182 #define POWERPC_SVR_8541             POWERPC_SVR_8541_v11
7183     POWERPC_SVR_8541_v10           = 0x80720010 | POWERPC_SVR_E500,
7184     POWERPC_SVR_8541_v11           = 0x80720011 | POWERPC_SVR_E500,
7185 #define POWERPC_SVR_8541E            POWERPC_SVR_8541E_v11
7186     POWERPC_SVR_8541E_v10          = 0x807A0010 | POWERPC_SVR_E500,
7187     POWERPC_SVR_8541E_v11          = 0x807A0011 | POWERPC_SVR_E500,
7188 #define POWERPC_SVR_8543             POWERPC_SVR_8543_v21
7189     POWERPC_SVR_8543_v10           = 0x80320010 | POWERPC_SVR_E500,
7190     POWERPC_SVR_8543_v11           = 0x80320011 | POWERPC_SVR_E500,
7191     POWERPC_SVR_8543_v20           = 0x80320020 | POWERPC_SVR_E500,
7192     POWERPC_SVR_8543_v21           = 0x80320021 | POWERPC_SVR_E500,
7193 #define POWERPC_SVR_8543E            POWERPC_SVR_8543E_v21
7194     POWERPC_SVR_8543E_v10          = 0x803A0010 | POWERPC_SVR_E500,
7195     POWERPC_SVR_8543E_v11          = 0x803A0011 | POWERPC_SVR_E500,
7196     POWERPC_SVR_8543E_v20          = 0x803A0020 | POWERPC_SVR_E500,
7197     POWERPC_SVR_8543E_v21          = 0x803A0021 | POWERPC_SVR_E500,
7198 #define POWERPC_SVR_8544             POWERPC_SVR_8544_v11
7199     POWERPC_SVR_8544_v10           = 0x80340110 | POWERPC_SVR_E500,
7200     POWERPC_SVR_8544_v11           = 0x80340111 | POWERPC_SVR_E500,
7201 #define POWERPC_SVR_8544E            POWERPC_SVR_8544E_v11
7202     POWERPC_SVR_8544E_v10          = 0x803C0110 | POWERPC_SVR_E500,
7203     POWERPC_SVR_8544E_v11          = 0x803C0111 | POWERPC_SVR_E500,
7204 #define POWERPC_SVR_8545             POWERPC_SVR_8545_v21
7205     POWERPC_SVR_8545_v20           = 0x80310220 | POWERPC_SVR_E500,
7206     POWERPC_SVR_8545_v21           = 0x80310221 | POWERPC_SVR_E500,
7207 #define POWERPC_SVR_8545E            POWERPC_SVR_8545E_v21
7208     POWERPC_SVR_8545E_v20          = 0x80390220 | POWERPC_SVR_E500,
7209     POWERPC_SVR_8545E_v21          = 0x80390221 | POWERPC_SVR_E500,
7210 #define POWERPC_SVR_8547E            POWERPC_SVR_8547E_v21
7211     POWERPC_SVR_8547E_v20          = 0x80390120 | POWERPC_SVR_E500,
7212     POWERPC_SVR_8547E_v21          = 0x80390121 | POWERPC_SVR_E500,
7213 #define POWERPC_SVR_8548             POWERPC_SVR_8548_v21
7214     POWERPC_SVR_8548_v10           = 0x80310010 | POWERPC_SVR_E500,
7215     POWERPC_SVR_8548_v11           = 0x80310011 | POWERPC_SVR_E500,
7216     POWERPC_SVR_8548_v20           = 0x80310020 | POWERPC_SVR_E500,
7217     POWERPC_SVR_8548_v21           = 0x80310021 | POWERPC_SVR_E500,
7218 #define POWERPC_SVR_8548E            POWERPC_SVR_8548E_v21
7219     POWERPC_SVR_8548E_v10          = 0x80390010 | POWERPC_SVR_E500,
7220     POWERPC_SVR_8548E_v11          = 0x80390011 | POWERPC_SVR_E500,
7221     POWERPC_SVR_8548E_v20          = 0x80390020 | POWERPC_SVR_E500,
7222     POWERPC_SVR_8548E_v21          = 0x80390021 | POWERPC_SVR_E500,
7223 #define POWERPC_SVR_8555             POWERPC_SVR_8555_v11
7224     POWERPC_SVR_8555_v10           = 0x80710010 | POWERPC_SVR_E500,
7225     POWERPC_SVR_8555_v11           = 0x80710011 | POWERPC_SVR_E500,
7226 #define POWERPC_SVR_8555E            POWERPC_SVR_8555_v11
7227     POWERPC_SVR_8555E_v10          = 0x80790010 | POWERPC_SVR_E500,
7228     POWERPC_SVR_8555E_v11          = 0x80790011 | POWERPC_SVR_E500,
7229 #define POWERPC_SVR_8560             POWERPC_SVR_8560_v21
7230     POWERPC_SVR_8560_v10           = 0x80700010 | POWERPC_SVR_E500,
7231     POWERPC_SVR_8560_v20           = 0x80700020 | POWERPC_SVR_E500,
7232     POWERPC_SVR_8560_v21           = 0x80700021 | POWERPC_SVR_E500,
7233     POWERPC_SVR_8567               = 0x80750111 | POWERPC_SVR_E500,
7234     POWERPC_SVR_8567E              = 0x807D0111 | POWERPC_SVR_E500,
7235     POWERPC_SVR_8568               = 0x80750011 | POWERPC_SVR_E500,
7236     POWERPC_SVR_8568E              = 0x807D0011 | POWERPC_SVR_E500,
7237     POWERPC_SVR_8572               = 0x80E00010 | POWERPC_SVR_E500,
7238     POWERPC_SVR_8572E              = 0x80E80010 | POWERPC_SVR_E500,
7239 #if 0
7240     POWERPC_SVR_8610               = xxx,
7241 #endif
7242     POWERPC_SVR_8641               = 0x80900021,
7243     POWERPC_SVR_8641D              = 0x80900121,
7244 };
7245
7246 /*****************************************************************************/
7247 /* PowerPC CPU definitions                                                   */
7248 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type)                             \
7249     {                                                                         \
7250         .name        = _name,                                                 \
7251         .pvr         = _pvr,                                                  \
7252         .svr         = _svr,                                                  \
7253         .insns_flags = glue(POWERPC_INSNS_,_type),                            \
7254         .msr_mask    = glue(POWERPC_MSRM_,_type),                             \
7255         .mmu_model   = glue(POWERPC_MMU_,_type),                              \
7256         .excp_model  = glue(POWERPC_EXCP_,_type),                             \
7257         .bus_model   = glue(POWERPC_INPUT_,_type),                            \
7258         .bfd_mach    = glue(POWERPC_BFDM_,_type),                             \
7259         .flags       = glue(POWERPC_FLAG_,_type),                             \
7260         .init_proc   = &glue(init_proc_,_type),                               \
7261         .check_pow   = &glue(check_pow_,_type),                               \
7262     }
7263 #define POWERPC_DEF(_name, _pvr, _type)                                       \
7264 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7265
7266 static const ppc_def_t ppc_defs[] = {
7267     /* Embedded PowerPC                                                      */
7268     /* PowerPC 401 family                                                    */
7269     /* Generic PowerPC 401 */
7270     POWERPC_DEF("401",           CPU_POWERPC_401,                    401),
7271     /* PowerPC 401 cores                                                     */
7272     /* PowerPC 401A1 */
7273     POWERPC_DEF("401A1",         CPU_POWERPC_401A1,                  401),
7274     /* PowerPC 401B2                                                         */
7275     POWERPC_DEF("401B2",         CPU_POWERPC_401B2,                  401x2),
7276 #if defined (TODO)
7277     /* PowerPC 401B3                                                         */
7278     POWERPC_DEF("401B3",         CPU_POWERPC_401B3,                  401x3),
7279 #endif
7280     /* PowerPC 401C2                                                         */
7281     POWERPC_DEF("401C2",         CPU_POWERPC_401C2,                  401x2),
7282     /* PowerPC 401D2                                                         */
7283     POWERPC_DEF("401D2",         CPU_POWERPC_401D2,                  401x2),
7284     /* PowerPC 401E2                                                         */
7285     POWERPC_DEF("401E2",         CPU_POWERPC_401E2,                  401x2),
7286     /* PowerPC 401F2                                                         */
7287     POWERPC_DEF("401F2",         CPU_POWERPC_401F2,                  401x2),
7288     /* PowerPC 401G2                                                         */
7289     /* XXX: to be checked */
7290     POWERPC_DEF("401G2",         CPU_POWERPC_401G2,                  401x2),
7291     /* PowerPC 401 microcontrolers                                           */
7292 #if defined (TODO)
7293     /* PowerPC 401GF                                                         */
7294     POWERPC_DEF("401GF",         CPU_POWERPC_401GF,                  401),
7295 #endif
7296     /* IOP480 (401 microcontroler)                                           */
7297     POWERPC_DEF("IOP480",        CPU_POWERPC_IOP480,                 IOP480),
7298     /* IBM Processor for Network Resources                                   */
7299     POWERPC_DEF("Cobra",         CPU_POWERPC_COBRA,                  401),
7300 #if defined (TODO)
7301     POWERPC_DEF("Xipchip",       CPU_POWERPC_XIPCHIP,                401),
7302 #endif
7303     /* PowerPC 403 family                                                    */
7304     /* Generic PowerPC 403                                                   */
7305     POWERPC_DEF("403",           CPU_POWERPC_403,                    403),
7306     /* PowerPC 403 microcontrolers                                           */
7307     /* PowerPC 403 GA                                                        */
7308     POWERPC_DEF("403GA",         CPU_POWERPC_403GA,                  403),
7309     /* PowerPC 403 GB                                                        */
7310     POWERPC_DEF("403GB",         CPU_POWERPC_403GB,                  403),
7311     /* PowerPC 403 GC                                                        */
7312     POWERPC_DEF("403GC",         CPU_POWERPC_403GC,                  403),
7313     /* PowerPC 403 GCX                                                       */
7314     POWERPC_DEF("403GCX",        CPU_POWERPC_403GCX,                 403GCX),
7315 #if defined (TODO)
7316     /* PowerPC 403 GP                                                        */
7317     POWERPC_DEF("403GP",         CPU_POWERPC_403GP,                  403),
7318 #endif
7319     /* PowerPC 405 family                                                    */
7320     /* Generic PowerPC 405                                                   */
7321     POWERPC_DEF("405",           CPU_POWERPC_405,                    405),
7322     /* PowerPC 405 cores                                                     */
7323 #if defined (TODO)
7324     /* PowerPC 405 A3                                                        */
7325     POWERPC_DEF("405A3",         CPU_POWERPC_405A3,                  405),
7326 #endif
7327 #if defined (TODO)
7328     /* PowerPC 405 A4                                                        */
7329     POWERPC_DEF("405A4",         CPU_POWERPC_405A4,                  405),
7330 #endif
7331 #if defined (TODO)
7332     /* PowerPC 405 B3                                                        */
7333     POWERPC_DEF("405B3",         CPU_POWERPC_405B3,                  405),
7334 #endif
7335 #if defined (TODO)
7336     /* PowerPC 405 B4                                                        */
7337     POWERPC_DEF("405B4",         CPU_POWERPC_405B4,                  405),
7338 #endif
7339 #if defined (TODO)
7340     /* PowerPC 405 C3                                                        */
7341     POWERPC_DEF("405C3",         CPU_POWERPC_405C3,                  405),
7342 #endif
7343 #if defined (TODO)
7344     /* PowerPC 405 C4                                                        */
7345     POWERPC_DEF("405C4",         CPU_POWERPC_405C4,                  405),
7346 #endif
7347     /* PowerPC 405 D2                                                        */
7348     POWERPC_DEF("405D2",         CPU_POWERPC_405D2,                  405),
7349 #if defined (TODO)
7350     /* PowerPC 405 D3                                                        */
7351     POWERPC_DEF("405D3",         CPU_POWERPC_405D3,                  405),
7352 #endif
7353     /* PowerPC 405 D4                                                        */
7354     POWERPC_DEF("405D4",         CPU_POWERPC_405D4,                  405),
7355 #if defined (TODO)
7356     /* PowerPC 405 D5                                                        */
7357     POWERPC_DEF("405D5",         CPU_POWERPC_405D5,                  405),
7358 #endif
7359 #if defined (TODO)
7360     /* PowerPC 405 E4                                                        */
7361     POWERPC_DEF("405E4",         CPU_POWERPC_405E4,                  405),
7362 #endif
7363 #if defined (TODO)
7364     /* PowerPC 405 F4                                                        */
7365     POWERPC_DEF("405F4",         CPU_POWERPC_405F4,                  405),
7366 #endif
7367 #if defined (TODO)
7368     /* PowerPC 405 F5                                                        */
7369     POWERPC_DEF("405F5",         CPU_POWERPC_405F5,                  405),
7370 #endif
7371 #if defined (TODO)
7372     /* PowerPC 405 F6                                                        */
7373     POWERPC_DEF("405F6",         CPU_POWERPC_405F6,                  405),
7374 #endif
7375     /* PowerPC 405 microcontrolers                                           */
7376     /* PowerPC 405 CR                                                        */
7377     POWERPC_DEF("405CR",         CPU_POWERPC_405CR,                  405),
7378     /* PowerPC 405 CRa                                                       */
7379     POWERPC_DEF("405CRa",        CPU_POWERPC_405CRa,                 405),
7380     /* PowerPC 405 CRb                                                       */
7381     POWERPC_DEF("405CRb",        CPU_POWERPC_405CRb,                 405),
7382     /* PowerPC 405 CRc                                                       */
7383     POWERPC_DEF("405CRc",        CPU_POWERPC_405CRc,                 405),
7384     /* PowerPC 405 EP                                                        */
7385     POWERPC_DEF("405EP",         CPU_POWERPC_405EP,                  405),
7386 #if defined(TODO)
7387     /* PowerPC 405 EXr                                                       */
7388     POWERPC_DEF("405EXr",        CPU_POWERPC_405EXr,                 405),
7389 #endif
7390     /* PowerPC 405 EZ                                                        */
7391     POWERPC_DEF("405EZ",         CPU_POWERPC_405EZ,                  405),
7392 #if defined(TODO)
7393     /* PowerPC 405 FX                                                        */
7394     POWERPC_DEF("405FX",         CPU_POWERPC_405FX,                  405),
7395 #endif
7396     /* PowerPC 405 GP                                                        */
7397     POWERPC_DEF("405GP",         CPU_POWERPC_405GP,                  405),
7398     /* PowerPC 405 GPa                                                       */
7399     POWERPC_DEF("405GPa",        CPU_POWERPC_405GPa,                 405),
7400     /* PowerPC 405 GPb                                                       */
7401     POWERPC_DEF("405GPb",        CPU_POWERPC_405GPb,                 405),
7402     /* PowerPC 405 GPc                                                       */
7403     POWERPC_DEF("405GPc",        CPU_POWERPC_405GPc,                 405),
7404     /* PowerPC 405 GPd                                                       */
7405     POWERPC_DEF("405GPd",        CPU_POWERPC_405GPd,                 405),
7406     /* PowerPC 405 GPe                                                       */
7407     POWERPC_DEF("405GPe",        CPU_POWERPC_405GPe,                 405),
7408     /* PowerPC 405 GPR                                                       */
7409     POWERPC_DEF("405GPR",        CPU_POWERPC_405GPR,                 405),
7410 #if defined(TODO)
7411     /* PowerPC 405 H                                                         */
7412     POWERPC_DEF("405H",          CPU_POWERPC_405H,                   405),
7413 #endif
7414 #if defined(TODO)
7415     /* PowerPC 405 L                                                         */
7416     POWERPC_DEF("405L",          CPU_POWERPC_405L,                   405),
7417 #endif
7418     /* PowerPC 405 LP                                                        */
7419     POWERPC_DEF("405LP",         CPU_POWERPC_405LP,                  405),
7420 #if defined(TODO)
7421     /* PowerPC 405 PM                                                        */
7422     POWERPC_DEF("405PM",         CPU_POWERPC_405PM,                  405),
7423 #endif
7424 #if defined(TODO)
7425     /* PowerPC 405 PS                                                        */
7426     POWERPC_DEF("405PS",         CPU_POWERPC_405PS,                  405),
7427 #endif
7428 #if defined(TODO)
7429     /* PowerPC 405 S                                                         */
7430     POWERPC_DEF("405S",          CPU_POWERPC_405S,                   405),
7431 #endif
7432     /* Npe405 H                                                              */
7433     POWERPC_DEF("Npe405H",       CPU_POWERPC_NPE405H,                405),
7434     /* Npe405 H2                                                             */
7435     POWERPC_DEF("Npe405H2",      CPU_POWERPC_NPE405H2,               405),
7436     /* Npe405 L                                                              */
7437     POWERPC_DEF("Npe405L",       CPU_POWERPC_NPE405L,                405),
7438     /* Npe4GS3                                                               */
7439     POWERPC_DEF("Npe4GS3",       CPU_POWERPC_NPE4GS3,                405),
7440 #if defined (TODO)
7441     POWERPC_DEF("Npcxx1",        CPU_POWERPC_NPCxx1,                 405),
7442 #endif
7443 #if defined (TODO)
7444     POWERPC_DEF("Npr161",        CPU_POWERPC_NPR161,                 405),
7445 #endif
7446 #if defined (TODO)
7447     /* PowerPC LC77700 (Sanyo)                                               */
7448     POWERPC_DEF("LC77700",       CPU_POWERPC_LC77700,                405),
7449 #endif
7450     /* PowerPC 401/403/405 based set-top-box microcontrolers                 */
7451 #if defined (TODO)
7452     /* STB010000                                                             */
7453     POWERPC_DEF("STB01000",      CPU_POWERPC_STB01000,               401x2),
7454 #endif
7455 #if defined (TODO)
7456     /* STB01010                                                              */
7457     POWERPC_DEF("STB01010",      CPU_POWERPC_STB01010,               401x2),
7458 #endif
7459 #if defined (TODO)
7460     /* STB0210                                                               */
7461     POWERPC_DEF("STB0210",       CPU_POWERPC_STB0210,                401x3),
7462 #endif
7463     /* STB03xx                                                               */
7464     POWERPC_DEF("STB03",         CPU_POWERPC_STB03,                  405),
7465 #if defined (TODO)
7466     /* STB043x                                                               */
7467     POWERPC_DEF("STB043",        CPU_POWERPC_STB043,                 405),
7468 #endif
7469 #if defined (TODO)
7470     /* STB045x                                                               */
7471     POWERPC_DEF("STB045",        CPU_POWERPC_STB045,                 405),
7472 #endif
7473     /* STB04xx                                                               */
7474     POWERPC_DEF("STB04",         CPU_POWERPC_STB04,                  405),
7475     /* STB25xx                                                               */
7476     POWERPC_DEF("STB25",         CPU_POWERPC_STB25,                  405),
7477 #if defined (TODO)
7478     /* STB130                                                                */
7479     POWERPC_DEF("STB130",        CPU_POWERPC_STB130,                 405),
7480 #endif
7481     /* Xilinx PowerPC 405 cores                                              */
7482     POWERPC_DEF("x2vp4",         CPU_POWERPC_X2VP4,                  405),
7483     POWERPC_DEF("x2vp7",         CPU_POWERPC_X2VP7,                  405),
7484     POWERPC_DEF("x2vp20",        CPU_POWERPC_X2VP20,                 405),
7485     POWERPC_DEF("x2vp50",        CPU_POWERPC_X2VP50,                 405),
7486 #if defined (TODO)
7487     /* Zarlink ZL10310                                                       */
7488     POWERPC_DEF("zl10310",       CPU_POWERPC_ZL10310,                405),
7489 #endif
7490 #if defined (TODO)
7491     /* Zarlink ZL10311                                                       */
7492     POWERPC_DEF("zl10311",       CPU_POWERPC_ZL10311,                405),
7493 #endif
7494 #if defined (TODO)
7495     /* Zarlink ZL10320                                                       */
7496     POWERPC_DEF("zl10320",       CPU_POWERPC_ZL10320,                405),
7497 #endif
7498 #if defined (TODO)
7499     /* Zarlink ZL10321                                                       */
7500     POWERPC_DEF("zl10321",       CPU_POWERPC_ZL10321,                405),
7501 #endif
7502     /* PowerPC 440 family                                                    */
7503 #if defined(TODO_USER_ONLY)
7504     /* Generic PowerPC 440                                                   */
7505     POWERPC_DEF("440",           CPU_POWERPC_440,                    440GP),
7506 #endif
7507     /* PowerPC 440 cores                                                     */
7508 #if defined (TODO)
7509     /* PowerPC 440 A4                                                        */
7510     POWERPC_DEF("440A4",         CPU_POWERPC_440A4,                  440x4),
7511 #endif
7512     /* PowerPC 440 Xilinx 5                                                  */
7513     POWERPC_DEF("440-Xilinx",    CPU_POWERPC_440_XILINX,             440x5),
7514 #if defined (TODO)
7515     /* PowerPC 440 A5                                                        */
7516     POWERPC_DEF("440A5",         CPU_POWERPC_440A5,                  440x5),
7517 #endif
7518 #if defined (TODO)
7519     /* PowerPC 440 B4                                                        */
7520     POWERPC_DEF("440B4",         CPU_POWERPC_440B4,                  440x4),
7521 #endif
7522 #if defined (TODO)
7523     /* PowerPC 440 G4                                                        */
7524     POWERPC_DEF("440G4",         CPU_POWERPC_440G4,                  440x4),
7525 #endif
7526 #if defined (TODO)
7527     /* PowerPC 440 F5                                                        */
7528     POWERPC_DEF("440F5",         CPU_POWERPC_440F5,                  440x5),
7529 #endif
7530 #if defined (TODO)
7531     /* PowerPC 440 G5                                                        */
7532     POWERPC_DEF("440G5",         CPU_POWERPC_440G5,                  440x5),
7533 #endif
7534 #if defined (TODO)
7535     /* PowerPC 440H4                                                         */
7536     POWERPC_DEF("440H4",         CPU_POWERPC_440H4,                  440x4),
7537 #endif
7538 #if defined (TODO)
7539     /* PowerPC 440H6                                                         */
7540     POWERPC_DEF("440H6",         CPU_POWERPC_440H6,                  440Gx5),
7541 #endif
7542     /* PowerPC 440 microcontrolers                                           */
7543 #if defined(TODO_USER_ONLY)
7544     /* PowerPC 440 EP                                                        */
7545     POWERPC_DEF("440EP",         CPU_POWERPC_440EP,                  440EP),
7546 #endif
7547 #if defined(TODO_USER_ONLY)
7548     /* PowerPC 440 EPa                                                       */
7549     POWERPC_DEF("440EPa",        CPU_POWERPC_440EPa,                 440EP),
7550 #endif
7551 #if defined(TODO_USER_ONLY)
7552     /* PowerPC 440 EPb                                                       */
7553     POWERPC_DEF("440EPb",        CPU_POWERPC_440EPb,                 440EP),
7554 #endif
7555 #if defined(TODO_USER_ONLY)
7556     /* PowerPC 440 EPX                                                       */
7557     POWERPC_DEF("440EPX",        CPU_POWERPC_440EPX,                 440EP),
7558 #endif
7559 #if defined(TODO_USER_ONLY)
7560     /* PowerPC 440 GP                                                        */
7561     POWERPC_DEF("440GP",         CPU_POWERPC_440GP,                  440GP),
7562 #endif
7563 #if defined(TODO_USER_ONLY)
7564     /* PowerPC 440 GPb                                                       */
7565     POWERPC_DEF("440GPb",        CPU_POWERPC_440GPb,                 440GP),
7566 #endif
7567 #if defined(TODO_USER_ONLY)
7568     /* PowerPC 440 GPc                                                       */
7569     POWERPC_DEF("440GPc",        CPU_POWERPC_440GPc,                 440GP),
7570 #endif
7571 #if defined(TODO_USER_ONLY)
7572     /* PowerPC 440 GR                                                        */
7573     POWERPC_DEF("440GR",         CPU_POWERPC_440GR,                  440x5),
7574 #endif
7575 #if defined(TODO_USER_ONLY)
7576     /* PowerPC 440 GRa                                                       */
7577     POWERPC_DEF("440GRa",        CPU_POWERPC_440GRa,                 440x5),
7578 #endif
7579 #if defined(TODO_USER_ONLY)
7580     /* PowerPC 440 GRX                                                       */
7581     POWERPC_DEF("440GRX",        CPU_POWERPC_440GRX,                 440x5),
7582 #endif
7583 #if defined(TODO_USER_ONLY)
7584     /* PowerPC 440 GX                                                        */
7585     POWERPC_DEF("440GX",         CPU_POWERPC_440GX,                  440EP),
7586 #endif
7587 #if defined(TODO_USER_ONLY)
7588     /* PowerPC 440 GXa                                                       */
7589     POWERPC_DEF("440GXa",        CPU_POWERPC_440GXa,                 440EP),
7590 #endif
7591 #if defined(TODO_USER_ONLY)
7592     /* PowerPC 440 GXb                                                       */
7593     POWERPC_DEF("440GXb",        CPU_POWERPC_440GXb,                 440EP),
7594 #endif
7595 #if defined(TODO_USER_ONLY)
7596     /* PowerPC 440 GXc                                                       */
7597     POWERPC_DEF("440GXc",        CPU_POWERPC_440GXc,                 440EP),
7598 #endif
7599 #if defined(TODO_USER_ONLY)
7600     /* PowerPC 440 GXf                                                       */
7601     POWERPC_DEF("440GXf",        CPU_POWERPC_440GXf,                 440EP),
7602 #endif
7603 #if defined(TODO)
7604     /* PowerPC 440 S                                                         */
7605     POWERPC_DEF("440S",          CPU_POWERPC_440S,                   440),
7606 #endif
7607 #if defined(TODO_USER_ONLY)
7608     /* PowerPC 440 SP                                                        */
7609     POWERPC_DEF("440SP",         CPU_POWERPC_440SP,                  440EP),
7610 #endif
7611 #if defined(TODO_USER_ONLY)
7612     /* PowerPC 440 SP2                                                       */
7613     POWERPC_DEF("440SP2",        CPU_POWERPC_440SP2,                 440EP),
7614 #endif
7615 #if defined(TODO_USER_ONLY)
7616     /* PowerPC 440 SPE                                                       */
7617     POWERPC_DEF("440SPE",        CPU_POWERPC_440SPE,                 440EP),
7618 #endif
7619     /* PowerPC 460 family                                                    */
7620 #if defined (TODO)
7621     /* Generic PowerPC 464                                                   */
7622     POWERPC_DEF("464",           CPU_POWERPC_464,                    460),
7623 #endif
7624     /* PowerPC 464 microcontrolers                                           */
7625 #if defined (TODO)
7626     /* PowerPC 464H90                                                        */
7627     POWERPC_DEF("464H90",        CPU_POWERPC_464H90,                 460),
7628 #endif
7629 #if defined (TODO)
7630     /* PowerPC 464H90F                                                       */
7631     POWERPC_DEF("464H90F",       CPU_POWERPC_464H90F,                460F),
7632 #endif
7633     /* Freescale embedded PowerPC cores                                      */
7634     /* MPC5xx family (aka RCPU)                                              */
7635 #if defined(TODO_USER_ONLY)
7636     /* Generic MPC5xx core                                                   */
7637     POWERPC_DEF("MPC5xx",        CPU_POWERPC_MPC5xx,                 MPC5xx),
7638 #endif
7639 #if defined(TODO_USER_ONLY)
7640     /* Codename for MPC5xx core                                              */
7641     POWERPC_DEF("RCPU",          CPU_POWERPC_MPC5xx,                 MPC5xx),
7642 #endif
7643     /* MPC5xx microcontrollers                                               */
7644 #if defined(TODO_USER_ONLY)
7645     /* MGT560                                                                */
7646     POWERPC_DEF("MGT560",        CPU_POWERPC_MGT560,                 MPC5xx),
7647 #endif
7648 #if defined(TODO_USER_ONLY)
7649     /* MPC509                                                                */
7650     POWERPC_DEF("MPC509",        CPU_POWERPC_MPC509,                 MPC5xx),
7651 #endif
7652 #if defined(TODO_USER_ONLY)
7653     /* MPC533                                                                */
7654     POWERPC_DEF("MPC533",        CPU_POWERPC_MPC533,                 MPC5xx),
7655 #endif
7656 #if defined(TODO_USER_ONLY)
7657     /* MPC534                                                                */
7658     POWERPC_DEF("MPC534",        CPU_POWERPC_MPC534,                 MPC5xx),
7659 #endif
7660 #if defined(TODO_USER_ONLY)
7661     /* MPC555                                                                */
7662     POWERPC_DEF("MPC555",        CPU_POWERPC_MPC555,                 MPC5xx),
7663 #endif
7664 #if defined(TODO_USER_ONLY)
7665     /* MPC556                                                                */
7666     POWERPC_DEF("MPC556",        CPU_POWERPC_MPC556,                 MPC5xx),
7667 #endif
7668 #if defined(TODO_USER_ONLY)
7669     /* MPC560                                                                */
7670     POWERPC_DEF("MPC560",        CPU_POWERPC_MPC560,                 MPC5xx),
7671 #endif
7672 #if defined(TODO_USER_ONLY)
7673     /* MPC561                                                                */
7674     POWERPC_DEF("MPC561",        CPU_POWERPC_MPC561,                 MPC5xx),
7675 #endif
7676 #if defined(TODO_USER_ONLY)
7677     /* MPC562                                                                */
7678     POWERPC_DEF("MPC562",        CPU_POWERPC_MPC562,                 MPC5xx),
7679 #endif
7680 #if defined(TODO_USER_ONLY)
7681     /* MPC563                                                                */
7682     POWERPC_DEF("MPC563",        CPU_POWERPC_MPC563,                 MPC5xx),
7683 #endif
7684 #if defined(TODO_USER_ONLY)
7685     /* MPC564                                                                */
7686     POWERPC_DEF("MPC564",        CPU_POWERPC_MPC564,                 MPC5xx),
7687 #endif
7688 #if defined(TODO_USER_ONLY)
7689     /* MPC565                                                                */
7690     POWERPC_DEF("MPC565",        CPU_POWERPC_MPC565,                 MPC5xx),
7691 #endif
7692 #if defined(TODO_USER_ONLY)
7693     /* MPC566                                                                */
7694     POWERPC_DEF("MPC566",        CPU_POWERPC_MPC566,                 MPC5xx),
7695 #endif
7696     /* MPC8xx family (aka PowerQUICC)                                        */
7697 #if defined(TODO_USER_ONLY)
7698     /* Generic MPC8xx core                                                   */
7699     POWERPC_DEF("MPC8xx",        CPU_POWERPC_MPC8xx,                 MPC8xx),
7700 #endif
7701 #if defined(TODO_USER_ONLY)
7702     /* Codename for MPC8xx core                                              */
7703     POWERPC_DEF("PowerQUICC",    CPU_POWERPC_MPC8xx,                 MPC8xx),
7704 #endif
7705     /* MPC8xx microcontrollers                                               */
7706 #if defined(TODO_USER_ONLY)
7707     /* MGT823                                                                */
7708     POWERPC_DEF("MGT823",        CPU_POWERPC_MGT823,                 MPC8xx),
7709 #endif
7710 #if defined(TODO_USER_ONLY)
7711     /* MPC821                                                                */
7712     POWERPC_DEF("MPC821",        CPU_POWERPC_MPC821,                 MPC8xx),
7713 #endif
7714 #if defined(TODO_USER_ONLY)
7715     /* MPC823                                                                */
7716     POWERPC_DEF("MPC823",        CPU_POWERPC_MPC823,                 MPC8xx),
7717 #endif
7718 #if defined(TODO_USER_ONLY)
7719     /* MPC850                                                                */
7720     POWERPC_DEF("MPC850",        CPU_POWERPC_MPC850,                 MPC8xx),
7721 #endif
7722 #if defined(TODO_USER_ONLY)
7723     /* MPC852T                                                               */
7724     POWERPC_DEF("MPC852T",       CPU_POWERPC_MPC852T,                MPC8xx),
7725 #endif
7726 #if defined(TODO_USER_ONLY)
7727     /* MPC855T                                                               */
7728     POWERPC_DEF("MPC855T",       CPU_POWERPC_MPC855T,                MPC8xx),
7729 #endif
7730 #if defined(TODO_USER_ONLY)
7731     /* MPC857                                                                */
7732     POWERPC_DEF("MPC857",        CPU_POWERPC_MPC857,                 MPC8xx),
7733 #endif
7734 #if defined(TODO_USER_ONLY)
7735     /* MPC859                                                                */
7736     POWERPC_DEF("MPC859",        CPU_POWERPC_MPC859,                 MPC8xx),
7737 #endif
7738 #if defined(TODO_USER_ONLY)
7739     /* MPC860                                                                */
7740     POWERPC_DEF("MPC860",        CPU_POWERPC_MPC860,                 MPC8xx),
7741 #endif
7742 #if defined(TODO_USER_ONLY)
7743     /* MPC862                                                                */
7744     POWERPC_DEF("MPC862",        CPU_POWERPC_MPC862,                 MPC8xx),
7745 #endif
7746 #if defined(TODO_USER_ONLY)
7747     /* MPC866                                                                */
7748     POWERPC_DEF("MPC866",        CPU_POWERPC_MPC866,                 MPC8xx),
7749 #endif
7750 #if defined(TODO_USER_ONLY)
7751     /* MPC870                                                                */
7752     POWERPC_DEF("MPC870",        CPU_POWERPC_MPC870,                 MPC8xx),
7753 #endif
7754 #if defined(TODO_USER_ONLY)
7755     /* MPC875                                                                */
7756     POWERPC_DEF("MPC875",        CPU_POWERPC_MPC875,                 MPC8xx),
7757 #endif
7758 #if defined(TODO_USER_ONLY)
7759     /* MPC880                                                                */
7760     POWERPC_DEF("MPC880",        CPU_POWERPC_MPC880,                 MPC8xx),
7761 #endif
7762 #if defined(TODO_USER_ONLY)
7763     /* MPC885                                                                */
7764     POWERPC_DEF("MPC885",        CPU_POWERPC_MPC885,                 MPC8xx),
7765 #endif
7766     /* MPC82xx family (aka PowerQUICC-II)                                    */
7767     /* Generic MPC52xx core                                                  */
7768     POWERPC_DEF_SVR("MPC52xx",
7769                     CPU_POWERPC_MPC52xx,      POWERPC_SVR_52xx,      G2LE),
7770     /* Generic MPC82xx core                                                  */
7771     POWERPC_DEF("MPC82xx",       CPU_POWERPC_MPC82xx,                G2),
7772     /* Codename for MPC82xx                                                  */
7773     POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx,                G2),
7774     /* PowerPC G2 core                                                       */
7775     POWERPC_DEF("G2",            CPU_POWERPC_G2,                     G2),
7776     /* PowerPC G2 H4 core                                                    */
7777     POWERPC_DEF("G2H4",          CPU_POWERPC_G2H4,                   G2),
7778     /* PowerPC G2 GP core                                                    */
7779     POWERPC_DEF("G2GP",          CPU_POWERPC_G2gp,                   G2),
7780     /* PowerPC G2 LS core                                                    */
7781     POWERPC_DEF("G2LS",          CPU_POWERPC_G2ls,                   G2),
7782     /* PowerPC G2 HiP3 core                                                  */
7783     POWERPC_DEF("G2HiP3",        CPU_POWERPC_G2_HIP3,                G2),
7784     /* PowerPC G2 HiP4 core                                                  */
7785     POWERPC_DEF("G2HiP4",        CPU_POWERPC_G2_HIP4,                G2),
7786     /* PowerPC MPC603 core                                                   */
7787     POWERPC_DEF("MPC603",        CPU_POWERPC_MPC603,                 603E),
7788     /* PowerPC G2le core (same as G2 plus little-endian mode support)        */
7789     POWERPC_DEF("G2le",          CPU_POWERPC_G2LE,                   G2LE),
7790     /* PowerPC G2LE GP core                                                  */
7791     POWERPC_DEF("G2leGP",        CPU_POWERPC_G2LEgp,                 G2LE),
7792     /* PowerPC G2LE LS core                                                  */
7793     POWERPC_DEF("G2leLS",        CPU_POWERPC_G2LEls,                 G2LE),
7794     /* PowerPC G2LE GP1 core                                                 */
7795     POWERPC_DEF("G2leGP1",       CPU_POWERPC_G2LEgp1,                G2LE),
7796     /* PowerPC G2LE GP3 core                                                 */
7797     POWERPC_DEF("G2leGP3",       CPU_POWERPC_G2LEgp1,                G2LE),
7798     /* PowerPC MPC603 microcontrollers                                       */
7799     /* MPC8240                                                               */
7800     POWERPC_DEF("MPC8240",       CPU_POWERPC_MPC8240,                603E),
7801     /* PowerPC G2 microcontrollers                                           */
7802 #if defined(TODO)
7803     /* MPC5121                                                               */
7804     POWERPC_DEF_SVR("MPC5121",
7805                     CPU_POWERPC_MPC5121,      POWERPC_SVR_5121,      G2LE),
7806 #endif
7807     /* MPC5200                                                               */
7808     POWERPC_DEF_SVR("MPC5200",
7809                     CPU_POWERPC_MPC5200,      POWERPC_SVR_5200,      G2LE),
7810     /* MPC5200 v1.0                                                          */
7811     POWERPC_DEF_SVR("MPC5200_v10",
7812                     CPU_POWERPC_MPC5200_v10,  POWERPC_SVR_5200_v10,  G2LE),
7813     /* MPC5200 v1.1                                                          */
7814     POWERPC_DEF_SVR("MPC5200_v11",
7815                     CPU_POWERPC_MPC5200_v11,  POWERPC_SVR_5200_v11,  G2LE),
7816     /* MPC5200 v1.2                                                          */
7817     POWERPC_DEF_SVR("MPC5200_v12",
7818                     CPU_POWERPC_MPC5200_v12,  POWERPC_SVR_5200_v12,  G2LE),
7819     /* MPC5200B                                                              */
7820     POWERPC_DEF_SVR("MPC5200B",
7821                     CPU_POWERPC_MPC5200B,     POWERPC_SVR_5200B,     G2LE),
7822     /* MPC5200B v2.0                                                         */
7823     POWERPC_DEF_SVR("MPC5200B_v20",
7824                     CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7825     /* MPC5200B v2.1                                                         */
7826     POWERPC_DEF_SVR("MPC5200B_v21",
7827                     CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7828     /* MPC8241                                                               */
7829     POWERPC_DEF("MPC8241",       CPU_POWERPC_MPC8241,                G2),
7830     /* MPC8245                                                               */
7831     POWERPC_DEF("MPC8245",       CPU_POWERPC_MPC8245,                G2),
7832     /* MPC8247                                                               */
7833     POWERPC_DEF("MPC8247",       CPU_POWERPC_MPC8247,                G2LE),
7834     /* MPC8248                                                               */
7835     POWERPC_DEF("MPC8248",       CPU_POWERPC_MPC8248,                G2LE),
7836     /* MPC8250                                                               */
7837     POWERPC_DEF("MPC8250",       CPU_POWERPC_MPC8250,                G2),
7838     /* MPC8250 HiP3                                                          */
7839     POWERPC_DEF("MPC8250_HiP3",  CPU_POWERPC_MPC8250_HiP3,           G2),
7840     /* MPC8250 HiP4                                                          */
7841     POWERPC_DEF("MPC8250_HiP4",  CPU_POWERPC_MPC8250_HiP4,           G2),
7842     /* MPC8255                                                               */
7843     POWERPC_DEF("MPC8255",       CPU_POWERPC_MPC8255,                G2),
7844     /* MPC8255 HiP3                                                          */
7845     POWERPC_DEF("MPC8255_HiP3",  CPU_POWERPC_MPC8255_HiP3,           G2),
7846     /* MPC8255 HiP4                                                          */
7847     POWERPC_DEF("MPC8255_HiP4",  CPU_POWERPC_MPC8255_HiP4,           G2),
7848     /* MPC8260                                                               */
7849     POWERPC_DEF("MPC8260",       CPU_POWERPC_MPC8260,                G2),
7850     /* MPC8260 HiP3                                                          */
7851     POWERPC_DEF("MPC8260_HiP3",  CPU_POWERPC_MPC8260_HiP3,           G2),
7852     /* MPC8260 HiP4                                                          */
7853     POWERPC_DEF("MPC8260_HiP4",  CPU_POWERPC_MPC8260_HiP4,           G2),
7854     /* MPC8264                                                               */
7855     POWERPC_DEF("MPC8264",       CPU_POWERPC_MPC8264,                G2),
7856     /* MPC8264 HiP3                                                          */
7857     POWERPC_DEF("MPC8264_HiP3",  CPU_POWERPC_MPC8264_HiP3,           G2),
7858     /* MPC8264 HiP4                                                          */
7859     POWERPC_DEF("MPC8264_HiP4",  CPU_POWERPC_MPC8264_HiP4,           G2),
7860     /* MPC8265                                                               */
7861     POWERPC_DEF("MPC8265",       CPU_POWERPC_MPC8265,                G2),
7862     /* MPC8265 HiP3                                                          */
7863     POWERPC_DEF("MPC8265_HiP3",  CPU_POWERPC_MPC8265_HiP3,           G2),
7864     /* MPC8265 HiP4                                                          */
7865     POWERPC_DEF("MPC8265_HiP4",  CPU_POWERPC_MPC8265_HiP4,           G2),
7866     /* MPC8266                                                               */
7867     POWERPC_DEF("MPC8266",       CPU_POWERPC_MPC8266,                G2),
7868     /* MPC8266 HiP3                                                          */
7869     POWERPC_DEF("MPC8266_HiP3",  CPU_POWERPC_MPC8266_HiP3,           G2),
7870     /* MPC8266 HiP4                                                          */
7871     POWERPC_DEF("MPC8266_HiP4",  CPU_POWERPC_MPC8266_HiP4,           G2),
7872     /* MPC8270                                                               */
7873     POWERPC_DEF("MPC8270",       CPU_POWERPC_MPC8270,                G2LE),
7874     /* MPC8271                                                               */
7875     POWERPC_DEF("MPC8271",       CPU_POWERPC_MPC8271,                G2LE),
7876     /* MPC8272                                                               */
7877     POWERPC_DEF("MPC8272",       CPU_POWERPC_MPC8272,                G2LE),
7878     /* MPC8275                                                               */
7879     POWERPC_DEF("MPC8275",       CPU_POWERPC_MPC8275,                G2LE),
7880     /* MPC8280                                                               */
7881     POWERPC_DEF("MPC8280",       CPU_POWERPC_MPC8280,                G2LE),
7882     /* e200 family                                                           */
7883     /* Generic PowerPC e200 core                                             */
7884     POWERPC_DEF("e200",          CPU_POWERPC_e200,                   e200),
7885     /* Generic MPC55xx core                                                  */
7886 #if defined (TODO)
7887     POWERPC_DEF_SVR("MPC55xx",
7888                     CPU_POWERPC_MPC55xx,      POWERPC_SVR_55xx,      e200),
7889 #endif
7890 #if defined (TODO)
7891     /* PowerPC e200z0 core                                                   */
7892     POWERPC_DEF("e200z0",        CPU_POWERPC_e200z0,                 e200),
7893 #endif
7894 #if defined (TODO)
7895     /* PowerPC e200z1 core                                                   */
7896     POWERPC_DEF("e200z1",        CPU_POWERPC_e200z1,                 e200),
7897 #endif
7898 #if defined (TODO)
7899     /* PowerPC e200z3 core                                                   */
7900     POWERPC_DEF("e200z3",        CPU_POWERPC_e200z3,                 e200),
7901 #endif
7902     /* PowerPC e200z5 core                                                   */
7903     POWERPC_DEF("e200z5",        CPU_POWERPC_e200z5,                 e200),
7904     /* PowerPC e200z6 core                                                   */
7905     POWERPC_DEF("e200z6",        CPU_POWERPC_e200z6,                 e200),
7906     /* PowerPC e200 microcontrollers                                         */
7907 #if defined (TODO)
7908     /* MPC5514E                                                              */
7909     POWERPC_DEF_SVR("MPC5514E",
7910                     CPU_POWERPC_MPC5514E,     POWERPC_SVR_5514E,     e200),
7911 #endif
7912 #if defined (TODO)
7913     /* MPC5514E v0                                                           */
7914     POWERPC_DEF_SVR("MPC5514E_v0",
7915                     CPU_POWERPC_MPC5514E_v0,  POWERPC_SVR_5514E_v0,  e200),
7916 #endif
7917 #if defined (TODO)
7918     /* MPC5514E v1                                                           */
7919     POWERPC_DEF_SVR("MPC5514E_v1",
7920                     CPU_POWERPC_MPC5514E_v1,  POWERPC_SVR_5514E_v1,  e200),
7921 #endif
7922 #if defined (TODO)
7923     /* MPC5514G                                                              */
7924     POWERPC_DEF_SVR("MPC5514G",
7925                     CPU_POWERPC_MPC5514G,     POWERPC_SVR_5514G,     e200),
7926 #endif
7927 #if defined (TODO)
7928     /* MPC5514G v0                                                           */
7929     POWERPC_DEF_SVR("MPC5514G_v0",
7930                     CPU_POWERPC_MPC5514G_v0,  POWERPC_SVR_5514G_v0,  e200),
7931 #endif
7932 #if defined (TODO)
7933     /* MPC5514G v1                                                           */
7934     POWERPC_DEF_SVR("MPC5514G_v1",
7935                     CPU_POWERPC_MPC5514G_v1,  POWERPC_SVR_5514G_v1,  e200),
7936 #endif
7937 #if defined (TODO)
7938     /* MPC5515S                                                              */
7939     POWERPC_DEF_SVR("MPC5515S",
7940                     CPU_POWERPC_MPC5515S,     POWERPC_SVR_5515S,     e200),
7941 #endif
7942 #if defined (TODO)
7943     /* MPC5516E                                                              */
7944     POWERPC_DEF_SVR("MPC5516E",
7945                     CPU_POWERPC_MPC5516E,     POWERPC_SVR_5516E,     e200),
7946 #endif
7947 #if defined (TODO)
7948     /* MPC5516E v0                                                           */
7949     POWERPC_DEF_SVR("MPC5516E_v0",
7950                     CPU_POWERPC_MPC5516E_v0,  POWERPC_SVR_5516E_v0,  e200),
7951 #endif
7952 #if defined (TODO)
7953     /* MPC5516E v1                                                           */
7954     POWERPC_DEF_SVR("MPC5516E_v1",
7955                     CPU_POWERPC_MPC5516E_v1,  POWERPC_SVR_5516E_v1,  e200),
7956 #endif
7957 #if defined (TODO)
7958     /* MPC5516G                                                              */
7959     POWERPC_DEF_SVR("MPC5516G",
7960                     CPU_POWERPC_MPC5516G,     POWERPC_SVR_5516G,     e200),
7961 #endif
7962 #if defined (TODO)
7963     /* MPC5516G v0                                                           */
7964     POWERPC_DEF_SVR("MPC5516G_v0",
7965                     CPU_POWERPC_MPC5516G_v0,  POWERPC_SVR_5516G_v0,  e200),
7966 #endif
7967 #if defined (TODO)
7968     /* MPC5516G v1                                                           */
7969     POWERPC_DEF_SVR("MPC5516G_v1",
7970                     CPU_POWERPC_MPC5516G_v1,  POWERPC_SVR_5516G_v1,  e200),
7971 #endif
7972 #if defined (TODO)
7973     /* MPC5516S                                                              */
7974     POWERPC_DEF_SVR("MPC5516S",
7975                     CPU_POWERPC_MPC5516S,     POWERPC_SVR_5516S,     e200),
7976 #endif
7977 #if defined (TODO)
7978     /* MPC5533                                                               */
7979     POWERPC_DEF_SVR("MPC5533",
7980                     CPU_POWERPC_MPC5533,      POWERPC_SVR_5533,      e200),
7981 #endif
7982 #if defined (TODO)
7983     /* MPC5534                                                               */
7984     POWERPC_DEF_SVR("MPC5534",
7985                     CPU_POWERPC_MPC5534,      POWERPC_SVR_5534,      e200),
7986 #endif
7987 #if defined (TODO)
7988     /* MPC5553                                                               */
7989     POWERPC_DEF_SVR("MPC5553",
7990                     CPU_POWERPC_MPC5553,      POWERPC_SVR_5553,      e200),
7991 #endif
7992 #if defined (TODO)
7993     /* MPC5554                                                               */
7994     POWERPC_DEF_SVR("MPC5554",
7995                     CPU_POWERPC_MPC5554,      POWERPC_SVR_5554,      e200),
7996 #endif
7997 #if defined (TODO)
7998     /* MPC5561                                                               */
7999     POWERPC_DEF_SVR("MPC5561",
8000                     CPU_POWERPC_MPC5561,      POWERPC_SVR_5561,      e200),
8001 #endif
8002 #if defined (TODO)
8003     /* MPC5565                                                               */
8004     POWERPC_DEF_SVR("MPC5565",
8005                     CPU_POWERPC_MPC5565,      POWERPC_SVR_5565,      e200),
8006 #endif
8007 #if defined (TODO)
8008     /* MPC5566                                                               */
8009     POWERPC_DEF_SVR("MPC5566",
8010                     CPU_POWERPC_MPC5566,      POWERPC_SVR_5566,      e200),
8011 #endif
8012 #if defined (TODO)
8013     /* MPC5567                                                               */
8014     POWERPC_DEF_SVR("MPC5567",
8015                     CPU_POWERPC_MPC5567,      POWERPC_SVR_5567,      e200),
8016 #endif
8017     /* e300 family                                                           */
8018     /* Generic PowerPC e300 core                                             */
8019     POWERPC_DEF("e300",          CPU_POWERPC_e300,                   e300),
8020     /* PowerPC e300c1 core                                                   */
8021     POWERPC_DEF("e300c1",        CPU_POWERPC_e300c1,                 e300),
8022     /* PowerPC e300c2 core                                                   */
8023     POWERPC_DEF("e300c2",        CPU_POWERPC_e300c2,                 e300),
8024     /* PowerPC e300c3 core                                                   */
8025     POWERPC_DEF("e300c3",        CPU_POWERPC_e300c3,                 e300),
8026     /* PowerPC e300c4 core                                                   */
8027     POWERPC_DEF("e300c4",        CPU_POWERPC_e300c4,                 e300),
8028     /* PowerPC e300 microcontrollers                                         */
8029 #if defined (TODO)
8030     /* MPC8313                                                               */
8031     POWERPC_DEF_SVR("MPC8313",
8032                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8313,      e300),
8033 #endif
8034 #if defined (TODO)
8035     /* MPC8313E                                                              */
8036     POWERPC_DEF_SVR("MPC8313E",
8037                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8313E,     e300),
8038 #endif
8039 #if defined (TODO)
8040     /* MPC8314                                                               */
8041     POWERPC_DEF_SVR("MPC8314",
8042                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8314,      e300),
8043 #endif
8044 #if defined (TODO)
8045     /* MPC8314E                                                              */
8046     POWERPC_DEF_SVR("MPC8314E",
8047                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8314E,     e300),
8048 #endif
8049 #if defined (TODO)
8050     /* MPC8315                                                               */
8051     POWERPC_DEF_SVR("MPC8315",
8052                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8315,      e300),
8053 #endif
8054 #if defined (TODO)
8055     /* MPC8315E                                                              */
8056     POWERPC_DEF_SVR("MPC8315E",
8057                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8315E,     e300),
8058 #endif
8059 #if defined (TODO)
8060     /* MPC8321                                                               */
8061     POWERPC_DEF_SVR("MPC8321",
8062                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8321,      e300),
8063 #endif
8064 #if defined (TODO)
8065     /* MPC8321E                                                              */
8066     POWERPC_DEF_SVR("MPC8321E",
8067                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8321E,     e300),
8068 #endif
8069 #if defined (TODO)
8070     /* MPC8323                                                               */
8071     POWERPC_DEF_SVR("MPC8323",
8072                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8323,      e300),
8073 #endif
8074 #if defined (TODO)
8075     /* MPC8323E                                                              */
8076     POWERPC_DEF_SVR("MPC8323E",
8077                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8323E,     e300),
8078 #endif
8079     /* MPC8343                                                               */
8080     POWERPC_DEF_SVR("MPC8343",
8081                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343,      e300),
8082     /* MPC8343A                                                              */
8083     POWERPC_DEF_SVR("MPC8343A",
8084                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343A,     e300),
8085     /* MPC8343E                                                              */
8086     POWERPC_DEF_SVR("MPC8343E",
8087                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343E,     e300),
8088     /* MPC8343EA                                                             */
8089     POWERPC_DEF_SVR("MPC8343EA",
8090                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343EA,    e300),
8091     /* MPC8347                                                               */
8092     POWERPC_DEF_SVR("MPC8347",
8093                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347,      e300),
8094     /* MPC8347T                                                              */
8095     POWERPC_DEF_SVR("MPC8347T",
8096                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347T,     e300),
8097     /* MPC8347P                                                              */
8098     POWERPC_DEF_SVR("MPC8347P",
8099                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347P,     e300),
8100     /* MPC8347A                                                              */
8101     POWERPC_DEF_SVR("MPC8347A",
8102                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347A,     e300),
8103     /* MPC8347AT                                                             */
8104     POWERPC_DEF_SVR("MPC8347AT",
8105                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347AT,    e300),
8106     /* MPC8347AP                                                             */
8107     POWERPC_DEF_SVR("MPC8347AP",
8108                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347AP,    e300),
8109     /* MPC8347E                                                              */
8110     POWERPC_DEF_SVR("MPC8347E",
8111                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347E,     e300),
8112     /* MPC8347ET                                                             */
8113     POWERPC_DEF_SVR("MPC8347ET",
8114                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347ET,    e300),
8115     /* MPC8343EP                                                             */
8116     POWERPC_DEF_SVR("MPC8347EP",
8117                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EP,    e300),
8118     /* MPC8347EA                                                             */
8119     POWERPC_DEF_SVR("MPC8347EA",
8120                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EA,    e300),
8121     /* MPC8347EAT                                                            */
8122     POWERPC_DEF_SVR("MPC8347EAT",
8123                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EAT,   e300),
8124     /* MPC8343EAP                                                            */
8125     POWERPC_DEF_SVR("MPC8347EAP",
8126                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EAP,   e300),
8127     /* MPC8349                                                               */
8128     POWERPC_DEF_SVR("MPC8349",
8129                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349,      e300),
8130     /* MPC8349A                                                              */
8131     POWERPC_DEF_SVR("MPC8349A",
8132                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349A,     e300),
8133     /* MPC8349E                                                              */
8134     POWERPC_DEF_SVR("MPC8349E",
8135                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349E,     e300),
8136     /* MPC8349EA                                                             */
8137     POWERPC_DEF_SVR("MPC8349EA",
8138                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349EA,    e300),
8139 #if defined (TODO)
8140     /* MPC8358E                                                              */
8141     POWERPC_DEF_SVR("MPC8358E",
8142                     CPU_POWERPC_MPC835x,      POWERPC_SVR_8358E,     e300),
8143 #endif
8144 #if defined (TODO)
8145     /* MPC8360E                                                              */
8146     POWERPC_DEF_SVR("MPC8360E",
8147                     CPU_POWERPC_MPC836x,      POWERPC_SVR_8360E,     e300),
8148 #endif
8149     /* MPC8377                                                               */
8150     POWERPC_DEF_SVR("MPC8377",
8151                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8377,      e300),
8152     /* MPC8377E                                                              */
8153     POWERPC_DEF_SVR("MPC8377E",
8154                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8377E,     e300),
8155     /* MPC8378                                                               */
8156     POWERPC_DEF_SVR("MPC8378",
8157                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8378,      e300),
8158     /* MPC8378E                                                              */
8159     POWERPC_DEF_SVR("MPC8378E",
8160                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8378E,     e300),
8161     /* MPC8379                                                               */
8162     POWERPC_DEF_SVR("MPC8379",
8163                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8379,      e300),
8164     /* MPC8379E                                                              */
8165     POWERPC_DEF_SVR("MPC8379E",
8166                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8379E,     e300),
8167     /* e500 family                                                           */
8168     /* PowerPC e500 core                                                     */
8169     POWERPC_DEF("e500",          CPU_POWERPC_e500v2_v22,             e500v2),
8170     /* PowerPC e500v1 core                                                   */
8171     POWERPC_DEF("e500v1",        CPU_POWERPC_e500v1,                 e500v1),
8172     /* PowerPC e500 v1.0 core                                                */
8173     POWERPC_DEF("e500_v10",      CPU_POWERPC_e500v1_v10,             e500v1),
8174     /* PowerPC e500 v2.0 core                                                */
8175     POWERPC_DEF("e500_v20",      CPU_POWERPC_e500v1_v20,             e500v1),
8176     /* PowerPC e500v2 core                                                   */
8177     POWERPC_DEF("e500v2",        CPU_POWERPC_e500v2,                 e500v2),
8178     /* PowerPC e500v2 v1.0 core                                              */
8179     POWERPC_DEF("e500v2_v10",    CPU_POWERPC_e500v2_v10,             e500v2),
8180     /* PowerPC e500v2 v2.0 core                                              */
8181     POWERPC_DEF("e500v2_v20",    CPU_POWERPC_e500v2_v20,             e500v2),
8182     /* PowerPC e500v2 v2.1 core                                              */
8183     POWERPC_DEF("e500v2_v21",    CPU_POWERPC_e500v2_v21,             e500v2),
8184     /* PowerPC e500v2 v2.2 core                                              */
8185     POWERPC_DEF("e500v2_v22",    CPU_POWERPC_e500v2_v22,             e500v2),
8186     /* PowerPC e500v2 v3.0 core                                              */
8187     POWERPC_DEF("e500v2_v30",    CPU_POWERPC_e500v2_v30,             e500v2),
8188     /* PowerPC e500 microcontrollers                                         */
8189     /* MPC8533                                                               */
8190     POWERPC_DEF_SVR("MPC8533",
8191                     CPU_POWERPC_MPC8533,      POWERPC_SVR_8533,      e500v2),
8192     /* MPC8533 v1.0                                                          */
8193     POWERPC_DEF_SVR("MPC8533_v10",
8194                     CPU_POWERPC_MPC8533_v10,  POWERPC_SVR_8533_v10,  e500v2),
8195     /* MPC8533 v1.1                                                          */
8196     POWERPC_DEF_SVR("MPC8533_v11",
8197                     CPU_POWERPC_MPC8533_v11,  POWERPC_SVR_8533_v11,  e500v2),
8198     /* MPC8533E                                                              */
8199     POWERPC_DEF_SVR("MPC8533E",
8200                     CPU_POWERPC_MPC8533E,     POWERPC_SVR_8533E,     e500v2),
8201     /* MPC8533E v1.0                                                         */
8202     POWERPC_DEF_SVR("MPC8533E_v10",
8203                     CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8204     POWERPC_DEF_SVR("MPC8533E_v11",
8205                     CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8206     /* MPC8540                                                               */
8207     POWERPC_DEF_SVR("MPC8540",
8208                     CPU_POWERPC_MPC8540,      POWERPC_SVR_8540,      e500v1),
8209     /* MPC8540 v1.0                                                          */
8210     POWERPC_DEF_SVR("MPC8540_v10",
8211                     CPU_POWERPC_MPC8540_v10,  POWERPC_SVR_8540_v10,  e500v1),
8212     /* MPC8540 v2.0                                                          */
8213     POWERPC_DEF_SVR("MPC8540_v20",
8214                     CPU_POWERPC_MPC8540_v20,  POWERPC_SVR_8540_v20,  e500v1),
8215     /* MPC8540 v2.1                                                          */
8216     POWERPC_DEF_SVR("MPC8540_v21",
8217                     CPU_POWERPC_MPC8540_v21,  POWERPC_SVR_8540_v21,  e500v1),
8218     /* MPC8541                                                               */
8219     POWERPC_DEF_SVR("MPC8541",
8220                     CPU_POWERPC_MPC8541,      POWERPC_SVR_8541,      e500v1),
8221     /* MPC8541 v1.0                                                          */
8222     POWERPC_DEF_SVR("MPC8541_v10",
8223                     CPU_POWERPC_MPC8541_v10,  POWERPC_SVR_8541_v10,  e500v1),
8224     /* MPC8541 v1.1                                                          */
8225     POWERPC_DEF_SVR("MPC8541_v11",
8226                     CPU_POWERPC_MPC8541_v11,  POWERPC_SVR_8541_v11,  e500v1),
8227     /* MPC8541E                                                              */
8228     POWERPC_DEF_SVR("MPC8541E",
8229                     CPU_POWERPC_MPC8541E,     POWERPC_SVR_8541E,     e500v1),
8230     /* MPC8541E v1.0                                                         */
8231     POWERPC_DEF_SVR("MPC8541E_v10",
8232                     CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8233     /* MPC8541E v1.1                                                         */
8234     POWERPC_DEF_SVR("MPC8541E_v11",
8235                     CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8236     /* MPC8543                                                               */
8237     POWERPC_DEF_SVR("MPC8543",
8238                     CPU_POWERPC_MPC8543,      POWERPC_SVR_8543,      e500v2),
8239     /* MPC8543 v1.0                                                          */
8240     POWERPC_DEF_SVR("MPC8543_v10",
8241                     CPU_POWERPC_MPC8543_v10,  POWERPC_SVR_8543_v10,  e500v2),
8242     /* MPC8543 v1.1                                                          */
8243     POWERPC_DEF_SVR("MPC8543_v11",
8244                     CPU_POWERPC_MPC8543_v11,  POWERPC_SVR_8543_v11,  e500v2),
8245     /* MPC8543 v2.0                                                          */
8246     POWERPC_DEF_SVR("MPC8543_v20",
8247                     CPU_POWERPC_MPC8543_v20,  POWERPC_SVR_8543_v20,  e500v2),
8248     /* MPC8543 v2.1                                                          */
8249     POWERPC_DEF_SVR("MPC8543_v21",
8250                     CPU_POWERPC_MPC8543_v21,  POWERPC_SVR_8543_v21,  e500v2),
8251     /* MPC8543E                                                              */
8252     POWERPC_DEF_SVR("MPC8543E",
8253                     CPU_POWERPC_MPC8543E,     POWERPC_SVR_8543E,     e500v2),
8254     /* MPC8543E v1.0                                                         */
8255     POWERPC_DEF_SVR("MPC8543E_v10",
8256                     CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8257     /* MPC8543E v1.1                                                         */
8258     POWERPC_DEF_SVR("MPC8543E_v11",
8259                     CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8260     /* MPC8543E v2.0                                                         */
8261     POWERPC_DEF_SVR("MPC8543E_v20",
8262                     CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8263     /* MPC8543E v2.1                                                         */
8264     POWERPC_DEF_SVR("MPC8543E_v21",
8265                     CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8266     /* MPC8544                                                               */
8267     POWERPC_DEF_SVR("MPC8544",
8268                     CPU_POWERPC_MPC8544,      POWERPC_SVR_8544,      e500v2),
8269     /* MPC8544 v1.0                                                          */
8270     POWERPC_DEF_SVR("MPC8544_v10",
8271                     CPU_POWERPC_MPC8544_v10,  POWERPC_SVR_8544_v10,  e500v2),
8272     /* MPC8544 v1.1                                                          */
8273     POWERPC_DEF_SVR("MPC8544_v11",
8274                     CPU_POWERPC_MPC8544_v11,  POWERPC_SVR_8544_v11,  e500v2),
8275     /* MPC8544E                                                              */
8276     POWERPC_DEF_SVR("MPC8544E",
8277                     CPU_POWERPC_MPC8544E,     POWERPC_SVR_8544E,     e500v2),
8278     /* MPC8544E v1.0                                                         */
8279     POWERPC_DEF_SVR("MPC8544E_v10",
8280                     CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8281     /* MPC8544E v1.1                                                         */
8282     POWERPC_DEF_SVR("MPC8544E_v11",
8283                     CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8284     /* MPC8545                                                               */
8285     POWERPC_DEF_SVR("MPC8545",
8286                     CPU_POWERPC_MPC8545,      POWERPC_SVR_8545,      e500v2),
8287     /* MPC8545 v2.0                                                          */
8288     POWERPC_DEF_SVR("MPC8545_v20",
8289                     CPU_POWERPC_MPC8545_v20,  POWERPC_SVR_8545_v20,  e500v2),
8290     /* MPC8545 v2.1                                                          */
8291     POWERPC_DEF_SVR("MPC8545_v21",
8292                     CPU_POWERPC_MPC8545_v21,  POWERPC_SVR_8545_v21,  e500v2),
8293     /* MPC8545E                                                              */
8294     POWERPC_DEF_SVR("MPC8545E",
8295                     CPU_POWERPC_MPC8545E,     POWERPC_SVR_8545E,     e500v2),
8296     /* MPC8545E v2.0                                                         */
8297     POWERPC_DEF_SVR("MPC8545E_v20",
8298                     CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8299     /* MPC8545E v2.1                                                         */
8300     POWERPC_DEF_SVR("MPC8545E_v21",
8301                     CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8302     /* MPC8547E                                                              */
8303     POWERPC_DEF_SVR("MPC8547E",
8304                     CPU_POWERPC_MPC8547E,     POWERPC_SVR_8547E,     e500v2),
8305     /* MPC8547E v2.0                                                         */
8306     POWERPC_DEF_SVR("MPC8547E_v20",
8307                     CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8308     /* MPC8547E v2.1                                                         */
8309     POWERPC_DEF_SVR("MPC8547E_v21",
8310                     CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8311     /* MPC8548                                                               */
8312     POWERPC_DEF_SVR("MPC8548",
8313                     CPU_POWERPC_MPC8548,      POWERPC_SVR_8548,      e500v2),
8314     /* MPC8548 v1.0                                                          */
8315     POWERPC_DEF_SVR("MPC8548_v10",
8316                     CPU_POWERPC_MPC8548_v10,  POWERPC_SVR_8548_v10,  e500v2),
8317     /* MPC8548 v1.1                                                          */
8318     POWERPC_DEF_SVR("MPC8548_v11",
8319                     CPU_POWERPC_MPC8548_v11,  POWERPC_SVR_8548_v11,  e500v2),
8320     /* MPC8548 v2.0                                                          */
8321     POWERPC_DEF_SVR("MPC8548_v20",
8322                     CPU_POWERPC_MPC8548_v20,  POWERPC_SVR_8548_v20,  e500v2),
8323     /* MPC8548 v2.1                                                          */
8324     POWERPC_DEF_SVR("MPC8548_v21",
8325                     CPU_POWERPC_MPC8548_v21,  POWERPC_SVR_8548_v21,  e500v2),
8326     /* MPC8548E                                                              */
8327     POWERPC_DEF_SVR("MPC8548E",
8328                     CPU_POWERPC_MPC8548E,     POWERPC_SVR_8548E,     e500v2),
8329     /* MPC8548E v1.0                                                         */
8330     POWERPC_DEF_SVR("MPC8548E_v10",
8331                     CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8332     /* MPC8548E v1.1                                                         */
8333     POWERPC_DEF_SVR("MPC8548E_v11",
8334                     CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8335     /* MPC8548E v2.0                                                         */
8336     POWERPC_DEF_SVR("MPC8548E_v20",
8337                     CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8338     /* MPC8548E v2.1                                                         */
8339     POWERPC_DEF_SVR("MPC8548E_v21",
8340                     CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8341     /* MPC8555                                                               */
8342     POWERPC_DEF_SVR("MPC8555",
8343                     CPU_POWERPC_MPC8555,      POWERPC_SVR_8555,      e500v2),
8344     /* MPC8555 v1.0                                                          */
8345     POWERPC_DEF_SVR("MPC8555_v10",
8346                     CPU_POWERPC_MPC8555_v10,  POWERPC_SVR_8555_v10,  e500v2),
8347     /* MPC8555 v1.1                                                          */
8348     POWERPC_DEF_SVR("MPC8555_v11",
8349                     CPU_POWERPC_MPC8555_v11,  POWERPC_SVR_8555_v11,  e500v2),
8350     /* MPC8555E                                                              */
8351     POWERPC_DEF_SVR("MPC8555E",
8352                     CPU_POWERPC_MPC8555E,     POWERPC_SVR_8555E,     e500v2),
8353     /* MPC8555E v1.0                                                         */
8354     POWERPC_DEF_SVR("MPC8555E_v10",
8355                     CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8356     /* MPC8555E v1.1                                                         */
8357     POWERPC_DEF_SVR("MPC8555E_v11",
8358                     CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8359     /* MPC8560                                                               */
8360     POWERPC_DEF_SVR("MPC8560",
8361                     CPU_POWERPC_MPC8560,      POWERPC_SVR_8560,      e500v2),
8362     /* MPC8560 v1.0                                                          */
8363     POWERPC_DEF_SVR("MPC8560_v10",
8364                     CPU_POWERPC_MPC8560_v10,  POWERPC_SVR_8560_v10,  e500v2),
8365     /* MPC8560 v2.0                                                          */
8366     POWERPC_DEF_SVR("MPC8560_v20",
8367                     CPU_POWERPC_MPC8560_v20,  POWERPC_SVR_8560_v20,  e500v2),
8368     /* MPC8560 v2.1                                                          */
8369     POWERPC_DEF_SVR("MPC8560_v21",
8370                     CPU_POWERPC_MPC8560_v21,  POWERPC_SVR_8560_v21,  e500v2),
8371     /* MPC8567                                                               */
8372     POWERPC_DEF_SVR("MPC8567",
8373                     CPU_POWERPC_MPC8567,      POWERPC_SVR_8567,      e500v2),
8374     /* MPC8567E                                                              */
8375     POWERPC_DEF_SVR("MPC8567E",
8376                     CPU_POWERPC_MPC8567E,     POWERPC_SVR_8567E,     e500v2),
8377     /* MPC8568                                                               */
8378     POWERPC_DEF_SVR("MPC8568",
8379                     CPU_POWERPC_MPC8568,      POWERPC_SVR_8568,      e500v2),
8380     /* MPC8568E                                                              */
8381     POWERPC_DEF_SVR("MPC8568E",
8382                     CPU_POWERPC_MPC8568E,     POWERPC_SVR_8568E,     e500v2),
8383     /* MPC8572                                                               */
8384     POWERPC_DEF_SVR("MPC8572",
8385                     CPU_POWERPC_MPC8572,      POWERPC_SVR_8572,      e500v2),
8386     /* MPC8572E                                                              */
8387     POWERPC_DEF_SVR("MPC8572E",
8388                     CPU_POWERPC_MPC8572E,     POWERPC_SVR_8572E,     e500v2),
8389     /* e600 family                                                           */
8390     /* PowerPC e600 core                                                     */
8391     POWERPC_DEF("e600",          CPU_POWERPC_e600,                   7400),
8392     /* PowerPC e600 microcontrollers                                         */
8393 #if defined (TODO)
8394     /* MPC8610                                                               */
8395     POWERPC_DEF_SVR("MPC8610",
8396                     CPU_POWERPC_MPC8610,      POWERPC_SVR_8610,      7400),
8397 #endif
8398     /* MPC8641                                                               */
8399     POWERPC_DEF_SVR("MPC8641",
8400                     CPU_POWERPC_MPC8641,      POWERPC_SVR_8641,      7400),
8401     /* MPC8641D                                                              */
8402     POWERPC_DEF_SVR("MPC8641D",
8403                     CPU_POWERPC_MPC8641D,     POWERPC_SVR_8641D,     7400),
8404     /* 32 bits "classic" PowerPC                                             */
8405     /* PowerPC 6xx family                                                    */
8406     /* PowerPC 601                                                           */
8407     POWERPC_DEF("601",           CPU_POWERPC_601,                    601v),
8408     /* PowerPC 601v0                                                         */
8409     POWERPC_DEF("601_v0",        CPU_POWERPC_601_v0,                 601),
8410     /* PowerPC 601v1                                                         */
8411     POWERPC_DEF("601_v1",        CPU_POWERPC_601_v1,                 601),
8412     /* PowerPC 601v                                                          */
8413     POWERPC_DEF("601v",          CPU_POWERPC_601v,                   601v),
8414     /* PowerPC 601v2                                                         */
8415     POWERPC_DEF("601_v2",        CPU_POWERPC_601_v2,                 601v),
8416     /* PowerPC 602                                                           */
8417     POWERPC_DEF("602",           CPU_POWERPC_602,                    602),
8418     /* PowerPC 603                                                           */
8419     POWERPC_DEF("603",           CPU_POWERPC_603,                    603),
8420     /* Code name for PowerPC 603                                             */
8421     POWERPC_DEF("Vanilla",       CPU_POWERPC_603,                    603),
8422     /* PowerPC 603e (aka PID6)                                               */
8423     POWERPC_DEF("603e",          CPU_POWERPC_603E,                   603E),
8424     /* Code name for PowerPC 603e                                            */
8425     POWERPC_DEF("Stretch",       CPU_POWERPC_603E,                   603E),
8426     /* PowerPC 603e v1.1                                                     */
8427     POWERPC_DEF("603e_v1.1",     CPU_POWERPC_603E_v11,               603E),
8428     /* PowerPC 603e v1.2                                                     */
8429     POWERPC_DEF("603e_v1.2",     CPU_POWERPC_603E_v12,               603E),
8430     /* PowerPC 603e v1.3                                                     */
8431     POWERPC_DEF("603e_v1.3",     CPU_POWERPC_603E_v13,               603E),
8432     /* PowerPC 603e v1.4                                                     */
8433     POWERPC_DEF("603e_v1.4",     CPU_POWERPC_603E_v14,               603E),
8434     /* PowerPC 603e v2.2                                                     */
8435     POWERPC_DEF("603e_v2.2",     CPU_POWERPC_603E_v22,               603E),
8436     /* PowerPC 603e v3                                                       */
8437     POWERPC_DEF("603e_v3",       CPU_POWERPC_603E_v3,                603E),
8438     /* PowerPC 603e v4                                                       */
8439     POWERPC_DEF("603e_v4",       CPU_POWERPC_603E_v4,                603E),
8440     /* PowerPC 603e v4.1                                                     */
8441     POWERPC_DEF("603e_v4.1",     CPU_POWERPC_603E_v41,               603E),
8442     /* PowerPC 603e (aka PID7)                                               */
8443     POWERPC_DEF("603e7",         CPU_POWERPC_603E7,                  603E),
8444     /* PowerPC 603e7t                                                        */
8445     POWERPC_DEF("603e7t",        CPU_POWERPC_603E7t,                 603E),
8446     /* PowerPC 603e7v                                                        */
8447     POWERPC_DEF("603e7v",        CPU_POWERPC_603E7v,                 603E),
8448     /* Code name for PowerPC 603ev                                           */
8449     POWERPC_DEF("Vaillant",      CPU_POWERPC_603E7v,                 603E),
8450     /* PowerPC 603e7v1                                                       */
8451     POWERPC_DEF("603e7v1",       CPU_POWERPC_603E7v1,                603E),
8452     /* PowerPC 603e7v2                                                       */
8453     POWERPC_DEF("603e7v2",       CPU_POWERPC_603E7v2,                603E),
8454     /* PowerPC 603p (aka PID7v)                                              */
8455     POWERPC_DEF("603p",          CPU_POWERPC_603P,                   603E),
8456     /* PowerPC 603r (aka PID7t)                                              */
8457     POWERPC_DEF("603r",          CPU_POWERPC_603R,                   603E),
8458     /* Code name for PowerPC 603r                                            */
8459     POWERPC_DEF("Goldeneye",     CPU_POWERPC_603R,                   603E),
8460     /* PowerPC 604                                                           */
8461     POWERPC_DEF("604",           CPU_POWERPC_604,                    604),
8462     /* PowerPC 604e (aka PID9)                                               */
8463     POWERPC_DEF("604e",          CPU_POWERPC_604E,                   604E),
8464     /* Code name for PowerPC 604e                                            */
8465     POWERPC_DEF("Sirocco",       CPU_POWERPC_604E,                   604E),
8466     /* PowerPC 604e v1.0                                                     */
8467     POWERPC_DEF("604e_v1.0",     CPU_POWERPC_604E_v10,               604E),
8468     /* PowerPC 604e v2.2                                                     */
8469     POWERPC_DEF("604e_v2.2",     CPU_POWERPC_604E_v22,               604E),
8470     /* PowerPC 604e v2.4                                                     */
8471     POWERPC_DEF("604e_v2.4",     CPU_POWERPC_604E_v24,               604E),
8472     /* PowerPC 604r (aka PIDA)                                               */
8473     POWERPC_DEF("604r",          CPU_POWERPC_604R,                   604E),
8474     /* Code name for PowerPC 604r                                            */
8475     POWERPC_DEF("Mach5",         CPU_POWERPC_604R,                   604E),
8476 #if defined(TODO)
8477     /* PowerPC 604ev                                                         */
8478     POWERPC_DEF("604ev",         CPU_POWERPC_604EV,                  604E),
8479 #endif
8480     /* PowerPC 7xx family                                                    */
8481     /* Generic PowerPC 740 (G3)                                              */
8482     POWERPC_DEF("740",           CPU_POWERPC_7x0,                    740),
8483     /* Code name for PowerPC 740                                             */
8484     POWERPC_DEF("Arthur",        CPU_POWERPC_7x0,                    740),
8485     /* Generic PowerPC 750 (G3)                                              */
8486     POWERPC_DEF("750",           CPU_POWERPC_7x0,                    750),
8487     /* Code name for PowerPC 750                                             */
8488     POWERPC_DEF("Typhoon",       CPU_POWERPC_7x0,                    750),
8489     /* PowerPC 740/750 is also known as G3                                   */
8490     POWERPC_DEF("G3",            CPU_POWERPC_7x0,                    750),
8491     /* PowerPC 740 v1.0 (G3)                                                 */
8492     POWERPC_DEF("740_v1.0",      CPU_POWERPC_7x0_v10,                740),
8493     /* PowerPC 750 v1.0 (G3)                                                 */
8494     POWERPC_DEF("750_v1.0",      CPU_POWERPC_7x0_v10,                750),
8495     /* PowerPC 740 v2.0 (G3)                                                 */
8496     POWERPC_DEF("740_v2.0",      CPU_POWERPC_7x0_v20,                740),
8497     /* PowerPC 750 v2.0 (G3)                                                 */
8498     POWERPC_DEF("750_v2.0",      CPU_POWERPC_7x0_v20,                750),
8499     /* PowerPC 740 v2.1 (G3)                                                 */
8500     POWERPC_DEF("740_v2.1",      CPU_POWERPC_7x0_v21,                740),
8501     /* PowerPC 750 v2.1 (G3)                                                 */
8502     POWERPC_DEF("750_v2.1",      CPU_POWERPC_7x0_v21,                750),
8503     /* PowerPC 740 v2.2 (G3)                                                 */
8504     POWERPC_DEF("740_v2.2",      CPU_POWERPC_7x0_v22,                740),
8505     /* PowerPC 750 v2.2 (G3)                                                 */
8506     POWERPC_DEF("750_v2.2",      CPU_POWERPC_7x0_v22,                750),
8507     /* PowerPC 740 v3.0 (G3)                                                 */
8508     POWERPC_DEF("740_v3.0",      CPU_POWERPC_7x0_v30,                740),
8509     /* PowerPC 750 v3.0 (G3)                                                 */
8510     POWERPC_DEF("750_v3.0",      CPU_POWERPC_7x0_v30,                750),
8511     /* PowerPC 740 v3.1 (G3)                                                 */
8512     POWERPC_DEF("740_v3.1",      CPU_POWERPC_7x0_v31,                740),
8513     /* PowerPC 750 v3.1 (G3)                                                 */
8514     POWERPC_DEF("750_v3.1",      CPU_POWERPC_7x0_v31,                750),
8515     /* PowerPC 740E (G3)                                                     */
8516     POWERPC_DEF("740e",          CPU_POWERPC_740E,                   740),
8517     /* PowerPC 750E (G3)                                                     */
8518     POWERPC_DEF("750e",          CPU_POWERPC_750E,                   750),
8519     /* PowerPC 740P (G3)                                                     */
8520     POWERPC_DEF("740p",          CPU_POWERPC_7x0P,                   740),
8521     /* PowerPC 750P (G3)                                                     */
8522     POWERPC_DEF("750p",          CPU_POWERPC_7x0P,                   750),
8523     /* Code name for PowerPC 740P/750P (G3)                                  */
8524     POWERPC_DEF("Conan/Doyle",   CPU_POWERPC_7x0P,                   750),
8525     /* PowerPC 750CL (G3 embedded)                                           */
8526     POWERPC_DEF("750cl",         CPU_POWERPC_750CL,                  750cl),
8527     /* PowerPC 750CL v1.0                                                    */
8528     POWERPC_DEF("750cl_v1.0",    CPU_POWERPC_750CL_v10,              750cl),
8529     /* PowerPC 750CL v2.0                                                    */
8530     POWERPC_DEF("750cl_v2.0",    CPU_POWERPC_750CL_v20,              750cl),
8531     /* PowerPC 750CX (G3 embedded)                                           */
8532     POWERPC_DEF("750cx",         CPU_POWERPC_750CX,                  750cx),
8533     /* PowerPC 750CX v1.0 (G3 embedded)                                      */
8534     POWERPC_DEF("750cx_v1.0",    CPU_POWERPC_750CX_v10,              750cx),
8535     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8536     POWERPC_DEF("750cx_v2.0",    CPU_POWERPC_750CX_v20,              750cx),
8537     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8538     POWERPC_DEF("750cx_v2.1",    CPU_POWERPC_750CX_v21,              750cx),
8539     /* PowerPC 750CX v2.2 (G3 embedded)                                      */
8540     POWERPC_DEF("750cx_v2.2",    CPU_POWERPC_750CX_v22,              750cx),
8541     /* PowerPC 750CXe (G3 embedded)                                          */
8542     POWERPC_DEF("750cxe",        CPU_POWERPC_750CXE,                 750cx),
8543     /* PowerPC 750CXe v2.1 (G3 embedded)                                     */
8544     POWERPC_DEF("750cxe_v2.1",   CPU_POWERPC_750CXE_v21,             750cx),
8545     /* PowerPC 750CXe v2.2 (G3 embedded)                                     */
8546     POWERPC_DEF("750cxe_v2.2",   CPU_POWERPC_750CXE_v22,             750cx),
8547     /* PowerPC 750CXe v2.3 (G3 embedded)                                     */
8548     POWERPC_DEF("750cxe_v2.3",   CPU_POWERPC_750CXE_v23,             750cx),
8549     /* PowerPC 750CXe v2.4 (G3 embedded)                                     */
8550     POWERPC_DEF("750cxe_v2.4",   CPU_POWERPC_750CXE_v24,             750cx),
8551     /* PowerPC 750CXe v2.4b (G3 embedded)                                    */
8552     POWERPC_DEF("750cxe_v2.4b",  CPU_POWERPC_750CXE_v24b,            750cx),
8553     /* PowerPC 750CXe v3.0 (G3 embedded)                                     */
8554     POWERPC_DEF("750cxe_v3.0",   CPU_POWERPC_750CXE_v30,             750cx),
8555     /* PowerPC 750CXe v3.1 (G3 embedded)                                     */
8556     POWERPC_DEF("750cxe_v3.1",   CPU_POWERPC_750CXE_v31,             750cx),
8557     /* PowerPC 750CXe v3.1b (G3 embedded)                                    */
8558     POWERPC_DEF("750cxe_v3.1b",  CPU_POWERPC_750CXE_v31b,            750cx),
8559     /* PowerPC 750CXr (G3 embedded)                                          */
8560     POWERPC_DEF("750cxr",        CPU_POWERPC_750CXR,                 750cx),
8561     /* PowerPC 750FL (G3 embedded)                                           */
8562     POWERPC_DEF("750fl",         CPU_POWERPC_750FL,                  750fx),
8563     /* PowerPC 750FX (G3 embedded)                                           */
8564     POWERPC_DEF("750fx",         CPU_POWERPC_750FX,                  750fx),
8565     /* PowerPC 750FX v1.0 (G3 embedded)                                      */
8566     POWERPC_DEF("750fx_v1.0",    CPU_POWERPC_750FX_v10,              750fx),
8567     /* PowerPC 750FX v2.0 (G3 embedded)                                      */
8568     POWERPC_DEF("750fx_v2.0",    CPU_POWERPC_750FX_v20,              750fx),
8569     /* PowerPC 750FX v2.1 (G3 embedded)                                      */
8570     POWERPC_DEF("750fx_v2.1",    CPU_POWERPC_750FX_v21,              750fx),
8571     /* PowerPC 750FX v2.2 (G3 embedded)                                      */
8572     POWERPC_DEF("750fx_v2.2",    CPU_POWERPC_750FX_v22,              750fx),
8573     /* PowerPC 750FX v2.3 (G3 embedded)                                      */
8574     POWERPC_DEF("750fx_v2.3",    CPU_POWERPC_750FX_v23,              750fx),
8575     /* PowerPC 750GL (G3 embedded)                                           */
8576     POWERPC_DEF("750gl",         CPU_POWERPC_750GL,                  750gx),
8577     /* PowerPC 750GX (G3 embedded)                                           */
8578     POWERPC_DEF("750gx",         CPU_POWERPC_750GX,                  750gx),
8579     /* PowerPC 750GX v1.0 (G3 embedded)                                      */
8580     POWERPC_DEF("750gx_v1.0",    CPU_POWERPC_750GX_v10,              750gx),
8581     /* PowerPC 750GX v1.1 (G3 embedded)                                      */
8582     POWERPC_DEF("750gx_v1.1",    CPU_POWERPC_750GX_v11,              750gx),
8583     /* PowerPC 750GX v1.2 (G3 embedded)                                      */
8584     POWERPC_DEF("750gx_v1.2",    CPU_POWERPC_750GX_v12,              750gx),
8585     /* PowerPC 750L (G3 embedded)                                            */
8586     POWERPC_DEF("750l",          CPU_POWERPC_750L,                   750),
8587     /* Code name for PowerPC 750L (G3 embedded)                              */
8588     POWERPC_DEF("LoneStar",      CPU_POWERPC_750L,                   750),
8589     /* PowerPC 750L v2.0 (G3 embedded)                                       */
8590     POWERPC_DEF("750l_v2.0",     CPU_POWERPC_750L_v20,               750),
8591     /* PowerPC 750L v2.1 (G3 embedded)                                       */
8592     POWERPC_DEF("750l_v2.1",     CPU_POWERPC_750L_v21,               750),
8593     /* PowerPC 750L v2.2 (G3 embedded)                                       */
8594     POWERPC_DEF("750l_v2.2",     CPU_POWERPC_750L_v22,               750),
8595     /* PowerPC 750L v3.0 (G3 embedded)                                       */
8596     POWERPC_DEF("750l_v3.0",     CPU_POWERPC_750L_v30,               750),
8597     /* PowerPC 750L v3.2 (G3 embedded)                                       */
8598     POWERPC_DEF("750l_v3.2",     CPU_POWERPC_750L_v32,               750),
8599     /* Generic PowerPC 745                                                   */
8600     POWERPC_DEF("745",           CPU_POWERPC_7x5,                    745),
8601     /* Generic PowerPC 755                                                   */
8602     POWERPC_DEF("755",           CPU_POWERPC_7x5,                    755),
8603     /* Code name for PowerPC 745/755                                         */
8604     POWERPC_DEF("Goldfinger",    CPU_POWERPC_7x5,                    755),
8605     /* PowerPC 745 v1.0                                                      */
8606     POWERPC_DEF("745_v1.0",      CPU_POWERPC_7x5_v10,                745),
8607     /* PowerPC 755 v1.0                                                      */
8608     POWERPC_DEF("755_v1.0",      CPU_POWERPC_7x5_v10,                755),
8609     /* PowerPC 745 v1.1                                                      */
8610     POWERPC_DEF("745_v1.1",      CPU_POWERPC_7x5_v11,                745),
8611     /* PowerPC 755 v1.1                                                      */
8612     POWERPC_DEF("755_v1.1",      CPU_POWERPC_7x5_v11,                755),
8613     /* PowerPC 745 v2.0                                                      */
8614     POWERPC_DEF("745_v2.0",      CPU_POWERPC_7x5_v20,                745),
8615     /* PowerPC 755 v2.0                                                      */
8616     POWERPC_DEF("755_v2.0",      CPU_POWERPC_7x5_v20,                755),
8617     /* PowerPC 745 v2.1                                                      */
8618     POWERPC_DEF("745_v2.1",      CPU_POWERPC_7x5_v21,                745),
8619     /* PowerPC 755 v2.1                                                      */
8620     POWERPC_DEF("755_v2.1",      CPU_POWERPC_7x5_v21,                755),
8621     /* PowerPC 745 v2.2                                                      */
8622     POWERPC_DEF("745_v2.2",      CPU_POWERPC_7x5_v22,                745),
8623     /* PowerPC 755 v2.2                                                      */
8624     POWERPC_DEF("755_v2.2",      CPU_POWERPC_7x5_v22,                755),
8625     /* PowerPC 745 v2.3                                                      */
8626     POWERPC_DEF("745_v2.3",      CPU_POWERPC_7x5_v23,                745),
8627     /* PowerPC 755 v2.3                                                      */
8628     POWERPC_DEF("755_v2.3",      CPU_POWERPC_7x5_v23,                755),
8629     /* PowerPC 745 v2.4                                                      */
8630     POWERPC_DEF("745_v2.4",      CPU_POWERPC_7x5_v24,                745),
8631     /* PowerPC 755 v2.4                                                      */
8632     POWERPC_DEF("755_v2.4",      CPU_POWERPC_7x5_v24,                755),
8633     /* PowerPC 745 v2.5                                                      */
8634     POWERPC_DEF("745_v2.5",      CPU_POWERPC_7x5_v25,                745),
8635     /* PowerPC 755 v2.5                                                      */
8636     POWERPC_DEF("755_v2.5",      CPU_POWERPC_7x5_v25,                755),
8637     /* PowerPC 745 v2.6                                                      */
8638     POWERPC_DEF("745_v2.6",      CPU_POWERPC_7x5_v26,                745),
8639     /* PowerPC 755 v2.6                                                      */
8640     POWERPC_DEF("755_v2.6",      CPU_POWERPC_7x5_v26,                755),
8641     /* PowerPC 745 v2.7                                                      */
8642     POWERPC_DEF("745_v2.7",      CPU_POWERPC_7x5_v27,                745),
8643     /* PowerPC 755 v2.7                                                      */
8644     POWERPC_DEF("755_v2.7",      CPU_POWERPC_7x5_v27,                755),
8645     /* PowerPC 745 v2.8                                                      */
8646     POWERPC_DEF("745_v2.8",      CPU_POWERPC_7x5_v28,                745),
8647     /* PowerPC 755 v2.8                                                      */
8648     POWERPC_DEF("755_v2.8",      CPU_POWERPC_7x5_v28,                755),
8649 #if defined (TODO)
8650     /* PowerPC 745P (G3)                                                     */
8651     POWERPC_DEF("745p",          CPU_POWERPC_7x5P,                   745),
8652     /* PowerPC 755P (G3)                                                     */
8653     POWERPC_DEF("755p",          CPU_POWERPC_7x5P,                   755),
8654 #endif
8655     /* PowerPC 74xx family                                                   */
8656     /* PowerPC 7400 (G4)                                                     */
8657     POWERPC_DEF("7400",          CPU_POWERPC_7400,                   7400),
8658     /* Code name for PowerPC 7400                                            */
8659     POWERPC_DEF("Max",           CPU_POWERPC_7400,                   7400),
8660     /* PowerPC 74xx is also well known as G4                                 */
8661     POWERPC_DEF("G4",            CPU_POWERPC_7400,                   7400),
8662     /* PowerPC 7400 v1.0 (G4)                                                */
8663     POWERPC_DEF("7400_v1.0",     CPU_POWERPC_7400_v10,               7400),
8664     /* PowerPC 7400 v1.1 (G4)                                                */
8665     POWERPC_DEF("7400_v1.1",     CPU_POWERPC_7400_v11,               7400),
8666     /* PowerPC 7400 v2.0 (G4)                                                */
8667     POWERPC_DEF("7400_v2.0",     CPU_POWERPC_7400_v20,               7400),
8668     /* PowerPC 7400 v2.1 (G4)                                                */
8669     POWERPC_DEF("7400_v2.1",     CPU_POWERPC_7400_v21,               7400),
8670     /* PowerPC 7400 v2.2 (G4)                                                */
8671     POWERPC_DEF("7400_v2.2",     CPU_POWERPC_7400_v22,               7400),
8672     /* PowerPC 7400 v2.6 (G4)                                                */
8673     POWERPC_DEF("7400_v2.6",     CPU_POWERPC_7400_v26,               7400),
8674     /* PowerPC 7400 v2.7 (G4)                                                */
8675     POWERPC_DEF("7400_v2.7",     CPU_POWERPC_7400_v27,               7400),
8676     /* PowerPC 7400 v2.8 (G4)                                                */
8677     POWERPC_DEF("7400_v2.8",     CPU_POWERPC_7400_v28,               7400),
8678     /* PowerPC 7400 v2.9 (G4)                                                */
8679     POWERPC_DEF("7400_v2.9",     CPU_POWERPC_7400_v29,               7400),
8680     /* PowerPC 7410 (G4)                                                     */
8681     POWERPC_DEF("7410",          CPU_POWERPC_7410,                   7410),
8682     /* Code name for PowerPC 7410                                            */
8683     POWERPC_DEF("Nitro",         CPU_POWERPC_7410,                   7410),
8684     /* PowerPC 7410 v1.0 (G4)                                                */
8685     POWERPC_DEF("7410_v1.0",     CPU_POWERPC_7410_v10,               7410),
8686     /* PowerPC 7410 v1.1 (G4)                                                */
8687     POWERPC_DEF("7410_v1.1",     CPU_POWERPC_7410_v11,               7410),
8688     /* PowerPC 7410 v1.2 (G4)                                                */
8689     POWERPC_DEF("7410_v1.2",     CPU_POWERPC_7410_v12,               7410),
8690     /* PowerPC 7410 v1.3 (G4)                                                */
8691     POWERPC_DEF("7410_v1.3",     CPU_POWERPC_7410_v13,               7410),
8692     /* PowerPC 7410 v1.4 (G4)                                                */
8693     POWERPC_DEF("7410_v1.4",     CPU_POWERPC_7410_v14,               7410),
8694     /* PowerPC 7448 (G4)                                                     */
8695     POWERPC_DEF("7448",          CPU_POWERPC_7448,                   7400),
8696     /* PowerPC 7448 v1.0 (G4)                                                */
8697     POWERPC_DEF("7448_v1.0",     CPU_POWERPC_7448_v10,               7400),
8698     /* PowerPC 7448 v1.1 (G4)                                                */
8699     POWERPC_DEF("7448_v1.1",     CPU_POWERPC_7448_v11,               7400),
8700     /* PowerPC 7448 v2.0 (G4)                                                */
8701     POWERPC_DEF("7448_v2.0",     CPU_POWERPC_7448_v20,               7400),
8702     /* PowerPC 7448 v2.1 (G4)                                                */
8703     POWERPC_DEF("7448_v2.1",     CPU_POWERPC_7448_v21,               7400),
8704     /* PowerPC 7450 (G4)                                                     */
8705     POWERPC_DEF("7450",          CPU_POWERPC_7450,                   7450),
8706     /* Code name for PowerPC 7450                                            */
8707     POWERPC_DEF("Vger",          CPU_POWERPC_7450,                   7450),
8708     /* PowerPC 7450 v1.0 (G4)                                                */
8709     POWERPC_DEF("7450_v1.0",     CPU_POWERPC_7450_v10,               7450),
8710     /* PowerPC 7450 v1.1 (G4)                                                */
8711     POWERPC_DEF("7450_v1.1",     CPU_POWERPC_7450_v11,               7450),
8712     /* PowerPC 7450 v1.2 (G4)                                                */
8713     POWERPC_DEF("7450_v1.2",     CPU_POWERPC_7450_v12,               7450),
8714     /* PowerPC 7450 v2.0 (G4)                                                */
8715     POWERPC_DEF("7450_v2.0",     CPU_POWERPC_7450_v20,               7450),
8716     /* PowerPC 7450 v2.1 (G4)                                                */
8717     POWERPC_DEF("7450_v2.1",     CPU_POWERPC_7450_v21,               7450),
8718     /* PowerPC 7441 (G4)                                                     */
8719     POWERPC_DEF("7441",          CPU_POWERPC_74x1,                   7440),
8720     /* PowerPC 7451 (G4)                                                     */
8721     POWERPC_DEF("7451",          CPU_POWERPC_74x1,                   7450),
8722     /* PowerPC 7441 v2.1 (G4)                                                */
8723     POWERPC_DEF("7441_v2.1",     CPU_POWERPC_7450_v21,               7440),
8724     /* PowerPC 7441 v2.3 (G4)                                                */
8725     POWERPC_DEF("7441_v2.3",     CPU_POWERPC_74x1_v23,               7440),
8726     /* PowerPC 7451 v2.3 (G4)                                                */
8727     POWERPC_DEF("7451_v2.3",     CPU_POWERPC_74x1_v23,               7450),
8728     /* PowerPC 7441 v2.10 (G4)                                                */
8729     POWERPC_DEF("7441_v2.10",    CPU_POWERPC_74x1_v210,              7440),
8730     /* PowerPC 7451 v2.10 (G4)                                               */
8731     POWERPC_DEF("7451_v2.10",    CPU_POWERPC_74x1_v210,              7450),
8732     /* PowerPC 7445 (G4)                                                     */
8733     POWERPC_DEF("7445",          CPU_POWERPC_74x5,                   7445),
8734     /* PowerPC 7455 (G4)                                                     */
8735     POWERPC_DEF("7455",          CPU_POWERPC_74x5,                   7455),
8736     /* Code name for PowerPC 7445/7455                                       */
8737     POWERPC_DEF("Apollo6",       CPU_POWERPC_74x5,                   7455),
8738     /* PowerPC 7445 v1.0 (G4)                                                */
8739     POWERPC_DEF("7445_v1.0",     CPU_POWERPC_74x5_v10,               7445),
8740     /* PowerPC 7455 v1.0 (G4)                                                */
8741     POWERPC_DEF("7455_v1.0",     CPU_POWERPC_74x5_v10,               7455),
8742     /* PowerPC 7445 v2.1 (G4)                                                */
8743     POWERPC_DEF("7445_v2.1",     CPU_POWERPC_74x5_v21,               7445),
8744     /* PowerPC 7455 v2.1 (G4)                                                */
8745     POWERPC_DEF("7455_v2.1",     CPU_POWERPC_74x5_v21,               7455),
8746     /* PowerPC 7445 v3.2 (G4)                                                */
8747     POWERPC_DEF("7445_v3.2",     CPU_POWERPC_74x5_v32,               7445),
8748     /* PowerPC 7455 v3.2 (G4)                                                */
8749     POWERPC_DEF("7455_v3.2",     CPU_POWERPC_74x5_v32,               7455),
8750     /* PowerPC 7445 v3.3 (G4)                                                */
8751     POWERPC_DEF("7445_v3.3",     CPU_POWERPC_74x5_v33,               7445),
8752     /* PowerPC 7455 v3.3 (G4)                                                */
8753     POWERPC_DEF("7455_v3.3",     CPU_POWERPC_74x5_v33,               7455),
8754     /* PowerPC 7445 v3.4 (G4)                                                */
8755     POWERPC_DEF("7445_v3.4",     CPU_POWERPC_74x5_v34,               7445),
8756     /* PowerPC 7455 v3.4 (G4)                                                */
8757     POWERPC_DEF("7455_v3.4",     CPU_POWERPC_74x5_v34,               7455),
8758     /* PowerPC 7447 (G4)                                                     */
8759     POWERPC_DEF("7447",          CPU_POWERPC_74x7,                   7445),
8760     /* PowerPC 7457 (G4)                                                     */
8761     POWERPC_DEF("7457",          CPU_POWERPC_74x7,                   7455),
8762     /* Code name for PowerPC 7447/7457                                       */
8763     POWERPC_DEF("Apollo7",       CPU_POWERPC_74x7,                   7455),
8764     /* PowerPC 7447 v1.0 (G4)                                                */
8765     POWERPC_DEF("7447_v1.0",     CPU_POWERPC_74x7_v10,               7445),
8766     /* PowerPC 7457 v1.0 (G4)                                                */
8767     POWERPC_DEF("7457_v1.0",     CPU_POWERPC_74x7_v10,               7455),
8768     /* PowerPC 7447 v1.1 (G4)                                                */
8769     POWERPC_DEF("7447_v1.1",     CPU_POWERPC_74x7_v11,               7445),
8770     /* PowerPC 7457 v1.1 (G4)                                                */
8771     POWERPC_DEF("7457_v1.1",     CPU_POWERPC_74x7_v11,               7455),
8772     /* PowerPC 7457 v1.2 (G4)                                                */
8773     POWERPC_DEF("7457_v1.2",     CPU_POWERPC_74x7_v12,               7455),
8774     /* PowerPC 7447A (G4)                                                    */
8775     POWERPC_DEF("7447A",         CPU_POWERPC_74x7A,                  7445),
8776     /* PowerPC 7457A (G4)                                                    */
8777     POWERPC_DEF("7457A",         CPU_POWERPC_74x7A,                  7455),
8778     /* PowerPC 7447A v1.0 (G4)                                               */
8779     POWERPC_DEF("7447A_v1.0",    CPU_POWERPC_74x7A_v10,              7445),
8780     /* PowerPC 7457A v1.0 (G4)                                               */
8781     POWERPC_DEF("7457A_v1.0",    CPU_POWERPC_74x7A_v10,              7455),
8782     /* Code name for PowerPC 7447A/7457A                                     */
8783     POWERPC_DEF("Apollo7PM",     CPU_POWERPC_74x7A_v10,              7455),
8784     /* PowerPC 7447A v1.1 (G4)                                               */
8785     POWERPC_DEF("7447A_v1.1",    CPU_POWERPC_74x7A_v11,              7445),
8786     /* PowerPC 7457A v1.1 (G4)                                               */
8787     POWERPC_DEF("7457A_v1.1",    CPU_POWERPC_74x7A_v11,              7455),
8788     /* PowerPC 7447A v1.2 (G4)                                               */
8789     POWERPC_DEF("7447A_v1.2",    CPU_POWERPC_74x7A_v12,              7445),
8790     /* PowerPC 7457A v1.2 (G4)                                               */
8791     POWERPC_DEF("7457A_v1.2",    CPU_POWERPC_74x7A_v12,              7455),
8792     /* 64 bits PowerPC                                                       */
8793 #if defined (TARGET_PPC64)
8794     /* PowerPC 620                                                           */
8795     POWERPC_DEF("620",           CPU_POWERPC_620,                    620),
8796     /* Code name for PowerPC 620                                             */
8797     POWERPC_DEF("Trident",       CPU_POWERPC_620,                    620),
8798 #if defined (TODO)
8799     /* PowerPC 630 (POWER3)                                                  */
8800     POWERPC_DEF("630",           CPU_POWERPC_630,                    630),
8801     POWERPC_DEF("POWER3",        CPU_POWERPC_630,                    630),
8802     /* Code names for POWER3                                                 */
8803     POWERPC_DEF("Boxer",         CPU_POWERPC_630,                    630),
8804     POWERPC_DEF("Dino",          CPU_POWERPC_630,                    630),
8805 #endif
8806 #if defined (TODO)
8807     /* PowerPC 631 (Power 3+)                                                */
8808     POWERPC_DEF("631",           CPU_POWERPC_631,                    631),
8809     POWERPC_DEF("POWER3+",       CPU_POWERPC_631,                    631),
8810 #endif
8811 #if defined (TODO)
8812     /* POWER4                                                                */
8813     POWERPC_DEF("POWER4",        CPU_POWERPC_POWER4,                 POWER4),
8814 #endif
8815 #if defined (TODO)
8816     /* POWER4p                                                               */
8817     POWERPC_DEF("POWER4+",       CPU_POWERPC_POWER4P,                POWER4P),
8818 #endif
8819 #if defined (TODO)
8820     /* POWER5                                                                */
8821     POWERPC_DEF("POWER5",        CPU_POWERPC_POWER5,                 POWER5),
8822     /* POWER5GR                                                              */
8823     POWERPC_DEF("POWER5gr",      CPU_POWERPC_POWER5GR,               POWER5),
8824 #endif
8825 #if defined (TODO)
8826     /* POWER5+                                                               */
8827     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P),
8828     /* POWER5GS                                                              */
8829     POWERPC_DEF("POWER5gs",      CPU_POWERPC_POWER5GS,               POWER5P),
8830 #endif
8831 #if defined (TODO)
8832     /* POWER6                                                                */
8833     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6),
8834     /* POWER6 running in POWER5 mode                                         */
8835     POWERPC_DEF("POWER6_5",      CPU_POWERPC_POWER6_5,               POWER5),
8836     /* POWER6A                                                               */
8837     POWERPC_DEF("POWER6A",       CPU_POWERPC_POWER6A,                POWER6),
8838 #endif
8839     /* PowerPC 970                                                           */
8840     POWERPC_DEF("970",           CPU_POWERPC_970,                    970),
8841     /* PowerPC 970FX (G5)                                                    */
8842     POWERPC_DEF("970fx",         CPU_POWERPC_970FX,                  970FX),
8843     /* PowerPC 970FX v1.0 (G5)                                               */
8844     POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970FX),
8845     /* PowerPC 970FX v2.0 (G5)                                               */
8846     POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970FX),
8847     /* PowerPC 970FX v2.1 (G5)                                               */
8848     POWERPC_DEF("970fx_v2.1",    CPU_POWERPC_970FX_v21,              970FX),
8849     /* PowerPC 970FX v3.0 (G5)                                               */
8850     POWERPC_DEF("970fx_v3.0",    CPU_POWERPC_970FX_v30,              970FX),
8851     /* PowerPC 970FX v3.1 (G5)                                               */
8852     POWERPC_DEF("970fx_v3.1",    CPU_POWERPC_970FX_v31,              970FX),
8853     /* PowerPC 970GX (G5)                                                    */
8854     POWERPC_DEF("970gx",         CPU_POWERPC_970GX,                  970GX),
8855     /* PowerPC 970MP                                                         */
8856     POWERPC_DEF("970mp",         CPU_POWERPC_970MP,                  970MP),
8857     /* PowerPC 970MP v1.0                                                    */
8858     POWERPC_DEF("970mp_v1.0",    CPU_POWERPC_970MP_v10,              970MP),
8859     /* PowerPC 970MP v1.1                                                    */
8860     POWERPC_DEF("970mp_v1.1",    CPU_POWERPC_970MP_v11,              970MP),
8861 #if defined (TODO)
8862     /* PowerPC Cell                                                          */
8863     POWERPC_DEF("Cell",          CPU_POWERPC_CELL,                   970),
8864 #endif
8865 #if defined (TODO)
8866     /* PowerPC Cell v1.0                                                     */
8867     POWERPC_DEF("Cell_v1.0",     CPU_POWERPC_CELL_v10,               970),
8868 #endif
8869 #if defined (TODO)
8870     /* PowerPC Cell v2.0                                                     */
8871     POWERPC_DEF("Cell_v2.0",     CPU_POWERPC_CELL_v20,               970),
8872 #endif
8873 #if defined (TODO)
8874     /* PowerPC Cell v3.0                                                     */
8875     POWERPC_DEF("Cell_v3.0",     CPU_POWERPC_CELL_v30,               970),
8876 #endif
8877 #if defined (TODO)
8878     /* PowerPC Cell v3.1                                                     */
8879     POWERPC_DEF("Cell_v3.1",     CPU_POWERPC_CELL_v31,               970),
8880 #endif
8881 #if defined (TODO)
8882     /* PowerPC Cell v3.2                                                     */
8883     POWERPC_DEF("Cell_v3.2",     CPU_POWERPC_CELL_v32,               970),
8884 #endif
8885 #if defined (TODO)
8886     /* RS64 (Apache/A35)                                                     */
8887     /* This one seems to support the whole POWER2 instruction set
8888      * and the PowerPC 64 one.
8889      */
8890     /* What about A10 & A30 ? */
8891     POWERPC_DEF("RS64",          CPU_POWERPC_RS64,                   RS64),
8892     POWERPC_DEF("Apache",        CPU_POWERPC_RS64,                   RS64),
8893     POWERPC_DEF("A35",           CPU_POWERPC_RS64,                   RS64),
8894 #endif
8895 #if defined (TODO)
8896     /* RS64-II (NorthStar/A50)                                               */
8897     POWERPC_DEF("RS64-II",       CPU_POWERPC_RS64II,                 RS64),
8898     POWERPC_DEF("NorthStar",     CPU_POWERPC_RS64II,                 RS64),
8899     POWERPC_DEF("A50",           CPU_POWERPC_RS64II,                 RS64),
8900 #endif
8901 #if defined (TODO)
8902     /* RS64-III (Pulsar)                                                     */
8903     POWERPC_DEF("RS64-III",      CPU_POWERPC_RS64III,                RS64),
8904     POWERPC_DEF("Pulsar",        CPU_POWERPC_RS64III,                RS64),
8905 #endif
8906 #if defined (TODO)
8907     /* RS64-IV (IceStar/IStar/SStar)                                         */
8908     POWERPC_DEF("RS64-IV",       CPU_POWERPC_RS64IV,                 RS64),
8909     POWERPC_DEF("IceStar",       CPU_POWERPC_RS64IV,                 RS64),
8910     POWERPC_DEF("IStar",         CPU_POWERPC_RS64IV,                 RS64),
8911     POWERPC_DEF("SStar",         CPU_POWERPC_RS64IV,                 RS64),
8912 #endif
8913 #endif /* defined (TARGET_PPC64) */
8914     /* POWER                                                                 */
8915 #if defined (TODO)
8916     /* Original POWER                                                        */
8917     POWERPC_DEF("POWER",         CPU_POWERPC_POWER,                  POWER),
8918     POWERPC_DEF("RIOS",          CPU_POWERPC_POWER,                  POWER),
8919     POWERPC_DEF("RSC",           CPU_POWERPC_POWER,                  POWER),
8920     POWERPC_DEF("RSC3308",       CPU_POWERPC_POWER,                  POWER),
8921     POWERPC_DEF("RSC4608",       CPU_POWERPC_POWER,                  POWER),
8922 #endif
8923 #if defined (TODO)
8924     /* POWER2                                                                */
8925     POWERPC_DEF("POWER2",        CPU_POWERPC_POWER2,                 POWER),
8926     POWERPC_DEF("RSC2",          CPU_POWERPC_POWER2,                 POWER),
8927     POWERPC_DEF("P2SC",          CPU_POWERPC_POWER2,                 POWER),
8928 #endif
8929     /* PA semi cores                                                         */
8930 #if defined (TODO)
8931     /* PA PA6T */
8932     POWERPC_DEF("PA6T",          CPU_POWERPC_PA6T,                   PA6T),
8933 #endif
8934     /* Generic PowerPCs                                                      */
8935 #if defined (TARGET_PPC64)
8936     POWERPC_DEF("ppc64",         CPU_POWERPC_PPC64,                  PPC64),
8937 #endif
8938     POWERPC_DEF("ppc32",         CPU_POWERPC_PPC32,                  PPC32),
8939     POWERPC_DEF("ppc",           CPU_POWERPC_DEFAULT,                DEFAULT),
8940     /* Fallback                                                              */
8941     POWERPC_DEF("default",       CPU_POWERPC_DEFAULT,                DEFAULT),
8942 };
8943
8944 /*****************************************************************************/
8945 /* Generic CPU instanciation routine                                         */
8946 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
8947 {
8948 #if !defined(CONFIG_USER_ONLY)
8949     int i;
8950
8951     env->irq_inputs = NULL;
8952     /* Set all exception vectors to an invalid address */
8953     for (i = 0; i < POWERPC_EXCP_NB; i++)
8954         env->excp_vectors[i] = (target_ulong)(-1ULL);
8955     env->hreset_excp_prefix = 0x00000000;
8956     env->ivor_mask = 0x00000000;
8957     env->ivpr_mask = 0x00000000;
8958     /* Default MMU definitions */
8959     env->nb_BATs = 0;
8960     env->nb_tlb = 0;
8961     env->nb_ways = 0;
8962 #endif
8963     /* Register SPR common to all PowerPC implementations */
8964     gen_spr_generic(env);
8965     spr_register(env, SPR_PVR, "PVR",
8966                  /* Linux permits userspace to read PVR */
8967 #if defined(CONFIG_LINUX_USER)
8968                  &spr_read_generic,
8969 #else
8970                  SPR_NOACCESS,
8971 #endif
8972                  SPR_NOACCESS,
8973                  &spr_read_generic, SPR_NOACCESS,
8974                  def->pvr);
8975     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8976     if (def->svr != POWERPC_SVR_NONE) {
8977         if (def->svr & POWERPC_SVR_E500) {
8978             spr_register(env, SPR_E500_SVR, "SVR",
8979                          SPR_NOACCESS, SPR_NOACCESS,
8980                          &spr_read_generic, SPR_NOACCESS,
8981                          def->svr & ~POWERPC_SVR_E500);
8982         } else {
8983             spr_register(env, SPR_SVR, "SVR",
8984                          SPR_NOACCESS, SPR_NOACCESS,
8985                          &spr_read_generic, SPR_NOACCESS,
8986                          def->svr);
8987         }
8988     }
8989     /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8990     (*def->init_proc)(env);
8991 #if !defined(CONFIG_USER_ONLY)
8992     env->excp_prefix = env->hreset_excp_prefix;
8993 #endif
8994     /* MSR bits & flags consistency checks */
8995     if (env->msr_mask & (1 << 25)) {
8996         switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8997         case POWERPC_FLAG_SPE:
8998         case POWERPC_FLAG_VRE:
8999             break;
9000         default:
9001             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9002                     "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9003             exit(1);
9004         }
9005     } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9006         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9007                 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9008         exit(1);
9009     }
9010     if (env->msr_mask & (1 << 17)) {
9011         switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9012         case POWERPC_FLAG_TGPR:
9013         case POWERPC_FLAG_CE:
9014             break;
9015         default:
9016             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9017                     "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9018             exit(1);
9019         }
9020     } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9021         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9022                 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9023         exit(1);
9024     }
9025     if (env->msr_mask & (1 << 10)) {
9026         switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9027                               POWERPC_FLAG_UBLE)) {
9028         case POWERPC_FLAG_SE:
9029         case POWERPC_FLAG_DWE:
9030         case POWERPC_FLAG_UBLE:
9031             break;
9032         default:
9033             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9034                     "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9035                     "POWERPC_FLAG_UBLE\n");
9036             exit(1);
9037         }
9038     } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9039                              POWERPC_FLAG_UBLE)) {
9040         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9041                 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9042                 "POWERPC_FLAG_UBLE\n");
9043             exit(1);
9044     }
9045     if (env->msr_mask & (1 << 9)) {
9046         switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9047         case POWERPC_FLAG_BE:
9048         case POWERPC_FLAG_DE:
9049             break;
9050         default:
9051             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9052                     "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9053             exit(1);
9054         }
9055     } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9056         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9057                 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9058         exit(1);
9059     }
9060     if (env->msr_mask & (1 << 2)) {
9061         switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9062         case POWERPC_FLAG_PX:
9063         case POWERPC_FLAG_PMM:
9064             break;
9065         default:
9066             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9067                     "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9068             exit(1);
9069         }
9070     } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9071         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9072                 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9073         exit(1);
9074     }
9075     if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9076         fprintf(stderr, "PowerPC flags inconsistency\n"
9077                 "Should define the time-base and decrementer clock source\n");
9078         exit(1);
9079     }
9080     /* Allocate TLBs buffer when needed */
9081 #if !defined(CONFIG_USER_ONLY)
9082     if (env->nb_tlb != 0) {
9083         int nb_tlb = env->nb_tlb;
9084         if (env->id_tlbs != 0)
9085             nb_tlb *= 2;
9086         env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
9087         /* Pre-compute some useful values */
9088         env->tlb_per_way = env->nb_tlb / env->nb_ways;
9089     }
9090     if (env->irq_inputs == NULL) {
9091         fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9092                 " Attempt Qemu to crash very soon !\n");
9093     }
9094 #endif
9095     if (env->check_pow == NULL) {
9096         fprintf(stderr, "WARNING: no power management check handler "
9097                 "registered.\n"
9098                 " Attempt Qemu to crash very soon !\n");
9099     }
9100 }
9101
9102 #if defined(PPC_DUMP_CPU)
9103 static void dump_ppc_sprs (CPUPPCState *env)
9104 {
9105     ppc_spr_t *spr;
9106 #if !defined(CONFIG_USER_ONLY)
9107     uint32_t sr, sw;
9108 #endif
9109     uint32_t ur, uw;
9110     int i, j, n;
9111
9112     printf("Special purpose registers:\n");
9113     for (i = 0; i < 32; i++) {
9114         for (j = 0; j < 32; j++) {
9115             n = (i << 5) | j;
9116             spr = &env->spr_cb[n];
9117             uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9118             ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9119 #if !defined(CONFIG_USER_ONLY)
9120             sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9121             sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9122             if (sw || sr || uw || ur) {
9123                 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9124                        (i << 5) | j, (i << 5) | j, spr->name,
9125                        sw ? 'w' : '-', sr ? 'r' : '-',
9126                        uw ? 'w' : '-', ur ? 'r' : '-');
9127             }
9128 #else
9129             if (uw || ur) {
9130                 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9131                        (i << 5) | j, (i << 5) | j, spr->name,
9132                        uw ? 'w' : '-', ur ? 'r' : '-');
9133             }
9134 #endif
9135         }
9136     }
9137     fflush(stdout);
9138     fflush(stderr);
9139 }
9140 #endif
9141
9142 /*****************************************************************************/
9143 #include <stdlib.h>
9144 #include <string.h>
9145
9146 /* Opcode types */
9147 enum {
9148     PPC_DIRECT   = 0, /* Opcode routine        */
9149     PPC_INDIRECT = 1, /* Indirect opcode table */
9150 };
9151
9152 static inline int is_indirect_opcode (void *handler)
9153 {
9154     return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9155 }
9156
9157 static inline opc_handler_t **ind_table(void *handler)
9158 {
9159     return (opc_handler_t **)((unsigned long)handler & ~3);
9160 }
9161
9162 /* Instruction table creation */
9163 /* Opcodes tables creation */
9164 static void fill_new_table (opc_handler_t **table, int len)
9165 {
9166     int i;
9167
9168     for (i = 0; i < len; i++)
9169         table[i] = &invalid_handler;
9170 }
9171
9172 static int create_new_table (opc_handler_t **table, unsigned char idx)
9173 {
9174     opc_handler_t **tmp;
9175
9176     tmp = malloc(0x20 * sizeof(opc_handler_t));
9177     fill_new_table(tmp, 0x20);
9178     table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9179
9180     return 0;
9181 }
9182
9183 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9184                             opc_handler_t *handler)
9185 {
9186     if (table[idx] != &invalid_handler)
9187         return -1;
9188     table[idx] = handler;
9189
9190     return 0;
9191 }
9192
9193 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9194                                  unsigned char idx, opc_handler_t *handler)
9195 {
9196     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9197         printf("*** ERROR: opcode %02x already assigned in main "
9198                "opcode table\n", idx);
9199 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9200         printf("           Registered handler '%s' - new handler '%s'\n",
9201                ppc_opcodes[idx]->oname, handler->oname);
9202 #endif
9203         return -1;
9204     }
9205
9206     return 0;
9207 }
9208
9209 static int register_ind_in_table (opc_handler_t **table,
9210                                   unsigned char idx1, unsigned char idx2,
9211                                   opc_handler_t *handler)
9212 {
9213     if (table[idx1] == &invalid_handler) {
9214         if (create_new_table(table, idx1) < 0) {
9215             printf("*** ERROR: unable to create indirect table "
9216                    "idx=%02x\n", idx1);
9217             return -1;
9218         }
9219     } else {
9220         if (!is_indirect_opcode(table[idx1])) {
9221             printf("*** ERROR: idx %02x already assigned to a direct "
9222                    "opcode\n", idx1);
9223 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9224             printf("           Registered handler '%s' - new handler '%s'\n",
9225                    ind_table(table[idx1])[idx2]->oname, handler->oname);
9226 #endif
9227             return -1;
9228         }
9229     }
9230     if (handler != NULL &&
9231         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9232         printf("*** ERROR: opcode %02x already assigned in "
9233                "opcode table %02x\n", idx2, idx1);
9234 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9235         printf("           Registered handler '%s' - new handler '%s'\n",
9236                ind_table(table[idx1])[idx2]->oname, handler->oname);
9237 #endif
9238         return -1;
9239     }
9240
9241     return 0;
9242 }
9243
9244 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9245                               unsigned char idx1, unsigned char idx2,
9246                               opc_handler_t *handler)
9247 {
9248     int ret;
9249
9250     ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9251
9252     return ret;
9253 }
9254
9255 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9256                                  unsigned char idx1, unsigned char idx2,
9257                                  unsigned char idx3, opc_handler_t *handler)
9258 {
9259     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9260         printf("*** ERROR: unable to join indirect table idx "
9261                "[%02x-%02x]\n", idx1, idx2);
9262         return -1;
9263     }
9264     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9265                               handler) < 0) {
9266         printf("*** ERROR: unable to insert opcode "
9267                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9268         return -1;
9269     }
9270
9271     return 0;
9272 }
9273
9274 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9275 {
9276     if (insn->opc2 != 0xFF) {
9277         if (insn->opc3 != 0xFF) {
9278             if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9279                                      insn->opc3, &insn->handler) < 0)
9280                 return -1;
9281         } else {
9282             if (register_ind_insn(ppc_opcodes, insn->opc1,
9283                                   insn->opc2, &insn->handler) < 0)
9284                 return -1;
9285         }
9286     } else {
9287         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9288             return -1;
9289     }
9290
9291     return 0;
9292 }
9293
9294 static int test_opcode_table (opc_handler_t **table, int len)
9295 {
9296     int i, count, tmp;
9297
9298     for (i = 0, count = 0; i < len; i++) {
9299         /* Consistency fixup */
9300         if (table[i] == NULL)
9301             table[i] = &invalid_handler;
9302         if (table[i] != &invalid_handler) {
9303             if (is_indirect_opcode(table[i])) {
9304                 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9305                 if (tmp == 0) {
9306                     free(table[i]);
9307                     table[i] = &invalid_handler;
9308                 } else {
9309                     count++;
9310                 }
9311             } else {
9312                 count++;
9313             }
9314         }
9315     }
9316
9317     return count;
9318 }
9319
9320 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9321 {
9322     if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9323         printf("*** WARNING: no opcode defined !\n");
9324 }
9325
9326 /*****************************************************************************/
9327 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9328 {
9329     opcode_t *opc;
9330
9331     fill_new_table(env->opcodes, 0x40);
9332     for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9333         if ((opc->handler.type & def->insns_flags) != 0) {
9334             if (register_insn(env->opcodes, opc) < 0) {
9335                 printf("*** ERROR initializing PowerPC instruction "
9336                        "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9337                        opc->opc3);
9338                 return -1;
9339             }
9340         }
9341     }
9342     fix_opcode_tables(env->opcodes);
9343     fflush(stdout);
9344     fflush(stderr);
9345
9346     return 0;
9347 }
9348
9349 #if defined(PPC_DUMP_CPU)
9350 static void dump_ppc_insns (CPUPPCState *env)
9351 {
9352     opc_handler_t **table, *handler;
9353     const char *p, *q;
9354     uint8_t opc1, opc2, opc3;
9355
9356     printf("Instructions set:\n");
9357     /* opc1 is 6 bits long */
9358     for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9359         table = env->opcodes;
9360         handler = table[opc1];
9361         if (is_indirect_opcode(handler)) {
9362             /* opc2 is 5 bits long */
9363             for (opc2 = 0; opc2 < 0x20; opc2++) {
9364                 table = env->opcodes;
9365                 handler = env->opcodes[opc1];
9366                 table = ind_table(handler);
9367                 handler = table[opc2];
9368                 if (is_indirect_opcode(handler)) {
9369                     table = ind_table(handler);
9370                     /* opc3 is 5 bits long */
9371                     for (opc3 = 0; opc3 < 0x20; opc3++) {
9372                         handler = table[opc3];
9373                         if (handler->handler != &gen_invalid) {
9374                             /* Special hack to properly dump SPE insns */
9375                             p = strchr(handler->oname, '_');
9376                             if (p == NULL) {
9377                                 printf("INSN: %02x %02x %02x (%02d %04d) : "
9378                                        "%s\n",
9379                                        opc1, opc2, opc3, opc1,
9380                                        (opc3 << 5) | opc2,
9381                                        handler->oname);
9382                             } else {
9383                                 q = "speundef";
9384                                 if ((p - handler->oname) != strlen(q) ||
9385                                     memcmp(handler->oname, q, strlen(q)) != 0) {
9386                                     /* First instruction */
9387                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9388                                            "%.*s\n",
9389                                            opc1, opc2 << 1, opc3, opc1,
9390                                            (opc3 << 6) | (opc2 << 1),
9391                                            (int)(p - handler->oname),
9392                                            handler->oname);
9393                                 }
9394                                 if (strcmp(p + 1, q) != 0) {
9395                                     /* Second instruction */
9396                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9397                                            "%s\n",
9398                                            opc1, (opc2 << 1) | 1, opc3, opc1,
9399                                            (opc3 << 6) | (opc2 << 1) | 1,
9400                                            p + 1);
9401                                 }
9402                             }
9403                         }
9404                     }
9405                 } else {
9406                     if (handler->handler != &gen_invalid) {
9407                         printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9408                                opc1, opc2, opc1, opc2, handler->oname);
9409                     }
9410                 }
9411             }
9412         } else {
9413             if (handler->handler != &gen_invalid) {
9414                 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9415                        opc1, opc1, handler->oname);
9416             }
9417         }
9418     }
9419 }
9420 #endif
9421
9422 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9423 {
9424     if (n < 32) {
9425         stfq_p(mem_buf, env->fpr[n]);
9426         return 8;
9427     }
9428     if (n == 32) {
9429         /* FPSCR not implemented  */
9430         memset(mem_buf, 0, 4);
9431         return 4;
9432     }
9433     return 0;
9434 }
9435
9436 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9437 {
9438     if (n < 32) {
9439         env->fpr[n] = ldfq_p(mem_buf);
9440         return 8;
9441     }
9442     if (n == 32) {
9443         /* FPSCR not implemented  */
9444         return 4;
9445     }
9446     return 0;
9447 }
9448
9449 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9450 {
9451     if (n < 32) {
9452 #ifdef HOST_WORDS_BIGENDIAN
9453         stq_p(mem_buf, env->avr[n].u64[0]);
9454         stq_p(mem_buf+8, env->avr[n].u64[1]);
9455 #else
9456         stq_p(mem_buf, env->avr[n].u64[1]);
9457         stq_p(mem_buf+8, env->avr[n].u64[0]);
9458 #endif
9459         return 16;
9460     }
9461     if (n == 32) {
9462         stl_p(mem_buf, env->vscr);
9463         return 4;
9464     }
9465     if (n == 33) {
9466         stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9467         return 4;
9468     }
9469     return 0;
9470 }
9471
9472 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9473 {
9474     if (n < 32) {
9475 #ifdef HOST_WORDS_BIGENDIAN
9476         env->avr[n].u64[0] = ldq_p(mem_buf);
9477         env->avr[n].u64[1] = ldq_p(mem_buf+8);
9478 #else
9479         env->avr[n].u64[1] = ldq_p(mem_buf);
9480         env->avr[n].u64[0] = ldq_p(mem_buf+8);
9481 #endif
9482         return 16;
9483     }
9484     if (n == 32) {
9485         env->vscr = ldl_p(mem_buf);
9486         return 4;
9487     }
9488     if (n == 33) {
9489         env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9490         return 4;
9491     }
9492     return 0;
9493 }
9494
9495 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9496 {
9497     if (n < 32) {
9498 #if defined(TARGET_PPC64)
9499         stl_p(mem_buf, env->gpr[n] >> 32);
9500 #else
9501         stl_p(mem_buf, env->gprh[n]);
9502 #endif
9503         return 4;
9504     }
9505     if (n == 32) {
9506         stq_p(mem_buf, env->spe_acc);
9507         return 8;
9508     }
9509     if (n == 33) {
9510         stl_p(mem_buf, env->spe_fscr);
9511         return 4;
9512     }
9513     return 0;
9514 }
9515
9516 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9517 {
9518     if (n < 32) {
9519 #if defined(TARGET_PPC64)
9520         target_ulong lo = (uint32_t)env->gpr[n];
9521         target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9522         env->gpr[n] = lo | hi;
9523 #else
9524         env->gprh[n] = ldl_p(mem_buf);
9525 #endif
9526         return 4;
9527     }
9528     if (n == 32) {
9529         env->spe_acc = ldq_p(mem_buf);
9530         return 8;
9531     }
9532     if (n == 33) {
9533         env->spe_fscr = ldl_p(mem_buf);
9534         return 4;
9535     }
9536     return 0;
9537 }
9538
9539 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9540 {
9541     env->msr_mask = def->msr_mask;
9542     env->mmu_model = def->mmu_model;
9543     env->excp_model = def->excp_model;
9544     env->bus_model = def->bus_model;
9545     env->insns_flags = def->insns_flags;
9546     env->flags = def->flags;
9547     env->bfd_mach = def->bfd_mach;
9548     env->check_pow = def->check_pow;
9549     if (create_ppc_opcodes(env, def) < 0)
9550         return -1;
9551     init_ppc_proc(env, def);
9552
9553     if (def->insns_flags & PPC_FLOAT) {
9554         gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9555                                  33, "power-fpu.xml", 0);
9556     }
9557     if (def->insns_flags & PPC_ALTIVEC) {
9558         gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9559                                  34, "power-altivec.xml", 0);
9560     }
9561     if (def->insns_flags & PPC_SPE) {
9562         gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9563                                  34, "power-spe.xml", 0);
9564     }
9565
9566 #if defined(PPC_DUMP_CPU)
9567     {
9568         const char *mmu_model, *excp_model, *bus_model;
9569         switch (env->mmu_model) {
9570         case POWERPC_MMU_32B:
9571             mmu_model = "PowerPC 32";
9572             break;
9573         case POWERPC_MMU_SOFT_6xx:
9574             mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9575             break;
9576         case POWERPC_MMU_SOFT_74xx:
9577             mmu_model = "PowerPC 74xx with software driven TLBs";
9578             break;
9579         case POWERPC_MMU_SOFT_4xx:
9580             mmu_model = "PowerPC 4xx with software driven TLBs";
9581             break;
9582         case POWERPC_MMU_SOFT_4xx_Z:
9583             mmu_model = "PowerPC 4xx with software driven TLBs "
9584                 "and zones protections";
9585             break;
9586         case POWERPC_MMU_REAL:
9587             mmu_model = "PowerPC real mode only";
9588             break;
9589         case POWERPC_MMU_MPC8xx:
9590             mmu_model = "PowerPC MPC8xx";
9591             break;
9592         case POWERPC_MMU_BOOKE:
9593             mmu_model = "PowerPC BookE";
9594             break;
9595         case POWERPC_MMU_BOOKE_FSL:
9596             mmu_model = "PowerPC BookE FSL";
9597             break;
9598         case POWERPC_MMU_601:
9599             mmu_model = "PowerPC 601";
9600             break;
9601 #if defined (TARGET_PPC64)
9602         case POWERPC_MMU_64B:
9603             mmu_model = "PowerPC 64";
9604             break;
9605         case POWERPC_MMU_620:
9606             mmu_model = "PowerPC 620";
9607             break;
9608 #endif
9609         default:
9610             mmu_model = "Unknown or invalid";
9611             break;
9612         }
9613         switch (env->excp_model) {
9614         case POWERPC_EXCP_STD:
9615             excp_model = "PowerPC";
9616             break;
9617         case POWERPC_EXCP_40x:
9618             excp_model = "PowerPC 40x";
9619             break;
9620         case POWERPC_EXCP_601:
9621             excp_model = "PowerPC 601";
9622             break;
9623         case POWERPC_EXCP_602:
9624             excp_model = "PowerPC 602";
9625             break;
9626         case POWERPC_EXCP_603:
9627             excp_model = "PowerPC 603";
9628             break;
9629         case POWERPC_EXCP_603E:
9630             excp_model = "PowerPC 603e";
9631             break;
9632         case POWERPC_EXCP_604:
9633             excp_model = "PowerPC 604";
9634             break;
9635         case POWERPC_EXCP_7x0:
9636             excp_model = "PowerPC 740/750";
9637             break;
9638         case POWERPC_EXCP_7x5:
9639             excp_model = "PowerPC 745/755";
9640             break;
9641         case POWERPC_EXCP_74xx:
9642             excp_model = "PowerPC 74xx";
9643             break;
9644         case POWERPC_EXCP_BOOKE:
9645             excp_model = "PowerPC BookE";
9646             break;
9647 #if defined (TARGET_PPC64)
9648         case POWERPC_EXCP_970:
9649             excp_model = "PowerPC 970";
9650             break;
9651 #endif
9652         default:
9653             excp_model = "Unknown or invalid";
9654             break;
9655         }
9656         switch (env->bus_model) {
9657         case PPC_FLAGS_INPUT_6xx:
9658             bus_model = "PowerPC 6xx";
9659             break;
9660         case PPC_FLAGS_INPUT_BookE:
9661             bus_model = "PowerPC BookE";
9662             break;
9663         case PPC_FLAGS_INPUT_405:
9664             bus_model = "PowerPC 405";
9665             break;
9666         case PPC_FLAGS_INPUT_401:
9667             bus_model = "PowerPC 401/403";
9668             break;
9669         case PPC_FLAGS_INPUT_RCPU:
9670             bus_model = "RCPU / MPC8xx";
9671             break;
9672 #if defined (TARGET_PPC64)
9673         case PPC_FLAGS_INPUT_970:
9674             bus_model = "PowerPC 970";
9675             break;
9676 #endif
9677         default:
9678             bus_model = "Unknown or invalid";
9679             break;
9680         }
9681         printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9682                "    MMU model        : %s\n",
9683                def->name, def->pvr, def->msr_mask, mmu_model);
9684 #if !defined(CONFIG_USER_ONLY)
9685         if (env->tlb != NULL) {
9686             printf("                       %d %s TLB in %d ways\n",
9687                    env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9688                    env->nb_ways);
9689         }
9690 #endif
9691         printf("    Exceptions model : %s\n"
9692                "    Bus model        : %s\n",
9693                excp_model, bus_model);
9694         printf("    MSR features     :\n");
9695         if (env->flags & POWERPC_FLAG_SPE)
9696             printf("                        signal processing engine enable"
9697                    "\n");
9698         else if (env->flags & POWERPC_FLAG_VRE)
9699             printf("                        vector processor enable\n");
9700         if (env->flags & POWERPC_FLAG_TGPR)
9701             printf("                        temporary GPRs\n");
9702         else if (env->flags & POWERPC_FLAG_CE)
9703             printf("                        critical input enable\n");
9704         if (env->flags & POWERPC_FLAG_SE)
9705             printf("                        single-step trace mode\n");
9706         else if (env->flags & POWERPC_FLAG_DWE)
9707             printf("                        debug wait enable\n");
9708         else if (env->flags & POWERPC_FLAG_UBLE)
9709             printf("                        user BTB lock enable\n");
9710         if (env->flags & POWERPC_FLAG_BE)
9711             printf("                        branch-step trace mode\n");
9712         else if (env->flags & POWERPC_FLAG_DE)
9713             printf("                        debug interrupt enable\n");
9714         if (env->flags & POWERPC_FLAG_PX)
9715             printf("                        inclusive protection\n");
9716         else if (env->flags & POWERPC_FLAG_PMM)
9717             printf("                        performance monitor mark\n");
9718         if (env->flags == POWERPC_FLAG_NONE)
9719             printf("                        none\n");
9720         printf("    Time-base/decrementer clock source: %s\n",
9721                env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9722     }
9723     dump_ppc_insns(env);
9724     dump_ppc_sprs(env);
9725     fflush(stdout);
9726 #endif
9727
9728     return 0;
9729 }
9730
9731 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
9732 {
9733     const ppc_def_t *ret;
9734     uint32_t pvr_rev;
9735     int i, best, match, best_match, max;
9736
9737     ret = NULL;
9738     max = ARRAY_SIZE(ppc_defs);
9739     best = -1;
9740     pvr_rev = pvr & 0xFFFF;
9741     /* We want all specified bits to match */
9742     best_match = 32 - ctz32(pvr_rev);
9743     for (i = 0; i < max; i++) {
9744         /* We check that the 16 higher bits are the same to ensure the CPU
9745          * model will be the choosen one.
9746          */
9747         if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9748             /* We want as much as possible of the low-level 16 bits
9749              * to be the same but we allow inexact matches.
9750              */
9751             match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9752             /* We check '>=' instead of '>' because the PPC_defs table
9753              * is ordered by increasing revision.
9754              * Then, we will match the higher revision compatible
9755              * with the requested PVR
9756              */
9757             if (match >= best_match) {
9758                 best = i;
9759                 best_match = match;
9760             }
9761         }
9762     }
9763     if (best != -1)
9764         ret = &ppc_defs[best];
9765
9766     return ret;
9767 }
9768
9769 #include <ctype.h>
9770
9771 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
9772 {
9773     const ppc_def_t *ret;
9774     const char *p;
9775     int i, max, len;
9776
9777     /* Check if the given name is a PVR */
9778     len = strlen(name);
9779     if (len == 10 && name[0] == '0' && name[1] == 'x') {
9780         p = name + 2;
9781         goto check_pvr;
9782     } else if (len == 8) {
9783         p = name;
9784     check_pvr:
9785         for (i = 0; i < 8; i++) {
9786             if (!qemu_isxdigit(*p++))
9787                 break;
9788         }
9789         if (i == 8)
9790             return ppc_find_by_pvr(strtoul(name, NULL, 16));
9791     }
9792     ret = NULL;
9793     max = ARRAY_SIZE(ppc_defs);
9794     for (i = 0; i < max; i++) {
9795         if (strcasecmp(name, ppc_defs[i].name) == 0) {
9796             ret = &ppc_defs[i];
9797             break;
9798         }
9799     }
9800
9801     return ret;
9802 }
9803
9804 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
9805 {
9806     int i, max;
9807
9808     max = ARRAY_SIZE(ppc_defs);
9809     for (i = 0; i < max; i++) {
9810         (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9811                        ppc_defs[i].name, ppc_defs[i].pvr);
9812     }
9813 }