target/openrisc/mmu.c

   1 /*
   2  * OpenRISC MMU.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Zhizhou Zhang <etouzh@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "qemu-common.h"
  25 #include "exec/gdbstub.h"
  26 #include "qemu/host-utils.h"
  27 #ifndef CONFIG_USER_ONLY
  28 #include "hw/loader.h"
  29 #endif
  30
  31 #ifndef CONFIG_USER_ONLY
  32 static inline int get_phys_nommu(hwaddr *physical, int *prot,
  33                                  target_ulong address)
  34 {
  35     *physical = address;
  36     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
  37     return TLBRET_MATCH;
  38 }
  39
  40 static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
  41                          target_ulong address, int rw, bool supervisor)
  42 {
  43     int vpn = address >> TARGET_PAGE_BITS;
  44     int idx = vpn & ITLB_MASK;
  45     int right = 0;
  46
  47     if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
  48         return TLBRET_NOMATCH;
  49     }
  50     if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) {
  51         return TLBRET_INVALID;
  52     }
  53     if (supervisor) {
  54         if (cpu->env.tlb.itlb[0][idx].tr & SXE) {
  55             right |= PAGE_EXEC;
  56         }
  57     } else {
  58         if (cpu->env.tlb.itlb[0][idx].tr & UXE) {
  59             right |= PAGE_EXEC;
  60         }
  61     }
  62     if ((rw & 2) && ((right & PAGE_EXEC) == 0)) {
  63         return TLBRET_BADADDR;
  64     }
  65
  66     *physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) |
  67                 (address & (TARGET_PAGE_SIZE-1));
  68     *prot = right;
  69     return TLBRET_MATCH;
  70 }
  71
  72 static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
  73                          target_ulong address, int rw, bool supervisor)
  74 {
  75     int vpn = address >> TARGET_PAGE_BITS;
  76     int idx = vpn & DTLB_MASK;
  77     int right = 0;
  78
  79     if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
  80         return TLBRET_NOMATCH;
  81     }
  82     if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) {
  83         return TLBRET_INVALID;
  84     }
  85     if (supervisor) {
  86         if (cpu->env.tlb.dtlb[0][idx].tr & SRE) {
  87             right |= PAGE_READ;
  88         }
  89         if (cpu->env.tlb.dtlb[0][idx].tr & SWE) {
  90             right |= PAGE_WRITE;
  91         }
  92     } else {
  93         if (cpu->env.tlb.dtlb[0][idx].tr & URE) {
  94             right |= PAGE_READ;
  95         }
  96         if (cpu->env.tlb.dtlb[0][idx].tr & UWE) {
  97             right |= PAGE_WRITE;
  98         }
  99     }
 100
 101     if (!(rw & 1) && ((right & PAGE_READ) == 0)) {
 102         return TLBRET_BADADDR;
 103     }
 104     if ((rw & 1) && ((right & PAGE_WRITE) == 0)) {
 105         return TLBRET_BADADDR;
 106     }
 107
 108     *physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) |
 109                 (address & (TARGET_PAGE_SIZE-1));
 110     *prot = right;
 111     return TLBRET_MATCH;
 112 }
 113
 114 static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical,
 115                          int *prot, target_ulong address, int rw)
 116 {
 117     bool supervisor = (cpu->env.sr & SR_SM) != 0;
 118     int ret;
 119
 120     /* Assume nommu results for a moment.  */
 121     ret = get_phys_nommu(physical, prot, address);
 122
 123     /* Overwrite with TLB lookup if enabled.  */
 124     if (rw == MMU_INST_FETCH) {
 125         if (cpu->env.sr & SR_IME) {
 126             ret = get_phys_code(cpu, physical, prot, address, rw, supervisor);
 127         }
 128     } else {
 129         if (cpu->env.sr & SR_DME) {
 130             ret = get_phys_data(cpu, physical, prot, address, rw, supervisor);
 131         }
 132     }
 133
 134     return ret;
 135 }
 136 #endif
 137
 138 static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
 139                                              target_ulong address,
 140                                              int rw, int tlb_error)
 141 {
 142     CPUState *cs = CPU(cpu);
 143     int exception = 0;
 144
 145     switch (tlb_error) {
 146     default:
 147         if (rw == 2) {
 148             exception = EXCP_IPF;
 149         } else {
 150             exception = EXCP_DPF;
 151         }
 152         break;
 153 #ifndef CONFIG_USER_ONLY
 154     case TLBRET_BADADDR:
 155         if (rw == 2) {
 156             exception = EXCP_IPF;
 157         } else {
 158             exception = EXCP_DPF;
 159         }
 160         break;
 161     case TLBRET_INVALID:
 162     case TLBRET_NOMATCH:
 163         /* No TLB match for a mapped address */
 164         if (rw == 2) {
 165             exception = EXCP_ITLBMISS;
 166         } else {
 167             exception = EXCP_DTLBMISS;
 168         }
 169         break;
 170 #endif
 171     }
 172
 173     cs->exception_index = exception;
 174     cpu->env.eear = address;
 175     cpu->env.lock_addr = -1;
 176 }
 177
 178 #ifndef CONFIG_USER_ONLY
 179 int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
 180                                   int rw, int mmu_idx)
 181 {
 182     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
 183     int ret = 0;
 184     hwaddr physical = 0;
 185     int prot = 0;
 186
 187     ret = get_phys_addr(cpu, &physical, &prot, address, rw);
 188
 189     if (ret == TLBRET_MATCH) {
 190         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 191                      physical & TARGET_PAGE_MASK, prot,
 192                      mmu_idx, TARGET_PAGE_SIZE);
 193         ret = 0;
 194     } else if (ret < 0) {
 195         cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
 196         ret = 1;
 197     }
 198
 199     return ret;
 200 }
 201 #else
 202 int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
 203                                   int rw, int mmu_idx)
 204 {
 205     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
 206     int ret = 0;
 207
 208     cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
 209     ret = 1;
 210
 211     return ret;
 212 }
 213 #endif
 214
 215 #ifndef CONFIG_USER_ONLY
 216 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 217 {
 218     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
 219     hwaddr phys_addr;
 220     int prot;
 221     int miss;
 222
 223     /* Check memory for any kind of address, since during debug the
 224        gdb can ask for anything, check data tlb for address */
 225     miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0);
 226
 227     /* Check instruction tlb */
 228     if (miss) {
 229         miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH);
 230     }
 231
 232     /* Last, fall back to a plain address */
 233     if (miss) {
 234         miss = get_phys_nommu(&phys_addr, &prot, addr);
 235     }
 236
 237     if (miss) {
 238         return -1;
 239     } else {
 240         return phys_addr;
 241     }
 242 }
 243
 244 void tlb_fill(CPUState *cs, target_ulong addr, int size,
 245               MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
 246 {
 247     int ret = openrisc_cpu_handle_mmu_fault(cs, addr, size,
 248                                             access_type, mmu_idx);
 249     if (ret) {
 250         /* Raise Exception.  */
 251         cpu_loop_exit_restore(cs, retaddr);
 252     }
 253 }
 254 #endif