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target/ppc: Merge 7x5 and 7x0 exception model IDs
[qemu.git] / target / ppc / cpu_init.c
blobd97f7183549f34339a568f08095df0c88b88ccc7
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "qapi/qapi-commands-machine-target.h"
44
45 #include "helper_regs.h"
46 #include "internal.h"
47 #include "spr_tcg.h"
48 #include "power8-pmu.h"
49
50 /* #define PPC_DEBUG_SPR */
51 /* #define USE_APPLE_GDB */
52
53 static inline void vscr_init(CPUPPCState *env, uint32_t val)
54 {
55 /* Altivec always uses round-to-nearest */
56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
57 ppc_store_vscr(env, val);
58 }
59
60 /**
61 * _spr_register
62 *
63 * Register an SPR with all the callbacks required for tcg,
64 * and the ID number for KVM.
65 *
66 * The reason for the conditional compilation is that the tcg functions
67 * may be compiled out, and the system kvm header may not be available
68 * for supplying the ID numbers. This is ugly, but the best we can do.
69 */
70
71 #ifdef CONFIG_TCG
72 # define USR_ARG(X) X,
73 # ifdef CONFIG_USER_ONLY
74 # define SYS_ARG(X)
75 # else
76 # define SYS_ARG(X) X,
77 # endif
78 #else
79 # define USR_ARG(X)
80 # define SYS_ARG(X)
81 #endif
82 #ifdef CONFIG_KVM
83 # define KVM_ARG(X) X,
84 #else
85 # define KVM_ARG(X)
86 #endif
87
88 typedef void spr_callback(DisasContext *, int, int);
89
90 static void _spr_register(CPUPPCState *env, int num, const char *name,
91 USR_ARG(spr_callback *uea_read)
92 USR_ARG(spr_callback *uea_write)
93 SYS_ARG(spr_callback *oea_read)
94 SYS_ARG(spr_callback *oea_write)
95 SYS_ARG(spr_callback *hea_read)
96 SYS_ARG(spr_callback *hea_write)
97 KVM_ARG(uint64_t one_reg_id)
98 target_ulong initial_value)
99 {
100 ppc_spr_t *spr = &env->spr_cb[num];
101
102 /* No SPR should be registered twice. */
103 assert(spr->name == NULL);
104 assert(name != NULL);
105
106 spr->name = name;
107 spr->default_value = initial_value;
108 env->spr[num] = initial_value;
109
110 #ifdef CONFIG_TCG
111 spr->uea_read = uea_read;
112 spr->uea_write = uea_write;
113 # ifndef CONFIG_USER_ONLY
114 spr->oea_read = oea_read;
115 spr->oea_write = oea_write;
116 spr->hea_read = hea_read;
117 spr->hea_write = hea_write;
118 # endif
119 #endif
120 #ifdef CONFIG_KVM
121 spr->one_reg_id = one_reg_id;
122 #endif
123 }
124
125 /* spr_register_kvm_hv passes all required arguments. */
126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
127 oea_read, oea_write, hea_read, hea_write, \
128 one_reg_id, initial_value) \
129 _spr_register(env, num, name, \
130 USR_ARG(uea_read) USR_ARG(uea_write) \
131 SYS_ARG(oea_read) SYS_ARG(oea_write) \
132 SYS_ARG(hea_read) SYS_ARG(hea_write) \
133 KVM_ARG(one_reg_id) initial_value)
134
135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
137 oea_read, oea_write, one_reg_id, ival) \
138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
139 oea_write, oea_read, oea_write, one_reg_id, ival)
140
141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */
142 #define spr_register_hv(env, num, name, uea_read, uea_write, \
143 oea_read, oea_write, hea_read, hea_write, ival) \
144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
145 oea_write, hea_read, hea_write, 0, ival)
146
147 #define spr_register(env, num, name, uea_read, uea_write, \
148 oea_read, oea_write, ival) \
149 spr_register_kvm(env, num, name, uea_read, uea_write, \
150 oea_read, oea_write, 0, ival)
151
152 /* Generic PowerPC SPRs */
153 static void register_generic_sprs(CPUPPCState *env)
154 {
155 /* Integer processing */
156 spr_register(env, SPR_XER, "XER",
157 &spr_read_xer, &spr_write_xer,
158 &spr_read_xer, &spr_write_xer,
159 0x00000000);
160 /* Branch control */
161 spr_register(env, SPR_LR, "LR",
162 &spr_read_lr, &spr_write_lr,
163 &spr_read_lr, &spr_write_lr,
164 0x00000000);
165 spr_register(env, SPR_CTR, "CTR",
166 &spr_read_ctr, &spr_write_ctr,
167 &spr_read_ctr, &spr_write_ctr,
168 0x00000000);
169 /* Interrupt processing */
170 spr_register(env, SPR_SRR0, "SRR0",
171 SPR_NOACCESS, SPR_NOACCESS,
172 &spr_read_generic, &spr_write_generic,
173 0x00000000);
174 spr_register(env, SPR_SRR1, "SRR1",
175 SPR_NOACCESS, SPR_NOACCESS,
176 &spr_read_generic, &spr_write_generic,
177 0x00000000);
178 /* Processor control */
179 spr_register(env, SPR_SPRG0, "SPRG0",
180 SPR_NOACCESS, SPR_NOACCESS,
181 &spr_read_generic, &spr_write_generic,
182 0x00000000);
183 spr_register(env, SPR_SPRG1, "SPRG1",
184 SPR_NOACCESS, SPR_NOACCESS,
185 &spr_read_generic, &spr_write_generic,
186 0x00000000);
187 spr_register(env, SPR_SPRG2, "SPRG2",
188 SPR_NOACCESS, SPR_NOACCESS,
189 &spr_read_generic, &spr_write_generic,
190 0x00000000);
191 spr_register(env, SPR_SPRG3, "SPRG3",
192 SPR_NOACCESS, SPR_NOACCESS,
193 &spr_read_generic, &spr_write_generic,
194 0x00000000);
195 }
196
197 /* SPR common to all non-embedded PowerPC, including 601 */
198 static void register_ne_601_sprs(CPUPPCState *env)
199 {
200 /* Exception processing */
201 spr_register_kvm(env, SPR_DSISR, "DSISR",
202 SPR_NOACCESS, SPR_NOACCESS,
203 &spr_read_generic, &spr_write_generic,
204 KVM_REG_PPC_DSISR, 0x00000000);
205 spr_register_kvm(env, SPR_DAR, "DAR",
206 SPR_NOACCESS, SPR_NOACCESS,
207 &spr_read_generic, &spr_write_generic,
208 KVM_REG_PPC_DAR, 0x00000000);
209 /* Timer */
210 spr_register(env, SPR_DECR, "DECR",
211 SPR_NOACCESS, SPR_NOACCESS,
212 &spr_read_decr, &spr_write_decr,
213 0x00000000);
214 }
215
216 /* Storage Description Register 1 */
217 static void register_sdr1_sprs(CPUPPCState *env)
218 {
219 #ifndef CONFIG_USER_ONLY
220 if (env->has_hv_mode) {
221 /*
222 * SDR1 is a hypervisor resource on CPUs which have a
223 * hypervisor mode
224 */
225 spr_register_hv(env, SPR_SDR1, "SDR1",
226 SPR_NOACCESS, SPR_NOACCESS,
227 SPR_NOACCESS, SPR_NOACCESS,
228 &spr_read_generic, &spr_write_sdr1,
229 0x00000000);
230 } else {
231 spr_register(env, SPR_SDR1, "SDR1",
232 SPR_NOACCESS, SPR_NOACCESS,
233 &spr_read_generic, &spr_write_sdr1,
234 0x00000000);
235 }
236 #endif
237 }
238
239 /* BATs 0-3 */
240 static void register_low_BATs(CPUPPCState *env)
241 {
242 #if !defined(CONFIG_USER_ONLY)
243 spr_register(env, SPR_IBAT0U, "IBAT0U",
244 SPR_NOACCESS, SPR_NOACCESS,
245 &spr_read_ibat, &spr_write_ibatu,
246 0x00000000);
247 spr_register(env, SPR_IBAT0L, "IBAT0L",
248 SPR_NOACCESS, SPR_NOACCESS,
249 &spr_read_ibat, &spr_write_ibatl,
250 0x00000000);
251 spr_register(env, SPR_IBAT1U, "IBAT1U",
252 SPR_NOACCESS, SPR_NOACCESS,
253 &spr_read_ibat, &spr_write_ibatu,
254 0x00000000);
255 spr_register(env, SPR_IBAT1L, "IBAT1L",
256 SPR_NOACCESS, SPR_NOACCESS,
257 &spr_read_ibat, &spr_write_ibatl,
258 0x00000000);
259 spr_register(env, SPR_IBAT2U, "IBAT2U",
260 SPR_NOACCESS, SPR_NOACCESS,
261 &spr_read_ibat, &spr_write_ibatu,
262 0x00000000);
263 spr_register(env, SPR_IBAT2L, "IBAT2L",
264 SPR_NOACCESS, SPR_NOACCESS,
265 &spr_read_ibat, &spr_write_ibatl,
266 0x00000000);
267 spr_register(env, SPR_IBAT3U, "IBAT3U",
268 SPR_NOACCESS, SPR_NOACCESS,
269 &spr_read_ibat, &spr_write_ibatu,
270 0x00000000);
271 spr_register(env, SPR_IBAT3L, "IBAT3L",
272 SPR_NOACCESS, SPR_NOACCESS,
273 &spr_read_ibat, &spr_write_ibatl,
274 0x00000000);
275 spr_register(env, SPR_DBAT0U, "DBAT0U",
276 SPR_NOACCESS, SPR_NOACCESS,
277 &spr_read_dbat, &spr_write_dbatu,
278 0x00000000);
279 spr_register(env, SPR_DBAT0L, "DBAT0L",
280 SPR_NOACCESS, SPR_NOACCESS,
281 &spr_read_dbat, &spr_write_dbatl,
282 0x00000000);
283 spr_register(env, SPR_DBAT1U, "DBAT1U",
284 SPR_NOACCESS, SPR_NOACCESS,
285 &spr_read_dbat, &spr_write_dbatu,
286 0x00000000);
287 spr_register(env, SPR_DBAT1L, "DBAT1L",
288 SPR_NOACCESS, SPR_NOACCESS,
289 &spr_read_dbat, &spr_write_dbatl,
290 0x00000000);
291 spr_register(env, SPR_DBAT2U, "DBAT2U",
292 SPR_NOACCESS, SPR_NOACCESS,
293 &spr_read_dbat, &spr_write_dbatu,
294 0x00000000);
295 spr_register(env, SPR_DBAT2L, "DBAT2L",
296 SPR_NOACCESS, SPR_NOACCESS,
297 &spr_read_dbat, &spr_write_dbatl,
298 0x00000000);
299 spr_register(env, SPR_DBAT3U, "DBAT3U",
300 SPR_NOACCESS, SPR_NOACCESS,
301 &spr_read_dbat, &spr_write_dbatu,
302 0x00000000);
303 spr_register(env, SPR_DBAT3L, "DBAT3L",
304 SPR_NOACCESS, SPR_NOACCESS,
305 &spr_read_dbat, &spr_write_dbatl,
306 0x00000000);
307 env->nb_BATs += 4;
308 #endif
309 }
310
311 /* BATs 4-7 */
312 static void register_high_BATs(CPUPPCState *env)
313 {
314 #if !defined(CONFIG_USER_ONLY)
315 spr_register(env, SPR_IBAT4U, "IBAT4U",
316 SPR_NOACCESS, SPR_NOACCESS,
317 &spr_read_ibat_h, &spr_write_ibatu_h,
318 0x00000000);
319 spr_register(env, SPR_IBAT4L, "IBAT4L",
320 SPR_NOACCESS, SPR_NOACCESS,
321 &spr_read_ibat_h, &spr_write_ibatl_h,
322 0x00000000);
323 spr_register(env, SPR_IBAT5U, "IBAT5U",
324 SPR_NOACCESS, SPR_NOACCESS,
325 &spr_read_ibat_h, &spr_write_ibatu_h,
326 0x00000000);
327 spr_register(env, SPR_IBAT5L, "IBAT5L",
328 SPR_NOACCESS, SPR_NOACCESS,
329 &spr_read_ibat_h, &spr_write_ibatl_h,
330 0x00000000);
331 spr_register(env, SPR_IBAT6U, "IBAT6U",
332 SPR_NOACCESS, SPR_NOACCESS,
333 &spr_read_ibat_h, &spr_write_ibatu_h,
334 0x00000000);
335 spr_register(env, SPR_IBAT6L, "IBAT6L",
336 SPR_NOACCESS, SPR_NOACCESS,
337 &spr_read_ibat_h, &spr_write_ibatl_h,
338 0x00000000);
339 spr_register(env, SPR_IBAT7U, "IBAT7U",
340 SPR_NOACCESS, SPR_NOACCESS,
341 &spr_read_ibat_h, &spr_write_ibatu_h,
342 0x00000000);
343 spr_register(env, SPR_IBAT7L, "IBAT7L",
344 SPR_NOACCESS, SPR_NOACCESS,
345 &spr_read_ibat_h, &spr_write_ibatl_h,
346 0x00000000);
347 spr_register(env, SPR_DBAT4U, "DBAT4U",
348 SPR_NOACCESS, SPR_NOACCESS,
349 &spr_read_dbat_h, &spr_write_dbatu_h,
350 0x00000000);
351 spr_register(env, SPR_DBAT4L, "DBAT4L",
352 SPR_NOACCESS, SPR_NOACCESS,
353 &spr_read_dbat_h, &spr_write_dbatl_h,
354 0x00000000);
355 spr_register(env, SPR_DBAT5U, "DBAT5U",
356 SPR_NOACCESS, SPR_NOACCESS,
357 &spr_read_dbat_h, &spr_write_dbatu_h,
358 0x00000000);
359 spr_register(env, SPR_DBAT5L, "DBAT5L",
360 SPR_NOACCESS, SPR_NOACCESS,
361 &spr_read_dbat_h, &spr_write_dbatl_h,
362 0x00000000);
363 spr_register(env, SPR_DBAT6U, "DBAT6U",
364 SPR_NOACCESS, SPR_NOACCESS,
365 &spr_read_dbat_h, &spr_write_dbatu_h,
366 0x00000000);
367 spr_register(env, SPR_DBAT6L, "DBAT6L",
368 SPR_NOACCESS, SPR_NOACCESS,
369 &spr_read_dbat_h, &spr_write_dbatl_h,
370 0x00000000);
371 spr_register(env, SPR_DBAT7U, "DBAT7U",
372 SPR_NOACCESS, SPR_NOACCESS,
373 &spr_read_dbat_h, &spr_write_dbatu_h,
374 0x00000000);
375 spr_register(env, SPR_DBAT7L, "DBAT7L",
376 SPR_NOACCESS, SPR_NOACCESS,
377 &spr_read_dbat_h, &spr_write_dbatl_h,
378 0x00000000);
379 env->nb_BATs += 4;
380 #endif
381 }
382
383 /* Generic PowerPC time base */
384 static void register_tbl(CPUPPCState *env)
385 {
386 spr_register(env, SPR_VTBL, "TBL",
387 &spr_read_tbl, SPR_NOACCESS,
388 &spr_read_tbl, SPR_NOACCESS,
389 0x00000000);
390 spr_register(env, SPR_TBL, "TBL",
391 &spr_read_tbl, SPR_NOACCESS,
392 &spr_read_tbl, &spr_write_tbl,
393 0x00000000);
394 spr_register(env, SPR_VTBU, "TBU",
395 &spr_read_tbu, SPR_NOACCESS,
396 &spr_read_tbu, SPR_NOACCESS,
397 0x00000000);
398 spr_register(env, SPR_TBU, "TBU",
399 &spr_read_tbu, SPR_NOACCESS,
400 &spr_read_tbu, &spr_write_tbu,
401 0x00000000);
402 }
403
404 /* Softare table search registers */
405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
406 {
407 #if !defined(CONFIG_USER_ONLY)
408 env->nb_tlb = nb_tlbs;
409 env->nb_ways = nb_ways;
410 env->id_tlbs = 1;
411 env->tlb_type = TLB_6XX;
412 spr_register(env, SPR_DMISS, "DMISS",
413 SPR_NOACCESS, SPR_NOACCESS,
414 &spr_read_generic, SPR_NOACCESS,
415 0x00000000);
416 spr_register(env, SPR_DCMP, "DCMP",
417 SPR_NOACCESS, SPR_NOACCESS,
418 &spr_read_generic, SPR_NOACCESS,
419 0x00000000);
420 spr_register(env, SPR_HASH1, "HASH1",
421 SPR_NOACCESS, SPR_NOACCESS,
422 &spr_read_generic, SPR_NOACCESS,
423 0x00000000);
424 spr_register(env, SPR_HASH2, "HASH2",
425 SPR_NOACCESS, SPR_NOACCESS,
426 &spr_read_generic, SPR_NOACCESS,
427 0x00000000);
428 spr_register(env, SPR_IMISS, "IMISS",
429 SPR_NOACCESS, SPR_NOACCESS,
430 &spr_read_generic, SPR_NOACCESS,
431 0x00000000);
432 spr_register(env, SPR_ICMP, "ICMP",
433 SPR_NOACCESS, SPR_NOACCESS,
434 &spr_read_generic, SPR_NOACCESS,
435 0x00000000);
436 spr_register(env, SPR_RPA, "RPA",
437 SPR_NOACCESS, SPR_NOACCESS,
438 &spr_read_generic, &spr_write_generic,
439 0x00000000);
440 #endif
441 }
442
443 /* SPR common to MPC755 and G2 */
444 static void register_G2_755_sprs(CPUPPCState *env)
445 {
446 /* SGPRs */
447 spr_register(env, SPR_SPRG4, "SPRG4",
448 SPR_NOACCESS, SPR_NOACCESS,
449 &spr_read_generic, &spr_write_generic,
450 0x00000000);
451 spr_register(env, SPR_SPRG5, "SPRG5",
452 SPR_NOACCESS, SPR_NOACCESS,
453 &spr_read_generic, &spr_write_generic,
454 0x00000000);
455 spr_register(env, SPR_SPRG6, "SPRG6",
456 SPR_NOACCESS, SPR_NOACCESS,
457 &spr_read_generic, &spr_write_generic,
458 0x00000000);
459 spr_register(env, SPR_SPRG7, "SPRG7",
460 SPR_NOACCESS, SPR_NOACCESS,
461 &spr_read_generic, &spr_write_generic,
462 0x00000000);
463 }
464
465 /* SPR common to all 7xx PowerPC implementations */
466 static void register_7xx_sprs(CPUPPCState *env)
467 {
468 /* Breakpoints */
469 /* XXX : not implemented */
470 spr_register_kvm(env, SPR_DABR, "DABR",
471 SPR_NOACCESS, SPR_NOACCESS,
472 &spr_read_generic, &spr_write_generic,
473 KVM_REG_PPC_DABR, 0x00000000);
474 /* XXX : not implemented */
475 spr_register(env, SPR_IABR, "IABR",
476 SPR_NOACCESS, SPR_NOACCESS,
477 &spr_read_generic, &spr_write_generic,
478 0x00000000);
479 /* Cache management */
480 /* XXX : not implemented */
481 spr_register(env, SPR_ICTC, "ICTC",
482 SPR_NOACCESS, SPR_NOACCESS,
483 &spr_read_generic, &spr_write_generic,
484 0x00000000);
485 /* Performance monitors */
486 /* XXX : not implemented */
487 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
488 SPR_NOACCESS, SPR_NOACCESS,
489 &spr_read_generic, &spr_write_generic,
490 0x00000000);
491 /* XXX : not implemented */
492 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
493 SPR_NOACCESS, SPR_NOACCESS,
494 &spr_read_generic, &spr_write_generic,
495 0x00000000);
496 /* XXX : not implemented */
497 spr_register(env, SPR_7XX_PMC1, "PMC1",
498 SPR_NOACCESS, SPR_NOACCESS,
499 &spr_read_generic, &spr_write_generic,
500 0x00000000);
501 /* XXX : not implemented */
502 spr_register(env, SPR_7XX_PMC2, "PMC2",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
505 0x00000000);
506 /* XXX : not implemented */
507 spr_register(env, SPR_7XX_PMC3, "PMC3",
508 SPR_NOACCESS, SPR_NOACCESS,
509 &spr_read_generic, &spr_write_generic,
510 0x00000000);
511 /* XXX : not implemented */
512 spr_register(env, SPR_7XX_PMC4, "PMC4",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_generic, &spr_write_generic,
515 0x00000000);
516 /* XXX : not implemented */
517 spr_register(env, SPR_7XX_SIAR, "SIAR",
518 SPR_NOACCESS, SPR_NOACCESS,
519 &spr_read_generic, SPR_NOACCESS,
520 0x00000000);
521 /* XXX : not implemented */
522 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
523 &spr_read_ureg, SPR_NOACCESS,
524 &spr_read_ureg, SPR_NOACCESS,
525 0x00000000);
526 /* XXX : not implemented */
527 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
528 &spr_read_ureg, SPR_NOACCESS,
529 &spr_read_ureg, SPR_NOACCESS,
530 0x00000000);
531 /* XXX : not implemented */
532 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
533 &spr_read_ureg, SPR_NOACCESS,
534 &spr_read_ureg, SPR_NOACCESS,
535 0x00000000);
536 /* XXX : not implemented */
537 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
538 &spr_read_ureg, SPR_NOACCESS,
539 &spr_read_ureg, SPR_NOACCESS,
540 0x00000000);
541 /* XXX : not implemented */
542 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
543 &spr_read_ureg, SPR_NOACCESS,
544 &spr_read_ureg, SPR_NOACCESS,
545 0x00000000);
546 /* XXX : not implemented */
547 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
548 &spr_read_ureg, SPR_NOACCESS,
549 &spr_read_ureg, SPR_NOACCESS,
550 0x00000000);
551 /* XXX : not implemented */
552 spr_register(env, SPR_7XX_USIAR, "USIAR",
553 &spr_read_ureg, SPR_NOACCESS,
554 &spr_read_ureg, SPR_NOACCESS,
555 0x00000000);
556 /* External access control */
557 /* XXX : not implemented */
558 spr_register(env, SPR_EAR, "EAR",
559 SPR_NOACCESS, SPR_NOACCESS,
560 &spr_read_generic, &spr_write_generic,
561 0x00000000);
562 }
563
564 #ifdef TARGET_PPC64
565 static void register_amr_sprs(CPUPPCState *env)
566 {
567 #ifndef CONFIG_USER_ONLY
568 /*
569 * Virtual Page Class Key protection
570 *
571 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
572 * userspace accessible, 29 is privileged. So we only need to set
573 * the kvm ONE_REG id on one of them, we use 29
574 */
575 spr_register(env, SPR_UAMR, "UAMR",
576 &spr_read_generic, &spr_write_amr,
577 &spr_read_generic, &spr_write_amr,
578 0);
579 spr_register_kvm_hv(env, SPR_AMR, "AMR",
580 SPR_NOACCESS, SPR_NOACCESS,
581 &spr_read_generic, &spr_write_amr,
582 &spr_read_generic, &spr_write_generic,
583 KVM_REG_PPC_AMR, 0);
584 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
585 SPR_NOACCESS, SPR_NOACCESS,
586 &spr_read_generic, &spr_write_uamor,
587 &spr_read_generic, &spr_write_generic,
588 KVM_REG_PPC_UAMOR, 0);
589 spr_register_hv(env, SPR_AMOR, "AMOR",
590 SPR_NOACCESS, SPR_NOACCESS,
591 SPR_NOACCESS, SPR_NOACCESS,
592 &spr_read_generic, &spr_write_generic,
593 0);
594 #endif /* !CONFIG_USER_ONLY */
595 }
596
597 static void register_iamr_sprs(CPUPPCState *env)
598 {
599 #ifndef CONFIG_USER_ONLY
600 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
601 SPR_NOACCESS, SPR_NOACCESS,
602 &spr_read_generic, &spr_write_iamr,
603 &spr_read_generic, &spr_write_generic,
604 KVM_REG_PPC_IAMR, 0);
605 #endif /* !CONFIG_USER_ONLY */
606 }
607 #endif /* TARGET_PPC64 */
608
609 static void register_thrm_sprs(CPUPPCState *env)
610 {
611 /* Thermal management */
612 /* XXX : not implemented */
613 spr_register(env, SPR_THRM1, "THRM1",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_thrm, &spr_write_generic,
616 0x00000000);
617 /* XXX : not implemented */
618 spr_register(env, SPR_THRM2, "THRM2",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_thrm, &spr_write_generic,
621 0x00000000);
622 /* XXX : not implemented */
623 spr_register(env, SPR_THRM3, "THRM3",
624 SPR_NOACCESS, SPR_NOACCESS,
625 &spr_read_thrm, &spr_write_generic,
626 0x00000000);
627 }
628
629 /* SPR specific to PowerPC 604 implementation */
630 static void register_604_sprs(CPUPPCState *env)
631 {
632 /* Processor identification */
633 spr_register(env, SPR_PIR, "PIR",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_generic, &spr_write_pir,
636 0x00000000);
637 /* Breakpoints */
638 /* XXX : not implemented */
639 spr_register(env, SPR_IABR, "IABR",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_generic, &spr_write_generic,
642 0x00000000);
643 /* XXX : not implemented */
644 spr_register_kvm(env, SPR_DABR, "DABR",
645 SPR_NOACCESS, SPR_NOACCESS,
646 &spr_read_generic, &spr_write_generic,
647 KVM_REG_PPC_DABR, 0x00000000);
648 /* Performance counters */
649 /* XXX : not implemented */
650 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 /* XXX : not implemented */
655 spr_register(env, SPR_7XX_PMC1, "PMC1",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 /* XXX : not implemented */
660 spr_register(env, SPR_7XX_PMC2, "PMC2",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_generic, &spr_write_generic,
663 0x00000000);
664 /* XXX : not implemented */
665 spr_register(env, SPR_7XX_SIAR, "SIAR",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_generic, SPR_NOACCESS,
668 0x00000000);
669 /* XXX : not implemented */
670 spr_register(env, SPR_SDA, "SDA",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_generic, SPR_NOACCESS,
673 0x00000000);
674 /* External access control */
675 /* XXX : not implemented */
676 spr_register(env, SPR_EAR, "EAR",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 }
681
682 /* SPR specific to PowerPC 603 implementation */
683 static void register_603_sprs(CPUPPCState *env)
684 {
685 /* External access control */
686 /* XXX : not implemented */
687 spr_register(env, SPR_EAR, "EAR",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_generic, &spr_write_generic,
690 0x00000000);
691 /* Breakpoints */
692 /* XXX : not implemented */
693 spr_register(env, SPR_IABR, "IABR",
694 SPR_NOACCESS, SPR_NOACCESS,
695 &spr_read_generic, &spr_write_generic,
696 0x00000000);
697
698 }
699
700 /* SPR specific to PowerPC G2 implementation */
701 static void register_G2_sprs(CPUPPCState *env)
702 {
703 /* Memory base address */
704 /* MBAR */
705 /* XXX : not implemented */
706 spr_register(env, SPR_MBAR, "MBAR",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_generic, &spr_write_generic,
709 0x00000000);
710 /* Exception processing */
711 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_generic, &spr_write_generic,
714 0x00000000);
715 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_generic, &spr_write_generic,
718 0x00000000);
719 /* Breakpoints */
720 /* XXX : not implemented */
721 spr_register(env, SPR_DABR, "DABR",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_generic, &spr_write_generic,
724 0x00000000);
725 /* XXX : not implemented */
726 spr_register(env, SPR_DABR2, "DABR2",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, &spr_write_generic,
729 0x00000000);
730 /* XXX : not implemented */
731 spr_register(env, SPR_IABR, "IABR",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_generic, &spr_write_generic,
734 0x00000000);
735 /* XXX : not implemented */
736 spr_register(env, SPR_IABR2, "IABR2",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, &spr_write_generic,
739 0x00000000);
740 /* XXX : not implemented */
741 spr_register(env, SPR_IBCR, "IBCR",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_generic, &spr_write_generic,
744 0x00000000);
745 /* XXX : not implemented */
746 spr_register(env, SPR_DBCR, "DBCR",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_generic, &spr_write_generic,
749 0x00000000);
750 }
751
752 static void register_74xx_sprs(CPUPPCState *env)
753 {
754 /* Processor identification */
755 spr_register(env, SPR_PIR, "PIR",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_generic, &spr_write_pir,
758 0x00000000);
759 /* XXX : not implemented */
760 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_generic, &spr_write_generic,
763 0x00000000);
764 /* XXX : not implemented */
765 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
766 &spr_read_ureg, SPR_NOACCESS,
767 &spr_read_ureg, SPR_NOACCESS,
768 0x00000000);
769 /* XXX: not implemented */
770 spr_register(env, SPR_BAMR, "BAMR",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_generic,
773 0x00000000);
774 /* XXX : not implemented */
775 spr_register(env, SPR_MSSCR0, "MSSCR0",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_generic,
778 0x00000000);
779 /* Hardware implementation registers */
780 /* XXX : not implemented */
781 spr_register(env, SPR_HID0, "HID0",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_generic, &spr_write_generic,
784 0x00000000);
785 /* XXX : not implemented */
786 spr_register(env, SPR_HID1, "HID1",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, &spr_write_generic,
789 0x00000000);
790 /* Altivec */
791 spr_register(env, SPR_VRSAVE, "VRSAVE",
792 &spr_read_generic, &spr_write_generic,
793 &spr_read_generic, &spr_write_generic,
794 0x00000000);
795 /* XXX : not implemented */
796 spr_register(env, SPR_L2CR, "L2CR",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_generic, spr_access_nop,
799 0x00000000);
800 }
801
802 static void register_l3_ctrl(CPUPPCState *env)
803 {
804 /* L3CR */
805 /* XXX : not implemented */
806 spr_register(env, SPR_L3CR, "L3CR",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
810 /* L3ITCR0 */
811 /* XXX : not implemented */
812 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816 /* L3PM */
817 /* XXX : not implemented */
818 spr_register(env, SPR_L3PM, "L3PM",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_generic, &spr_write_generic,
821 0x00000000);
822 }
823
824 static void register_usprg3_sprs(CPUPPCState *env)
825 {
826 spr_register(env, SPR_USPRG3, "USPRG3",
827 &spr_read_ureg, SPR_NOACCESS,
828 &spr_read_ureg, SPR_NOACCESS,
829 0x00000000);
830 }
831
832 static void register_usprgh_sprs(CPUPPCState *env)
833 {
834 spr_register(env, SPR_USPRG4, "USPRG4",
835 &spr_read_ureg, SPR_NOACCESS,
836 &spr_read_ureg, SPR_NOACCESS,
837 0x00000000);
838 spr_register(env, SPR_USPRG5, "USPRG5",
839 &spr_read_ureg, SPR_NOACCESS,
840 &spr_read_ureg, SPR_NOACCESS,
841 0x00000000);
842 spr_register(env, SPR_USPRG6, "USPRG6",
843 &spr_read_ureg, SPR_NOACCESS,
844 &spr_read_ureg, SPR_NOACCESS,
845 0x00000000);
846 spr_register(env, SPR_USPRG7, "USPRG7",
847 &spr_read_ureg, SPR_NOACCESS,
848 &spr_read_ureg, SPR_NOACCESS,
849 0x00000000);
850 }
851
852 /* PowerPC BookE SPR */
853 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
854 {
855 const char *ivor_names[64] = {
856 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
857 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
858 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
859 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
860 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
861 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
862 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
863 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
864 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
865 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
866 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
867 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
868 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
869 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
870 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
871 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
872 };
873 #define SPR_BOOKE_IVORxx (-1)
874 int ivor_sprn[64] = {
875 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
876 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
877 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
878 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
879 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
880 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
881 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
882 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
883 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
884 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
885 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
886 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
887 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
888 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
889 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
890 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
891 };
892 int i;
893
894 /* Interrupt processing */
895 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_generic,
898 0x00000000);
899 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, &spr_write_generic,
902 0x00000000);
903 /* Debug */
904 /* XXX : not implemented */
905 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 /* XXX : not implemented */
910 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 /* XXX : not implemented */
915 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
916 SPR_NOACCESS, SPR_NOACCESS,
917 &spr_read_generic, &spr_write_generic,
918 0x00000000);
919 /* XXX : not implemented */
920 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 0x00000000);
924 /* XXX : not implemented */
925 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
926 SPR_NOACCESS, SPR_NOACCESS,
927 &spr_read_generic, &spr_write_40x_dbcr0,
928 0x00000000);
929 /* XXX : not implemented */
930 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* XXX : not implemented */
935 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_clear,
951 0x00000000);
952 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, &spr_write_generic,
955 0x00000000);
956 spr_register(env, SPR_BOOKE_ESR, "ESR",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, &spr_write_generic,
959 0x00000000);
960 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_excp_prefix,
963 0x00000000);
964 /* Exception vectors */
965 for (i = 0; i < 64; i++) {
966 if (ivor_mask & (1ULL << i)) {
967 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
968 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
969 exit(1);
970 }
971 spr_register(env, ivor_sprn[i], ivor_names[i],
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_excp_vector,
974 0x00000000);
975 }
976 }
977 spr_register(env, SPR_BOOKE_PID, "PID",
978 SPR_NOACCESS, SPR_NOACCESS,
979 &spr_read_generic, &spr_write_booke_pid,
980 0x00000000);
981 spr_register(env, SPR_BOOKE_TCR, "TCR",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_booke_tcr,
984 0x00000000);
985 spr_register(env, SPR_BOOKE_TSR, "TSR",
986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_booke_tsr,
988 0x00000000);
989 /* Timer */
990 spr_register(env, SPR_DECR, "DECR",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_decr, &spr_write_decr,
993 0x00000000);
994 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
995 SPR_NOACCESS, SPR_NOACCESS,
996 SPR_NOACCESS, &spr_write_generic,
997 0x00000000);
998 /* SPRGs */
999 spr_register(env, SPR_USPRG0, "USPRG0",
1000 &spr_read_generic, &spr_write_generic,
1001 &spr_read_generic, &spr_write_generic,
1002 0x00000000);
1003 spr_register(env, SPR_SPRG4, "SPRG4",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 spr_register(env, SPR_SPRG5, "SPRG5",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011 spr_register(env, SPR_SPRG6, "SPRG6",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_generic,
1014 0x00000000);
1015 spr_register(env, SPR_SPRG7, "SPRG7",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, &spr_write_generic,
1022 0x00000000);
1023 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, &spr_write_generic,
1026 0x00000000);
1027 }
1028
1029 #if !defined(CONFIG_USER_ONLY)
1030 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1031 uint32_t maxsize, uint32_t flags,
1032 uint32_t nentries)
1033 {
1034 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1035 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1036 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1037 flags | nentries;
1038 }
1039 #endif /* !CONFIG_USER_ONLY */
1040
1041 /* BookE 2.06 storage control registers */
1042 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1043 uint32_t *tlbncfg, uint32_t mmucfg)
1044 {
1045 #if !defined(CONFIG_USER_ONLY)
1046 const char *mas_names[8] = {
1047 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1048 };
1049 int mas_sprn[8] = {
1050 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1051 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1052 };
1053 int i;
1054
1055 /* TLB assist registers */
1056 /* XXX : not implemented */
1057 for (i = 0; i < 8; i++) {
1058 if (mas_mask & (1 << i)) {
1059 spr_register(env, mas_sprn[i], mas_names[i],
1060 SPR_NOACCESS, SPR_NOACCESS,
1061 &spr_read_generic,
1062 (i == 2 && (env->insns_flags & PPC_64B))
1063 ? &spr_write_generic : &spr_write_generic32,
1064 0x00000000);
1065 }
1066 }
1067 if (env->nb_pids > 1) {
1068 /* XXX : not implemented */
1069 spr_register(env, SPR_BOOKE_PID1, "PID1",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_booke_pid,
1072 0x00000000);
1073 }
1074 if (env->nb_pids > 2) {
1075 /* XXX : not implemented */
1076 spr_register(env, SPR_BOOKE_PID2, "PID2",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, &spr_write_booke_pid,
1079 0x00000000);
1080 }
1081
1082 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_eplc,
1085 0x00000000);
1086 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1087 SPR_NOACCESS, SPR_NOACCESS,
1088 &spr_read_generic, &spr_write_epsc,
1089 0x00000000);
1090
1091 /* XXX : not implemented */
1092 spr_register(env, SPR_MMUCFG, "MMUCFG",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, SPR_NOACCESS,
1095 mmucfg);
1096 switch (env->nb_ways) {
1097 case 4:
1098 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, SPR_NOACCESS,
1101 tlbncfg[3]);
1102 /* Fallthru */
1103 case 3:
1104 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1105 SPR_NOACCESS, SPR_NOACCESS,
1106 &spr_read_generic, SPR_NOACCESS,
1107 tlbncfg[2]);
1108 /* Fallthru */
1109 case 2:
1110 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, SPR_NOACCESS,
1113 tlbncfg[1]);
1114 /* Fallthru */
1115 case 1:
1116 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, SPR_NOACCESS,
1119 tlbncfg[0]);
1120 /* Fallthru */
1121 case 0:
1122 default:
1123 break;
1124 }
1125 #endif
1126
1127 register_usprgh_sprs(env);
1128 }
1129
1130 /* SPR specific to PowerPC 440 implementation */
1131 static void register_440_sprs(CPUPPCState *env)
1132 {
1133 /* Cache control */
1134 /* XXX : not implemented */
1135 spr_register(env, SPR_440_DNV0, "DNV0",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, &spr_write_generic,
1138 0x00000000);
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_440_DNV1, "DNV1",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, &spr_write_generic,
1143 0x00000000);
1144 /* XXX : not implemented */
1145 spr_register(env, SPR_440_DNV2, "DNV2",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_generic, &spr_write_generic,
1148 0x00000000);
1149 /* XXX : not implemented */
1150 spr_register(env, SPR_440_DNV3, "DNV3",
1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, &spr_write_generic,
1153 0x00000000);
1154 /* XXX : not implemented */
1155 spr_register(env, SPR_440_DTV0, "DTV0",
1156 SPR_NOACCESS, SPR_NOACCESS,
1157 &spr_read_generic, &spr_write_generic,
1158 0x00000000);
1159 /* XXX : not implemented */
1160 spr_register(env, SPR_440_DTV1, "DTV1",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
1164 /* XXX : not implemented */
1165 spr_register(env, SPR_440_DTV2, "DTV2",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_generic, &spr_write_generic,
1168 0x00000000);
1169 /* XXX : not implemented */
1170 spr_register(env, SPR_440_DTV3, "DTV3",
1171 SPR_NOACCESS, SPR_NOACCESS,
1172 &spr_read_generic, &spr_write_generic,
1173 0x00000000);
1174 /* XXX : not implemented */
1175 spr_register(env, SPR_440_DVLIM, "DVLIM",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
1179 /* XXX : not implemented */
1180 spr_register(env, SPR_440_INV0, "INV0",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184 /* XXX : not implemented */
1185 spr_register(env, SPR_440_INV1, "INV1",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* XXX : not implemented */
1190 spr_register(env, SPR_440_INV2, "INV2",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* XXX : not implemented */
1195 spr_register(env, SPR_440_INV3, "INV3",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_440_ITV0, "ITV0",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204 /* XXX : not implemented */
1205 spr_register(env, SPR_440_ITV1, "ITV1",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 /* XXX : not implemented */
1210 spr_register(env, SPR_440_ITV2, "ITV2",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_generic,
1213 0x00000000);
1214 /* XXX : not implemented */
1215 spr_register(env, SPR_440_ITV3, "ITV3",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_generic,
1218 0x00000000);
1219 /* XXX : not implemented */
1220 spr_register(env, SPR_440_IVLIM, "IVLIM",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* Cache debug */
1225 /* XXX : not implemented */
1226 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, SPR_NOACCESS,
1229 0x00000000);
1230 /* XXX : not implemented */
1231 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_generic, SPR_NOACCESS,
1234 0x00000000);
1235 /* XXX : not implemented */
1236 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, SPR_NOACCESS,
1239 0x00000000);
1240 /* XXX : not implemented */
1241 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, SPR_NOACCESS,
1244 0x00000000);
1245 /* XXX : not implemented */
1246 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_generic, SPR_NOACCESS,
1249 0x00000000);
1250 /* XXX : not implemented */
1251 spr_register(env, SPR_440_DBDR, "DBDR",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1254 0x00000000);
1255 /* Processor control */
1256 spr_register(env, SPR_4xx_CCR0, "CCR0",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_generic, &spr_write_generic,
1259 0x00000000);
1260 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, SPR_NOACCESS,
1263 0x00000000);
1264 /* Storage control */
1265 spr_register(env, SPR_440_MMUCR, "MMUCR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 0x00000000);
1269 }
1270
1271 /* SPR shared between PowerPC 40x implementations */
1272 static void register_40x_sprs(CPUPPCState *env)
1273 {
1274 /* Cache */
1275 /* not emulated, as QEMU do not emulate caches */
1276 spr_register(env, SPR_40x_DCCR, "DCCR",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1279 0x00000000);
1280 /* not emulated, as QEMU do not emulate caches */
1281 spr_register(env, SPR_40x_ICCR, "ICCR",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
1285 /* not emulated, as QEMU do not emulate caches */
1286 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, SPR_NOACCESS,
1289 0x00000000);
1290 /* Exception */
1291 spr_register(env, SPR_40x_DEAR, "DEAR",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 spr_register(env, SPR_40x_ESR, "ESR",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 spr_register(env, SPR_40x_EVPR, "EVPR",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_excp_prefix,
1302 0x00000000);
1303 spr_register(env, SPR_40x_SRR2, "SRR2",
1304 &spr_read_generic, &spr_write_generic,
1305 &spr_read_generic, &spr_write_generic,
1306 0x00000000);
1307 spr_register(env, SPR_40x_SRR3, "SRR3",
1308 &spr_read_generic, &spr_write_generic,
1309 &spr_read_generic, &spr_write_generic,
1310 0x00000000);
1311 /* Timers */
1312 spr_register(env, SPR_40x_PIT, "PIT",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_40x_pit, &spr_write_40x_pit,
1315 0x00000000);
1316 spr_register(env, SPR_40x_TCR, "TCR",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_40x_tcr,
1319 0x00000000);
1320 spr_register(env, SPR_40x_TSR, "TSR",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_40x_tsr,
1323 0x00000000);
1324 }
1325
1326 /* SPR specific to PowerPC 405 implementation */
1327 static void register_405_sprs(CPUPPCState *env)
1328 {
1329 /* MMU */
1330 spr_register(env, SPR_40x_PID, "PID",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_40x_pid,
1333 0x00000000);
1334 spr_register(env, SPR_4xx_CCR0, "CCR0",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00700000);
1338 /* Debug interface */
1339 /* XXX : not implemented */
1340 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_40x_dbcr0,
1343 0x00000000);
1344 /* XXX : not implemented */
1345 spr_register(env, SPR_405_DBCR1, "DBCR1",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_40x_DBSR, "DBSR",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_clear,
1353 /* Last reset was system reset */
1354 0x00000300);
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_40x_DAC1, "DAC1",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 spr_register(env, SPR_40x_DAC2, "DAC2",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_405_DVC1, "DVC1",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_405_DVC2, "DVC2",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_40x_IAC1, "IAC1",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 spr_register(env, SPR_40x_IAC2, "IAC2",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383 /* XXX : not implemented */
1384 spr_register(env, SPR_405_IAC3, "IAC3",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388 /* XXX : not implemented */
1389 spr_register(env, SPR_405_IAC4, "IAC4",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393 /* Storage control */
1394 /* XXX: TODO: not implemented */
1395 spr_register(env, SPR_405_SLER, "SLER",
1396 SPR_NOACCESS, SPR_NOACCESS,
1397 &spr_read_generic, &spr_write_40x_sler,
1398 0x00000000);
1399 spr_register(env, SPR_40x_ZPR, "ZPR",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403 /* XXX : not implemented */
1404 spr_register(env, SPR_405_SU0R, "SU0R",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_generic,
1407 0x00000000);
1408 /* SPRG */
1409 spr_register(env, SPR_USPRG0, "USPRG0",
1410 &spr_read_ureg, SPR_NOACCESS,
1411 &spr_read_ureg, SPR_NOACCESS,
1412 0x00000000);
1413 spr_register(env, SPR_SPRG4, "SPRG4",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 spr_register(env, SPR_SPRG5, "SPRG5",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 spr_read_generic, &spr_write_generic,
1420 0x00000000);
1421 spr_register(env, SPR_SPRG6, "SPRG6",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 spr_read_generic, &spr_write_generic,
1424 0x00000000);
1425 spr_register(env, SPR_SPRG7, "SPRG7",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 spr_read_generic, &spr_write_generic,
1428 0x00000000);
1429 register_usprgh_sprs(env);
1430 }
1431
1432
1433 static void register_5xx_8xx_sprs(CPUPPCState *env)
1434 {
1435 /* Exception processing */
1436 spr_register_kvm(env, SPR_DSISR, "DSISR",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, &spr_write_generic,
1439 KVM_REG_PPC_DSISR, 0x00000000);
1440 spr_register_kvm(env, SPR_DAR, "DAR",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_generic,
1443 KVM_REG_PPC_DAR, 0x00000000);
1444 /* Timer */
1445 spr_register(env, SPR_DECR, "DECR",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 &spr_read_decr, &spr_write_decr,
1448 0x00000000);
1449 /* XXX : not implemented */
1450 spr_register(env, SPR_MPC_EIE, "EIE",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_generic,
1453 0x00000000);
1454 /* XXX : not implemented */
1455 spr_register(env, SPR_MPC_EID, "EID",
1456 SPR_NOACCESS, SPR_NOACCESS,
1457 &spr_read_generic, &spr_write_generic,
1458 0x00000000);
1459 /* XXX : not implemented */
1460 spr_register(env, SPR_MPC_NRI, "NRI",
1461 SPR_NOACCESS, SPR_NOACCESS,
1462 &spr_read_generic, &spr_write_generic,
1463 0x00000000);
1464 /* XXX : not implemented */
1465 spr_register(env, SPR_MPC_CMPA, "CMPA",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_generic, &spr_write_generic,
1468 0x00000000);
1469 /* XXX : not implemented */
1470 spr_register(env, SPR_MPC_CMPB, "CMPB",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 /* XXX : not implemented */
1475 spr_register(env, SPR_MPC_CMPC, "CMPC",
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_generic, &spr_write_generic,
1478 0x00000000);
1479 /* XXX : not implemented */
1480 spr_register(env, SPR_MPC_CMPD, "CMPD",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_generic,
1483 0x00000000);
1484 /* XXX : not implemented */
1485 spr_register(env, SPR_MPC_ECR, "ECR",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 /* XXX : not implemented */
1490 spr_register(env, SPR_MPC_DER, "DER",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494 /* XXX : not implemented */
1495 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 /* XXX : not implemented */
1500 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, &spr_write_generic,
1503 0x00000000);
1504 /* XXX : not implemented */
1505 spr_register(env, SPR_MPC_CMPE, "CMPE",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 /* XXX : not implemented */
1510 spr_register(env, SPR_MPC_CMPF, "CMPF",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, &spr_write_generic,
1513 0x00000000);
1514 /* XXX : not implemented */
1515 spr_register(env, SPR_MPC_CMPG, "CMPG",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, &spr_write_generic,
1518 0x00000000);
1519 /* XXX : not implemented */
1520 spr_register(env, SPR_MPC_CMPH, "CMPH",
1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_generic,
1523 0x00000000);
1524 /* XXX : not implemented */
1525 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1526 SPR_NOACCESS, SPR_NOACCESS,
1527 &spr_read_generic, &spr_write_generic,
1528 0x00000000);
1529 /* XXX : not implemented */
1530 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_generic,
1533 0x00000000);
1534 /* XXX : not implemented */
1535 spr_register(env, SPR_MPC_BAR, "BAR",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539 /* XXX : not implemented */
1540 spr_register(env, SPR_MPC_DPDR, "DPDR",
1541 SPR_NOACCESS, SPR_NOACCESS,
1542 &spr_read_generic, &spr_write_generic,
1543 0x00000000);
1544 /* XXX : not implemented */
1545 spr_register(env, SPR_MPC_IMMR, "IMMR",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 }
1550
1551 static void register_5xx_sprs(CPUPPCState *env)
1552 {
1553 /* XXX : not implemented */
1554 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
1558 /* XXX : not implemented */
1559 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 /* XXX : not implemented */
1564 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568 /* XXX : not implemented */
1569 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 /* XXX : not implemented */
1579 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
1583 /* XXX : not implemented */
1584 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, &spr_write_generic,
1587 0x00000000);
1588 /* XXX : not implemented */
1589 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_generic,
1592 0x00000000);
1593 /* XXX : not implemented */
1594 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 /* XXX : not implemented */
1599 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_generic,
1602 0x00000000);
1603 /* XXX : not implemented */
1604 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_generic,
1607 0x00000000);
1608 /* XXX : not implemented */
1609 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_generic,
1612 0x00000000);
1613 /* XXX : not implemented */
1614 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, &spr_write_generic,
1617 0x00000000);
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_generic,
1622 0x00000000);
1623 /* XXX : not implemented */
1624 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 /* XXX : not implemented */
1629 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, &spr_write_generic,
1632 0x00000000);
1633 /* XXX : not implemented */
1634 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 /* XXX : not implemented */
1639 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, &spr_write_generic,
1642 0x00000000);
1643 /* XXX : not implemented */
1644 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_generic,
1647 0x00000000);
1648 /* XXX : not implemented */
1649 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1650 SPR_NOACCESS, SPR_NOACCESS,
1651 &spr_read_generic, &spr_write_generic,
1652 0x00000000);
1653 /* XXX : not implemented */
1654 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, &spr_write_generic,
1657 0x00000000);
1658 }
1659
1660 static void register_8xx_sprs(CPUPPCState *env)
1661 {
1662 /* XXX : not implemented */
1663 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 /* XXX : not implemented */
1668 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* XXX : not implemented */
1773 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
1778 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 /* XXX : not implemented */
1783 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 }
1788
1789 /*
1790 * AMR => SPR 29 (Power 2.04)
1791 * CTRL => SPR 136 (Power 2.04)
1792 * CTRL => SPR 152 (Power 2.04)
1793 * SCOMC => SPR 276 (64 bits ?)
1794 * SCOMD => SPR 277 (64 bits ?)
1795 * TBU40 => SPR 286 (Power 2.04 hypv)
1796 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1797 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1798 * HDSISR => SPR 306 (Power 2.04 hypv)
1799 * HDAR => SPR 307 (Power 2.04 hypv)
1800 * PURR => SPR 309 (Power 2.04 hypv)
1801 * HDEC => SPR 310 (Power 2.04 hypv)
1802 * HIOR => SPR 311 (hypv)
1803 * RMOR => SPR 312 (970)
1804 * HRMOR => SPR 313 (Power 2.04 hypv)
1805 * HSRR0 => SPR 314 (Power 2.04 hypv)
1806 * HSRR1 => SPR 315 (Power 2.04 hypv)
1807 * LPIDR => SPR 317 (970)
1808 * EPR => SPR 702 (Power 2.04 emb)
1809 * perf => 768-783 (Power 2.04)
1810 * perf => 784-799 (Power 2.04)
1811 * PPR => SPR 896 (Power 2.04)
1812 * DABRX => 1015 (Power 2.04 hypv)
1813 * FPECR => SPR 1022 (?)
1814 * ... and more (thermal management, performance counters, ...)
1815 */
1816
1817 /*****************************************************************************/
1818 /* Exception vectors models */
1819 static void init_excp_4xx_softmmu(CPUPPCState *env)
1820 {
1821 #if !defined(CONFIG_USER_ONLY)
1822 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1823 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1824 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1825 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1826 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1827 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1828 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1829 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1830 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1831 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1832 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1833 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1834 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1835 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1836 env->ivor_mask = 0x0000FFF0UL;
1837 env->ivpr_mask = 0xFFFF0000UL;
1838 /* Hardware reset vector */
1839 env->hreset_vector = 0xFFFFFFFCUL;
1840 #endif
1841 }
1842
1843 static void init_excp_MPC5xx(CPUPPCState *env)
1844 {
1845 #if !defined(CONFIG_USER_ONLY)
1846 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1847 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1848 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1849 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1850 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1851 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1852 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1853 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1854 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1855 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1856 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1857 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1858 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1859 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1860 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1861 env->ivor_mask = 0x0000FFF0UL;
1862 env->ivpr_mask = 0xFFFF0000UL;
1863 /* Hardware reset vector */
1864 env->hreset_vector = 0x00000100UL;
1865 #endif
1866 }
1867
1868 static void init_excp_MPC8xx(CPUPPCState *env)
1869 {
1870 #if !defined(CONFIG_USER_ONLY)
1871 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1872 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1873 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1874 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1875 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1876 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1877 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1878 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1879 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1880 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1881 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1882 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1883 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1884 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1885 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1886 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1887 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1888 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1889 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1890 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1891 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1892 env->ivor_mask = 0x0000FFF0UL;
1893 env->ivpr_mask = 0xFFFF0000UL;
1894 /* Hardware reset vector */
1895 env->hreset_vector = 0x00000100UL;
1896 #endif
1897 }
1898
1899 static void init_excp_G2(CPUPPCState *env)
1900 {
1901 #if !defined(CONFIG_USER_ONLY)
1902 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1903 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1904 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1905 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1906 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1907 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1908 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1909 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1910 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1911 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1912 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1913 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1914 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1915 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1916 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1917 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1918 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1919 /* Hardware reset vector */
1920 env->hreset_vector = 0x00000100UL;
1921 #endif
1922 }
1923
1924 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
1925 {
1926 #if !defined(CONFIG_USER_ONLY)
1927 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1928 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1929 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1930 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1931 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1932 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1933 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1934 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1935 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1936 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1937 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1938 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1939 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1940 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1941 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1942 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1943 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1944 /*
1945 * These two are the same IVOR as POWERPC_EXCP_VPU and
1946 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1947 * powerpc_excp().
1948 */
1949 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1950 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1951
1952 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1953 env->ivor_mask = 0x0000FFF7UL;
1954 env->ivpr_mask = ivpr_mask;
1955 /* Hardware reset vector */
1956 env->hreset_vector = 0xFFFFFFFCUL;
1957 #endif
1958 }
1959
1960 static void init_excp_BookE(CPUPPCState *env)
1961 {
1962 #if !defined(CONFIG_USER_ONLY)
1963 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1964 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1965 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1966 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1967 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1968 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1969 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1970 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1971 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1972 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1973 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1974 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1975 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1976 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1977 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1978 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1979 env->ivor_mask = 0x0000FFF0UL;
1980 env->ivpr_mask = 0xFFFF0000UL;
1981 /* Hardware reset vector */
1982 env->hreset_vector = 0xFFFFFFFCUL;
1983 #endif
1984 }
1985
1986 static void init_excp_603(CPUPPCState *env)
1987 {
1988 #if !defined(CONFIG_USER_ONLY)
1989 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1990 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1991 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1992 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1993 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1994 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1995 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1996 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1997 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1998 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1999 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2000 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2001 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2002 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2003 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2004 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2005 /* Hardware reset vector */
2006 env->hreset_vector = 0x00000100UL;
2007 #endif
2008 }
2009
2010 static void init_excp_604(CPUPPCState *env)
2011 {
2012 #if !defined(CONFIG_USER_ONLY)
2013 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2014 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2015 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2016 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2017 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2018 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2019 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2020 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2021 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2022 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2023 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2024 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2025 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2026 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2027 /* Hardware reset vector */
2028 env->hreset_vector = 0x00000100UL;
2029 #endif
2030 }
2031
2032 static void init_excp_7x0(CPUPPCState *env)
2033 {
2034 #if !defined(CONFIG_USER_ONLY)
2035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2038 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2039 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2040 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2041 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2042 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2043 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2044 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2045 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2046 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2047 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2048 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2049 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2050 /* Hardware reset vector */
2051 env->hreset_vector = 0x00000100UL;
2052 #endif
2053 }
2054
2055 static void init_excp_750cl(CPUPPCState *env)
2056 {
2057 #if !defined(CONFIG_USER_ONLY)
2058 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2059 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2060 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2061 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2062 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2063 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2064 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2065 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2066 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2067 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2068 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2069 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2070 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2071 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2072 /* Hardware reset vector */
2073 env->hreset_vector = 0x00000100UL;
2074 #endif
2075 }
2076
2077 static void init_excp_750cx(CPUPPCState *env)
2078 {
2079 #if !defined(CONFIG_USER_ONLY)
2080 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2081 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2082 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2083 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2084 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2085 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2086 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2087 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2088 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2089 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2090 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2091 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2092 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2093 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2094 /* Hardware reset vector */
2095 env->hreset_vector = 0x00000100UL;
2096 #endif
2097 }
2098
2099 /* XXX: Check if this is correct */
2100 static void init_excp_7x5(CPUPPCState *env)
2101 {
2102 #if !defined(CONFIG_USER_ONLY)
2103 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2104 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2105 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2106 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2107 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2108 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2109 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2110 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2111 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2112 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2113 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2114 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2115 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2116 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2117 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2118 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2119 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2120 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2121 /* Hardware reset vector */
2122 env->hreset_vector = 0x00000100UL;
2123 #endif
2124 }
2125
2126 static void init_excp_7400(CPUPPCState *env)
2127 {
2128 #if !defined(CONFIG_USER_ONLY)
2129 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2130 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2131 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2132 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2133 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2134 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2135 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2136 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2137 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2138 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2139 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2140 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2141 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2142 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2143 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2144 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2145 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2146 /* Hardware reset vector */
2147 env->hreset_vector = 0x00000100UL;
2148 #endif
2149 }
2150
2151 static void init_excp_7450(CPUPPCState *env)
2152 {
2153 #if !defined(CONFIG_USER_ONLY)
2154 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2155 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2156 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2157 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2158 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2159 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2160 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2161 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2162 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2163 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2164 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2165 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2166 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2167 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2168 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2169 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2170 /* Hardware reset vector */
2171 env->hreset_vector = 0x00000100UL;
2172 #endif
2173 }
2174
2175 #if defined(TARGET_PPC64)
2176 static void init_excp_970(CPUPPCState *env)
2177 {
2178 #if !defined(CONFIG_USER_ONLY)
2179 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2180 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2181 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2182 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2183 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2184 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2185 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2186 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2187 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2188 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2189 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2190 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2191 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2192 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2193 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2194 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2195 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2196 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2197 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2198 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2199 /* Hardware reset vector */
2200 env->hreset_vector = 0x0000000000000100ULL;
2201 #endif
2202 }
2203
2204 static void init_excp_POWER7(CPUPPCState *env)
2205 {
2206 #if !defined(CONFIG_USER_ONLY)
2207 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2208 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2209 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2210 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2211 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2212 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2213 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2214 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2215 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2216 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2217 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2218 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2219 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2220 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2221 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2222 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2223 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2224 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2225 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2226 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2227 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2228 /* Hardware reset vector */
2229 env->hreset_vector = 0x0000000000000100ULL;
2230 #endif
2231 }
2232
2233 static void init_excp_POWER8(CPUPPCState *env)
2234 {
2235 init_excp_POWER7(env);
2236
2237 #if !defined(CONFIG_USER_ONLY)
2238 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2239 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2240 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2241 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2242 #endif
2243 }
2244
2245 static void init_excp_POWER9(CPUPPCState *env)
2246 {
2247 init_excp_POWER8(env);
2248
2249 #if !defined(CONFIG_USER_ONLY)
2250 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2251 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2252 #endif
2253 }
2254
2255 static void init_excp_POWER10(CPUPPCState *env)
2256 {
2257 init_excp_POWER9(env);
2258 }
2259
2260 #endif
2261
2262 /*****************************************************************************/
2263 /* Power management enable checks */
2264 static int check_pow_none(CPUPPCState *env)
2265 {
2266 return 0;
2267 }
2268
2269 static int check_pow_nocheck(CPUPPCState *env)
2270 {
2271 return 1;
2272 }
2273
2274 static int check_pow_hid0(CPUPPCState *env)
2275 {
2276 if (env->spr[SPR_HID0] & 0x00E00000) {
2277 return 1;
2278 }
2279
2280 return 0;
2281 }
2282
2283 static int check_pow_hid0_74xx(CPUPPCState *env)
2284 {
2285 if (env->spr[SPR_HID0] & 0x00600000) {
2286 return 1;
2287 }
2288
2289 return 0;
2290 }
2291
2292 /*****************************************************************************/
2293 /* PowerPC implementations definitions */
2294
2295 #define POWERPC_FAMILY(_name) \
2296 static void \
2297 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2298 \
2299 static const TypeInfo \
2300 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2301 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2302 .parent = TYPE_POWERPC_CPU, \
2303 .abstract = true, \
2304 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2305 }; \
2306 \
2307 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2308 { \
2309 type_register_static( \
2310 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2311 } \
2312 \
2313 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2314 \
2315 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2316
2317 static void init_proc_405(CPUPPCState *env)
2318 {
2319 /* Time base */
2320 register_tbl(env);
2321 register_40x_sprs(env);
2322 register_405_sprs(env);
2323 /* Bus access control */
2324 /* not emulated, as QEMU never does speculative access */
2325 spr_register(env, SPR_40x_SGR, "SGR",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_generic, &spr_write_generic,
2328 0xFFFFFFFF);
2329 /* not emulated, as QEMU do not emulate caches */
2330 spr_register(env, SPR_40x_DCWR, "DCWR",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 /* Memory management */
2335 #if !defined(CONFIG_USER_ONLY)
2336 env->nb_tlb = 64;
2337 env->nb_ways = 1;
2338 env->id_tlbs = 0;
2339 env->tlb_type = TLB_EMB;
2340 #endif
2341 init_excp_4xx_softmmu(env);
2342 env->dcache_line_size = 32;
2343 env->icache_line_size = 32;
2344 /* Allocate hardware IRQ controller */
2345 ppc40x_irq_init(env_archcpu(env));
2346
2347 SET_FIT_PERIOD(8, 12, 16, 20);
2348 SET_WDT_PERIOD(16, 20, 24, 28);
2349 }
2350
2351 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2352 {
2353 DeviceClass *dc = DEVICE_CLASS(oc);
2354 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2355
2356 dc->desc = "PowerPC 405";
2357 pcc->init_proc = init_proc_405;
2358 pcc->check_pow = check_pow_nocheck;
2359 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2360 PPC_DCR | PPC_WRTEE |
2361 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2362 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2363 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2364 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2365 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2366 pcc->msr_mask = (1ull << MSR_WE) |
2367 (1ull << MSR_CE) |
2368 (1ull << MSR_EE) |
2369 (1ull << MSR_PR) |
2370 (1ull << MSR_FP) |
2371 (1ull << MSR_ME) |
2372 (1ull << MSR_DWE) |
2373 (1ull << MSR_DE) |
2374 (1ull << MSR_IR) |
2375 (1ull << MSR_DR);
2376 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2377 pcc->excp_model = POWERPC_EXCP_40x;
2378 pcc->bus_model = PPC_FLAGS_INPUT_405;
2379 pcc->bfd_mach = bfd_mach_ppc_403;
2380 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2381 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2382 }
2383
2384 static void init_proc_440EP(CPUPPCState *env)
2385 {
2386 /* Time base */
2387 register_tbl(env);
2388 register_BookE_sprs(env, 0x000000000000FFFFULL);
2389 register_440_sprs(env);
2390 register_usprgh_sprs(env);
2391 /* Processor identification */
2392 spr_register(env, SPR_BOOKE_PIR, "PIR",
2393 SPR_NOACCESS, SPR_NOACCESS,
2394 &spr_read_generic, &spr_write_pir,
2395 0x00000000);
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_generic,
2400 0x00000000);
2401 /* XXX : not implemented */
2402 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_generic, &spr_write_generic,
2405 0x00000000);
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_440_CCR1, "CCR1",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 /* Memory management */
2435 #if !defined(CONFIG_USER_ONLY)
2436 env->nb_tlb = 64;
2437 env->nb_ways = 1;
2438 env->id_tlbs = 0;
2439 env->tlb_type = TLB_EMB;
2440 #endif
2441 init_excp_BookE(env);
2442 env->dcache_line_size = 32;
2443 env->icache_line_size = 32;
2444 ppc40x_irq_init(env_archcpu(env));
2445
2446 SET_FIT_PERIOD(12, 16, 20, 24);
2447 SET_WDT_PERIOD(20, 24, 28, 32);
2448 }
2449
2450 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2451 {
2452 DeviceClass *dc = DEVICE_CLASS(oc);
2453 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2454
2455 dc->desc = "PowerPC 440 EP";
2456 pcc->init_proc = init_proc_440EP;
2457 pcc->check_pow = check_pow_nocheck;
2458 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2459 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2460 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2461 PPC_FLOAT_STFIWX |
2462 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2463 PPC_CACHE | PPC_CACHE_ICBI |
2464 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2465 PPC_MEM_TLBSYNC | PPC_MFTB |
2466 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2467 PPC_440_SPEC;
2468 pcc->msr_mask = (1ull << MSR_POW) |
2469 (1ull << MSR_CE) |
2470 (1ull << MSR_EE) |
2471 (1ull << MSR_PR) |
2472 (1ull << MSR_FP) |
2473 (1ull << MSR_ME) |
2474 (1ull << MSR_FE0) |
2475 (1ull << MSR_DWE) |
2476 (1ull << MSR_DE) |
2477 (1ull << MSR_FE1) |
2478 (1ull << MSR_IR) |
2479 (1ull << MSR_DR);
2480 pcc->mmu_model = POWERPC_MMU_BOOKE;
2481 pcc->excp_model = POWERPC_EXCP_BOOKE;
2482 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2483 pcc->bfd_mach = bfd_mach_ppc_403;
2484 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2485 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2486 }
2487
2488 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2489 {
2490 DeviceClass *dc = DEVICE_CLASS(oc);
2491 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2492
2493 dc->desc = "PowerPC 460 EX";
2494 pcc->init_proc = init_proc_440EP;
2495 pcc->check_pow = check_pow_nocheck;
2496 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2497 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2498 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2499 PPC_FLOAT_STFIWX |
2500 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2501 PPC_CACHE | PPC_CACHE_ICBI |
2502 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2503 PPC_MEM_TLBSYNC | PPC_MFTB |
2504 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2505 PPC_440_SPEC;
2506 pcc->msr_mask = (1ull << MSR_POW) |
2507 (1ull << MSR_CE) |
2508 (1ull << MSR_EE) |
2509 (1ull << MSR_PR) |
2510 (1ull << MSR_FP) |
2511 (1ull << MSR_ME) |
2512 (1ull << MSR_FE0) |
2513 (1ull << MSR_DWE) |
2514 (1ull << MSR_DE) |
2515 (1ull << MSR_FE1) |
2516 (1ull << MSR_IR) |
2517 (1ull << MSR_DR);
2518 pcc->mmu_model = POWERPC_MMU_BOOKE;
2519 pcc->excp_model = POWERPC_EXCP_BOOKE;
2520 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2521 pcc->bfd_mach = bfd_mach_ppc_403;
2522 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2523 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2524 }
2525
2526 static void init_proc_440GP(CPUPPCState *env)
2527 {
2528 /* Time base */
2529 register_tbl(env);
2530 register_BookE_sprs(env, 0x000000000000FFFFULL);
2531 register_440_sprs(env);
2532 register_usprgh_sprs(env);
2533 /* Processor identification */
2534 spr_register(env, SPR_BOOKE_PIR, "PIR",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_pir,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* Memory management */
2559 #if !defined(CONFIG_USER_ONLY)
2560 env->nb_tlb = 64;
2561 env->nb_ways = 1;
2562 env->id_tlbs = 0;
2563 env->tlb_type = TLB_EMB;
2564 #endif
2565 init_excp_BookE(env);
2566 env->dcache_line_size = 32;
2567 env->icache_line_size = 32;
2568 /* XXX: TODO: allocate internal IRQ controller */
2569
2570 SET_FIT_PERIOD(12, 16, 20, 24);
2571 SET_WDT_PERIOD(20, 24, 28, 32);
2572 }
2573
2574 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2575 {
2576 DeviceClass *dc = DEVICE_CLASS(oc);
2577 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2578
2579 dc->desc = "PowerPC 440 GP";
2580 pcc->init_proc = init_proc_440GP;
2581 pcc->check_pow = check_pow_nocheck;
2582 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2583 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2584 PPC_CACHE | PPC_CACHE_ICBI |
2585 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2586 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2587 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2588 PPC_440_SPEC;
2589 pcc->msr_mask = (1ull << MSR_POW) |
2590 (1ull << MSR_CE) |
2591 (1ull << MSR_EE) |
2592 (1ull << MSR_PR) |
2593 (1ull << MSR_FP) |
2594 (1ull << MSR_ME) |
2595 (1ull << MSR_FE0) |
2596 (1ull << MSR_DWE) |
2597 (1ull << MSR_DE) |
2598 (1ull << MSR_FE1) |
2599 (1ull << MSR_IR) |
2600 (1ull << MSR_DR);
2601 pcc->mmu_model = POWERPC_MMU_BOOKE;
2602 pcc->excp_model = POWERPC_EXCP_BOOKE;
2603 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2604 pcc->bfd_mach = bfd_mach_ppc_403;
2605 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2606 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2607 }
2608
2609 static void init_proc_440x5(CPUPPCState *env)
2610 {
2611 /* Time base */
2612 register_tbl(env);
2613 register_BookE_sprs(env, 0x000000000000FFFFULL);
2614 register_440_sprs(env);
2615 register_usprgh_sprs(env);
2616 /* Processor identification */
2617 spr_register(env, SPR_BOOKE_PIR, "PIR",
2618 SPR_NOACCESS, SPR_NOACCESS,
2619 &spr_read_generic, &spr_write_pir,
2620 0x00000000);
2621 /* XXX : not implemented */
2622 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2623 SPR_NOACCESS, SPR_NOACCESS,
2624 &spr_read_generic, &spr_write_generic,
2625 0x00000000);
2626 /* XXX : not implemented */
2627 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2628 SPR_NOACCESS, SPR_NOACCESS,
2629 &spr_read_generic, &spr_write_generic,
2630 0x00000000);
2631 /* XXX : not implemented */
2632 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2633 SPR_NOACCESS, SPR_NOACCESS,
2634 &spr_read_generic, &spr_write_generic,
2635 0x00000000);
2636 /* XXX : not implemented */
2637 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2638 SPR_NOACCESS, SPR_NOACCESS,
2639 &spr_read_generic, &spr_write_generic,
2640 0x00000000);
2641 /* XXX : not implemented */
2642 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2643 SPR_NOACCESS, SPR_NOACCESS,
2644 &spr_read_generic, &spr_write_generic,
2645 0x00000000);
2646 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2651 SPR_NOACCESS, SPR_NOACCESS,
2652 &spr_read_generic, &spr_write_generic,
2653 0x00000000);
2654 /* XXX : not implemented */
2655 spr_register(env, SPR_440_CCR1, "CCR1",
2656 SPR_NOACCESS, SPR_NOACCESS,
2657 &spr_read_generic, &spr_write_generic,
2658 0x00000000);
2659 /* Memory management */
2660 #if !defined(CONFIG_USER_ONLY)
2661 env->nb_tlb = 64;
2662 env->nb_ways = 1;
2663 env->id_tlbs = 0;
2664 env->tlb_type = TLB_EMB;
2665 #endif
2666 init_excp_BookE(env);
2667 env->dcache_line_size = 32;
2668 env->icache_line_size = 32;
2669 ppc40x_irq_init(env_archcpu(env));
2670
2671 SET_FIT_PERIOD(12, 16, 20, 24);
2672 SET_WDT_PERIOD(20, 24, 28, 32);
2673 }
2674
2675 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2676 {
2677 DeviceClass *dc = DEVICE_CLASS(oc);
2678 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2679
2680 dc->desc = "PowerPC 440x5";
2681 pcc->init_proc = init_proc_440x5;
2682 pcc->check_pow = check_pow_nocheck;
2683 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2684 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2685 PPC_CACHE | PPC_CACHE_ICBI |
2686 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2687 PPC_MEM_TLBSYNC | PPC_MFTB |
2688 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2689 PPC_440_SPEC;
2690 pcc->msr_mask = (1ull << MSR_POW) |
2691 (1ull << MSR_CE) |
2692 (1ull << MSR_EE) |
2693 (1ull << MSR_PR) |
2694 (1ull << MSR_FP) |
2695 (1ull << MSR_ME) |
2696 (1ull << MSR_FE0) |
2697 (1ull << MSR_DWE) |
2698 (1ull << MSR_DE) |
2699 (1ull << MSR_FE1) |
2700 (1ull << MSR_IR) |
2701 (1ull << MSR_DR);
2702 pcc->mmu_model = POWERPC_MMU_BOOKE;
2703 pcc->excp_model = POWERPC_EXCP_BOOKE;
2704 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2705 pcc->bfd_mach = bfd_mach_ppc_403;
2706 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2707 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2708 }
2709
2710 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2711 {
2712 DeviceClass *dc = DEVICE_CLASS(oc);
2713 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2714
2715 dc->desc = "PowerPC 440x5 with double precision FPU";
2716 pcc->init_proc = init_proc_440x5;
2717 pcc->check_pow = check_pow_nocheck;
2718 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2719 PPC_FLOAT | PPC_FLOAT_FSQRT |
2720 PPC_FLOAT_STFIWX |
2721 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2722 PPC_CACHE | PPC_CACHE_ICBI |
2723 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2724 PPC_MEM_TLBSYNC | PPC_MFTB |
2725 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2726 PPC_440_SPEC;
2727 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2728 pcc->msr_mask = (1ull << MSR_POW) |
2729 (1ull << MSR_CE) |
2730 (1ull << MSR_EE) |
2731 (1ull << MSR_PR) |
2732 (1ull << MSR_FP) |
2733 (1ull << MSR_ME) |
2734 (1ull << MSR_FE0) |
2735 (1ull << MSR_DWE) |
2736 (1ull << MSR_DE) |
2737 (1ull << MSR_FE1) |
2738 (1ull << MSR_IR) |
2739 (1ull << MSR_DR);
2740 pcc->mmu_model = POWERPC_MMU_BOOKE;
2741 pcc->excp_model = POWERPC_EXCP_BOOKE;
2742 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2743 pcc->bfd_mach = bfd_mach_ppc_403;
2744 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2745 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2746 }
2747
2748 static void init_proc_MPC5xx(CPUPPCState *env)
2749 {
2750 /* Time base */
2751 register_tbl(env);
2752 register_5xx_8xx_sprs(env);
2753 register_5xx_sprs(env);
2754 init_excp_MPC5xx(env);
2755 env->dcache_line_size = 32;
2756 env->icache_line_size = 32;
2757 /* XXX: TODO: allocate internal IRQ controller */
2758 }
2759
2760 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2761 {
2762 DeviceClass *dc = DEVICE_CLASS(oc);
2763 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2764
2765 dc->desc = "Freescale 5xx cores (aka RCPU)";
2766 pcc->init_proc = init_proc_MPC5xx;
2767 pcc->check_pow = check_pow_none;
2768 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2769 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2770 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2771 PPC_MFTB;
2772 pcc->msr_mask = (1ull << MSR_ILE) |
2773 (1ull << MSR_EE) |
2774 (1ull << MSR_PR) |
2775 (1ull << MSR_FP) |
2776 (1ull << MSR_ME) |
2777 (1ull << MSR_FE0) |
2778 (1ull << MSR_SE) |
2779 (1ull << MSR_DE) |
2780 (1ull << MSR_FE1) |
2781 (1ull << MSR_EP) |
2782 (1ull << MSR_RI) |
2783 (1ull << MSR_LE);
2784 pcc->mmu_model = POWERPC_MMU_REAL;
2785 pcc->excp_model = POWERPC_EXCP_6xx;
2786 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2787 pcc->bfd_mach = bfd_mach_ppc_505;
2788 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2789 POWERPC_FLAG_BUS_CLK;
2790 }
2791
2792 static void init_proc_MPC8xx(CPUPPCState *env)
2793 {
2794 /* Time base */
2795 register_tbl(env);
2796 register_5xx_8xx_sprs(env);
2797 register_8xx_sprs(env);
2798 init_excp_MPC8xx(env);
2799 env->dcache_line_size = 32;
2800 env->icache_line_size = 32;
2801 /* XXX: TODO: allocate internal IRQ controller */
2802 }
2803
2804 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2805 {
2806 DeviceClass *dc = DEVICE_CLASS(oc);
2807 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2808
2809 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2810 pcc->init_proc = init_proc_MPC8xx;
2811 pcc->check_pow = check_pow_none;
2812 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2813 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2814 PPC_CACHE_ICBI | PPC_MFTB;
2815 pcc->msr_mask = (1ull << MSR_ILE) |
2816 (1ull << MSR_EE) |
2817 (1ull << MSR_PR) |
2818 (1ull << MSR_FP) |
2819 (1ull << MSR_ME) |
2820 (1ull << MSR_SE) |
2821 (1ull << MSR_DE) |
2822 (1ull << MSR_EP) |
2823 (1ull << MSR_IR) |
2824 (1ull << MSR_DR) |
2825 (1ull << MSR_RI) |
2826 (1ull << MSR_LE);
2827 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2828 pcc->excp_model = POWERPC_EXCP_6xx;
2829 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2830 pcc->bfd_mach = bfd_mach_ppc_860;
2831 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2832 POWERPC_FLAG_BUS_CLK;
2833 }
2834
2835 /* Freescale 82xx cores (aka PowerQUICC-II) */
2836
2837 static void init_proc_G2(CPUPPCState *env)
2838 {
2839 register_ne_601_sprs(env);
2840 register_sdr1_sprs(env);
2841 register_G2_755_sprs(env);
2842 register_G2_sprs(env);
2843 /* Time base */
2844 register_tbl(env);
2845 /* External access control */
2846 /* XXX : not implemented */
2847 spr_register(env, SPR_EAR, "EAR",
2848 SPR_NOACCESS, SPR_NOACCESS,
2849 &spr_read_generic, &spr_write_generic,
2850 0x00000000);
2851 /* Hardware implementation register */
2852 /* XXX : not implemented */
2853 spr_register(env, SPR_HID0, "HID0",
2854 SPR_NOACCESS, SPR_NOACCESS,
2855 &spr_read_generic, &spr_write_generic,
2856 0x00000000);
2857 /* XXX : not implemented */
2858 spr_register(env, SPR_HID1, "HID1",
2859 SPR_NOACCESS, SPR_NOACCESS,
2860 &spr_read_generic, &spr_write_generic,
2861 0x00000000);
2862 /* XXX : not implemented */
2863 spr_register(env, SPR_HID2, "HID2",
2864 SPR_NOACCESS, SPR_NOACCESS,
2865 &spr_read_generic, &spr_write_generic,
2866 0x00000000);
2867 /* Memory management */
2868 register_low_BATs(env);
2869 register_high_BATs(env);
2870 register_6xx_7xx_soft_tlb(env, 64, 2);
2871 init_excp_G2(env);
2872 env->dcache_line_size = 32;
2873 env->icache_line_size = 32;
2874 /* Allocate hardware IRQ controller */
2875 ppc6xx_irq_init(env_archcpu(env));
2876 }
2877
2878 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
2879 {
2880 DeviceClass *dc = DEVICE_CLASS(oc);
2881 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2882
2883 dc->desc = "PowerPC G2";
2884 pcc->init_proc = init_proc_G2;
2885 pcc->check_pow = check_pow_hid0;
2886 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2887 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2888 PPC_FLOAT_STFIWX |
2889 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2890 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2891 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2892 PPC_SEGMENT | PPC_EXTERN;
2893 pcc->msr_mask = (1ull << MSR_POW) |
2894 (1ull << MSR_TGPR) |
2895 (1ull << MSR_EE) |
2896 (1ull << MSR_PR) |
2897 (1ull << MSR_FP) |
2898 (1ull << MSR_ME) |
2899 (1ull << MSR_FE0) |
2900 (1ull << MSR_SE) |
2901 (1ull << MSR_DE) |
2902 (1ull << MSR_FE1) |
2903 (1ull << MSR_AL) |
2904 (1ull << MSR_EP) |
2905 (1ull << MSR_IR) |
2906 (1ull << MSR_DR) |
2907 (1ull << MSR_RI);
2908 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2909 pcc->excp_model = POWERPC_EXCP_6xx;
2910 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2911 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2912 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2913 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2914 }
2915
2916 static void init_proc_G2LE(CPUPPCState *env)
2917 {
2918 register_ne_601_sprs(env);
2919 register_sdr1_sprs(env);
2920 register_G2_755_sprs(env);
2921 register_G2_sprs(env);
2922 /* Time base */
2923 register_tbl(env);
2924 /* External access control */
2925 /* XXX : not implemented */
2926 spr_register(env, SPR_EAR, "EAR",
2927 SPR_NOACCESS, SPR_NOACCESS,
2928 &spr_read_generic, &spr_write_generic,
2929 0x00000000);
2930 /* Hardware implementation register */
2931 /* XXX : not implemented */
2932 spr_register(env, SPR_HID0, "HID0",
2933 SPR_NOACCESS, SPR_NOACCESS,
2934 &spr_read_generic, &spr_write_generic,
2935 0x00000000);
2936 /* XXX : not implemented */
2937 spr_register(env, SPR_HID1, "HID1",
2938 SPR_NOACCESS, SPR_NOACCESS,
2939 &spr_read_generic, &spr_write_generic,
2940 0x00000000);
2941 /* XXX : not implemented */
2942 spr_register(env, SPR_HID2, "HID2",
2943 SPR_NOACCESS, SPR_NOACCESS,
2944 &spr_read_generic, &spr_write_generic,
2945 0x00000000);
2946
2947 /* Memory management */
2948 register_low_BATs(env);
2949 register_high_BATs(env);
2950 register_6xx_7xx_soft_tlb(env, 64, 2);
2951 init_excp_G2(env);
2952 env->dcache_line_size = 32;
2953 env->icache_line_size = 32;
2954 /* Allocate hardware IRQ controller */
2955 ppc6xx_irq_init(env_archcpu(env));
2956 }
2957
2958 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
2959 {
2960 DeviceClass *dc = DEVICE_CLASS(oc);
2961 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2962
2963 dc->desc = "PowerPC G2LE";
2964 pcc->init_proc = init_proc_G2LE;
2965 pcc->check_pow = check_pow_hid0;
2966 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2967 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2968 PPC_FLOAT_STFIWX |
2969 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2970 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2971 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2972 PPC_SEGMENT | PPC_EXTERN;
2973 pcc->msr_mask = (1ull << MSR_POW) |
2974 (1ull << MSR_TGPR) |
2975 (1ull << MSR_ILE) |
2976 (1ull << MSR_EE) |
2977 (1ull << MSR_PR) |
2978 (1ull << MSR_FP) |
2979 (1ull << MSR_ME) |
2980 (1ull << MSR_FE0) |
2981 (1ull << MSR_SE) |
2982 (1ull << MSR_DE) |
2983 (1ull << MSR_FE1) |
2984 (1ull << MSR_AL) |
2985 (1ull << MSR_EP) |
2986 (1ull << MSR_IR) |
2987 (1ull << MSR_DR) |
2988 (1ull << MSR_RI) |
2989 (1ull << MSR_LE);
2990 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2991 pcc->excp_model = POWERPC_EXCP_6xx;
2992 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2993 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2994 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2995 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2996 }
2997
2998 static void init_proc_e200(CPUPPCState *env)
2999 {
3000 /* Time base */
3001 register_tbl(env);
3002 register_BookE_sprs(env, 0x000000070000FFFFULL);
3003 /* XXX : not implemented */
3004 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3005 &spr_read_spefscr, &spr_write_spefscr,
3006 &spr_read_spefscr, &spr_write_spefscr,
3007 0x00000000);
3008 /* Memory management */
3009 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
3010 /* XXX : not implemented */
3011 spr_register(env, SPR_HID0, "HID0",
3012 SPR_NOACCESS, SPR_NOACCESS,
3013 &spr_read_generic, &spr_write_generic,
3014 0x00000000);
3015 /* XXX : not implemented */
3016 spr_register(env, SPR_HID1, "HID1",
3017 SPR_NOACCESS, SPR_NOACCESS,
3018 &spr_read_generic, &spr_write_generic,
3019 0x00000000);
3020 /* XXX : not implemented */
3021 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3022 SPR_NOACCESS, SPR_NOACCESS,
3023 &spr_read_generic, &spr_write_generic,
3024 0x00000000);
3025 /* XXX : not implemented */
3026 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3027 SPR_NOACCESS, SPR_NOACCESS,
3028 &spr_read_generic, &spr_write_generic,
3029 0x00000000);
3030 /* XXX : not implemented */
3031 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3032 SPR_NOACCESS, SPR_NOACCESS,
3033 &spr_read_generic, &spr_write_generic,
3034 0x00000000);
3035 /* XXX : not implemented */
3036 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3037 SPR_NOACCESS, SPR_NOACCESS,
3038 &spr_read_generic, &spr_write_generic,
3039 0x00000000);
3040 /* XXX : not implemented */
3041 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3042 SPR_NOACCESS, SPR_NOACCESS,
3043 &spr_read_generic, &spr_write_generic,
3044 0x00000000);
3045 /* XXX : not implemented */
3046 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3047 &spr_read_generic, SPR_NOACCESS,
3048 &spr_read_generic, SPR_NOACCESS,
3049 0x00000000);
3050 /* XXX : not implemented */
3051 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3052 SPR_NOACCESS, SPR_NOACCESS,
3053 &spr_read_generic, &spr_write_generic,
3054 0x00000000);
3055 /* XXX : not implemented */
3056 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3057 SPR_NOACCESS, SPR_NOACCESS,
3058 &spr_read_generic, &spr_write_generic,
3059 0x00000000);
3060 /* XXX : not implemented */
3061 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3062 SPR_NOACCESS, SPR_NOACCESS,
3063 &spr_read_generic, &spr_write_generic,
3064 0x00000000);
3065 /* XXX : not implemented */
3066 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3067 SPR_NOACCESS, SPR_NOACCESS,
3068 &spr_read_generic, &spr_write_generic,
3069 0x00000000);
3070 /* XXX : not implemented */
3071 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3072 SPR_NOACCESS, SPR_NOACCESS,
3073 &spr_read_generic, &spr_write_generic,
3074 0x00000000);
3075 /* XXX : not implemented */
3076 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3077 SPR_NOACCESS, SPR_NOACCESS,
3078 &spr_read_generic, &spr_write_generic,
3079 0x00000000);
3080 /* XXX : not implemented */
3081 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3082 SPR_NOACCESS, SPR_NOACCESS,
3083 &spr_read_generic, &spr_write_generic,
3084 0x00000000); /* TOFIX */
3085 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3086 SPR_NOACCESS, SPR_NOACCESS,
3087 &spr_read_generic, &spr_write_generic,
3088 0x00000000);
3089 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3090 SPR_NOACCESS, SPR_NOACCESS,
3091 &spr_read_generic, &spr_write_generic,
3092 0x00000000);
3093 #if !defined(CONFIG_USER_ONLY)
3094 env->nb_tlb = 64;
3095 env->nb_ways = 1;
3096 env->id_tlbs = 0;
3097 env->tlb_type = TLB_EMB;
3098 #endif
3099 init_excp_e200(env, 0xFFFF0000UL);
3100 env->dcache_line_size = 32;
3101 env->icache_line_size = 32;
3102 /* XXX: TODO: allocate internal IRQ controller */
3103 }
3104
3105 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3106 {
3107 DeviceClass *dc = DEVICE_CLASS(oc);
3108 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3109
3110 dc->desc = "e200 core";
3111 pcc->init_proc = init_proc_e200;
3112 pcc->check_pow = check_pow_hid0;
3113 /*
3114 * XXX: unimplemented instructions:
3115 * dcblc
3116 * dcbtlst
3117 * dcbtstls
3118 * icblc
3119 * icbtls
3120 * tlbivax
3121 * all SPE multiply-accumulate instructions
3122 */
3123 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3124 PPC_SPE | PPC_SPE_SINGLE |
3125 PPC_WRTEE | PPC_RFDI |
3126 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3127 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3128 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3129 PPC_BOOKE;
3130 pcc->msr_mask = (1ull << MSR_UCLE) |
3131 (1ull << MSR_SPE) |
3132 (1ull << MSR_POW) |
3133 (1ull << MSR_CE) |
3134 (1ull << MSR_EE) |
3135 (1ull << MSR_PR) |
3136 (1ull << MSR_FP) |
3137 (1ull << MSR_ME) |
3138 (1ull << MSR_FE0) |
3139 (1ull << MSR_DWE) |
3140 (1ull << MSR_DE) |
3141 (1ull << MSR_FE1) |
3142 (1ull << MSR_IR) |
3143 (1ull << MSR_DR);
3144 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3145 pcc->excp_model = POWERPC_EXCP_BOOKE;
3146 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3147 pcc->bfd_mach = bfd_mach_ppc_860;
3148 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3149 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3150 POWERPC_FLAG_BUS_CLK;
3151 }
3152
3153 static void init_proc_e300(CPUPPCState *env)
3154 {
3155 register_ne_601_sprs(env);
3156 register_sdr1_sprs(env);
3157 register_603_sprs(env);
3158 /* Time base */
3159 register_tbl(env);
3160 /* hardware implementation registers */
3161 /* XXX : not implemented */
3162 spr_register(env, SPR_HID0, "HID0",
3163 SPR_NOACCESS, SPR_NOACCESS,
3164 &spr_read_generic, &spr_write_generic,
3165 0x00000000);
3166 /* XXX : not implemented */
3167 spr_register(env, SPR_HID1, "HID1",
3168 SPR_NOACCESS, SPR_NOACCESS,
3169 &spr_read_generic, &spr_write_generic,
3170 0x00000000);
3171 /* XXX : not implemented */
3172 spr_register(env, SPR_HID2, "HID2",
3173 SPR_NOACCESS, SPR_NOACCESS,
3174 &spr_read_generic, &spr_write_generic,
3175 0x00000000);
3176 /* Breakpoints */
3177 /* XXX : not implemented */
3178 spr_register(env, SPR_DABR, "DABR",
3179 SPR_NOACCESS, SPR_NOACCESS,
3180 &spr_read_generic, &spr_write_generic,
3181 0x00000000);
3182 /* XXX : not implemented */
3183 spr_register(env, SPR_DABR2, "DABR2",
3184 SPR_NOACCESS, SPR_NOACCESS,
3185 &spr_read_generic, &spr_write_generic,
3186 0x00000000);
3187 /* XXX : not implemented */
3188 spr_register(env, SPR_IABR2, "IABR2",
3189 SPR_NOACCESS, SPR_NOACCESS,
3190 &spr_read_generic, &spr_write_generic,
3191 0x00000000);
3192 /* XXX : not implemented */
3193 spr_register(env, SPR_IBCR, "IBCR",
3194 SPR_NOACCESS, SPR_NOACCESS,
3195 &spr_read_generic, &spr_write_generic,
3196 0x00000000);
3197 /* XXX : not implemented */
3198 spr_register(env, SPR_DBCR, "DBCR",
3199 SPR_NOACCESS, SPR_NOACCESS,
3200 &spr_read_generic, &spr_write_generic,
3201 0x00000000);
3202 /* Memory management */
3203 register_low_BATs(env);
3204 register_high_BATs(env);
3205 register_6xx_7xx_soft_tlb(env, 64, 2);
3206 init_excp_603(env);
3207 env->dcache_line_size = 32;
3208 env->icache_line_size = 32;
3209 /* Allocate hardware IRQ controller */
3210 ppc6xx_irq_init(env_archcpu(env));
3211 }
3212
3213 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3214 {
3215 DeviceClass *dc = DEVICE_CLASS(oc);
3216 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3217
3218 dc->desc = "e300 core";
3219 pcc->init_proc = init_proc_e300;
3220 pcc->check_pow = check_pow_hid0;
3221 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3222 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3223 PPC_FLOAT_STFIWX |
3224 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3225 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3226 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3227 PPC_SEGMENT | PPC_EXTERN;
3228 pcc->msr_mask = (1ull << MSR_POW) |
3229 (1ull << MSR_TGPR) |
3230 (1ull << MSR_ILE) |
3231 (1ull << MSR_EE) |
3232 (1ull << MSR_PR) |
3233 (1ull << MSR_FP) |
3234 (1ull << MSR_ME) |
3235 (1ull << MSR_FE0) |
3236 (1ull << MSR_SE) |
3237 (1ull << MSR_DE) |
3238 (1ull << MSR_FE1) |
3239 (1ull << MSR_AL) |
3240 (1ull << MSR_EP) |
3241 (1ull << MSR_IR) |
3242 (1ull << MSR_DR) |
3243 (1ull << MSR_RI) |
3244 (1ull << MSR_LE);
3245 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3246 pcc->excp_model = POWERPC_EXCP_6xx;
3247 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3248 pcc->bfd_mach = bfd_mach_ppc_603;
3249 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3250 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3251 }
3252
3253 enum fsl_e500_version {
3254 fsl_e500v1,
3255 fsl_e500v2,
3256 fsl_e500mc,
3257 fsl_e5500,
3258 fsl_e6500,
3259 };
3260
3261 static void init_proc_e500(CPUPPCState *env, int version)
3262 {
3263 uint32_t tlbncfg[2];
3264 uint64_t ivor_mask;
3265 uint64_t ivpr_mask = 0xFFFF0000ULL;
3266 uint32_t l1cfg0 = 0x3800 /* 8 ways */
3267 | 0x0020; /* 32 kb */
3268 uint32_t l1cfg1 = 0x3800 /* 8 ways */
3269 | 0x0020; /* 32 kb */
3270 uint32_t mmucfg = 0;
3271 #if !defined(CONFIG_USER_ONLY)
3272 int i;
3273 #endif
3274
3275 /* Time base */
3276 register_tbl(env);
3277 /*
3278 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
3279 * complain when accessing them.
3280 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
3281 */
3282 switch (version) {
3283 case fsl_e500v1:
3284 case fsl_e500v2:
3285 default:
3286 ivor_mask = 0x0000000F0000FFFFULL;
3287 break;
3288 case fsl_e500mc:
3289 case fsl_e5500:
3290 ivor_mask = 0x000003FE0000FFFFULL;
3291 break;
3292 case fsl_e6500:
3293 ivor_mask = 0x000003FF0000FFFFULL;
3294 break;
3295 }
3296 register_BookE_sprs(env, ivor_mask);
3297 register_usprg3_sprs(env);
3298 /* Processor identification */
3299 spr_register(env, SPR_BOOKE_PIR, "PIR",
3300 SPR_NOACCESS, SPR_NOACCESS,
3301 &spr_read_generic, &spr_write_pir,
3302 0x00000000);
3303 /* XXX : not implemented */
3304 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3305 &spr_read_spefscr, &spr_write_spefscr,
3306 &spr_read_spefscr, &spr_write_spefscr,
3307 0x00000000);
3308 #if !defined(CONFIG_USER_ONLY)
3309 /* Memory management */
3310 env->nb_pids = 3;
3311 env->nb_ways = 2;
3312 env->id_tlbs = 0;
3313 switch (version) {
3314 case fsl_e500v1:
3315 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
3316 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3317 break;
3318 case fsl_e500v2:
3319 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3320 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3321 break;
3322 case fsl_e500mc:
3323 case fsl_e5500:
3324 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3325 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
3326 break;
3327 case fsl_e6500:
3328 mmucfg = 0x6510B45;
3329 env->nb_pids = 1;
3330 tlbncfg[0] = 0x08052400;
3331 tlbncfg[1] = 0x40028040;
3332 break;
3333 default:
3334 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3335 env->spr[SPR_PVR]);
3336 }
3337 #endif
3338 /* Cache sizes */
3339 switch (version) {
3340 case fsl_e500v1:
3341 case fsl_e500v2:
3342 env->dcache_line_size = 32;
3343 env->icache_line_size = 32;
3344 break;
3345 case fsl_e500mc:
3346 case fsl_e5500:
3347 env->dcache_line_size = 64;
3348 env->icache_line_size = 64;
3349 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
3350 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
3351 break;
3352 case fsl_e6500:
3353 env->dcache_line_size = 32;
3354 env->icache_line_size = 32;
3355 l1cfg0 |= 0x0F83820;
3356 l1cfg1 |= 0x0B83820;
3357 break;
3358 default:
3359 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3360 env->spr[SPR_PVR]);
3361 }
3362 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
3363 /* XXX : not implemented */
3364 spr_register(env, SPR_HID0, "HID0",
3365 SPR_NOACCESS, SPR_NOACCESS,
3366 &spr_read_generic, &spr_write_generic,
3367 0x00000000);
3368 /* XXX : not implemented */
3369 spr_register(env, SPR_HID1, "HID1",
3370 SPR_NOACCESS, SPR_NOACCESS,
3371 &spr_read_generic, &spr_write_generic,
3372 0x00000000);
3373 /* XXX : not implemented */
3374 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
3375 SPR_NOACCESS, SPR_NOACCESS,
3376 &spr_read_generic, &spr_write_generic,
3377 0x00000000);
3378 /* XXX : not implemented */
3379 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
3380 SPR_NOACCESS, SPR_NOACCESS,
3381 &spr_read_generic, &spr_write_generic,
3382 0x00000000);
3383 /* XXX : not implemented */
3384 spr_register(env, SPR_Exxx_MCAR, "MCAR",
3385 SPR_NOACCESS, SPR_NOACCESS,
3386 &spr_read_generic, &spr_write_generic,
3387 0x00000000);
3388 /* XXX : not implemented */
3389 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3390 SPR_NOACCESS, SPR_NOACCESS,
3391 &spr_read_generic, &spr_write_generic,
3392 0x00000000);
3393 /* XXX : not implemented */
3394 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
3395 SPR_NOACCESS, SPR_NOACCESS,
3396 &spr_read_generic, &spr_write_generic,
3397 0x00000000);
3398 /* XXX : not implemented */
3399 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3400 SPR_NOACCESS, SPR_NOACCESS,
3401 &spr_read_generic, &spr_write_generic,
3402 0x00000000);
3403 /* XXX : not implemented */
3404 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3405 &spr_read_generic, SPR_NOACCESS,
3406 &spr_read_generic, SPR_NOACCESS,
3407 l1cfg0);
3408 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
3409 &spr_read_generic, SPR_NOACCESS,
3410 &spr_read_generic, SPR_NOACCESS,
3411 l1cfg1);
3412 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3413 SPR_NOACCESS, SPR_NOACCESS,
3414 &spr_read_generic, &spr_write_e500_l1csr0,
3415 0x00000000);
3416 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
3417 SPR_NOACCESS, SPR_NOACCESS,
3418 &spr_read_generic, &spr_write_e500_l1csr1,
3419 0x00000000);
3420 if (version != fsl_e500v1 && version != fsl_e500v2) {
3421 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
3422 SPR_NOACCESS, SPR_NOACCESS,
3423 &spr_read_generic, &spr_write_e500_l2csr0,
3424 0x00000000);
3425 }
3426 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3427 SPR_NOACCESS, SPR_NOACCESS,
3428 &spr_read_generic, &spr_write_generic,
3429 0x00000000);
3430 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3431 SPR_NOACCESS, SPR_NOACCESS,
3432 &spr_read_generic, &spr_write_generic,
3433 0x00000000);
3434 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3435 SPR_NOACCESS, SPR_NOACCESS,
3436 &spr_read_generic, &spr_write_booke206_mmucsr0,
3437 0x00000000);
3438 spr_register(env, SPR_BOOKE_EPR, "EPR",
3439 SPR_NOACCESS, SPR_NOACCESS,
3440 &spr_read_generic, SPR_NOACCESS,
3441 0x00000000);
3442 /* XXX better abstract into Emb.xxx features */
3443 if ((version == fsl_e5500) || (version == fsl_e6500)) {
3444 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
3445 SPR_NOACCESS, SPR_NOACCESS,
3446 &spr_read_generic, &spr_write_generic,
3447 0x00000000);
3448 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
3449 SPR_NOACCESS, SPR_NOACCESS,
3450 &spr_read_mas73, &spr_write_mas73,
3451 0x00000000);
3452 ivpr_mask = (target_ulong)~0xFFFFULL;
3453 }
3454
3455 if (version == fsl_e6500) {
3456 /* Thread identification */
3457 spr_register(env, SPR_TIR, "TIR",
3458 SPR_NOACCESS, SPR_NOACCESS,
3459 &spr_read_generic, SPR_NOACCESS,
3460 0x00000000);
3461 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3462 SPR_NOACCESS, SPR_NOACCESS,
3463 &spr_read_generic, SPR_NOACCESS,
3464 0x00000004);
3465 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3466 SPR_NOACCESS, SPR_NOACCESS,
3467 &spr_read_generic, SPR_NOACCESS,
3468 0x7FFFFFFC);
3469 }
3470
3471 #if !defined(CONFIG_USER_ONLY)
3472 env->nb_tlb = 0;
3473 env->tlb_type = TLB_MAS;
3474 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3475 env->nb_tlb += booke206_tlb_size(env, i);
3476 }
3477 #endif
3478
3479 init_excp_e200(env, ivpr_mask);
3480 /* Allocate hardware IRQ controller */
3481 ppce500_irq_init(env_archcpu(env));
3482 }
3483
3484 static void init_proc_e500v1(CPUPPCState *env)
3485 {
3486 init_proc_e500(env, fsl_e500v1);
3487 }
3488
3489 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3490 {
3491 DeviceClass *dc = DEVICE_CLASS(oc);
3492 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3493
3494 dc->desc = "e500v1 core";
3495 pcc->init_proc = init_proc_e500v1;
3496 pcc->check_pow = check_pow_hid0;
3497 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3498 PPC_SPE | PPC_SPE_SINGLE |
3499 PPC_WRTEE | PPC_RFDI |
3500 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3501 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3502 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3503 pcc->insns_flags2 = PPC2_BOOKE206;
3504 pcc->msr_mask = (1ull << MSR_UCLE) |
3505 (1ull << MSR_SPE) |
3506 (1ull << MSR_POW) |
3507 (1ull << MSR_CE) |
3508 (1ull << MSR_EE) |
3509 (1ull << MSR_PR) |
3510 (1ull << MSR_FP) |
3511 (1ull << MSR_ME) |
3512 (1ull << MSR_FE0) |
3513 (1ull << MSR_DWE) |
3514 (1ull << MSR_DE) |
3515 (1ull << MSR_FE1) |
3516 (1ull << MSR_IR) |
3517 (1ull << MSR_DR);
3518 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3519 pcc->excp_model = POWERPC_EXCP_BOOKE;
3520 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3521 pcc->bfd_mach = bfd_mach_ppc_860;
3522 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3523 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3524 POWERPC_FLAG_BUS_CLK;
3525 }
3526
3527 static void init_proc_e500v2(CPUPPCState *env)
3528 {
3529 init_proc_e500(env, fsl_e500v2);
3530 }
3531
3532 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3533 {
3534 DeviceClass *dc = DEVICE_CLASS(oc);
3535 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3536
3537 dc->desc = "e500v2 core";
3538 pcc->init_proc = init_proc_e500v2;
3539 pcc->check_pow = check_pow_hid0;
3540 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3541 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3542 PPC_WRTEE | PPC_RFDI |
3543 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3544 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3545 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3546 pcc->insns_flags2 = PPC2_BOOKE206;
3547 pcc->msr_mask = (1ull << MSR_UCLE) |
3548 (1ull << MSR_SPE) |
3549 (1ull << MSR_POW) |
3550 (1ull << MSR_CE) |
3551 (1ull << MSR_EE) |
3552 (1ull << MSR_PR) |
3553 (1ull << MSR_FP) |
3554 (1ull << MSR_ME) |
3555 (1ull << MSR_FE0) |
3556 (1ull << MSR_DWE) |
3557 (1ull << MSR_DE) |
3558 (1ull << MSR_FE1) |
3559 (1ull << MSR_IR) |
3560 (1ull << MSR_DR);
3561 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3562 pcc->excp_model = POWERPC_EXCP_BOOKE;
3563 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3564 pcc->bfd_mach = bfd_mach_ppc_860;
3565 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3566 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3567 POWERPC_FLAG_BUS_CLK;
3568 }
3569
3570 static void init_proc_e500mc(CPUPPCState *env)
3571 {
3572 init_proc_e500(env, fsl_e500mc);
3573 }
3574
3575 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3576 {
3577 DeviceClass *dc = DEVICE_CLASS(oc);
3578 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3579
3580 dc->desc = "e500mc core";
3581 pcc->init_proc = init_proc_e500mc;
3582 pcc->check_pow = check_pow_none;
3583 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3584 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3585 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3586 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3587 PPC_FLOAT | PPC_FLOAT_FRES |
3588 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3589 PPC_FLOAT_STFIWX | PPC_WAIT |
3590 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3591 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3592 pcc->msr_mask = (1ull << MSR_GS) |
3593 (1ull << MSR_UCLE) |
3594 (1ull << MSR_CE) |
3595 (1ull << MSR_EE) |
3596 (1ull << MSR_PR) |
3597 (1ull << MSR_FP) |
3598 (1ull << MSR_ME) |
3599 (1ull << MSR_FE0) |
3600 (1ull << MSR_DE) |
3601 (1ull << MSR_FE1) |
3602 (1ull << MSR_IR) |
3603 (1ull << MSR_DR) |
3604 (1ull << MSR_PX) |
3605 (1ull << MSR_RI);
3606 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3607 pcc->excp_model = POWERPC_EXCP_BOOKE;
3608 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3609 /* FIXME: figure out the correct flag for e500mc */
3610 pcc->bfd_mach = bfd_mach_ppc_e500;
3611 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3612 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3613 }
3614
3615 #ifdef TARGET_PPC64
3616 static void init_proc_e5500(CPUPPCState *env)
3617 {
3618 init_proc_e500(env, fsl_e5500);
3619 }
3620
3621 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3622 {
3623 DeviceClass *dc = DEVICE_CLASS(oc);
3624 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3625
3626 dc->desc = "e5500 core";
3627 pcc->init_proc = init_proc_e5500;
3628 pcc->check_pow = check_pow_none;
3629 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3630 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3631 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3632 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3633 PPC_FLOAT | PPC_FLOAT_FRES |
3634 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3635 PPC_FLOAT_STFIWX | PPC_WAIT |
3636 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3637 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3638 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3639 PPC2_FP_CVT_S64;
3640 pcc->msr_mask = (1ull << MSR_CM) |
3641 (1ull << MSR_GS) |
3642 (1ull << MSR_UCLE) |
3643 (1ull << MSR_CE) |
3644 (1ull << MSR_EE) |
3645 (1ull << MSR_PR) |
3646 (1ull << MSR_FP) |
3647 (1ull << MSR_ME) |
3648 (1ull << MSR_FE0) |
3649 (1ull << MSR_DE) |
3650 (1ull << MSR_FE1) |
3651 (1ull << MSR_IR) |
3652 (1ull << MSR_DR) |
3653 (1ull << MSR_PX) |
3654 (1ull << MSR_RI);
3655 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3656 pcc->excp_model = POWERPC_EXCP_BOOKE;
3657 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3658 /* FIXME: figure out the correct flag for e5500 */
3659 pcc->bfd_mach = bfd_mach_ppc_e500;
3660 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3661 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3662 }
3663
3664 static void init_proc_e6500(CPUPPCState *env)
3665 {
3666 init_proc_e500(env, fsl_e6500);
3667 }
3668
3669 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3670 {
3671 DeviceClass *dc = DEVICE_CLASS(oc);
3672 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3673
3674 dc->desc = "e6500 core";
3675 pcc->init_proc = init_proc_e6500;
3676 pcc->check_pow = check_pow_none;
3677 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3678 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3679 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3680 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3681 PPC_FLOAT | PPC_FLOAT_FRES |
3682 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3683 PPC_FLOAT_STFIWX | PPC_WAIT |
3684 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3685 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3686 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3687 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3688 pcc->msr_mask = (1ull << MSR_CM) |
3689 (1ull << MSR_GS) |
3690 (1ull << MSR_UCLE) |
3691 (1ull << MSR_CE) |
3692 (1ull << MSR_EE) |
3693 (1ull << MSR_PR) |
3694 (1ull << MSR_FP) |
3695 (1ull << MSR_ME) |
3696 (1ull << MSR_FE0) |
3697 (1ull << MSR_DE) |
3698 (1ull << MSR_FE1) |
3699 (1ull << MSR_IS) |
3700 (1ull << MSR_DS) |
3701 (1ull << MSR_PX) |
3702 (1ull << MSR_RI) |
3703 (1ull << MSR_VR);
3704 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3705 pcc->excp_model = POWERPC_EXCP_BOOKE;
3706 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3707 pcc->bfd_mach = bfd_mach_ppc_e500;
3708 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3709 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3710 }
3711
3712 #endif
3713
3714 /* Non-embedded PowerPC */
3715 static void init_proc_603(CPUPPCState *env)
3716 {
3717 register_ne_601_sprs(env);
3718 register_sdr1_sprs(env);
3719 register_603_sprs(env);
3720 /* Time base */
3721 register_tbl(env);
3722 /* hardware implementation registers */
3723 /* XXX : not implemented */
3724 spr_register(env, SPR_HID0, "HID0",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_generic,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_HID1, "HID1",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 /* Memory management */
3734 register_low_BATs(env);
3735 register_6xx_7xx_soft_tlb(env, 64, 2);
3736 init_excp_603(env);
3737 env->dcache_line_size = 32;
3738 env->icache_line_size = 32;
3739 /* Allocate hardware IRQ controller */
3740 ppc6xx_irq_init(env_archcpu(env));
3741 }
3742
3743 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3744 {
3745 DeviceClass *dc = DEVICE_CLASS(oc);
3746 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3747
3748 dc->desc = "PowerPC 603";
3749 pcc->init_proc = init_proc_603;
3750 pcc->check_pow = check_pow_hid0;
3751 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3752 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3753 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3754 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3755 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3756 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3757 PPC_SEGMENT | PPC_EXTERN;
3758 pcc->msr_mask = (1ull << MSR_POW) |
3759 (1ull << MSR_TGPR) |
3760 (1ull << MSR_ILE) |
3761 (1ull << MSR_EE) |
3762 (1ull << MSR_PR) |
3763 (1ull << MSR_FP) |
3764 (1ull << MSR_ME) |
3765 (1ull << MSR_FE0) |
3766 (1ull << MSR_SE) |
3767 (1ull << MSR_DE) |
3768 (1ull << MSR_FE1) |
3769 (1ull << MSR_EP) |
3770 (1ull << MSR_IR) |
3771 (1ull << MSR_DR) |
3772 (1ull << MSR_RI) |
3773 (1ull << MSR_LE);
3774 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3775 pcc->excp_model = POWERPC_EXCP_6xx;
3776 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3777 pcc->bfd_mach = bfd_mach_ppc_603;
3778 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3779 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3780 }
3781
3782 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3783 {
3784 DeviceClass *dc = DEVICE_CLASS(oc);
3785 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3786
3787 dc->desc = "PowerPC 603e";
3788 pcc->init_proc = init_proc_603;
3789 pcc->check_pow = check_pow_hid0;
3790 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3791 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3792 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3793 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3794 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3795 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3796 PPC_SEGMENT | PPC_EXTERN;
3797 pcc->msr_mask = (1ull << MSR_POW) |
3798 (1ull << MSR_TGPR) |
3799 (1ull << MSR_ILE) |
3800 (1ull << MSR_EE) |
3801 (1ull << MSR_PR) |
3802 (1ull << MSR_FP) |
3803 (1ull << MSR_ME) |
3804 (1ull << MSR_FE0) |
3805 (1ull << MSR_SE) |
3806 (1ull << MSR_DE) |
3807 (1ull << MSR_FE1) |
3808 (1ull << MSR_EP) |
3809 (1ull << MSR_IR) |
3810 (1ull << MSR_DR) |
3811 (1ull << MSR_RI) |
3812 (1ull << MSR_LE);
3813 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3814 pcc->excp_model = POWERPC_EXCP_6xx;
3815 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3816 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3817 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3818 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3819 }
3820
3821 static void init_proc_604(CPUPPCState *env)
3822 {
3823 register_ne_601_sprs(env);
3824 register_sdr1_sprs(env);
3825 register_604_sprs(env);
3826 /* Time base */
3827 register_tbl(env);
3828 /* Hardware implementation registers */
3829 /* XXX : not implemented */
3830 spr_register(env, SPR_HID0, "HID0",
3831 SPR_NOACCESS, SPR_NOACCESS,
3832 &spr_read_generic, &spr_write_generic,
3833 0x00000000);
3834 /* Memory management */
3835 register_low_BATs(env);
3836 init_excp_604(env);
3837 env->dcache_line_size = 32;
3838 env->icache_line_size = 32;
3839 /* Allocate hardware IRQ controller */
3840 ppc6xx_irq_init(env_archcpu(env));
3841 }
3842
3843 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3844 {
3845 DeviceClass *dc = DEVICE_CLASS(oc);
3846 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3847
3848 dc->desc = "PowerPC 604";
3849 pcc->init_proc = init_proc_604;
3850 pcc->check_pow = check_pow_nocheck;
3851 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3852 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3853 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3854 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3855 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3856 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3857 PPC_SEGMENT | PPC_EXTERN;
3858 pcc->msr_mask = (1ull << MSR_POW) |
3859 (1ull << MSR_ILE) |
3860 (1ull << MSR_EE) |
3861 (1ull << MSR_PR) |
3862 (1ull << MSR_FP) |
3863 (1ull << MSR_ME) |
3864 (1ull << MSR_FE0) |
3865 (1ull << MSR_SE) |
3866 (1ull << MSR_DE) |
3867 (1ull << MSR_FE1) |
3868 (1ull << MSR_EP) |
3869 (1ull << MSR_IR) |
3870 (1ull << MSR_DR) |
3871 (1ull << MSR_PMM) |
3872 (1ull << MSR_RI) |
3873 (1ull << MSR_LE);
3874 pcc->mmu_model = POWERPC_MMU_32B;
3875 pcc->excp_model = POWERPC_EXCP_6xx;
3876 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3877 pcc->bfd_mach = bfd_mach_ppc_604;
3878 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3879 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3880 }
3881
3882 static void init_proc_604E(CPUPPCState *env)
3883 {
3884 register_ne_601_sprs(env);
3885 register_sdr1_sprs(env);
3886 register_604_sprs(env);
3887 /* XXX : not implemented */
3888 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
3889 SPR_NOACCESS, SPR_NOACCESS,
3890 &spr_read_generic, &spr_write_generic,
3891 0x00000000);
3892 /* XXX : not implemented */
3893 spr_register(env, SPR_7XX_PMC3, "PMC3",
3894 SPR_NOACCESS, SPR_NOACCESS,
3895 &spr_read_generic, &spr_write_generic,
3896 0x00000000);
3897 /* XXX : not implemented */
3898 spr_register(env, SPR_7XX_PMC4, "PMC4",
3899 SPR_NOACCESS, SPR_NOACCESS,
3900 &spr_read_generic, &spr_write_generic,
3901 0x00000000);
3902 /* Time base */
3903 register_tbl(env);
3904 /* Hardware implementation registers */
3905 /* XXX : not implemented */
3906 spr_register(env, SPR_HID0, "HID0",
3907 SPR_NOACCESS, SPR_NOACCESS,
3908 &spr_read_generic, &spr_write_generic,
3909 0x00000000);
3910 /* XXX : not implemented */
3911 spr_register(env, SPR_HID1, "HID1",
3912 SPR_NOACCESS, SPR_NOACCESS,
3913 &spr_read_generic, &spr_write_generic,
3914 0x00000000);
3915 /* Memory management */
3916 register_low_BATs(env);
3917 init_excp_604(env);
3918 env->dcache_line_size = 32;
3919 env->icache_line_size = 32;
3920 /* Allocate hardware IRQ controller */
3921 ppc6xx_irq_init(env_archcpu(env));
3922 }
3923
3924 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3925 {
3926 DeviceClass *dc = DEVICE_CLASS(oc);
3927 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3928
3929 dc->desc = "PowerPC 604E";
3930 pcc->init_proc = init_proc_604E;
3931 pcc->check_pow = check_pow_nocheck;
3932 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3933 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3934 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3935 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3936 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3937 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3938 PPC_SEGMENT | PPC_EXTERN;
3939 pcc->msr_mask = (1ull << MSR_POW) |
3940 (1ull << MSR_ILE) |
3941 (1ull << MSR_EE) |
3942 (1ull << MSR_PR) |
3943 (1ull << MSR_FP) |
3944 (1ull << MSR_ME) |
3945 (1ull << MSR_FE0) |
3946 (1ull << MSR_SE) |
3947 (1ull << MSR_DE) |
3948 (1ull << MSR_FE1) |
3949 (1ull << MSR_EP) |
3950 (1ull << MSR_IR) |
3951 (1ull << MSR_DR) |
3952 (1ull << MSR_PMM) |
3953 (1ull << MSR_RI) |
3954 (1ull << MSR_LE);
3955 pcc->mmu_model = POWERPC_MMU_32B;
3956 pcc->excp_model = POWERPC_EXCP_6xx;
3957 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3958 pcc->bfd_mach = bfd_mach_ppc_604;
3959 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3960 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3961 }
3962
3963 static void init_proc_740(CPUPPCState *env)
3964 {
3965 register_ne_601_sprs(env);
3966 register_sdr1_sprs(env);
3967 register_7xx_sprs(env);
3968 /* Time base */
3969 register_tbl(env);
3970 /* Thermal management */
3971 register_thrm_sprs(env);
3972 /* Hardware implementation registers */
3973 /* XXX : not implemented */
3974 spr_register(env, SPR_HID0, "HID0",
3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_generic,
3977 0x00000000);
3978 /* XXX : not implemented */
3979 spr_register(env, SPR_HID1, "HID1",
3980 SPR_NOACCESS, SPR_NOACCESS,
3981 &spr_read_generic, &spr_write_generic,
3982 0x00000000);
3983 /* Memory management */
3984 register_low_BATs(env);
3985 init_excp_7x0(env);
3986 env->dcache_line_size = 32;
3987 env->icache_line_size = 32;
3988 /* Allocate hardware IRQ controller */
3989 ppc6xx_irq_init(env_archcpu(env));
3990 }
3991
3992 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3993 {
3994 DeviceClass *dc = DEVICE_CLASS(oc);
3995 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3996
3997 dc->desc = "PowerPC 740";
3998 pcc->init_proc = init_proc_740;
3999 pcc->check_pow = check_pow_hid0;
4000 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4001 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4002 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4003 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4004 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4005 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4006 PPC_SEGMENT | PPC_EXTERN;
4007 pcc->msr_mask = (1ull << MSR_POW) |
4008 (1ull << MSR_ILE) |
4009 (1ull << MSR_EE) |
4010 (1ull << MSR_PR) |
4011 (1ull << MSR_FP) |
4012 (1ull << MSR_ME) |
4013 (1ull << MSR_FE0) |
4014 (1ull << MSR_SE) |
4015 (1ull << MSR_DE) |
4016 (1ull << MSR_FE1) |
4017 (1ull << MSR_EP) |
4018 (1ull << MSR_IR) |
4019 (1ull << MSR_DR) |
4020 (1ull << MSR_PMM) |
4021 (1ull << MSR_RI) |
4022 (1ull << MSR_LE);
4023 pcc->mmu_model = POWERPC_MMU_32B;
4024 pcc->excp_model = POWERPC_EXCP_7xx;
4025 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4026 pcc->bfd_mach = bfd_mach_ppc_750;
4027 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4028 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4029 }
4030
4031 static void init_proc_750(CPUPPCState *env)
4032 {
4033 register_ne_601_sprs(env);
4034 register_sdr1_sprs(env);
4035 register_7xx_sprs(env);
4036 /* XXX : not implemented */
4037 spr_register(env, SPR_L2CR, "L2CR",
4038 SPR_NOACCESS, SPR_NOACCESS,
4039 &spr_read_generic, spr_access_nop,
4040 0x00000000);
4041 /* Time base */
4042 register_tbl(env);
4043 /* Thermal management */
4044 register_thrm_sprs(env);
4045 /* Hardware implementation registers */
4046 /* XXX : not implemented */
4047 spr_register(env, SPR_HID0, "HID0",
4048 SPR_NOACCESS, SPR_NOACCESS,
4049 &spr_read_generic, &spr_write_generic,
4050 0x00000000);
4051 /* XXX : not implemented */
4052 spr_register(env, SPR_HID1, "HID1",
4053 SPR_NOACCESS, SPR_NOACCESS,
4054 &spr_read_generic, &spr_write_generic,
4055 0x00000000);
4056 /* Memory management */
4057 register_low_BATs(env);
4058 /*
4059 * XXX: high BATs are also present but are known to be bugged on
4060 * die version 1.x
4061 */
4062 init_excp_7x0(env);
4063 env->dcache_line_size = 32;
4064 env->icache_line_size = 32;
4065 /* Allocate hardware IRQ controller */
4066 ppc6xx_irq_init(env_archcpu(env));
4067 }
4068
4069 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
4070 {
4071 DeviceClass *dc = DEVICE_CLASS(oc);
4072 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4073
4074 dc->desc = "PowerPC 750";
4075 pcc->init_proc = init_proc_750;
4076 pcc->check_pow = check_pow_hid0;
4077 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4078 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4079 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4080 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4081 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4082 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4083 PPC_SEGMENT | PPC_EXTERN;
4084 pcc->msr_mask = (1ull << MSR_POW) |
4085 (1ull << MSR_ILE) |
4086 (1ull << MSR_EE) |
4087 (1ull << MSR_PR) |
4088 (1ull << MSR_FP) |
4089 (1ull << MSR_ME) |
4090 (1ull << MSR_FE0) |
4091 (1ull << MSR_SE) |
4092 (1ull << MSR_DE) |
4093 (1ull << MSR_FE1) |
4094 (1ull << MSR_EP) |
4095 (1ull << MSR_IR) |
4096 (1ull << MSR_DR) |
4097 (1ull << MSR_PMM) |
4098 (1ull << MSR_RI) |
4099 (1ull << MSR_LE);
4100 pcc->mmu_model = POWERPC_MMU_32B;
4101 pcc->excp_model = POWERPC_EXCP_7xx;
4102 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4103 pcc->bfd_mach = bfd_mach_ppc_750;
4104 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4105 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4106 }
4107
4108 static void init_proc_750cl(CPUPPCState *env)
4109 {
4110 register_ne_601_sprs(env);
4111 register_sdr1_sprs(env);
4112 register_7xx_sprs(env);
4113 /* XXX : not implemented */
4114 spr_register(env, SPR_L2CR, "L2CR",
4115 SPR_NOACCESS, SPR_NOACCESS,
4116 &spr_read_generic, spr_access_nop,
4117 0x00000000);
4118 /* Time base */
4119 register_tbl(env);
4120 /* Thermal management */
4121 /* Those registers are fake on 750CL */
4122 spr_register(env, SPR_THRM1, "THRM1",
4123 SPR_NOACCESS, SPR_NOACCESS,
4124 &spr_read_generic, &spr_write_generic,
4125 0x00000000);
4126 spr_register(env, SPR_THRM2, "THRM2",
4127 SPR_NOACCESS, SPR_NOACCESS,
4128 &spr_read_generic, &spr_write_generic,
4129 0x00000000);
4130 spr_register(env, SPR_THRM3, "THRM3",
4131 SPR_NOACCESS, SPR_NOACCESS,
4132 &spr_read_generic, &spr_write_generic,
4133 0x00000000);
4134 /* XXX: not implemented */
4135 spr_register(env, SPR_750_TDCL, "TDCL",
4136 SPR_NOACCESS, SPR_NOACCESS,
4137 &spr_read_generic, &spr_write_generic,
4138 0x00000000);
4139 spr_register(env, SPR_750_TDCH, "TDCH",
4140 SPR_NOACCESS, SPR_NOACCESS,
4141 &spr_read_generic, &spr_write_generic,
4142 0x00000000);
4143 /* DMA */
4144 /* XXX : not implemented */
4145 spr_register(env, SPR_750_WPAR, "WPAR",
4146 SPR_NOACCESS, SPR_NOACCESS,
4147 &spr_read_generic, &spr_write_generic,
4148 0x00000000);
4149 spr_register(env, SPR_750_DMAL, "DMAL",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
4152 0x00000000);
4153 spr_register(env, SPR_750_DMAU, "DMAU",
4154 SPR_NOACCESS, SPR_NOACCESS,
4155 &spr_read_generic, &spr_write_generic,
4156 0x00000000);
4157 /* Hardware implementation registers */
4158 /* XXX : not implemented */
4159 spr_register(env, SPR_HID0, "HID0",
4160 SPR_NOACCESS, SPR_NOACCESS,
4161 &spr_read_generic, &spr_write_generic,
4162 0x00000000);
4163 /* XXX : not implemented */
4164 spr_register(env, SPR_HID1, "HID1",
4165 SPR_NOACCESS, SPR_NOACCESS,
4166 &spr_read_generic, &spr_write_generic,
4167 0x00000000);
4168 /* XXX : not implemented */
4169 spr_register(env, SPR_750CL_HID2, "HID2",
4170 SPR_NOACCESS, SPR_NOACCESS,
4171 &spr_read_generic, &spr_write_generic,
4172 0x00000000);
4173 /* XXX : not implemented */
4174 spr_register(env, SPR_750CL_HID4, "HID4",
4175 SPR_NOACCESS, SPR_NOACCESS,
4176 &spr_read_generic, &spr_write_generic,
4177 0x00000000);
4178 /* Quantization registers */
4179 /* XXX : not implemented */
4180 spr_register(env, SPR_750_GQR0, "GQR0",
4181 SPR_NOACCESS, SPR_NOACCESS,
4182 &spr_read_generic, &spr_write_generic,
4183 0x00000000);
4184 /* XXX : not implemented */
4185 spr_register(env, SPR_750_GQR1, "GQR1",
4186 SPR_NOACCESS, SPR_NOACCESS,
4187 &spr_read_generic, &spr_write_generic,
4188 0x00000000);
4189 /* XXX : not implemented */
4190 spr_register(env, SPR_750_GQR2, "GQR2",
4191 SPR_NOACCESS, SPR_NOACCESS,
4192 &spr_read_generic, &spr_write_generic,
4193 0x00000000);
4194 /* XXX : not implemented */
4195 spr_register(env, SPR_750_GQR3, "GQR3",
4196 SPR_NOACCESS, SPR_NOACCESS,
4197 &spr_read_generic, &spr_write_generic,
4198 0x00000000);
4199 /* XXX : not implemented */
4200 spr_register(env, SPR_750_GQR4, "GQR4",
4201 SPR_NOACCESS, SPR_NOACCESS,
4202 &spr_read_generic, &spr_write_generic,
4203 0x00000000);
4204 /* XXX : not implemented */
4205 spr_register(env, SPR_750_GQR5, "GQR5",
4206 SPR_NOACCESS, SPR_NOACCESS,
4207 &spr_read_generic, &spr_write_generic,
4208 0x00000000);
4209 /* XXX : not implemented */
4210 spr_register(env, SPR_750_GQR6, "GQR6",
4211 SPR_NOACCESS, SPR_NOACCESS,
4212 &spr_read_generic, &spr_write_generic,
4213 0x00000000);
4214 /* XXX : not implemented */
4215 spr_register(env, SPR_750_GQR7, "GQR7",
4216 SPR_NOACCESS, SPR_NOACCESS,
4217 &spr_read_generic, &spr_write_generic,
4218 0x00000000);
4219 /* Memory management */
4220 register_low_BATs(env);
4221 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4222 register_high_BATs(env);
4223 init_excp_750cl(env);
4224 env->dcache_line_size = 32;
4225 env->icache_line_size = 32;
4226 /* Allocate hardware IRQ controller */
4227 ppc6xx_irq_init(env_archcpu(env));
4228 }
4229
4230 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
4231 {
4232 DeviceClass *dc = DEVICE_CLASS(oc);
4233 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4234
4235 dc->desc = "PowerPC 750 CL";
4236 pcc->init_proc = init_proc_750cl;
4237 pcc->check_pow = check_pow_hid0;
4238 /*
4239 * XXX: not implemented:
4240 * cache lock instructions:
4241 * dcbz_l
4242 * floating point paired instructions
4243 * psq_lux
4244 * psq_lx
4245 * psq_stux
4246 * psq_stx
4247 * ps_abs
4248 * ps_add
4249 * ps_cmpo0
4250 * ps_cmpo1
4251 * ps_cmpu0
4252 * ps_cmpu1
4253 * ps_div
4254 * ps_madd
4255 * ps_madds0
4256 * ps_madds1
4257 * ps_merge00
4258 * ps_merge01
4259 * ps_merge10
4260 * ps_merge11
4261 * ps_mr
4262 * ps_msub
4263 * ps_mul
4264 * ps_muls0
4265 * ps_muls1
4266 * ps_nabs
4267 * ps_neg
4268 * ps_nmadd
4269 * ps_nmsub
4270 * ps_res
4271 * ps_rsqrte
4272 * ps_sel
4273 * ps_sub
4274 * ps_sum0
4275 * ps_sum1
4276 */
4277 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4278 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4279 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4280 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4281 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4282 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4283 PPC_SEGMENT | PPC_EXTERN;
4284 pcc->msr_mask = (1ull << MSR_POW) |
4285 (1ull << MSR_ILE) |
4286 (1ull << MSR_EE) |
4287 (1ull << MSR_PR) |
4288 (1ull << MSR_FP) |
4289 (1ull << MSR_ME) |
4290 (1ull << MSR_FE0) |
4291 (1ull << MSR_SE) |
4292 (1ull << MSR_DE) |
4293 (1ull << MSR_FE1) |
4294 (1ull << MSR_EP) |
4295 (1ull << MSR_IR) |
4296 (1ull << MSR_DR) |
4297 (1ull << MSR_PMM) |
4298 (1ull << MSR_RI) |
4299 (1ull << MSR_LE);
4300 pcc->mmu_model = POWERPC_MMU_32B;
4301 pcc->excp_model = POWERPC_EXCP_7xx;
4302 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4303 pcc->bfd_mach = bfd_mach_ppc_750;
4304 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4305 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4306 }
4307
4308 static void init_proc_750cx(CPUPPCState *env)
4309 {
4310 register_ne_601_sprs(env);
4311 register_sdr1_sprs(env);
4312 register_7xx_sprs(env);
4313 /* XXX : not implemented */
4314 spr_register(env, SPR_L2CR, "L2CR",
4315 SPR_NOACCESS, SPR_NOACCESS,
4316 &spr_read_generic, spr_access_nop,
4317 0x00000000);
4318 /* Time base */
4319 register_tbl(env);
4320 /* Thermal management */
4321 register_thrm_sprs(env);
4322 /* This register is not implemented but is present for compatibility */
4323 spr_register(env, SPR_SDA, "SDA",
4324 SPR_NOACCESS, SPR_NOACCESS,
4325 &spr_read_generic, &spr_write_generic,
4326 0x00000000);
4327 /* Hardware implementation registers */
4328 /* XXX : not implemented */
4329 spr_register(env, SPR_HID0, "HID0",
4330 SPR_NOACCESS, SPR_NOACCESS,
4331 &spr_read_generic, &spr_write_generic,
4332 0x00000000);
4333 /* XXX : not implemented */
4334 spr_register(env, SPR_HID1, "HID1",
4335 SPR_NOACCESS, SPR_NOACCESS,
4336 &spr_read_generic, &spr_write_generic,
4337 0x00000000);
4338 /* Memory management */
4339 register_low_BATs(env);
4340 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4341 register_high_BATs(env);
4342 init_excp_750cx(env);
4343 env->dcache_line_size = 32;
4344 env->icache_line_size = 32;
4345 /* Allocate hardware IRQ controller */
4346 ppc6xx_irq_init(env_archcpu(env));
4347 }
4348
4349 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
4350 {
4351 DeviceClass *dc = DEVICE_CLASS(oc);
4352 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4353
4354 dc->desc = "PowerPC 750CX";
4355 pcc->init_proc = init_proc_750cx;
4356 pcc->check_pow = check_pow_hid0;
4357 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4358 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4359 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4360 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4361 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4362 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4363 PPC_SEGMENT | PPC_EXTERN;
4364 pcc->msr_mask = (1ull << MSR_POW) |
4365 (1ull << MSR_ILE) |
4366 (1ull << MSR_EE) |
4367 (1ull << MSR_PR) |
4368 (1ull << MSR_FP) |
4369 (1ull << MSR_ME) |
4370 (1ull << MSR_FE0) |
4371 (1ull << MSR_SE) |
4372 (1ull << MSR_DE) |
4373 (1ull << MSR_FE1) |
4374 (1ull << MSR_EP) |
4375 (1ull << MSR_IR) |
4376 (1ull << MSR_DR) |
4377 (1ull << MSR_PMM) |
4378 (1ull << MSR_RI) |
4379 (1ull << MSR_LE);
4380 pcc->mmu_model = POWERPC_MMU_32B;
4381 pcc->excp_model = POWERPC_EXCP_7xx;
4382 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4383 pcc->bfd_mach = bfd_mach_ppc_750;
4384 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4385 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4386 }
4387
4388 static void init_proc_750fx(CPUPPCState *env)
4389 {
4390 register_ne_601_sprs(env);
4391 register_sdr1_sprs(env);
4392 register_7xx_sprs(env);
4393 /* XXX : not implemented */
4394 spr_register(env, SPR_L2CR, "L2CR",
4395 SPR_NOACCESS, SPR_NOACCESS,
4396 &spr_read_generic, spr_access_nop,
4397 0x00000000);
4398 /* Time base */
4399 register_tbl(env);
4400 /* Thermal management */
4401 register_thrm_sprs(env);
4402 /* XXX : not implemented */
4403 spr_register(env, SPR_750_THRM4, "THRM4",
4404 SPR_NOACCESS, SPR_NOACCESS,
4405 &spr_read_generic, &spr_write_generic,
4406 0x00000000);
4407 /* Hardware implementation registers */
4408 /* XXX : not implemented */
4409 spr_register(env, SPR_HID0, "HID0",
4410 SPR_NOACCESS, SPR_NOACCESS,
4411 &spr_read_generic, &spr_write_generic,
4412 0x00000000);
4413 /* XXX : not implemented */
4414 spr_register(env, SPR_HID1, "HID1",
4415 SPR_NOACCESS, SPR_NOACCESS,
4416 &spr_read_generic, &spr_write_generic,
4417 0x00000000);
4418 /* XXX : not implemented */
4419 spr_register(env, SPR_750FX_HID2, "HID2",
4420 SPR_NOACCESS, SPR_NOACCESS,
4421 &spr_read_generic, &spr_write_generic,
4422 0x00000000);
4423 /* Memory management */
4424 register_low_BATs(env);
4425 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4426 register_high_BATs(env);
4427 init_excp_7x0(env);
4428 env->dcache_line_size = 32;
4429 env->icache_line_size = 32;
4430 /* Allocate hardware IRQ controller */
4431 ppc6xx_irq_init(env_archcpu(env));
4432 }
4433
4434 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
4435 {
4436 DeviceClass *dc = DEVICE_CLASS(oc);
4437 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4438
4439 dc->desc = "PowerPC 750FX";
4440 pcc->init_proc = init_proc_750fx;
4441 pcc->check_pow = check_pow_hid0;
4442 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4443 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4444 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4445 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4446 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4447 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4448 PPC_SEGMENT | PPC_EXTERN;
4449 pcc->msr_mask = (1ull << MSR_POW) |
4450 (1ull << MSR_ILE) |
4451 (1ull << MSR_EE) |
4452 (1ull << MSR_PR) |
4453 (1ull << MSR_FP) |
4454 (1ull << MSR_ME) |
4455 (1ull << MSR_FE0) |
4456 (1ull << MSR_SE) |
4457 (1ull << MSR_DE) |
4458 (1ull << MSR_FE1) |
4459 (1ull << MSR_EP) |
4460 (1ull << MSR_IR) |
4461 (1ull << MSR_DR) |
4462 (1ull << MSR_PMM) |
4463 (1ull << MSR_RI) |
4464 (1ull << MSR_LE);
4465 pcc->mmu_model = POWERPC_MMU_32B;
4466 pcc->excp_model = POWERPC_EXCP_7xx;
4467 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4468 pcc->bfd_mach = bfd_mach_ppc_750;
4469 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4470 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4471 }
4472
4473 static void init_proc_750gx(CPUPPCState *env)
4474 {
4475 register_ne_601_sprs(env);
4476 register_sdr1_sprs(env);
4477 register_7xx_sprs(env);
4478 /* XXX : not implemented (XXX: different from 750fx) */
4479 spr_register(env, SPR_L2CR, "L2CR",
4480 SPR_NOACCESS, SPR_NOACCESS,
4481 &spr_read_generic, spr_access_nop,
4482 0x00000000);
4483 /* Time base */
4484 register_tbl(env);
4485 /* Thermal management */
4486 register_thrm_sprs(env);
4487 /* XXX : not implemented */
4488 spr_register(env, SPR_750_THRM4, "THRM4",
4489 SPR_NOACCESS, SPR_NOACCESS,
4490 &spr_read_generic, &spr_write_generic,
4491 0x00000000);
4492 /* Hardware implementation registers */
4493 /* XXX : not implemented (XXX: different from 750fx) */
4494 spr_register(env, SPR_HID0, "HID0",
4495 SPR_NOACCESS, SPR_NOACCESS,
4496 &spr_read_generic, &spr_write_generic,
4497 0x00000000);
4498 /* XXX : not implemented */
4499 spr_register(env, SPR_HID1, "HID1",
4500 SPR_NOACCESS, SPR_NOACCESS,
4501 &spr_read_generic, &spr_write_generic,
4502 0x00000000);
4503 /* XXX : not implemented (XXX: different from 750fx) */
4504 spr_register(env, SPR_750FX_HID2, "HID2",
4505 SPR_NOACCESS, SPR_NOACCESS,
4506 &spr_read_generic, &spr_write_generic,
4507 0x00000000);
4508 /* Memory management */
4509 register_low_BATs(env);
4510 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4511 register_high_BATs(env);
4512 init_excp_7x0(env);
4513 env->dcache_line_size = 32;
4514 env->icache_line_size = 32;
4515 /* Allocate hardware IRQ controller */
4516 ppc6xx_irq_init(env_archcpu(env));
4517 }
4518
4519 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
4520 {
4521 DeviceClass *dc = DEVICE_CLASS(oc);
4522 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4523
4524 dc->desc = "PowerPC 750GX";
4525 pcc->init_proc = init_proc_750gx;
4526 pcc->check_pow = check_pow_hid0;
4527 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4528 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4529 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4530 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4531 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4532 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4533 PPC_SEGMENT | PPC_EXTERN;
4534 pcc->msr_mask = (1ull << MSR_POW) |
4535 (1ull << MSR_ILE) |
4536 (1ull << MSR_EE) |
4537 (1ull << MSR_PR) |
4538 (1ull << MSR_FP) |
4539 (1ull << MSR_ME) |
4540 (1ull << MSR_FE0) |
4541 (1ull << MSR_SE) |
4542 (1ull << MSR_DE) |
4543 (1ull << MSR_FE1) |
4544 (1ull << MSR_EP) |
4545 (1ull << MSR_IR) |
4546 (1ull << MSR_DR) |
4547 (1ull << MSR_PMM) |
4548 (1ull << MSR_RI) |
4549 (1ull << MSR_LE);
4550 pcc->mmu_model = POWERPC_MMU_32B;
4551 pcc->excp_model = POWERPC_EXCP_7xx;
4552 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4553 pcc->bfd_mach = bfd_mach_ppc_750;
4554 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4555 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4556 }
4557
4558 static void init_proc_745(CPUPPCState *env)
4559 {
4560 register_ne_601_sprs(env);
4561 register_sdr1_sprs(env);
4562 register_7xx_sprs(env);
4563 register_G2_755_sprs(env);
4564 /* Time base */
4565 register_tbl(env);
4566 /* Thermal management */
4567 register_thrm_sprs(env);
4568 /* Hardware implementation registers */
4569 /* XXX : not implemented */
4570 spr_register(env, SPR_HID0, "HID0",
4571 SPR_NOACCESS, SPR_NOACCESS,
4572 &spr_read_generic, &spr_write_generic,
4573 0x00000000);
4574 /* XXX : not implemented */
4575 spr_register(env, SPR_HID1, "HID1",
4576 SPR_NOACCESS, SPR_NOACCESS,
4577 &spr_read_generic, &spr_write_generic,
4578 0x00000000);
4579 /* XXX : not implemented */
4580 spr_register(env, SPR_HID2, "HID2",
4581 SPR_NOACCESS, SPR_NOACCESS,
4582 &spr_read_generic, &spr_write_generic,
4583 0x00000000);
4584 /* Memory management */
4585 register_low_BATs(env);
4586 register_high_BATs(env);
4587 register_6xx_7xx_soft_tlb(env, 64, 2);
4588 init_excp_7x5(env);
4589 env->dcache_line_size = 32;
4590 env->icache_line_size = 32;
4591 /* Allocate hardware IRQ controller */
4592 ppc6xx_irq_init(env_archcpu(env));
4593 }
4594
4595 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4596 {
4597 DeviceClass *dc = DEVICE_CLASS(oc);
4598 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4599
4600 dc->desc = "PowerPC 745";
4601 pcc->init_proc = init_proc_745;
4602 pcc->check_pow = check_pow_hid0;
4603 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4604 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4605 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4606 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4607 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4608 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4609 PPC_SEGMENT | PPC_EXTERN;
4610 pcc->msr_mask = (1ull << MSR_POW) |
4611 (1ull << MSR_ILE) |
4612 (1ull << MSR_EE) |
4613 (1ull << MSR_PR) |
4614 (1ull << MSR_FP) |
4615 (1ull << MSR_ME) |
4616 (1ull << MSR_FE0) |
4617 (1ull << MSR_SE) |
4618 (1ull << MSR_DE) |
4619 (1ull << MSR_FE1) |
4620 (1ull << MSR_EP) |
4621 (1ull << MSR_IR) |
4622 (1ull << MSR_DR) |
4623 (1ull << MSR_PMM) |
4624 (1ull << MSR_RI) |
4625 (1ull << MSR_LE);
4626 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4627 pcc->excp_model = POWERPC_EXCP_7xx;
4628 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4629 pcc->bfd_mach = bfd_mach_ppc_750;
4630 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4631 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4632 }
4633
4634 static void init_proc_755(CPUPPCState *env)
4635 {
4636 register_ne_601_sprs(env);
4637 register_sdr1_sprs(env);
4638 register_7xx_sprs(env);
4639 register_G2_755_sprs(env);
4640 /* Time base */
4641 register_tbl(env);
4642 /* L2 cache control */
4643 /* XXX : not implemented */
4644 spr_register(env, SPR_L2CR, "L2CR",
4645 SPR_NOACCESS, SPR_NOACCESS,
4646 &spr_read_generic, spr_access_nop,
4647 0x00000000);
4648 /* XXX : not implemented */
4649 spr_register(env, SPR_L2PMCR, "L2PMCR",
4650 SPR_NOACCESS, SPR_NOACCESS,
4651 &spr_read_generic, &spr_write_generic,
4652 0x00000000);
4653 /* Thermal management */
4654 register_thrm_sprs(env);
4655 /* Hardware implementation registers */
4656 /* XXX : not implemented */
4657 spr_register(env, SPR_HID0, "HID0",
4658 SPR_NOACCESS, SPR_NOACCESS,
4659 &spr_read_generic, &spr_write_generic,
4660 0x00000000);
4661 /* XXX : not implemented */
4662 spr_register(env, SPR_HID1, "HID1",
4663 SPR_NOACCESS, SPR_NOACCESS,
4664 &spr_read_generic, &spr_write_generic,
4665 0x00000000);
4666 /* XXX : not implemented */
4667 spr_register(env, SPR_HID2, "HID2",
4668 SPR_NOACCESS, SPR_NOACCESS,
4669 &spr_read_generic, &spr_write_generic,
4670 0x00000000);
4671 /* Memory management */
4672 register_low_BATs(env);
4673 register_high_BATs(env);
4674 register_6xx_7xx_soft_tlb(env, 64, 2);
4675 init_excp_7x5(env);
4676 env->dcache_line_size = 32;
4677 env->icache_line_size = 32;
4678 /* Allocate hardware IRQ controller */
4679 ppc6xx_irq_init(env_archcpu(env));
4680 }
4681
4682 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4683 {
4684 DeviceClass *dc = DEVICE_CLASS(oc);
4685 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4686
4687 dc->desc = "PowerPC 755";
4688 pcc->init_proc = init_proc_755;
4689 pcc->check_pow = check_pow_hid0;
4690 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4691 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4692 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4693 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4694 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4695 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4696 PPC_SEGMENT | PPC_EXTERN;
4697 pcc->msr_mask = (1ull << MSR_POW) |
4698 (1ull << MSR_ILE) |
4699 (1ull << MSR_EE) |
4700 (1ull << MSR_PR) |
4701 (1ull << MSR_FP) |
4702 (1ull << MSR_ME) |
4703 (1ull << MSR_FE0) |
4704 (1ull << MSR_SE) |
4705 (1ull << MSR_DE) |
4706 (1ull << MSR_FE1) |
4707 (1ull << MSR_EP) |
4708 (1ull << MSR_IR) |
4709 (1ull << MSR_DR) |
4710 (1ull << MSR_PMM) |
4711 (1ull << MSR_RI) |
4712 (1ull << MSR_LE);
4713 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4714 pcc->excp_model = POWERPC_EXCP_7xx;
4715 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4716 pcc->bfd_mach = bfd_mach_ppc_750;
4717 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4718 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4719 }
4720
4721 static void init_proc_7400(CPUPPCState *env)
4722 {
4723 register_ne_601_sprs(env);
4724 register_sdr1_sprs(env);
4725 register_7xx_sprs(env);
4726 /* Time base */
4727 register_tbl(env);
4728 /* 74xx specific SPR */
4729 register_74xx_sprs(env);
4730 vscr_init(env, 0x00010000);
4731 /* XXX : not implemented */
4732 spr_register(env, SPR_UBAMR, "UBAMR",
4733 &spr_read_ureg, SPR_NOACCESS,
4734 &spr_read_ureg, SPR_NOACCESS,
4735 0x00000000);
4736 /* XXX: this seems not implemented on all revisions. */
4737 /* XXX : not implemented */
4738 spr_register(env, SPR_MSSCR1, "MSSCR1",
4739 SPR_NOACCESS, SPR_NOACCESS,
4740 &spr_read_generic, &spr_write_generic,
4741 0x00000000);
4742 /* Thermal management */
4743 register_thrm_sprs(env);
4744 /* Memory management */
4745 register_low_BATs(env);
4746 init_excp_7400(env);
4747 env->dcache_line_size = 32;
4748 env->icache_line_size = 32;
4749 /* Allocate hardware IRQ controller */
4750 ppc6xx_irq_init(env_archcpu(env));
4751 }
4752
4753 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4754 {
4755 DeviceClass *dc = DEVICE_CLASS(oc);
4756 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4757
4758 dc->desc = "PowerPC 7400 (aka G4)";
4759 pcc->init_proc = init_proc_7400;
4760 pcc->check_pow = check_pow_hid0;
4761 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4762 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4763 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4764 PPC_FLOAT_STFIWX |
4765 PPC_CACHE | PPC_CACHE_ICBI |
4766 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4767 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4768 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4769 PPC_MEM_TLBIA |
4770 PPC_SEGMENT | PPC_EXTERN |
4771 PPC_ALTIVEC;
4772 pcc->msr_mask = (1ull << MSR_VR) |
4773 (1ull << MSR_POW) |
4774 (1ull << MSR_ILE) |
4775 (1ull << MSR_EE) |
4776 (1ull << MSR_PR) |
4777 (1ull << MSR_FP) |
4778 (1ull << MSR_ME) |
4779 (1ull << MSR_FE0) |
4780 (1ull << MSR_SE) |
4781 (1ull << MSR_DE) |
4782 (1ull << MSR_FE1) |
4783 (1ull << MSR_EP) |
4784 (1ull << MSR_IR) |
4785 (1ull << MSR_DR) |
4786 (1ull << MSR_PMM) |
4787 (1ull << MSR_RI) |
4788 (1ull << MSR_LE);
4789 pcc->mmu_model = POWERPC_MMU_32B;
4790 pcc->excp_model = POWERPC_EXCP_74xx;
4791 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4792 pcc->bfd_mach = bfd_mach_ppc_7400;
4793 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4794 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4795 POWERPC_FLAG_BUS_CLK;
4796 }
4797
4798 static void init_proc_7410(CPUPPCState *env)
4799 {
4800 register_ne_601_sprs(env);
4801 register_sdr1_sprs(env);
4802 register_7xx_sprs(env);
4803 /* Time base */
4804 register_tbl(env);
4805 /* 74xx specific SPR */
4806 register_74xx_sprs(env);
4807 vscr_init(env, 0x00010000);
4808 /* XXX : not implemented */
4809 spr_register(env, SPR_UBAMR, "UBAMR",
4810 &spr_read_ureg, SPR_NOACCESS,
4811 &spr_read_ureg, SPR_NOACCESS,
4812 0x00000000);
4813 /* Thermal management */
4814 register_thrm_sprs(env);
4815 /* L2PMCR */
4816 /* XXX : not implemented */
4817 spr_register(env, SPR_L2PMCR, "L2PMCR",
4818 SPR_NOACCESS, SPR_NOACCESS,
4819 &spr_read_generic, &spr_write_generic,
4820 0x00000000);
4821 /* LDSTDB */
4822 /* XXX : not implemented */
4823 spr_register(env, SPR_LDSTDB, "LDSTDB",
4824 SPR_NOACCESS, SPR_NOACCESS,
4825 &spr_read_generic, &spr_write_generic,
4826 0x00000000);
4827 /* Memory management */
4828 register_low_BATs(env);
4829 init_excp_7400(env);
4830 env->dcache_line_size = 32;
4831 env->icache_line_size = 32;
4832 /* Allocate hardware IRQ controller */
4833 ppc6xx_irq_init(env_archcpu(env));
4834 }
4835
4836 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4837 {
4838 DeviceClass *dc = DEVICE_CLASS(oc);
4839 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4840
4841 dc->desc = "PowerPC 7410 (aka G4)";
4842 pcc->init_proc = init_proc_7410;
4843 pcc->check_pow = check_pow_hid0;
4844 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4845 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4846 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4847 PPC_FLOAT_STFIWX |
4848 PPC_CACHE | PPC_CACHE_ICBI |
4849 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4850 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4851 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4852 PPC_MEM_TLBIA |
4853 PPC_SEGMENT | PPC_EXTERN |
4854 PPC_ALTIVEC;
4855 pcc->msr_mask = (1ull << MSR_VR) |
4856 (1ull << MSR_POW) |
4857 (1ull << MSR_ILE) |
4858 (1ull << MSR_EE) |
4859 (1ull << MSR_PR) |
4860 (1ull << MSR_FP) |
4861 (1ull << MSR_ME) |
4862 (1ull << MSR_FE0) |
4863 (1ull << MSR_SE) |
4864 (1ull << MSR_DE) |
4865 (1ull << MSR_FE1) |
4866 (1ull << MSR_EP) |
4867 (1ull << MSR_IR) |
4868 (1ull << MSR_DR) |
4869 (1ull << MSR_PMM) |
4870 (1ull << MSR_RI) |
4871 (1ull << MSR_LE);
4872 pcc->mmu_model = POWERPC_MMU_32B;
4873 pcc->excp_model = POWERPC_EXCP_74xx;
4874 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4875 pcc->bfd_mach = bfd_mach_ppc_7400;
4876 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4877 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4878 POWERPC_FLAG_BUS_CLK;
4879 }
4880
4881 static void init_proc_7440(CPUPPCState *env)
4882 {
4883 register_ne_601_sprs(env);
4884 register_sdr1_sprs(env);
4885 register_7xx_sprs(env);
4886 /* Time base */
4887 register_tbl(env);
4888 /* 74xx specific SPR */
4889 register_74xx_sprs(env);
4890 vscr_init(env, 0x00010000);
4891 /* XXX : not implemented */
4892 spr_register(env, SPR_UBAMR, "UBAMR",
4893 &spr_read_ureg, SPR_NOACCESS,
4894 &spr_read_ureg, SPR_NOACCESS,
4895 0x00000000);
4896 /* LDSTCR */
4897 /* XXX : not implemented */
4898 spr_register(env, SPR_LDSTCR, "LDSTCR",
4899 SPR_NOACCESS, SPR_NOACCESS,
4900 &spr_read_generic, &spr_write_generic,
4901 0x00000000);
4902 /* ICTRL */
4903 /* XXX : not implemented */
4904 spr_register(env, SPR_ICTRL, "ICTRL",
4905 SPR_NOACCESS, SPR_NOACCESS,
4906 &spr_read_generic, &spr_write_generic,
4907 0x00000000);
4908 /* MSSSR0 */
4909 /* XXX : not implemented */
4910 spr_register(env, SPR_MSSSR0, "MSSSR0",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914 /* PMC */
4915 /* XXX : not implemented */
4916 spr_register(env, SPR_7XX_PMC5, "PMC5",
4917 SPR_NOACCESS, SPR_NOACCESS,
4918 &spr_read_generic, &spr_write_generic,
4919 0x00000000);
4920 /* XXX : not implemented */
4921 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4922 &spr_read_ureg, SPR_NOACCESS,
4923 &spr_read_ureg, SPR_NOACCESS,
4924 0x00000000);
4925 /* XXX : not implemented */
4926 spr_register(env, SPR_7XX_PMC6, "PMC6",
4927 SPR_NOACCESS, SPR_NOACCESS,
4928 &spr_read_generic, &spr_write_generic,
4929 0x00000000);
4930 /* XXX : not implemented */
4931 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4932 &spr_read_ureg, SPR_NOACCESS,
4933 &spr_read_ureg, SPR_NOACCESS,
4934 0x00000000);
4935 /* Memory management */
4936 register_low_BATs(env);
4937 init_excp_7450(env);
4938 env->dcache_line_size = 32;
4939 env->icache_line_size = 32;
4940 /* Allocate hardware IRQ controller */
4941 ppc6xx_irq_init(env_archcpu(env));
4942 }
4943
4944 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4945 {
4946 DeviceClass *dc = DEVICE_CLASS(oc);
4947 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4948
4949 dc->desc = "PowerPC 7440 (aka G4)";
4950 pcc->init_proc = init_proc_7440;
4951 pcc->check_pow = check_pow_hid0_74xx;
4952 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4953 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4954 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4955 PPC_FLOAT_STFIWX |
4956 PPC_CACHE | PPC_CACHE_ICBI |
4957 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4958 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4959 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4960 PPC_MEM_TLBIA |
4961 PPC_SEGMENT | PPC_EXTERN |
4962 PPC_ALTIVEC;
4963 pcc->msr_mask = (1ull << MSR_VR) |
4964 (1ull << MSR_POW) |
4965 (1ull << MSR_ILE) |
4966 (1ull << MSR_EE) |
4967 (1ull << MSR_PR) |
4968 (1ull << MSR_FP) |
4969 (1ull << MSR_ME) |
4970 (1ull << MSR_FE0) |
4971 (1ull << MSR_SE) |
4972 (1ull << MSR_DE) |
4973 (1ull << MSR_FE1) |
4974 (1ull << MSR_EP) |
4975 (1ull << MSR_IR) |
4976 (1ull << MSR_DR) |
4977 (1ull << MSR_PMM) |
4978 (1ull << MSR_RI) |
4979 (1ull << MSR_LE);
4980 pcc->mmu_model = POWERPC_MMU_32B;
4981 pcc->excp_model = POWERPC_EXCP_74xx;
4982 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4983 pcc->bfd_mach = bfd_mach_ppc_7400;
4984 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4985 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4986 POWERPC_FLAG_BUS_CLK;
4987 }
4988
4989 static void init_proc_7450(CPUPPCState *env)
4990 {
4991 register_ne_601_sprs(env);
4992 register_sdr1_sprs(env);
4993 register_7xx_sprs(env);
4994 /* Time base */
4995 register_tbl(env);
4996 /* 74xx specific SPR */
4997 register_74xx_sprs(env);
4998 vscr_init(env, 0x00010000);
4999 /* Level 3 cache control */
5000 register_l3_ctrl(env);
5001 /* L3ITCR1 */
5002 /* XXX : not implemented */
5003 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5004 SPR_NOACCESS, SPR_NOACCESS,
5005 &spr_read_generic, &spr_write_generic,
5006 0x00000000);
5007 /* L3ITCR2 */
5008 /* XXX : not implemented */
5009 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5010 SPR_NOACCESS, SPR_NOACCESS,
5011 &spr_read_generic, &spr_write_generic,
5012 0x00000000);
5013 /* L3ITCR3 */
5014 /* XXX : not implemented */
5015 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5016 SPR_NOACCESS, SPR_NOACCESS,
5017 &spr_read_generic, &spr_write_generic,
5018 0x00000000);
5019 /* L3OHCR */
5020 /* XXX : not implemented */
5021 spr_register(env, SPR_L3OHCR, "L3OHCR",
5022 SPR_NOACCESS, SPR_NOACCESS,
5023 &spr_read_generic, &spr_write_generic,
5024 0x00000000);
5025 /* XXX : not implemented */
5026 spr_register(env, SPR_UBAMR, "UBAMR",
5027 &spr_read_ureg, SPR_NOACCESS,
5028 &spr_read_ureg, SPR_NOACCESS,
5029 0x00000000);
5030 /* LDSTCR */
5031 /* XXX : not implemented */
5032 spr_register(env, SPR_LDSTCR, "LDSTCR",
5033 SPR_NOACCESS, SPR_NOACCESS,
5034 &spr_read_generic, &spr_write_generic,
5035 0x00000000);
5036 /* ICTRL */
5037 /* XXX : not implemented */
5038 spr_register(env, SPR_ICTRL, "ICTRL",
5039 SPR_NOACCESS, SPR_NOACCESS,
5040 &spr_read_generic, &spr_write_generic,
5041 0x00000000);
5042 /* MSSSR0 */
5043 /* XXX : not implemented */
5044 spr_register(env, SPR_MSSSR0, "MSSSR0",
5045 SPR_NOACCESS, SPR_NOACCESS,
5046 &spr_read_generic, &spr_write_generic,
5047 0x00000000);
5048 /* PMC */
5049 /* XXX : not implemented */
5050 spr_register(env, SPR_7XX_PMC5, "PMC5",
5051 SPR_NOACCESS, SPR_NOACCESS,
5052 &spr_read_generic, &spr_write_generic,
5053 0x00000000);
5054 /* XXX : not implemented */
5055 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5056 &spr_read_ureg, SPR_NOACCESS,
5057 &spr_read_ureg, SPR_NOACCESS,
5058 0x00000000);
5059 /* XXX : not implemented */
5060 spr_register(env, SPR_7XX_PMC6, "PMC6",
5061 SPR_NOACCESS, SPR_NOACCESS,
5062 &spr_read_generic, &spr_write_generic,
5063 0x00000000);
5064 /* XXX : not implemented */
5065 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5066 &spr_read_ureg, SPR_NOACCESS,
5067 &spr_read_ureg, SPR_NOACCESS,
5068 0x00000000);
5069 /* Memory management */
5070 register_low_BATs(env);
5071 init_excp_7450(env);
5072 env->dcache_line_size = 32;
5073 env->icache_line_size = 32;
5074 /* Allocate hardware IRQ controller */
5075 ppc6xx_irq_init(env_archcpu(env));
5076 }
5077
5078 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
5079 {
5080 DeviceClass *dc = DEVICE_CLASS(oc);
5081 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5082
5083 dc->desc = "PowerPC 7450 (aka G4)";
5084 pcc->init_proc = init_proc_7450;
5085 pcc->check_pow = check_pow_hid0_74xx;
5086 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5087 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5088 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5089 PPC_FLOAT_STFIWX |
5090 PPC_CACHE | PPC_CACHE_ICBI |
5091 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5092 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5093 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5094 PPC_MEM_TLBIA |
5095 PPC_SEGMENT | PPC_EXTERN |
5096 PPC_ALTIVEC;
5097 pcc->msr_mask = (1ull << MSR_VR) |
5098 (1ull << MSR_POW) |
5099 (1ull << MSR_ILE) |
5100 (1ull << MSR_EE) |
5101 (1ull << MSR_PR) |
5102 (1ull << MSR_FP) |
5103 (1ull << MSR_ME) |
5104 (1ull << MSR_FE0) |
5105 (1ull << MSR_SE) |
5106 (1ull << MSR_DE) |
5107 (1ull << MSR_FE1) |
5108 (1ull << MSR_EP) |
5109 (1ull << MSR_IR) |
5110 (1ull << MSR_DR) |
5111 (1ull << MSR_PMM) |
5112 (1ull << MSR_RI) |
5113 (1ull << MSR_LE);
5114 pcc->mmu_model = POWERPC_MMU_32B;
5115 pcc->excp_model = POWERPC_EXCP_74xx;
5116 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5117 pcc->bfd_mach = bfd_mach_ppc_7400;
5118 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5119 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5120 POWERPC_FLAG_BUS_CLK;
5121 }
5122
5123 static void init_proc_7445(CPUPPCState *env)
5124 {
5125 register_ne_601_sprs(env);
5126 register_sdr1_sprs(env);
5127 register_7xx_sprs(env);
5128 /* Time base */
5129 register_tbl(env);
5130 /* 74xx specific SPR */
5131 register_74xx_sprs(env);
5132 vscr_init(env, 0x00010000);
5133 /* LDSTCR */
5134 /* XXX : not implemented */
5135 spr_register(env, SPR_LDSTCR, "LDSTCR",
5136 SPR_NOACCESS, SPR_NOACCESS,
5137 &spr_read_generic, &spr_write_generic,
5138 0x00000000);
5139 /* ICTRL */
5140 /* XXX : not implemented */
5141 spr_register(env, SPR_ICTRL, "ICTRL",
5142 SPR_NOACCESS, SPR_NOACCESS,
5143 &spr_read_generic, &spr_write_generic,
5144 0x00000000);
5145 /* MSSSR0 */
5146 /* XXX : not implemented */
5147 spr_register(env, SPR_MSSSR0, "MSSSR0",
5148 SPR_NOACCESS, SPR_NOACCESS,
5149 &spr_read_generic, &spr_write_generic,
5150 0x00000000);
5151 /* PMC */
5152 /* XXX : not implemented */
5153 spr_register(env, SPR_7XX_PMC5, "PMC5",
5154 SPR_NOACCESS, SPR_NOACCESS,
5155 &spr_read_generic, &spr_write_generic,
5156 0x00000000);
5157 /* XXX : not implemented */
5158 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5159 &spr_read_ureg, SPR_NOACCESS,
5160 &spr_read_ureg, SPR_NOACCESS,
5161 0x00000000);
5162 /* XXX : not implemented */
5163 spr_register(env, SPR_7XX_PMC6, "PMC6",
5164 SPR_NOACCESS, SPR_NOACCESS,
5165 &spr_read_generic, &spr_write_generic,
5166 0x00000000);
5167 /* XXX : not implemented */
5168 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5169 &spr_read_ureg, SPR_NOACCESS,
5170 &spr_read_ureg, SPR_NOACCESS,
5171 0x00000000);
5172 /* SPRGs */
5173 spr_register(env, SPR_SPRG4, "SPRG4",
5174 SPR_NOACCESS, SPR_NOACCESS,
5175 &spr_read_generic, &spr_write_generic,
5176 0x00000000);
5177 spr_register(env, SPR_USPRG4, "USPRG4",
5178 &spr_read_ureg, SPR_NOACCESS,
5179 &spr_read_ureg, SPR_NOACCESS,
5180 0x00000000);
5181 spr_register(env, SPR_SPRG5, "SPRG5",
5182 SPR_NOACCESS, SPR_NOACCESS,
5183 &spr_read_generic, &spr_write_generic,
5184 0x00000000);
5185 spr_register(env, SPR_USPRG5, "USPRG5",
5186 &spr_read_ureg, SPR_NOACCESS,
5187 &spr_read_ureg, SPR_NOACCESS,
5188 0x00000000);
5189 spr_register(env, SPR_SPRG6, "SPRG6",
5190 SPR_NOACCESS, SPR_NOACCESS,
5191 &spr_read_generic, &spr_write_generic,
5192 0x00000000);
5193 spr_register(env, SPR_USPRG6, "USPRG6",
5194 &spr_read_ureg, SPR_NOACCESS,
5195 &spr_read_ureg, SPR_NOACCESS,
5196 0x00000000);
5197 spr_register(env, SPR_SPRG7, "SPRG7",
5198 SPR_NOACCESS, SPR_NOACCESS,
5199 &spr_read_generic, &spr_write_generic,
5200 0x00000000);
5201 spr_register(env, SPR_USPRG7, "USPRG7",
5202 &spr_read_ureg, SPR_NOACCESS,
5203 &spr_read_ureg, SPR_NOACCESS,
5204 0x00000000);
5205 /* Memory management */
5206 register_low_BATs(env);
5207 register_high_BATs(env);
5208 init_excp_7450(env);
5209 env->dcache_line_size = 32;
5210 env->icache_line_size = 32;
5211 /* Allocate hardware IRQ controller */
5212 ppc6xx_irq_init(env_archcpu(env));
5213 }
5214
5215 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
5216 {
5217 DeviceClass *dc = DEVICE_CLASS(oc);
5218 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5219
5220 dc->desc = "PowerPC 7445 (aka G4)";
5221 pcc->init_proc = init_proc_7445;
5222 pcc->check_pow = check_pow_hid0_74xx;
5223 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5224 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5225 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5226 PPC_FLOAT_STFIWX |
5227 PPC_CACHE | PPC_CACHE_ICBI |
5228 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5229 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5230 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5231 PPC_MEM_TLBIA |
5232 PPC_SEGMENT | PPC_EXTERN |
5233 PPC_ALTIVEC;
5234 pcc->msr_mask = (1ull << MSR_VR) |
5235 (1ull << MSR_POW) |
5236 (1ull << MSR_ILE) |
5237 (1ull << MSR_EE) |
5238 (1ull << MSR_PR) |
5239 (1ull << MSR_FP) |
5240 (1ull << MSR_ME) |
5241 (1ull << MSR_FE0) |
5242 (1ull << MSR_SE) |
5243 (1ull << MSR_DE) |
5244 (1ull << MSR_FE1) |
5245 (1ull << MSR_EP) |
5246 (1ull << MSR_IR) |
5247 (1ull << MSR_DR) |
5248 (1ull << MSR_PMM) |
5249 (1ull << MSR_RI) |
5250 (1ull << MSR_LE);
5251 pcc->mmu_model = POWERPC_MMU_32B;
5252 pcc->excp_model = POWERPC_EXCP_74xx;
5253 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5254 pcc->bfd_mach = bfd_mach_ppc_7400;
5255 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5256 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5257 POWERPC_FLAG_BUS_CLK;
5258 }
5259
5260 static void init_proc_7455(CPUPPCState *env)
5261 {
5262 register_ne_601_sprs(env);
5263 register_sdr1_sprs(env);
5264 register_7xx_sprs(env);
5265 /* Time base */
5266 register_tbl(env);
5267 /* 74xx specific SPR */
5268 register_74xx_sprs(env);
5269 vscr_init(env, 0x00010000);
5270 /* Level 3 cache control */
5271 register_l3_ctrl(env);
5272 /* LDSTCR */
5273 /* XXX : not implemented */
5274 spr_register(env, SPR_LDSTCR, "LDSTCR",
5275 SPR_NOACCESS, SPR_NOACCESS,
5276 &spr_read_generic, &spr_write_generic,
5277 0x00000000);
5278 /* ICTRL */
5279 /* XXX : not implemented */
5280 spr_register(env, SPR_ICTRL, "ICTRL",
5281 SPR_NOACCESS, SPR_NOACCESS,
5282 &spr_read_generic, &spr_write_generic,
5283 0x00000000);
5284 /* MSSSR0 */
5285 /* XXX : not implemented */
5286 spr_register(env, SPR_MSSSR0, "MSSSR0",
5287 SPR_NOACCESS, SPR_NOACCESS,
5288 &spr_read_generic, &spr_write_generic,
5289 0x00000000);
5290 /* PMC */
5291 /* XXX : not implemented */
5292 spr_register(env, SPR_7XX_PMC5, "PMC5",
5293 SPR_NOACCESS, SPR_NOACCESS,
5294 &spr_read_generic, &spr_write_generic,
5295 0x00000000);
5296 /* XXX : not implemented */
5297 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5298 &spr_read_ureg, SPR_NOACCESS,
5299 &spr_read_ureg, SPR_NOACCESS,
5300 0x00000000);
5301 /* XXX : not implemented */
5302 spr_register(env, SPR_7XX_PMC6, "PMC6",
5303 SPR_NOACCESS, SPR_NOACCESS,
5304 &spr_read_generic, &spr_write_generic,
5305 0x00000000);
5306 /* XXX : not implemented */
5307 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5308 &spr_read_ureg, SPR_NOACCESS,
5309 &spr_read_ureg, SPR_NOACCESS,
5310 0x00000000);
5311 /* SPRGs */
5312 spr_register(env, SPR_SPRG4, "SPRG4",
5313 SPR_NOACCESS, SPR_NOACCESS,
5314 &spr_read_generic, &spr_write_generic,
5315 0x00000000);
5316 spr_register(env, SPR_USPRG4, "USPRG4",
5317 &spr_read_ureg, SPR_NOACCESS,
5318 &spr_read_ureg, SPR_NOACCESS,
5319 0x00000000);
5320 spr_register(env, SPR_SPRG5, "SPRG5",
5321 SPR_NOACCESS, SPR_NOACCESS,
5322 &spr_read_generic, &spr_write_generic,
5323 0x00000000);
5324 spr_register(env, SPR_USPRG5, "USPRG5",
5325 &spr_read_ureg, SPR_NOACCESS,
5326 &spr_read_ureg, SPR_NOACCESS,
5327 0x00000000);
5328 spr_register(env, SPR_SPRG6, "SPRG6",
5329 SPR_NOACCESS, SPR_NOACCESS,
5330 &spr_read_generic, &spr_write_generic,
5331 0x00000000);
5332 spr_register(env, SPR_USPRG6, "USPRG6",
5333 &spr_read_ureg, SPR_NOACCESS,
5334 &spr_read_ureg, SPR_NOACCESS,
5335 0x00000000);
5336 spr_register(env, SPR_SPRG7, "SPRG7",
5337 SPR_NOACCESS, SPR_NOACCESS,
5338 &spr_read_generic, &spr_write_generic,
5339 0x00000000);
5340 spr_register(env, SPR_USPRG7, "USPRG7",
5341 &spr_read_ureg, SPR_NOACCESS,
5342 &spr_read_ureg, SPR_NOACCESS,
5343 0x00000000);
5344 /* Memory management */
5345 register_low_BATs(env);
5346 register_high_BATs(env);
5347 init_excp_7450(env);
5348 env->dcache_line_size = 32;
5349 env->icache_line_size = 32;
5350 /* Allocate hardware IRQ controller */
5351 ppc6xx_irq_init(env_archcpu(env));
5352 }
5353
5354 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
5355 {
5356 DeviceClass *dc = DEVICE_CLASS(oc);
5357 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5358
5359 dc->desc = "PowerPC 7455 (aka G4)";
5360 pcc->init_proc = init_proc_7455;
5361 pcc->check_pow = check_pow_hid0_74xx;
5362 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5363 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5364 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5365 PPC_FLOAT_STFIWX |
5366 PPC_CACHE | PPC_CACHE_ICBI |
5367 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5368 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5369 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5370 PPC_MEM_TLBIA |
5371 PPC_SEGMENT | PPC_EXTERN |
5372 PPC_ALTIVEC;
5373 pcc->msr_mask = (1ull << MSR_VR) |
5374 (1ull << MSR_POW) |
5375 (1ull << MSR_ILE) |
5376 (1ull << MSR_EE) |
5377 (1ull << MSR_PR) |
5378 (1ull << MSR_FP) |
5379 (1ull << MSR_ME) |
5380 (1ull << MSR_FE0) |
5381 (1ull << MSR_SE) |
5382 (1ull << MSR_DE) |
5383 (1ull << MSR_FE1) |
5384 (1ull << MSR_EP) |
5385 (1ull << MSR_IR) |
5386 (1ull << MSR_DR) |
5387 (1ull << MSR_PMM) |
5388 (1ull << MSR_RI) |
5389 (1ull << MSR_LE);
5390 pcc->mmu_model = POWERPC_MMU_32B;
5391 pcc->excp_model = POWERPC_EXCP_74xx;
5392 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5393 pcc->bfd_mach = bfd_mach_ppc_7400;
5394 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5395 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5396 POWERPC_FLAG_BUS_CLK;
5397 }
5398
5399 static void init_proc_7457(CPUPPCState *env)
5400 {
5401 register_ne_601_sprs(env);
5402 register_sdr1_sprs(env);
5403 register_7xx_sprs(env);
5404 /* Time base */
5405 register_tbl(env);
5406 /* 74xx specific SPR */
5407 register_74xx_sprs(env);
5408 vscr_init(env, 0x00010000);
5409 /* Level 3 cache control */
5410 register_l3_ctrl(env);
5411 /* L3ITCR1 */
5412 /* XXX : not implemented */
5413 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5414 SPR_NOACCESS, SPR_NOACCESS,
5415 &spr_read_generic, &spr_write_generic,
5416 0x00000000);
5417 /* L3ITCR2 */
5418 /* XXX : not implemented */
5419 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 &spr_read_generic, &spr_write_generic,
5422 0x00000000);
5423 /* L3ITCR3 */
5424 /* XXX : not implemented */
5425 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5426 SPR_NOACCESS, SPR_NOACCESS,
5427 &spr_read_generic, &spr_write_generic,
5428 0x00000000);
5429 /* L3OHCR */
5430 /* XXX : not implemented */
5431 spr_register(env, SPR_L3OHCR, "L3OHCR",
5432 SPR_NOACCESS, SPR_NOACCESS,
5433 &spr_read_generic, &spr_write_generic,
5434 0x00000000);
5435 /* LDSTCR */
5436 /* XXX : not implemented */
5437 spr_register(env, SPR_LDSTCR, "LDSTCR",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 /* ICTRL */
5442 /* XXX : not implemented */
5443 spr_register(env, SPR_ICTRL, "ICTRL",
5444 SPR_NOACCESS, SPR_NOACCESS,
5445 &spr_read_generic, &spr_write_generic,
5446 0x00000000);
5447 /* MSSSR0 */
5448 /* XXX : not implemented */
5449 spr_register(env, SPR_MSSSR0, "MSSSR0",
5450 SPR_NOACCESS, SPR_NOACCESS,
5451 &spr_read_generic, &spr_write_generic,
5452 0x00000000);
5453 /* PMC */
5454 /* XXX : not implemented */
5455 spr_register(env, SPR_7XX_PMC5, "PMC5",
5456 SPR_NOACCESS, SPR_NOACCESS,
5457 &spr_read_generic, &spr_write_generic,
5458 0x00000000);
5459 /* XXX : not implemented */
5460 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5461 &spr_read_ureg, SPR_NOACCESS,
5462 &spr_read_ureg, SPR_NOACCESS,
5463 0x00000000);
5464 /* XXX : not implemented */
5465 spr_register(env, SPR_7XX_PMC6, "PMC6",
5466 SPR_NOACCESS, SPR_NOACCESS,
5467 &spr_read_generic, &spr_write_generic,
5468 0x00000000);
5469 /* XXX : not implemented */
5470 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5471 &spr_read_ureg, SPR_NOACCESS,
5472 &spr_read_ureg, SPR_NOACCESS,
5473 0x00000000);
5474 /* SPRGs */
5475 spr_register(env, SPR_SPRG4, "SPRG4",
5476 SPR_NOACCESS, SPR_NOACCESS,
5477 &spr_read_generic, &spr_write_generic,
5478 0x00000000);
5479 spr_register(env, SPR_USPRG4, "USPRG4",
5480 &spr_read_ureg, SPR_NOACCESS,
5481 &spr_read_ureg, SPR_NOACCESS,
5482 0x00000000);
5483 spr_register(env, SPR_SPRG5, "SPRG5",
5484 SPR_NOACCESS, SPR_NOACCESS,
5485 &spr_read_generic, &spr_write_generic,
5486 0x00000000);
5487 spr_register(env, SPR_USPRG5, "USPRG5",
5488 &spr_read_ureg, SPR_NOACCESS,
5489 &spr_read_ureg, SPR_NOACCESS,
5490 0x00000000);
5491 spr_register(env, SPR_SPRG6, "SPRG6",
5492 SPR_NOACCESS, SPR_NOACCESS,
5493 &spr_read_generic, &spr_write_generic,
5494 0x00000000);
5495 spr_register(env, SPR_USPRG6, "USPRG6",
5496 &spr_read_ureg, SPR_NOACCESS,
5497 &spr_read_ureg, SPR_NOACCESS,
5498 0x00000000);
5499 spr_register(env, SPR_SPRG7, "SPRG7",
5500 SPR_NOACCESS, SPR_NOACCESS,
5501 &spr_read_generic, &spr_write_generic,
5502 0x00000000);
5503 spr_register(env, SPR_USPRG7, "USPRG7",
5504 &spr_read_ureg, SPR_NOACCESS,
5505 &spr_read_ureg, SPR_NOACCESS,
5506 0x00000000);
5507 /* Memory management */
5508 register_low_BATs(env);
5509 register_high_BATs(env);
5510 init_excp_7450(env);
5511 env->dcache_line_size = 32;
5512 env->icache_line_size = 32;
5513 /* Allocate hardware IRQ controller */
5514 ppc6xx_irq_init(env_archcpu(env));
5515 }
5516
5517 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
5518 {
5519 DeviceClass *dc = DEVICE_CLASS(oc);
5520 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5521
5522 dc->desc = "PowerPC 7457 (aka G4)";
5523 pcc->init_proc = init_proc_7457;
5524 pcc->check_pow = check_pow_hid0_74xx;
5525 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5526 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5527 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5528 PPC_FLOAT_STFIWX |
5529 PPC_CACHE | PPC_CACHE_ICBI |
5530 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5531 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5532 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5533 PPC_MEM_TLBIA |
5534 PPC_SEGMENT | PPC_EXTERN |
5535 PPC_ALTIVEC;
5536 pcc->msr_mask = (1ull << MSR_VR) |
5537 (1ull << MSR_POW) |
5538 (1ull << MSR_ILE) |
5539 (1ull << MSR_EE) |
5540 (1ull << MSR_PR) |
5541 (1ull << MSR_FP) |
5542 (1ull << MSR_ME) |
5543 (1ull << MSR_FE0) |
5544 (1ull << MSR_SE) |
5545 (1ull << MSR_DE) |
5546 (1ull << MSR_FE1) |
5547 (1ull << MSR_EP) |
5548 (1ull << MSR_IR) |
5549 (1ull << MSR_DR) |
5550 (1ull << MSR_PMM) |
5551 (1ull << MSR_RI) |
5552 (1ull << MSR_LE);
5553 pcc->mmu_model = POWERPC_MMU_32B;
5554 pcc->excp_model = POWERPC_EXCP_74xx;
5555 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5556 pcc->bfd_mach = bfd_mach_ppc_7400;
5557 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5558 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5559 POWERPC_FLAG_BUS_CLK;
5560 }
5561
5562 static void init_proc_e600(CPUPPCState *env)
5563 {
5564 register_ne_601_sprs(env);
5565 register_sdr1_sprs(env);
5566 register_7xx_sprs(env);
5567 /* Time base */
5568 register_tbl(env);
5569 /* 74xx specific SPR */
5570 register_74xx_sprs(env);
5571 vscr_init(env, 0x00010000);
5572 /* XXX : not implemented */
5573 spr_register(env, SPR_UBAMR, "UBAMR",
5574 &spr_read_ureg, SPR_NOACCESS,
5575 &spr_read_ureg, SPR_NOACCESS,
5576 0x00000000);
5577 /* XXX : not implemented */
5578 spr_register(env, SPR_LDSTCR, "LDSTCR",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_generic,
5581 0x00000000);
5582 /* XXX : not implemented */
5583 spr_register(env, SPR_ICTRL, "ICTRL",
5584 SPR_NOACCESS, SPR_NOACCESS,
5585 &spr_read_generic, &spr_write_generic,
5586 0x00000000);
5587 /* XXX : not implemented */
5588 spr_register(env, SPR_MSSSR0, "MSSSR0",
5589 SPR_NOACCESS, SPR_NOACCESS,
5590 &spr_read_generic, &spr_write_generic,
5591 0x00000000);
5592 /* XXX : not implemented */
5593 spr_register(env, SPR_7XX_PMC5, "PMC5",
5594 SPR_NOACCESS, SPR_NOACCESS,
5595 &spr_read_generic, &spr_write_generic,
5596 0x00000000);
5597 /* XXX : not implemented */
5598 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5599 &spr_read_ureg, SPR_NOACCESS,
5600 &spr_read_ureg, SPR_NOACCESS,
5601 0x00000000);
5602 /* XXX : not implemented */
5603 spr_register(env, SPR_7XX_PMC6, "PMC6",
5604 SPR_NOACCESS, SPR_NOACCESS,
5605 &spr_read_generic, &spr_write_generic,
5606 0x00000000);
5607 /* XXX : not implemented */
5608 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5609 &spr_read_ureg, SPR_NOACCESS,
5610 &spr_read_ureg, SPR_NOACCESS,
5611 0x00000000);
5612 /* SPRGs */
5613 spr_register(env, SPR_SPRG4, "SPRG4",
5614 SPR_NOACCESS, SPR_NOACCESS,
5615 &spr_read_generic, &spr_write_generic,
5616 0x00000000);
5617 spr_register(env, SPR_USPRG4, "USPRG4",
5618 &spr_read_ureg, SPR_NOACCESS,
5619 &spr_read_ureg, SPR_NOACCESS,
5620 0x00000000);
5621 spr_register(env, SPR_SPRG5, "SPRG5",
5622 SPR_NOACCESS, SPR_NOACCESS,
5623 &spr_read_generic, &spr_write_generic,
5624 0x00000000);
5625 spr_register(env, SPR_USPRG5, "USPRG5",
5626 &spr_read_ureg, SPR_NOACCESS,
5627 &spr_read_ureg, SPR_NOACCESS,
5628 0x00000000);
5629 spr_register(env, SPR_SPRG6, "SPRG6",
5630 SPR_NOACCESS, SPR_NOACCESS,
5631 &spr_read_generic, &spr_write_generic,
5632 0x00000000);
5633 spr_register(env, SPR_USPRG6, "USPRG6",
5634 &spr_read_ureg, SPR_NOACCESS,
5635 &spr_read_ureg, SPR_NOACCESS,
5636 0x00000000);
5637 spr_register(env, SPR_SPRG7, "SPRG7",
5638 SPR_NOACCESS, SPR_NOACCESS,
5639 &spr_read_generic, &spr_write_generic,
5640 0x00000000);
5641 spr_register(env, SPR_USPRG7, "USPRG7",
5642 &spr_read_ureg, SPR_NOACCESS,
5643 &spr_read_ureg, SPR_NOACCESS,
5644 0x00000000);
5645 /* Memory management */
5646 register_low_BATs(env);
5647 register_high_BATs(env);
5648 init_excp_7450(env);
5649 env->dcache_line_size = 32;
5650 env->icache_line_size = 32;
5651 /* Allocate hardware IRQ controller */
5652 ppc6xx_irq_init(env_archcpu(env));
5653 }
5654
5655 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
5656 {
5657 DeviceClass *dc = DEVICE_CLASS(oc);
5658 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5659
5660 dc->desc = "PowerPC e600";
5661 pcc->init_proc = init_proc_e600;
5662 pcc->check_pow = check_pow_hid0_74xx;
5663 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5664 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5665 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5666 PPC_FLOAT_STFIWX |
5667 PPC_CACHE | PPC_CACHE_ICBI |
5668 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5669 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5670 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5671 PPC_MEM_TLBIA |
5672 PPC_SEGMENT | PPC_EXTERN |
5673 PPC_ALTIVEC;
5674 pcc->insns_flags2 = PPC_NONE;
5675 pcc->msr_mask = (1ull << MSR_VR) |
5676 (1ull << MSR_POW) |
5677 (1ull << MSR_ILE) |
5678 (1ull << MSR_EE) |
5679 (1ull << MSR_PR) |
5680 (1ull << MSR_FP) |
5681 (1ull << MSR_ME) |
5682 (1ull << MSR_FE0) |
5683 (1ull << MSR_SE) |
5684 (1ull << MSR_DE) |
5685 (1ull << MSR_FE1) |
5686 (1ull << MSR_EP) |
5687 (1ull << MSR_IR) |
5688 (1ull << MSR_DR) |
5689 (1ull << MSR_PMM) |
5690 (1ull << MSR_RI) |
5691 (1ull << MSR_LE);
5692 pcc->mmu_model = POWERPC_MMU_32B;
5693 pcc->excp_model = POWERPC_EXCP_74xx;
5694 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5695 pcc->bfd_mach = bfd_mach_ppc_7400;
5696 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5697 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5698 POWERPC_FLAG_BUS_CLK;
5699 }
5700
5701 #if defined(TARGET_PPC64)
5702 #if defined(CONFIG_USER_ONLY)
5703 #define POWERPC970_HID5_INIT 0x00000080
5704 #else
5705 #define POWERPC970_HID5_INIT 0x00000000
5706 #endif
5707
5708 static int check_pow_970(CPUPPCState *env)
5709 {
5710 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5711 return 1;
5712 }
5713
5714 return 0;
5715 }
5716
5717 static void register_970_hid_sprs(CPUPPCState *env)
5718 {
5719 /* Hardware implementation registers */
5720 /* XXX : not implemented */
5721 spr_register(env, SPR_HID0, "HID0",
5722 SPR_NOACCESS, SPR_NOACCESS,
5723 &spr_read_generic, &spr_write_clear,
5724 0x60000000);
5725 spr_register(env, SPR_HID1, "HID1",
5726 SPR_NOACCESS, SPR_NOACCESS,
5727 &spr_read_generic, &spr_write_generic,
5728 0x00000000);
5729 spr_register(env, SPR_970_HID5, "HID5",
5730 SPR_NOACCESS, SPR_NOACCESS,
5731 &spr_read_generic, &spr_write_generic,
5732 POWERPC970_HID5_INIT);
5733 }
5734
5735 static void register_970_hior_sprs(CPUPPCState *env)
5736 {
5737 spr_register(env, SPR_HIOR, "SPR_HIOR",
5738 SPR_NOACCESS, SPR_NOACCESS,
5739 &spr_read_hior, &spr_write_hior,
5740 0x00000000);
5741 }
5742
5743 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5744 {
5745 spr_register(env, SPR_CTRL, "SPR_CTRL",
5746 SPR_NOACCESS, SPR_NOACCESS,
5747 SPR_NOACCESS, &spr_write_CTRL,
5748 0x00000000);
5749 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
5750 &spr_read_ureg, SPR_NOACCESS,
5751 &spr_read_ureg, SPR_NOACCESS,
5752 0x00000000);
5753 }
5754
5755 static void register_book3s_altivec_sprs(CPUPPCState *env)
5756 {
5757 if (!(env->insns_flags & PPC_ALTIVEC)) {
5758 return;
5759 }
5760
5761 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5762 &spr_read_generic, &spr_write_generic,
5763 &spr_read_generic, &spr_write_generic,
5764 KVM_REG_PPC_VRSAVE, 0x00000000);
5765
5766 }
5767
5768 static void register_book3s_dbg_sprs(CPUPPCState *env)
5769 {
5770 /*
5771 * TODO: different specs define different scopes for these,
5772 * will have to address this:
5773 * 970: super/write and super/read
5774 * powerisa 2.03..2.04: hypv/write and super/read.
5775 * powerisa 2.05 and newer: hypv/write and hypv/read.
5776 */
5777 spr_register_kvm(env, SPR_DABR, "DABR",
5778 SPR_NOACCESS, SPR_NOACCESS,
5779 &spr_read_generic, &spr_write_generic,
5780 KVM_REG_PPC_DABR, 0x00000000);
5781 spr_register_kvm(env, SPR_DABRX, "DABRX",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_generic,
5784 KVM_REG_PPC_DABRX, 0x00000000);
5785 }
5786
5787 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5788 {
5789 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5790 SPR_NOACCESS, SPR_NOACCESS,
5791 SPR_NOACCESS, SPR_NOACCESS,
5792 &spr_read_generic, &spr_write_generic,
5793 KVM_REG_PPC_DAWR, 0x00000000);
5794 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5795 SPR_NOACCESS, SPR_NOACCESS,
5796 SPR_NOACCESS, SPR_NOACCESS,
5797 &spr_read_generic, &spr_write_generic,
5798 KVM_REG_PPC_DAWRX, 0x00000000);
5799 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5800 SPR_NOACCESS, SPR_NOACCESS,
5801 SPR_NOACCESS, SPR_NOACCESS,
5802 &spr_read_generic, &spr_write_generic,
5803 KVM_REG_PPC_CIABR, 0x00000000);
5804 }
5805
5806 static void register_970_dbg_sprs(CPUPPCState *env)
5807 {
5808 /* Breakpoints */
5809 spr_register(env, SPR_IABR, "IABR",
5810 SPR_NOACCESS, SPR_NOACCESS,
5811 &spr_read_generic, &spr_write_generic,
5812 0x00000000);
5813 }
5814
5815 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5816 {
5817 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5818 SPR_NOACCESS, SPR_NOACCESS,
5819 &spr_read_generic, &spr_write_MMCR0,
5820 KVM_REG_PPC_MMCR0, 0x80000000);
5821 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5822 SPR_NOACCESS, SPR_NOACCESS,
5823 &spr_read_generic, &spr_write_MMCR1,
5824 KVM_REG_PPC_MMCR1, 0x00000000);
5825 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5826 SPR_NOACCESS, SPR_NOACCESS,
5827 &spr_read_generic, &spr_write_generic,
5828 KVM_REG_PPC_MMCRA, 0x00000000);
5829 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5830 SPR_NOACCESS, SPR_NOACCESS,
5831 &spr_read_PMC, &spr_write_PMC,
5832 KVM_REG_PPC_PMC1, 0x00000000);
5833 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5834 SPR_NOACCESS, SPR_NOACCESS,
5835 &spr_read_PMC, &spr_write_PMC,
5836 KVM_REG_PPC_PMC2, 0x00000000);
5837 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5838 SPR_NOACCESS, SPR_NOACCESS,
5839 &spr_read_PMC, &spr_write_PMC,
5840 KVM_REG_PPC_PMC3, 0x00000000);
5841 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5842 SPR_NOACCESS, SPR_NOACCESS,
5843 &spr_read_PMC, &spr_write_PMC,
5844 KVM_REG_PPC_PMC4, 0x00000000);
5845 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5846 SPR_NOACCESS, SPR_NOACCESS,
5847 &spr_read_PMC, &spr_write_PMC,
5848 KVM_REG_PPC_PMC5, 0x00000000);
5849 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5850 SPR_NOACCESS, SPR_NOACCESS,
5851 &spr_read_PMC, &spr_write_PMC,
5852 KVM_REG_PPC_PMC6, 0x00000000);
5853 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5854 SPR_NOACCESS, SPR_NOACCESS,
5855 &spr_read_generic, &spr_write_generic,
5856 KVM_REG_PPC_SIAR, 0x00000000);
5857 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5858 SPR_NOACCESS, SPR_NOACCESS,
5859 &spr_read_generic, &spr_write_generic,
5860 KVM_REG_PPC_SDAR, 0x00000000);
5861 }
5862
5863 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5864 {
5865 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5866 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5867 &spr_read_ureg, &spr_write_ureg,
5868 0x80000000);
5869 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5870 &spr_read_ureg, SPR_NOACCESS,
5871 &spr_read_ureg, &spr_write_ureg,
5872 0x00000000);
5873 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5874 &spr_read_ureg, SPR_NOACCESS,
5875 &spr_read_ureg, &spr_write_ureg,
5876 0x00000000);
5877 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5878 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5879 &spr_read_ureg, &spr_write_ureg,
5880 0x00000000);
5881 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5882 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5883 &spr_read_ureg, &spr_write_ureg,
5884 0x00000000);
5885 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5886 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5887 &spr_read_ureg, &spr_write_ureg,
5888 0x00000000);
5889 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5890 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5891 &spr_read_ureg, &spr_write_ureg,
5892 0x00000000);
5893 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5894 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5895 &spr_read_ureg, &spr_write_ureg,
5896 0x00000000);
5897 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5898 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5899 &spr_read_ureg, &spr_write_ureg,
5900 0x00000000);
5901 spr_register(env, SPR_POWER_USIAR, "USIAR",
5902 &spr_read_ureg, SPR_NOACCESS,
5903 &spr_read_ureg, &spr_write_ureg,
5904 0x00000000);
5905 spr_register(env, SPR_POWER_USDAR, "USDAR",
5906 &spr_read_ureg, SPR_NOACCESS,
5907 &spr_read_ureg, &spr_write_ureg,
5908 0x00000000);
5909 }
5910
5911 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5912 {
5913 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5914 SPR_NOACCESS, SPR_NOACCESS,
5915 &spr_read_generic, &spr_write_generic,
5916 KVM_REG_PPC_PMC7, 0x00000000);
5917 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5918 SPR_NOACCESS, SPR_NOACCESS,
5919 &spr_read_generic, &spr_write_generic,
5920 KVM_REG_PPC_PMC8, 0x00000000);
5921 }
5922
5923 static void register_970_pmu_user_sprs(CPUPPCState *env)
5924 {
5925 spr_register(env, SPR_970_UPMC7, "UPMC7",
5926 &spr_read_ureg, SPR_NOACCESS,
5927 &spr_read_ureg, &spr_write_ureg,
5928 0x00000000);
5929 spr_register(env, SPR_970_UPMC8, "UPMC8",
5930 &spr_read_ureg, SPR_NOACCESS,
5931 &spr_read_ureg, &spr_write_ureg,
5932 0x00000000);
5933 }
5934
5935 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5936 {
5937 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5938 SPR_NOACCESS, SPR_NOACCESS,
5939 &spr_read_generic, &spr_write_generic,
5940 KVM_REG_PPC_MMCR2, 0x00000000);
5941 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5942 SPR_NOACCESS, SPR_NOACCESS,
5943 &spr_read_generic, &spr_write_generic,
5944 KVM_REG_PPC_MMCRS, 0x00000000);
5945 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5946 SPR_NOACCESS, SPR_NOACCESS,
5947 &spr_read_generic, &spr_write_generic,
5948 KVM_REG_PPC_SIER, 0x00000000);
5949 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5950 SPR_NOACCESS, SPR_NOACCESS,
5951 &spr_read_generic, &spr_write_generic,
5952 KVM_REG_PPC_SPMC1, 0x00000000);
5953 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 &spr_read_generic, &spr_write_generic,
5956 KVM_REG_PPC_SPMC2, 0x00000000);
5957 spr_register_kvm(env, SPR_TACR, "TACR",
5958 SPR_NOACCESS, SPR_NOACCESS,
5959 &spr_read_generic, &spr_write_generic,
5960 KVM_REG_PPC_TACR, 0x00000000);
5961 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5962 SPR_NOACCESS, SPR_NOACCESS,
5963 &spr_read_generic, &spr_write_generic,
5964 KVM_REG_PPC_TCSCR, 0x00000000);
5965 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5966 SPR_NOACCESS, SPR_NOACCESS,
5967 &spr_read_generic, &spr_write_generic,
5968 KVM_REG_PPC_CSIGR, 0x00000000);
5969 }
5970
5971 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5972 {
5973 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5974 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5975 &spr_read_ureg, &spr_write_ureg,
5976 0x00000000);
5977 spr_register(env, SPR_POWER_USIER, "USIER",
5978 &spr_read_generic, SPR_NOACCESS,
5979 &spr_read_generic, &spr_write_generic,
5980 0x00000000);
5981 }
5982
5983 static void register_power5p_ear_sprs(CPUPPCState *env)
5984 {
5985 /* External access control */
5986 spr_register(env, SPR_EAR, "EAR",
5987 SPR_NOACCESS, SPR_NOACCESS,
5988 &spr_read_generic, &spr_write_generic,
5989 0x00000000);
5990 }
5991
5992 static void register_power5p_tb_sprs(CPUPPCState *env)
5993 {
5994 /* TBU40 (High 40 bits of the Timebase register */
5995 spr_register_hv(env, SPR_TBU40, "TBU40",
5996 SPR_NOACCESS, SPR_NOACCESS,
5997 SPR_NOACCESS, SPR_NOACCESS,
5998 SPR_NOACCESS, &spr_write_tbu40,
5999 0x00000000);
6000 }
6001
6002 static void register_970_lpar_sprs(CPUPPCState *env)
6003 {
6004 #if !defined(CONFIG_USER_ONLY)
6005 /*
6006 * PPC970: HID4 covers things later controlled by the LPCR and
6007 * RMOR in later CPUs, but with a different encoding. We only
6008 * support the 970 in "Apple mode" which has all hypervisor
6009 * facilities disabled by strapping, so we can basically just
6010 * ignore it
6011 */
6012 spr_register(env, SPR_970_HID4, "HID4",
6013 SPR_NOACCESS, SPR_NOACCESS,
6014 &spr_read_generic, &spr_write_generic,
6015 0x00000000);
6016 #endif
6017 }
6018
6019 static void register_power5p_lpar_sprs(CPUPPCState *env)
6020 {
6021 #if !defined(CONFIG_USER_ONLY)
6022 /* Logical partitionning */
6023 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
6024 SPR_NOACCESS, SPR_NOACCESS,
6025 SPR_NOACCESS, SPR_NOACCESS,
6026 &spr_read_generic, &spr_write_lpcr,
6027 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
6028 spr_register_hv(env, SPR_HDEC, "HDEC",
6029 SPR_NOACCESS, SPR_NOACCESS,
6030 SPR_NOACCESS, SPR_NOACCESS,
6031 &spr_read_hdecr, &spr_write_hdecr, 0);
6032 #endif
6033 }
6034
6035 static void register_book3s_ids_sprs(CPUPPCState *env)
6036 {
6037 /* FIXME: Will need to deal with thread vs core only SPRs */
6038
6039 /* Processor identification */
6040 spr_register_hv(env, SPR_PIR, "PIR",
6041 SPR_NOACCESS, SPR_NOACCESS,
6042 &spr_read_generic, SPR_NOACCESS,
6043 &spr_read_generic, NULL,
6044 0x00000000);
6045 spr_register_hv(env, SPR_HID0, "HID0",
6046 SPR_NOACCESS, SPR_NOACCESS,
6047 SPR_NOACCESS, SPR_NOACCESS,
6048 &spr_read_generic, &spr_write_generic,
6049 0x00000000);
6050 spr_register_hv(env, SPR_TSCR, "TSCR",
6051 SPR_NOACCESS, SPR_NOACCESS,
6052 SPR_NOACCESS, SPR_NOACCESS,
6053 &spr_read_generic, &spr_write_generic,
6054 0x00000000);
6055 spr_register_hv(env, SPR_HMER, "HMER",
6056 SPR_NOACCESS, SPR_NOACCESS,
6057 SPR_NOACCESS, SPR_NOACCESS,
6058 &spr_read_generic, &spr_write_hmer,
6059 0x00000000);
6060 spr_register_hv(env, SPR_HMEER, "HMEER",
6061 SPR_NOACCESS, SPR_NOACCESS,
6062 SPR_NOACCESS, SPR_NOACCESS,
6063 &spr_read_generic, &spr_write_generic,
6064 0x00000000);
6065 spr_register_hv(env, SPR_TFMR, "TFMR",
6066 SPR_NOACCESS, SPR_NOACCESS,
6067 SPR_NOACCESS, SPR_NOACCESS,
6068 &spr_read_generic, &spr_write_generic,
6069 0x00000000);
6070 spr_register_hv(env, SPR_LPIDR, "LPIDR",
6071 SPR_NOACCESS, SPR_NOACCESS,
6072 SPR_NOACCESS, SPR_NOACCESS,
6073 &spr_read_generic, &spr_write_lpidr,
6074 0x00000000);
6075 spr_register_hv(env, SPR_HFSCR, "HFSCR",
6076 SPR_NOACCESS, SPR_NOACCESS,
6077 SPR_NOACCESS, SPR_NOACCESS,
6078 &spr_read_generic, &spr_write_generic,
6079 0x00000000);
6080 spr_register_hv(env, SPR_MMCRC, "MMCRC",
6081 SPR_NOACCESS, SPR_NOACCESS,
6082 SPR_NOACCESS, SPR_NOACCESS,
6083 &spr_read_generic, &spr_write_generic,
6084 0x00000000);
6085 spr_register_hv(env, SPR_MMCRH, "MMCRH",
6086 SPR_NOACCESS, SPR_NOACCESS,
6087 SPR_NOACCESS, SPR_NOACCESS,
6088 &spr_read_generic, &spr_write_generic,
6089 0x00000000);
6090 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
6091 SPR_NOACCESS, SPR_NOACCESS,
6092 SPR_NOACCESS, SPR_NOACCESS,
6093 &spr_read_generic, &spr_write_generic,
6094 0x00000000);
6095 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
6096 SPR_NOACCESS, SPR_NOACCESS,
6097 SPR_NOACCESS, SPR_NOACCESS,
6098 &spr_read_generic, &spr_write_generic,
6099 0x00000000);
6100 spr_register_hv(env, SPR_HSRR0, "HSRR0",
6101 SPR_NOACCESS, SPR_NOACCESS,
6102 SPR_NOACCESS, SPR_NOACCESS,
6103 &spr_read_generic, &spr_write_generic,
6104 0x00000000);
6105 spr_register_hv(env, SPR_HSRR1, "HSRR1",
6106 SPR_NOACCESS, SPR_NOACCESS,
6107 SPR_NOACCESS, SPR_NOACCESS,
6108 &spr_read_generic, &spr_write_generic,
6109 0x00000000);
6110 spr_register_hv(env, SPR_HDAR, "HDAR",
6111 SPR_NOACCESS, SPR_NOACCESS,
6112 SPR_NOACCESS, SPR_NOACCESS,
6113 &spr_read_generic, &spr_write_generic,
6114 0x00000000);
6115 spr_register_hv(env, SPR_HDSISR, "HDSISR",
6116 SPR_NOACCESS, SPR_NOACCESS,
6117 SPR_NOACCESS, SPR_NOACCESS,
6118 &spr_read_generic, &spr_write_generic,
6119 0x00000000);
6120 spr_register_hv(env, SPR_HRMOR, "HRMOR",
6121 SPR_NOACCESS, SPR_NOACCESS,
6122 SPR_NOACCESS, SPR_NOACCESS,
6123 &spr_read_generic, &spr_write_generic,
6124 0x00000000);
6125 }
6126
6127 static void register_rmor_sprs(CPUPPCState *env)
6128 {
6129 spr_register_hv(env, SPR_RMOR, "RMOR",
6130 SPR_NOACCESS, SPR_NOACCESS,
6131 SPR_NOACCESS, SPR_NOACCESS,
6132 &spr_read_generic, &spr_write_generic,
6133 0x00000000);
6134 }
6135
6136 static void register_power8_ids_sprs(CPUPPCState *env)
6137 {
6138 /* Thread identification */
6139 spr_register(env, SPR_TIR, "TIR",
6140 SPR_NOACCESS, SPR_NOACCESS,
6141 &spr_read_generic, SPR_NOACCESS,
6142 0x00000000);
6143 }
6144
6145 static void register_book3s_purr_sprs(CPUPPCState *env)
6146 {
6147 #if !defined(CONFIG_USER_ONLY)
6148 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6149 spr_register_kvm_hv(env, SPR_PURR, "PURR",
6150 &spr_read_purr, SPR_NOACCESS,
6151 &spr_read_purr, SPR_NOACCESS,
6152 &spr_read_purr, &spr_write_purr,
6153 KVM_REG_PPC_PURR, 0x00000000);
6154 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
6155 &spr_read_purr, SPR_NOACCESS,
6156 &spr_read_purr, SPR_NOACCESS,
6157 &spr_read_purr, &spr_write_purr,
6158 KVM_REG_PPC_SPURR, 0x00000000);
6159 #endif
6160 }
6161
6162 static void register_power6_dbg_sprs(CPUPPCState *env)
6163 {
6164 #if !defined(CONFIG_USER_ONLY)
6165 spr_register(env, SPR_CFAR, "SPR_CFAR",
6166 SPR_NOACCESS, SPR_NOACCESS,
6167 &spr_read_cfar, &spr_write_cfar,
6168 0x00000000);
6169 #endif
6170 }
6171
6172 static void register_power5p_common_sprs(CPUPPCState *env)
6173 {
6174 spr_register_kvm(env, SPR_PPR, "PPR",
6175 &spr_read_generic, &spr_write_generic,
6176 &spr_read_generic, &spr_write_generic,
6177 KVM_REG_PPC_PPR, 0x00000000);
6178 }
6179
6180 static void register_power6_common_sprs(CPUPPCState *env)
6181 {
6182 #if !defined(CONFIG_USER_ONLY)
6183 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6184 SPR_NOACCESS, SPR_NOACCESS,
6185 &spr_read_generic, &spr_write_generic,
6186 KVM_REG_PPC_DSCR, 0x00000000);
6187 #endif
6188 /*
6189 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
6190 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
6191 */
6192 spr_register_hv(env, SPR_PCR, "PCR",
6193 SPR_NOACCESS, SPR_NOACCESS,
6194 SPR_NOACCESS, SPR_NOACCESS,
6195 &spr_read_generic, &spr_write_pcr,
6196 0x00000000);
6197 }
6198
6199 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
6200 {
6201 spr_register_kvm(env, SPR_TAR, "TAR",
6202 &spr_read_tar, &spr_write_tar,
6203 &spr_read_generic, &spr_write_generic,
6204 KVM_REG_PPC_TAR, 0x00000000);
6205 }
6206
6207 static void register_power8_tm_sprs(CPUPPCState *env)
6208 {
6209 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
6210 &spr_read_tm, &spr_write_tm,
6211 &spr_read_tm, &spr_write_tm,
6212 KVM_REG_PPC_TFHAR, 0x00000000);
6213 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
6214 &spr_read_tm, &spr_write_tm,
6215 &spr_read_tm, &spr_write_tm,
6216 KVM_REG_PPC_TFIAR, 0x00000000);
6217 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
6218 &spr_read_tm, &spr_write_tm,
6219 &spr_read_tm, &spr_write_tm,
6220 KVM_REG_PPC_TEXASR, 0x00000000);
6221 spr_register(env, SPR_TEXASRU, "TEXASRU",
6222 &spr_read_tm_upper32, &spr_write_tm_upper32,
6223 &spr_read_tm_upper32, &spr_write_tm_upper32,
6224 0x00000000);
6225 }
6226
6227 static void register_power8_ebb_sprs(CPUPPCState *env)
6228 {
6229 spr_register(env, SPR_BESCRS, "BESCRS",
6230 &spr_read_ebb, &spr_write_ebb,
6231 &spr_read_generic, &spr_write_generic,
6232 0x00000000);
6233 spr_register(env, SPR_BESCRSU, "BESCRSU",
6234 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6235 &spr_read_prev_upper32, &spr_write_prev_upper32,
6236 0x00000000);
6237 spr_register(env, SPR_BESCRR, "BESCRR",
6238 &spr_read_ebb, &spr_write_ebb,
6239 &spr_read_generic, &spr_write_generic,
6240 0x00000000);
6241 spr_register(env, SPR_BESCRRU, "BESCRRU",
6242 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6243 &spr_read_prev_upper32, &spr_write_prev_upper32,
6244 0x00000000);
6245 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
6246 &spr_read_ebb, &spr_write_ebb,
6247 &spr_read_generic, &spr_write_generic,
6248 KVM_REG_PPC_EBBHR, 0x00000000);
6249 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
6250 &spr_read_ebb, &spr_write_ebb,
6251 &spr_read_generic, &spr_write_generic,
6252 KVM_REG_PPC_EBBRR, 0x00000000);
6253 spr_register_kvm(env, SPR_BESCR, "BESCR",
6254 &spr_read_ebb, &spr_write_ebb,
6255 &spr_read_generic, &spr_write_generic,
6256 KVM_REG_PPC_BESCR, 0x00000000);
6257 }
6258
6259 /* Virtual Time Base */
6260 static void register_vtb_sprs(CPUPPCState *env)
6261 {
6262 spr_register_kvm_hv(env, SPR_VTB, "VTB",
6263 SPR_NOACCESS, SPR_NOACCESS,
6264 &spr_read_vtb, SPR_NOACCESS,
6265 &spr_read_vtb, &spr_write_vtb,
6266 KVM_REG_PPC_VTB, 0x00000000);
6267 }
6268
6269 static void register_power8_fscr_sprs(CPUPPCState *env)
6270 {
6271 #if defined(CONFIG_USER_ONLY)
6272 target_ulong initval = 1ULL << FSCR_TAR;
6273 #else
6274 target_ulong initval = 0;
6275 #endif
6276 spr_register_kvm(env, SPR_FSCR, "FSCR",
6277 SPR_NOACCESS, SPR_NOACCESS,
6278 &spr_read_generic, &spr_write_generic,
6279 KVM_REG_PPC_FSCR, initval);
6280 }
6281
6282 static void register_power8_pspb_sprs(CPUPPCState *env)
6283 {
6284 spr_register_kvm(env, SPR_PSPB, "PSPB",
6285 SPR_NOACCESS, SPR_NOACCESS,
6286 &spr_read_generic, &spr_write_generic32,
6287 KVM_REG_PPC_PSPB, 0);
6288 }
6289
6290 static void register_power8_dpdes_sprs(CPUPPCState *env)
6291 {
6292 #if !defined(CONFIG_USER_ONLY)
6293 /* Directed Privileged Door-bell Exception State, used for IPI */
6294 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
6295 SPR_NOACCESS, SPR_NOACCESS,
6296 &spr_read_dpdes, SPR_NOACCESS,
6297 &spr_read_dpdes, &spr_write_dpdes,
6298 KVM_REG_PPC_DPDES, 0x00000000);
6299 #endif
6300 }
6301
6302 static void register_power8_ic_sprs(CPUPPCState *env)
6303 {
6304 #if !defined(CONFIG_USER_ONLY)
6305 spr_register_hv(env, SPR_IC, "IC",
6306 SPR_NOACCESS, SPR_NOACCESS,
6307 &spr_read_generic, SPR_NOACCESS,
6308 &spr_read_generic, &spr_write_generic,
6309 0);
6310 #endif
6311 }
6312
6313 static void register_power8_book4_sprs(CPUPPCState *env)
6314 {
6315 /* Add a number of P8 book4 registers */
6316 #if !defined(CONFIG_USER_ONLY)
6317 spr_register_kvm(env, SPR_ACOP, "ACOP",
6318 SPR_NOACCESS, SPR_NOACCESS,
6319 &spr_read_generic, &spr_write_generic,
6320 KVM_REG_PPC_ACOP, 0);
6321 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6322 SPR_NOACCESS, SPR_NOACCESS,
6323 &spr_read_generic, &spr_write_pidr,
6324 KVM_REG_PPC_PID, 0);
6325 spr_register_kvm(env, SPR_WORT, "WORT",
6326 SPR_NOACCESS, SPR_NOACCESS,
6327 &spr_read_generic, &spr_write_generic,
6328 KVM_REG_PPC_WORT, 0);
6329 #endif
6330 }
6331
6332 static void register_power7_book4_sprs(CPUPPCState *env)
6333 {
6334 /* Add a number of P7 book4 registers */
6335 #if !defined(CONFIG_USER_ONLY)
6336 spr_register_kvm(env, SPR_ACOP, "ACOP",
6337 SPR_NOACCESS, SPR_NOACCESS,
6338 &spr_read_generic, &spr_write_generic,
6339 KVM_REG_PPC_ACOP, 0);
6340 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6341 SPR_NOACCESS, SPR_NOACCESS,
6342 &spr_read_generic, &spr_write_generic,
6343 KVM_REG_PPC_PID, 0);
6344 #endif
6345 }
6346
6347 static void register_power8_rpr_sprs(CPUPPCState *env)
6348 {
6349 #if !defined(CONFIG_USER_ONLY)
6350 spr_register_hv(env, SPR_RPR, "RPR",
6351 SPR_NOACCESS, SPR_NOACCESS,
6352 SPR_NOACCESS, SPR_NOACCESS,
6353 &spr_read_generic, &spr_write_generic,
6354 0x00000103070F1F3F);
6355 #endif
6356 }
6357
6358 static void register_power9_mmu_sprs(CPUPPCState *env)
6359 {
6360 #if !defined(CONFIG_USER_ONLY)
6361 /* Partition Table Control */
6362 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
6363 SPR_NOACCESS, SPR_NOACCESS,
6364 SPR_NOACCESS, SPR_NOACCESS,
6365 &spr_read_generic, &spr_write_ptcr,
6366 KVM_REG_PPC_PTCR, 0x00000000);
6367 /* Address Segment Descriptor Register */
6368 spr_register_hv(env, SPR_ASDR, "ASDR",
6369 SPR_NOACCESS, SPR_NOACCESS,
6370 SPR_NOACCESS, SPR_NOACCESS,
6371 &spr_read_generic, &spr_write_generic,
6372 0x0000000000000000);
6373 #endif
6374 }
6375
6376 /*
6377 * Initialize PMU counter overflow timers for Power8 and
6378 * newer Power chips when using TCG.
6379 */
6380 static void init_tcg_pmu_power8(CPUPPCState *env)
6381 {
6382 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
6383 /* Init PMU overflow timers */
6384 if (!kvm_enabled()) {
6385 cpu_ppc_pmu_init(env);
6386 }
6387 #endif
6388 }
6389
6390 static void init_proc_book3s_common(CPUPPCState *env)
6391 {
6392 register_ne_601_sprs(env);
6393 register_tbl(env);
6394 register_usprg3_sprs(env);
6395 register_book3s_altivec_sprs(env);
6396 register_book3s_pmu_sup_sprs(env);
6397 register_book3s_pmu_user_sprs(env);
6398 register_book3s_ctrl_sprs(env);
6399 /*
6400 * Can't find information on what this should be on reset. This
6401 * value is the one used by 74xx processors.
6402 */
6403 vscr_init(env, 0x00010000);
6404 }
6405
6406 static void init_proc_970(CPUPPCState *env)
6407 {
6408 /* Common Registers */
6409 init_proc_book3s_common(env);
6410 register_sdr1_sprs(env);
6411 register_book3s_dbg_sprs(env);
6412
6413 /* 970 Specific Registers */
6414 register_970_hid_sprs(env);
6415 register_970_hior_sprs(env);
6416 register_low_BATs(env);
6417 register_970_pmu_sup_sprs(env);
6418 register_970_pmu_user_sprs(env);
6419 register_970_lpar_sprs(env);
6420 register_970_dbg_sprs(env);
6421
6422 /* env variables */
6423 env->dcache_line_size = 128;
6424 env->icache_line_size = 128;
6425
6426 /* Allocate hardware IRQ controller */
6427 init_excp_970(env);
6428 ppc970_irq_init(env_archcpu(env));
6429 }
6430
6431 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6432 {
6433 DeviceClass *dc = DEVICE_CLASS(oc);
6434 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6435
6436 dc->desc = "PowerPC 970";
6437 pcc->init_proc = init_proc_970;
6438 pcc->check_pow = check_pow_970;
6439 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6440 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6441 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6442 PPC_FLOAT_STFIWX |
6443 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6444 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6445 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6446 PPC_64B | PPC_ALTIVEC |
6447 PPC_SEGMENT_64B | PPC_SLBI;
6448 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6449 pcc->msr_mask = (1ull << MSR_SF) |
6450 (1ull << MSR_VR) |
6451 (1ull << MSR_POW) |
6452 (1ull << MSR_EE) |
6453 (1ull << MSR_PR) |
6454 (1ull << MSR_FP) |
6455 (1ull << MSR_ME) |
6456 (1ull << MSR_FE0) |
6457 (1ull << MSR_SE) |
6458 (1ull << MSR_DE) |
6459 (1ull << MSR_FE1) |
6460 (1ull << MSR_IR) |
6461 (1ull << MSR_DR) |
6462 (1ull << MSR_PMM) |
6463 (1ull << MSR_RI);
6464 pcc->mmu_model = POWERPC_MMU_64B;
6465 #if defined(CONFIG_SOFTMMU)
6466 pcc->hash64_opts = &ppc_hash64_opts_basic;
6467 #endif
6468 pcc->excp_model = POWERPC_EXCP_970;
6469 pcc->bus_model = PPC_FLAGS_INPUT_970;
6470 pcc->bfd_mach = bfd_mach_ppc64;
6471 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6472 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6473 POWERPC_FLAG_BUS_CLK;
6474 pcc->l1_dcache_size = 0x8000;
6475 pcc->l1_icache_size = 0x10000;
6476 }
6477
6478 static void init_proc_power5plus(CPUPPCState *env)
6479 {
6480 /* Common Registers */
6481 init_proc_book3s_common(env);
6482 register_sdr1_sprs(env);
6483 register_book3s_dbg_sprs(env);
6484
6485 /* POWER5+ Specific Registers */
6486 register_970_hid_sprs(env);
6487 register_970_hior_sprs(env);
6488 register_low_BATs(env);
6489 register_970_pmu_sup_sprs(env);
6490 register_970_pmu_user_sprs(env);
6491 register_power5p_common_sprs(env);
6492 register_power5p_lpar_sprs(env);
6493 register_power5p_ear_sprs(env);
6494 register_power5p_tb_sprs(env);
6495
6496 /* env variables */
6497 env->dcache_line_size = 128;
6498 env->icache_line_size = 128;
6499
6500 /* Allocate hardware IRQ controller */
6501 init_excp_970(env);
6502 ppc970_irq_init(env_archcpu(env));
6503 }
6504
6505 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6506 {
6507 DeviceClass *dc = DEVICE_CLASS(oc);
6508 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6509
6510 dc->fw_name = "PowerPC,POWER5";
6511 dc->desc = "POWER5+";
6512 pcc->init_proc = init_proc_power5plus;
6513 pcc->check_pow = check_pow_970;
6514 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6515 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6516 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6517 PPC_FLOAT_STFIWX |
6518 PPC_FLOAT_EXT |
6519 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6520 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6521 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6522 PPC_64B |
6523 PPC_POPCNTB |
6524 PPC_SEGMENT_64B | PPC_SLBI;
6525 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6526 pcc->msr_mask = (1ull << MSR_SF) |
6527 (1ull << MSR_VR) |
6528 (1ull << MSR_POW) |
6529 (1ull << MSR_EE) |
6530 (1ull << MSR_PR) |
6531 (1ull << MSR_FP) |
6532 (1ull << MSR_ME) |
6533 (1ull << MSR_FE0) |
6534 (1ull << MSR_SE) |
6535 (1ull << MSR_DE) |
6536 (1ull << MSR_FE1) |
6537 (1ull << MSR_IR) |
6538 (1ull << MSR_DR) |
6539 (1ull << MSR_PMM) |
6540 (1ull << MSR_RI);
6541 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6542 LPCR_RMI | LPCR_HDICE;
6543 pcc->mmu_model = POWERPC_MMU_2_03;
6544 #if defined(CONFIG_SOFTMMU)
6545 pcc->hash64_opts = &ppc_hash64_opts_basic;
6546 pcc->lrg_decr_bits = 32;
6547 #endif
6548 pcc->excp_model = POWERPC_EXCP_970;
6549 pcc->bus_model = PPC_FLAGS_INPUT_970;
6550 pcc->bfd_mach = bfd_mach_ppc64;
6551 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6552 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6553 POWERPC_FLAG_BUS_CLK;
6554 pcc->l1_dcache_size = 0x8000;
6555 pcc->l1_icache_size = 0x10000;
6556 }
6557
6558 static void init_proc_POWER7(CPUPPCState *env)
6559 {
6560 /* Common Registers */
6561 init_proc_book3s_common(env);
6562 register_sdr1_sprs(env);
6563 register_book3s_dbg_sprs(env);
6564
6565 /* POWER7 Specific Registers */
6566 register_book3s_ids_sprs(env);
6567 register_rmor_sprs(env);
6568 register_amr_sprs(env);
6569 register_book3s_purr_sprs(env);
6570 register_power5p_common_sprs(env);
6571 register_power5p_lpar_sprs(env);
6572 register_power5p_ear_sprs(env);
6573 register_power5p_tb_sprs(env);
6574 register_power6_common_sprs(env);
6575 register_power6_dbg_sprs(env);
6576 register_power7_book4_sprs(env);
6577
6578 /* env variables */
6579 env->dcache_line_size = 128;
6580 env->icache_line_size = 128;
6581
6582 /* Allocate hardware IRQ controller */
6583 init_excp_POWER7(env);
6584 ppcPOWER7_irq_init(env_archcpu(env));
6585 }
6586
6587 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
6588 {
6589 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
6590 return true;
6591 }
6592 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
6593 return true;
6594 }
6595 return false;
6596 }
6597
6598 static bool cpu_has_work_POWER7(CPUState *cs)
6599 {
6600 PowerPCCPU *cpu = POWERPC_CPU(cs);
6601 CPUPPCState *env = &cpu->env;
6602
6603 if (cs->halted) {
6604 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6605 return false;
6606 }
6607 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6608 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
6609 return true;
6610 }
6611 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6612 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
6613 return true;
6614 }
6615 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6616 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6617 return true;
6618 }
6619 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6620 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6621 return true;
6622 }
6623 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6624 return true;
6625 }
6626 return false;
6627 } else {
6628 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6629 }
6630 }
6631
6632 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6633 {
6634 DeviceClass *dc = DEVICE_CLASS(oc);
6635 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6636 CPUClass *cc = CPU_CLASS(oc);
6637
6638 dc->fw_name = "PowerPC,POWER7";
6639 dc->desc = "POWER7";
6640 pcc->pvr_match = ppc_pvr_match_power7;
6641 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6642 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6643 pcc->init_proc = init_proc_POWER7;
6644 pcc->check_pow = check_pow_nocheck;
6645 cc->has_work = cpu_has_work_POWER7;
6646 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6647 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6648 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6649 PPC_FLOAT_FRSQRTES |
6650 PPC_FLOAT_STFIWX |
6651 PPC_FLOAT_EXT |
6652 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6653 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6654 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6655 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6656 PPC_SEGMENT_64B | PPC_SLBI |
6657 PPC_POPCNTB | PPC_POPCNTWD |
6658 PPC_CILDST;
6659 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6660 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6661 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6662 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6663 PPC2_PM_ISA206;
6664 pcc->msr_mask = (1ull << MSR_SF) |
6665 (1ull << MSR_VR) |
6666 (1ull << MSR_VSX) |
6667 (1ull << MSR_EE) |
6668 (1ull << MSR_PR) |
6669 (1ull << MSR_FP) |
6670 (1ull << MSR_ME) |
6671 (1ull << MSR_FE0) |
6672 (1ull << MSR_SE) |
6673 (1ull << MSR_DE) |
6674 (1ull << MSR_FE1) |
6675 (1ull << MSR_IR) |
6676 (1ull << MSR_DR) |
6677 (1ull << MSR_PMM) |
6678 (1ull << MSR_RI) |
6679 (1ull << MSR_LE);
6680 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6681 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6682 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6683 LPCR_MER | LPCR_TC |
6684 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6685 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6686 pcc->mmu_model = POWERPC_MMU_2_06;
6687 #if defined(CONFIG_SOFTMMU)
6688 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6689 pcc->lrg_decr_bits = 32;
6690 #endif
6691 pcc->excp_model = POWERPC_EXCP_POWER7;
6692 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6693 pcc->bfd_mach = bfd_mach_ppc64;
6694 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6695 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6696 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6697 POWERPC_FLAG_VSX;
6698 pcc->l1_dcache_size = 0x8000;
6699 pcc->l1_icache_size = 0x8000;
6700 }
6701
6702 static void init_proc_POWER8(CPUPPCState *env)
6703 {
6704 /* Common Registers */
6705 init_proc_book3s_common(env);
6706 register_sdr1_sprs(env);
6707 register_book3s_207_dbg_sprs(env);
6708
6709 /* Common TCG PMU */
6710 init_tcg_pmu_power8(env);
6711
6712 /* POWER8 Specific Registers */
6713 register_book3s_ids_sprs(env);
6714 register_rmor_sprs(env);
6715 register_amr_sprs(env);
6716 register_iamr_sprs(env);
6717 register_book3s_purr_sprs(env);
6718 register_power5p_common_sprs(env);
6719 register_power5p_lpar_sprs(env);
6720 register_power5p_ear_sprs(env);
6721 register_power5p_tb_sprs(env);
6722 register_power6_common_sprs(env);
6723 register_power6_dbg_sprs(env);
6724 register_power8_tce_address_control_sprs(env);
6725 register_power8_ids_sprs(env);
6726 register_power8_ebb_sprs(env);
6727 register_power8_fscr_sprs(env);
6728 register_power8_pmu_sup_sprs(env);
6729 register_power8_pmu_user_sprs(env);
6730 register_power8_tm_sprs(env);
6731 register_power8_pspb_sprs(env);
6732 register_power8_dpdes_sprs(env);
6733 register_vtb_sprs(env);
6734 register_power8_ic_sprs(env);
6735 register_power8_book4_sprs(env);
6736 register_power8_rpr_sprs(env);
6737
6738 /* env variables */
6739 env->dcache_line_size = 128;
6740 env->icache_line_size = 128;
6741
6742 /* Allocate hardware IRQ controller */
6743 init_excp_POWER8(env);
6744 ppcPOWER7_irq_init(env_archcpu(env));
6745 }
6746
6747 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
6748 {
6749 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
6750 return true;
6751 }
6752 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
6753 return true;
6754 }
6755 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
6756 return true;
6757 }
6758 return false;
6759 }
6760
6761 static bool cpu_has_work_POWER8(CPUState *cs)
6762 {
6763 PowerPCCPU *cpu = POWERPC_CPU(cs);
6764 CPUPPCState *env = &cpu->env;
6765
6766 if (cs->halted) {
6767 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6768 return false;
6769 }
6770 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6771 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
6772 return true;
6773 }
6774 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6775 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
6776 return true;
6777 }
6778 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6779 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6780 return true;
6781 }
6782 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6783 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6784 return true;
6785 }
6786 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6787 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
6788 return true;
6789 }
6790 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6791 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
6792 return true;
6793 }
6794 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6795 return true;
6796 }
6797 return false;
6798 } else {
6799 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6800 }
6801 }
6802
6803 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6804 {
6805 DeviceClass *dc = DEVICE_CLASS(oc);
6806 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6807 CPUClass *cc = CPU_CLASS(oc);
6808
6809 dc->fw_name = "PowerPC,POWER8";
6810 dc->desc = "POWER8";
6811 pcc->pvr_match = ppc_pvr_match_power8;
6812 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6813 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6814 pcc->init_proc = init_proc_POWER8;
6815 pcc->check_pow = check_pow_nocheck;
6816 cc->has_work = cpu_has_work_POWER8;
6817 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6818 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6819 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6820 PPC_FLOAT_FRSQRTES |
6821 PPC_FLOAT_STFIWX |
6822 PPC_FLOAT_EXT |
6823 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6824 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6825 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6826 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6827 PPC_SEGMENT_64B | PPC_SLBI |
6828 PPC_POPCNTB | PPC_POPCNTWD |
6829 PPC_CILDST;
6830 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6831 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6832 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6833 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6834 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6835 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6836 PPC2_TM | PPC2_PM_ISA206;
6837 pcc->msr_mask = (1ull << MSR_SF) |
6838 (1ull << MSR_HV) |
6839 (1ull << MSR_TM) |
6840 (1ull << MSR_VR) |
6841 (1ull << MSR_VSX) |
6842 (1ull << MSR_EE) |
6843 (1ull << MSR_PR) |
6844 (1ull << MSR_FP) |
6845 (1ull << MSR_ME) |
6846 (1ull << MSR_FE0) |
6847 (1ull << MSR_SE) |
6848 (1ull << MSR_DE) |
6849 (1ull << MSR_FE1) |
6850 (1ull << MSR_IR) |
6851 (1ull << MSR_DR) |
6852 (1ull << MSR_PMM) |
6853 (1ull << MSR_RI) |
6854 (1ull << MSR_TS0) |
6855 (1ull << MSR_TS1) |
6856 (1ull << MSR_LE);
6857 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6858 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6859 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6860 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6861 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6862 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6863 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6864 pcc->mmu_model = POWERPC_MMU_2_07;
6865 #if defined(CONFIG_SOFTMMU)
6866 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6867 pcc->lrg_decr_bits = 32;
6868 pcc->n_host_threads = 8;
6869 #endif
6870 pcc->excp_model = POWERPC_EXCP_POWER8;
6871 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6872 pcc->bfd_mach = bfd_mach_ppc64;
6873 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6874 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6875 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6876 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6877 pcc->l1_dcache_size = 0x8000;
6878 pcc->l1_icache_size = 0x8000;
6879 }
6880
6881 #ifdef CONFIG_SOFTMMU
6882 /*
6883 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6884 * Encoded as array of int_32s in the form:
6885 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6886 * x -> AP encoding
6887 * y -> radix mode supported page size (encoded as a shift)
6888 */
6889 static struct ppc_radix_page_info POWER9_radix_page_info = {
6890 .count = 4,
6891 .entries = {
6892 0x0000000c, /* 4K - enc: 0x0 */
6893 0xa0000010, /* 64K - enc: 0x5 */
6894 0x20000015, /* 2M - enc: 0x1 */
6895 0x4000001e /* 1G - enc: 0x2 */
6896 }
6897 };
6898 #endif /* CONFIG_SOFTMMU */
6899
6900 static void init_proc_POWER9(CPUPPCState *env)
6901 {
6902 /* Common Registers */
6903 init_proc_book3s_common(env);
6904 register_book3s_207_dbg_sprs(env);
6905
6906 /* Common TCG PMU */
6907 init_tcg_pmu_power8(env);
6908
6909 /* POWER8 Specific Registers */
6910 register_book3s_ids_sprs(env);
6911 register_amr_sprs(env);
6912 register_iamr_sprs(env);
6913 register_book3s_purr_sprs(env);
6914 register_power5p_common_sprs(env);
6915 register_power5p_lpar_sprs(env);
6916 register_power5p_ear_sprs(env);
6917 register_power5p_tb_sprs(env);
6918 register_power6_common_sprs(env);
6919 register_power6_dbg_sprs(env);
6920 register_power8_tce_address_control_sprs(env);
6921 register_power8_ids_sprs(env);
6922 register_power8_ebb_sprs(env);
6923 register_power8_fscr_sprs(env);
6924 register_power8_pmu_sup_sprs(env);
6925 register_power8_pmu_user_sprs(env);
6926 register_power8_tm_sprs(env);
6927 register_power8_pspb_sprs(env);
6928 register_power8_dpdes_sprs(env);
6929 register_vtb_sprs(env);
6930 register_power8_ic_sprs(env);
6931 register_power8_book4_sprs(env);
6932 register_power8_rpr_sprs(env);
6933 register_power9_mmu_sprs(env);
6934
6935 /* POWER9 Specific registers */
6936 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6937 spr_read_generic, spr_write_generic,
6938 KVM_REG_PPC_TIDR, 0);
6939
6940 /* FIXME: Filter fields properly based on privilege level */
6941 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6942 spr_read_generic, spr_write_generic,
6943 KVM_REG_PPC_PSSCR, 0);
6944
6945 /* env variables */
6946 env->dcache_line_size = 128;
6947 env->icache_line_size = 128;
6948
6949 /* Allocate hardware IRQ controller */
6950 init_excp_POWER9(env);
6951 ppcPOWER9_irq_init(env_archcpu(env));
6952 }
6953
6954 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
6955 {
6956 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
6957 return true;
6958 }
6959 return false;
6960 }
6961
6962 static bool cpu_has_work_POWER9(CPUState *cs)
6963 {
6964 PowerPCCPU *cpu = POWERPC_CPU(cs);
6965 CPUPPCState *env = &cpu->env;
6966
6967 if (cs->halted) {
6968 uint64_t psscr = env->spr[SPR_PSSCR];
6969
6970 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6971 return false;
6972 }
6973
6974 /* If EC is clear, just return true on any pending interrupt */
6975 if (!(psscr & PSSCR_EC)) {
6976 return true;
6977 }
6978 /* External Exception */
6979 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6980 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6981 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
6982 if (heic == 0 || !msr_hv || msr_pr) {
6983 return true;
6984 }
6985 }
6986 /* Decrementer Exception */
6987 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6988 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6989 return true;
6990 }
6991 /* Machine Check or Hypervisor Maintenance Exception */
6992 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6993 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6994 return true;
6995 }
6996 /* Privileged Doorbell Exception */
6997 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6998 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6999 return true;
7000 }
7001 /* Hypervisor Doorbell Exception */
7002 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7003 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7004 return true;
7005 }
7006 /* Hypervisor virtualization exception */
7007 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7008 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7009 return true;
7010 }
7011 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7012 return true;
7013 }
7014 return false;
7015 } else {
7016 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7017 }
7018 }
7019
7020 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
7021 {
7022 DeviceClass *dc = DEVICE_CLASS(oc);
7023 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7024 CPUClass *cc = CPU_CLASS(oc);
7025
7026 dc->fw_name = "PowerPC,POWER9";
7027 dc->desc = "POWER9";
7028 pcc->pvr_match = ppc_pvr_match_power9;
7029 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
7030 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
7031 PCR_COMPAT_2_05;
7032 pcc->init_proc = init_proc_POWER9;
7033 pcc->check_pow = check_pow_nocheck;
7034 cc->has_work = cpu_has_work_POWER9;
7035 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7036 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7037 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7038 PPC_FLOAT_FRSQRTES |
7039 PPC_FLOAT_STFIWX |
7040 PPC_FLOAT_EXT |
7041 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7042 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7043 PPC_MEM_TLBSYNC |
7044 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7045 PPC_SEGMENT_64B | PPC_SLBI |
7046 PPC_POPCNTB | PPC_POPCNTWD |
7047 PPC_CILDST;
7048 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7049 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7050 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7051 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7052 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7053 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7054 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
7055 pcc->msr_mask = (1ull << MSR_SF) |
7056 (1ull << MSR_HV) |
7057 (1ull << MSR_TM) |
7058 (1ull << MSR_VR) |
7059 (1ull << MSR_VSX) |
7060 (1ull << MSR_EE) |
7061 (1ull << MSR_PR) |
7062 (1ull << MSR_FP) |
7063 (1ull << MSR_ME) |
7064 (1ull << MSR_FE0) |
7065 (1ull << MSR_SE) |
7066 (1ull << MSR_DE) |
7067 (1ull << MSR_FE1) |
7068 (1ull << MSR_IR) |
7069 (1ull << MSR_DR) |
7070 (1ull << MSR_PMM) |
7071 (1ull << MSR_RI) |
7072 (1ull << MSR_LE);
7073 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
7074 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
7075 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
7076 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
7077 LPCR_DEE | LPCR_OEE))
7078 | LPCR_MER | LPCR_GTSE | LPCR_TC |
7079 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
7080 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
7081 pcc->mmu_model = POWERPC_MMU_3_00;
7082 #if defined(CONFIG_SOFTMMU)
7083 /* segment page size remain the same */
7084 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7085 pcc->radix_page_info = &POWER9_radix_page_info;
7086 pcc->lrg_decr_bits = 56;
7087 pcc->n_host_threads = 4;
7088 #endif
7089 pcc->excp_model = POWERPC_EXCP_POWER9;
7090 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
7091 pcc->bfd_mach = bfd_mach_ppc64;
7092 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7093 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7094 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7095 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
7096 pcc->l1_dcache_size = 0x8000;
7097 pcc->l1_icache_size = 0x8000;
7098 }
7099
7100 #ifdef CONFIG_SOFTMMU
7101 /*
7102 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
7103 * Encoded as array of int_32s in the form:
7104 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
7105 * x -> AP encoding
7106 * y -> radix mode supported page size (encoded as a shift)
7107 */
7108 static struct ppc_radix_page_info POWER10_radix_page_info = {
7109 .count = 4,
7110 .entries = {
7111 0x0000000c, /* 4K - enc: 0x0 */
7112 0xa0000010, /* 64K - enc: 0x5 */
7113 0x20000015, /* 2M - enc: 0x1 */
7114 0x4000001e /* 1G - enc: 0x2 */
7115 }
7116 };
7117 #endif /* CONFIG_SOFTMMU */
7118
7119 static void init_proc_POWER10(CPUPPCState *env)
7120 {
7121 /* Common Registers */
7122 init_proc_book3s_common(env);
7123 register_book3s_207_dbg_sprs(env);
7124
7125 /* Common TCG PMU */
7126 init_tcg_pmu_power8(env);
7127
7128 /* POWER8 Specific Registers */
7129 register_book3s_ids_sprs(env);
7130 register_amr_sprs(env);
7131 register_iamr_sprs(env);
7132 register_book3s_purr_sprs(env);
7133 register_power5p_common_sprs(env);
7134 register_power5p_lpar_sprs(env);
7135 register_power5p_ear_sprs(env);
7136 register_power6_common_sprs(env);
7137 register_power6_dbg_sprs(env);
7138 register_power8_tce_address_control_sprs(env);
7139 register_power8_ids_sprs(env);
7140 register_power8_ebb_sprs(env);
7141 register_power8_fscr_sprs(env);
7142 register_power8_pmu_sup_sprs(env);
7143 register_power8_pmu_user_sprs(env);
7144 register_power8_tm_sprs(env);
7145 register_power8_pspb_sprs(env);
7146 register_vtb_sprs(env);
7147 register_power8_ic_sprs(env);
7148 register_power8_book4_sprs(env);
7149 register_power8_rpr_sprs(env);
7150 register_power9_mmu_sprs(env);
7151
7152 /* FIXME: Filter fields properly based on privilege level */
7153 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
7154 spr_read_generic, spr_write_generic,
7155 KVM_REG_PPC_PSSCR, 0);
7156
7157 /* env variables */
7158 env->dcache_line_size = 128;
7159 env->icache_line_size = 128;
7160
7161 /* Allocate hardware IRQ controller */
7162 init_excp_POWER10(env);
7163 ppcPOWER9_irq_init(env_archcpu(env));
7164 }
7165
7166 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
7167 {
7168 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
7169 return true;
7170 }
7171 return false;
7172 }
7173
7174 static bool cpu_has_work_POWER10(CPUState *cs)
7175 {
7176 PowerPCCPU *cpu = POWERPC_CPU(cs);
7177 CPUPPCState *env = &cpu->env;
7178
7179 if (cs->halted) {
7180 uint64_t psscr = env->spr[SPR_PSSCR];
7181
7182 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7183 return false;
7184 }
7185
7186 /* If EC is clear, just return true on any pending interrupt */
7187 if (!(psscr & PSSCR_EC)) {
7188 return true;
7189 }
7190 /* External Exception */
7191 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7192 (env->spr[SPR_LPCR] & LPCR_EEE)) {
7193 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
7194 if (heic == 0 || !msr_hv || msr_pr) {
7195 return true;
7196 }
7197 }
7198 /* Decrementer Exception */
7199 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7200 (env->spr[SPR_LPCR] & LPCR_DEE)) {
7201 return true;
7202 }
7203 /* Machine Check or Hypervisor Maintenance Exception */
7204 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
7205 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
7206 return true;
7207 }
7208 /* Privileged Doorbell Exception */
7209 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7210 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
7211 return true;
7212 }
7213 /* Hypervisor Doorbell Exception */
7214 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7215 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7216 return true;
7217 }
7218 /* Hypervisor virtualization exception */
7219 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7220 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7221 return true;
7222 }
7223 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7224 return true;
7225 }
7226 return false;
7227 } else {
7228 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7229 }
7230 }
7231
7232 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
7233 {
7234 DeviceClass *dc = DEVICE_CLASS(oc);
7235 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7236 CPUClass *cc = CPU_CLASS(oc);
7237
7238 dc->fw_name = "PowerPC,POWER10";
7239 dc->desc = "POWER10";
7240 pcc->pvr_match = ppc_pvr_match_power10;
7241 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
7242 PCR_COMPAT_3_00;
7243 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
7244 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7245 pcc->init_proc = init_proc_POWER10;
7246 pcc->check_pow = check_pow_nocheck;
7247 cc->has_work = cpu_has_work_POWER10;
7248 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7249 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7250 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7251 PPC_FLOAT_FRSQRTES |
7252 PPC_FLOAT_STFIWX |
7253 PPC_FLOAT_EXT |
7254 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7255 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7256 PPC_MEM_TLBSYNC |
7257 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7258 PPC_SEGMENT_64B | PPC_SLBI |
7259 PPC_POPCNTB | PPC_POPCNTWD |
7260 PPC_CILDST;
7261 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7262 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7263 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7264 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7265 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7266 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7267 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
7268 pcc->msr_mask = (1ull << MSR_SF) |
7269 (1ull << MSR_HV) |
7270 (1ull << MSR_TM) |
7271 (1ull << MSR_VR) |
7272 (1ull << MSR_VSX) |
7273 (1ull << MSR_EE) |
7274 (1ull << MSR_PR) |
7275 (1ull << MSR_FP) |
7276 (1ull << MSR_ME) |
7277 (1ull << MSR_FE0) |
7278 (1ull << MSR_SE) |
7279 (1ull << MSR_DE) |
7280 (1ull << MSR_FE1) |
7281 (1ull << MSR_IR) |
7282 (1ull << MSR_DR) |
7283 (1ull << MSR_PMM) |
7284 (1ull << MSR_RI) |
7285 (1ull << MSR_LE);
7286 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
7287 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
7288 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
7289 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
7290 LPCR_DEE | LPCR_OEE))
7291 | LPCR_MER | LPCR_GTSE | LPCR_TC |
7292 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
7293 /* DD2 adds an extra HAIL bit */
7294 pcc->lpcr_mask |= LPCR_HAIL;
7295
7296 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
7297 pcc->mmu_model = POWERPC_MMU_3_00;
7298 #if defined(CONFIG_SOFTMMU)
7299 /* segment page size remain the same */
7300 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7301 pcc->radix_page_info = &POWER10_radix_page_info;
7302 pcc->lrg_decr_bits = 56;
7303 #endif
7304 pcc->excp_model = POWERPC_EXCP_POWER10;
7305 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
7306 pcc->bfd_mach = bfd_mach_ppc64;
7307 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7308 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7309 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7310 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
7311 pcc->l1_dcache_size = 0x8000;
7312 pcc->l1_icache_size = 0x8000;
7313 }
7314
7315 #if !defined(CONFIG_USER_ONLY)
7316 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
7317 {
7318 CPUPPCState *env = &cpu->env;
7319
7320 cpu->vhyp = vhyp;
7321
7322 /*
7323 * With a virtual hypervisor mode we never allow the CPU to go
7324 * hypervisor mode itself
7325 */
7326 env->msr_mask &= ~MSR_HVB;
7327 }
7328
7329 #endif /* !defined(CONFIG_USER_ONLY) */
7330
7331 #endif /* defined(TARGET_PPC64) */
7332
7333 /*****************************************************************************/
7334 /* Generic CPU instantiation routine */
7335 static void init_ppc_proc(PowerPCCPU *cpu)
7336 {
7337 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7338 CPUPPCState *env = &cpu->env;
7339 #if !defined(CONFIG_USER_ONLY)
7340 int i;
7341
7342 env->irq_inputs = NULL;
7343 /* Set all exception vectors to an invalid address */
7344 for (i = 0; i < POWERPC_EXCP_NB; i++) {
7345 env->excp_vectors[i] = (target_ulong)(-1ULL);
7346 }
7347 env->ivor_mask = 0x00000000;
7348 env->ivpr_mask = 0x00000000;
7349 /* Default MMU definitions */
7350 env->nb_BATs = 0;
7351 env->nb_tlb = 0;
7352 env->nb_ways = 0;
7353 env->tlb_type = TLB_NONE;
7354 #endif
7355 /* Register SPR common to all PowerPC implementations */
7356 register_generic_sprs(env);
7357 spr_register(env, SPR_PVR, "PVR",
7358 /* Linux permits userspace to read PVR */
7359 #if defined(CONFIG_LINUX_USER)
7360 &spr_read_generic,
7361 #else
7362 SPR_NOACCESS,
7363 #endif
7364 SPR_NOACCESS,
7365 &spr_read_generic, SPR_NOACCESS,
7366 pcc->pvr);
7367 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7368 if (pcc->svr != POWERPC_SVR_NONE) {
7369 if (pcc->svr & POWERPC_SVR_E500) {
7370 spr_register(env, SPR_E500_SVR, "SVR",
7371 SPR_NOACCESS, SPR_NOACCESS,
7372 &spr_read_generic, SPR_NOACCESS,
7373 pcc->svr & ~POWERPC_SVR_E500);
7374 } else {
7375 spr_register(env, SPR_SVR, "SVR",
7376 SPR_NOACCESS, SPR_NOACCESS,
7377 &spr_read_generic, SPR_NOACCESS,
7378 pcc->svr);
7379 }
7380 }
7381 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7382 (*pcc->init_proc)(env);
7383
7384 #if !defined(CONFIG_USER_ONLY)
7385 ppc_gdb_gen_spr_xml(cpu);
7386 #endif
7387
7388 /* MSR bits & flags consistency checks */
7389 if (env->msr_mask & (1 << 25)) {
7390 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7391 case POWERPC_FLAG_SPE:
7392 case POWERPC_FLAG_VRE:
7393 break;
7394 default:
7395 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7396 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7397 exit(1);
7398 }
7399 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7400 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7401 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7402 exit(1);
7403 }
7404 if (env->msr_mask & (1 << 17)) {
7405 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7406 case POWERPC_FLAG_TGPR:
7407 case POWERPC_FLAG_CE:
7408 break;
7409 default:
7410 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7411 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7412 exit(1);
7413 }
7414 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7415 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7416 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7417 exit(1);
7418 }
7419 if (env->msr_mask & (1 << 10)) {
7420 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7421 POWERPC_FLAG_UBLE)) {
7422 case POWERPC_FLAG_SE:
7423 case POWERPC_FLAG_DWE:
7424 case POWERPC_FLAG_UBLE:
7425 break;
7426 default:
7427 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7428 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7429 "POWERPC_FLAG_UBLE\n");
7430 exit(1);
7431 }
7432 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7433 POWERPC_FLAG_UBLE)) {
7434 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7435 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7436 "POWERPC_FLAG_UBLE\n");
7437 exit(1);
7438 }
7439 if (env->msr_mask & (1 << 9)) {
7440 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7441 case POWERPC_FLAG_BE:
7442 case POWERPC_FLAG_DE:
7443 break;
7444 default:
7445 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7446 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7447 exit(1);
7448 }
7449 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7450 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7451 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7452 exit(1);
7453 }
7454 if (env->msr_mask & (1 << 2)) {
7455 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7456 case POWERPC_FLAG_PX:
7457 case POWERPC_FLAG_PMM:
7458 break;
7459 default:
7460 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7461 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7462 exit(1);
7463 }
7464 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7465 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7466 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7467 exit(1);
7468 }
7469 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
7470 fprintf(stderr, "PowerPC flags inconsistency\n"
7471 "Should define the time-base and decrementer clock source\n");
7472 exit(1);
7473 }
7474 /* Allocate TLBs buffer when needed */
7475 #if !defined(CONFIG_USER_ONLY)
7476 if (env->nb_tlb != 0) {
7477 int nb_tlb = env->nb_tlb;
7478 if (env->id_tlbs != 0) {
7479 nb_tlb *= 2;
7480 }
7481 switch (env->tlb_type) {
7482 case TLB_6XX:
7483 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
7484 break;
7485 case TLB_EMB:
7486 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
7487 break;
7488 case TLB_MAS:
7489 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
7490 break;
7491 }
7492 /* Pre-compute some useful values */
7493 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7494 }
7495 if (env->irq_inputs == NULL) {
7496 warn_report("no internal IRQ controller registered."
7497 " Attempt QEMU to crash very soon !");
7498 }
7499 #endif
7500 if (env->check_pow == NULL) {
7501 warn_report("no power management check handler registered."
7502 " Attempt QEMU to crash very soon !");
7503 }
7504 }
7505
7506
7507 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
7508 {
7509 CPUState *cs = CPU(dev);
7510 PowerPCCPU *cpu = POWERPC_CPU(dev);
7511 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7512 Error *local_err = NULL;
7513
7514 cpu_exec_realizefn(cs, &local_err);
7515 if (local_err != NULL) {
7516 error_propagate(errp, local_err);
7517 return;
7518 }
7519 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
7520 cpu->vcpu_id = cs->cpu_index;
7521 }
7522
7523 if (tcg_enabled()) {
7524 if (ppc_fixup_cpu(cpu) != 0) {
7525 error_setg(errp, "Unable to emulate selected CPU with TCG");
7526 goto unrealize;
7527 }
7528 }
7529
7530 create_ppc_opcodes(cpu, &local_err);
7531 if (local_err != NULL) {
7532 error_propagate(errp, local_err);
7533 goto unrealize;
7534 }
7535 init_ppc_proc(cpu);
7536
7537 ppc_gdb_init(cs, pcc);
7538 qemu_init_vcpu(cs);
7539
7540 pcc->parent_realize(dev, errp);
7541
7542 return;
7543
7544 unrealize:
7545 cpu_exec_unrealizefn(cs);
7546 }
7547
7548 static void ppc_cpu_unrealize(DeviceState *dev)
7549 {
7550 PowerPCCPU *cpu = POWERPC_CPU(dev);
7551 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7552
7553 pcc->parent_unrealize(dev);
7554
7555 cpu_remove_sync(CPU(cpu));
7556
7557 destroy_ppc_opcodes(cpu);
7558 }
7559
7560 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7561 {
7562 ObjectClass *oc = (ObjectClass *)a;
7563 uint32_t pvr = *(uint32_t *)b;
7564 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7565
7566 /* -cpu host does a PVR lookup during construction */
7567 if (unlikely(strcmp(object_class_get_name(oc),
7568 TYPE_HOST_POWERPC_CPU) == 0)) {
7569 return -1;
7570 }
7571
7572 return pcc->pvr == pvr ? 0 : -1;
7573 }
7574
7575 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7576 {
7577 GSList *list, *item;
7578 PowerPCCPUClass *pcc = NULL;
7579
7580 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7581 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7582 if (item != NULL) {
7583 pcc = POWERPC_CPU_CLASS(item->data);
7584 }
7585 g_slist_free(list);
7586
7587 return pcc;
7588 }
7589
7590 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
7591 {
7592 ObjectClass *oc = (ObjectClass *)a;
7593 uint32_t pvr = *(uint32_t *)b;
7594 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7595
7596 /* -cpu host does a PVR lookup during construction */
7597 if (unlikely(strcmp(object_class_get_name(oc),
7598 TYPE_HOST_POWERPC_CPU) == 0)) {
7599 return -1;
7600 }
7601
7602 if (pcc->pvr_match(pcc, pvr)) {
7603 return 0;
7604 }
7605
7606 return -1;
7607 }
7608
7609 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
7610 {
7611 GSList *list, *item;
7612 PowerPCCPUClass *pcc = NULL;
7613
7614 list = object_class_get_list(TYPE_POWERPC_CPU, true);
7615 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
7616 if (item != NULL) {
7617 pcc = POWERPC_CPU_CLASS(item->data);
7618 }
7619 g_slist_free(list);
7620
7621 return pcc;
7622 }
7623
7624 static const char *ppc_cpu_lookup_alias(const char *alias)
7625 {
7626 int ai;
7627
7628 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
7629 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7630 return ppc_cpu_aliases[ai].model;
7631 }
7632 }
7633
7634 return NULL;
7635 }
7636
7637 static ObjectClass *ppc_cpu_class_by_name(const char *name)
7638 {
7639 char *cpu_model, *typename;
7640 ObjectClass *oc;
7641 const char *p;
7642 unsigned long pvr;
7643
7644 /*
7645 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7646 * 0x prefix if present)
7647 */
7648 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7649 int len = p - name;
7650 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7651 if ((len == 8) && (*p == '\0')) {
7652 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
7653 }
7654 }
7655
7656 cpu_model = g_ascii_strdown(name, -1);
7657 p = ppc_cpu_lookup_alias(cpu_model);
7658 if (p) {
7659 g_free(cpu_model);
7660 cpu_model = g_strdup(p);
7661 }
7662
7663 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7664 oc = object_class_by_name(typename);
7665 g_free(typename);
7666 g_free(cpu_model);
7667
7668 return oc;
7669 }
7670
7671 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7672 {
7673 ObjectClass *oc = OBJECT_CLASS(pcc);
7674
7675 while (oc && !object_class_is_abstract(oc)) {
7676 oc = object_class_get_parent(oc);
7677 }
7678 assert(oc);
7679
7680 return POWERPC_CPU_CLASS(oc);
7681 }
7682
7683 /* Sort by PVR, ordering special case "host" last. */
7684 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7685 {
7686 ObjectClass *oc_a = (ObjectClass *)a;
7687 ObjectClass *oc_b = (ObjectClass *)b;
7688 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7689 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7690 const char *name_a = object_class_get_name(oc_a);
7691 const char *name_b = object_class_get_name(oc_b);
7692
7693 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7694 return 1;
7695 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7696 return -1;
7697 } else {
7698 /* Avoid an integer overflow during subtraction */
7699 if (pcc_a->pvr < pcc_b->pvr) {
7700 return -1;
7701 } else if (pcc_a->pvr > pcc_b->pvr) {
7702 return 1;
7703 } else {
7704 return 0;
7705 }
7706 }
7707 }
7708
7709 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7710 {
7711 ObjectClass *oc = data;
7712 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7713 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7714 const char *typename = object_class_get_name(oc);
7715 char *name;
7716 int i;
7717
7718 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7719 return;
7720 }
7721
7722 name = g_strndup(typename,
7723 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7724 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
7725 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7726 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7727 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7728
7729 if (alias_oc != oc) {
7730 continue;
7731 }
7732 /*
7733 * If running with KVM, we might update the family alias later, so
7734 * avoid printing the wrong alias here and use "preferred" instead
7735 */
7736 if (strcmp(alias->alias, family->desc) == 0) {
7737 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7738 alias->alias, family->desc);
7739 } else {
7740 qemu_printf("PowerPC %-16s (alias for %s)\n",
7741 alias->alias, name);
7742 }
7743 }
7744 g_free(name);
7745 }
7746
7747 void ppc_cpu_list(void)
7748 {
7749 GSList *list;
7750
7751 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7752 list = g_slist_sort(list, ppc_cpu_list_compare);
7753 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7754 g_slist_free(list);
7755
7756 #ifdef CONFIG_KVM
7757 qemu_printf("\n");
7758 qemu_printf("PowerPC %s\n", "host");
7759 #endif
7760 }
7761
7762 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
7763 {
7764 ObjectClass *oc = data;
7765 CpuDefinitionInfoList **first = user_data;
7766 const char *typename;
7767 CpuDefinitionInfo *info;
7768
7769 typename = object_class_get_name(oc);
7770 info = g_malloc0(sizeof(*info));
7771 info->name = g_strndup(typename,
7772 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7773
7774 QAPI_LIST_PREPEND(*first, info);
7775 }
7776
7777 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
7778 {
7779 CpuDefinitionInfoList *cpu_list = NULL;
7780 GSList *list;
7781 int i;
7782
7783 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7784 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
7785 g_slist_free(list);
7786
7787 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7788 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7789 ObjectClass *oc;
7790 CpuDefinitionInfo *info;
7791
7792 oc = ppc_cpu_class_by_name(alias->model);
7793 if (oc == NULL) {
7794 continue;
7795 }
7796
7797 info = g_malloc0(sizeof(*info));
7798 info->name = g_strdup(alias->alias);
7799 info->q_typename = g_strdup(object_class_get_name(oc));
7800
7801 QAPI_LIST_PREPEND(cpu_list, info);
7802 }
7803
7804 return cpu_list;
7805 }
7806
7807 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7808 {
7809 PowerPCCPU *cpu = POWERPC_CPU(cs);
7810
7811 cpu->env.nip = value;
7812 }
7813
7814 static bool ppc_cpu_has_work(CPUState *cs)
7815 {
7816 PowerPCCPU *cpu = POWERPC_CPU(cs);
7817 CPUPPCState *env = &cpu->env;
7818
7819 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7820 }
7821
7822 static void ppc_cpu_reset(DeviceState *dev)
7823 {
7824 CPUState *s = CPU(dev);
7825 PowerPCCPU *cpu = POWERPC_CPU(s);
7826 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7827 CPUPPCState *env = &cpu->env;
7828 target_ulong msr;
7829 int i;
7830
7831 pcc->parent_reset(dev);
7832
7833 msr = (target_ulong)0;
7834 msr |= (target_ulong)MSR_HVB;
7835 msr |= (target_ulong)1 << MSR_EP;
7836 #if defined(DO_SINGLE_STEP) && 0
7837 /* Single step trace mode */
7838 msr |= (target_ulong)1 << MSR_SE;
7839 msr |= (target_ulong)1 << MSR_BE;
7840 #endif
7841 #if defined(CONFIG_USER_ONLY)
7842 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7843 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7844 msr |= (target_ulong)1 << MSR_FE1;
7845 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7846 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7847 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7848 msr |= (target_ulong)1 << MSR_PR;
7849 #if defined(TARGET_PPC64)
7850 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7851 #endif
7852 #if !defined(TARGET_WORDS_BIGENDIAN)
7853 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7854 if (!((env->msr_mask >> MSR_LE) & 1)) {
7855 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7856 exit(1);
7857 }
7858 #endif
7859 #endif
7860
7861 #if defined(TARGET_PPC64)
7862 if (mmu_is_64bit(env->mmu_model)) {
7863 msr |= (1ULL << MSR_SF);
7864 }
7865 #endif
7866
7867 hreg_store_msr(env, msr, 1);
7868
7869 #if !defined(CONFIG_USER_ONLY)
7870 env->nip = env->hreset_vector | env->excp_prefix;
7871 #if defined(CONFIG_TCG)
7872 if (env->mmu_model != POWERPC_MMU_REAL) {
7873 ppc_tlb_invalidate_all(env);
7874 }
7875 #endif /* CONFIG_TCG */
7876 #endif
7877
7878 pmu_update_summaries(env);
7879 hreg_compute_hflags(env);
7880 env->reserve_addr = (target_ulong)-1ULL;
7881 /* Be sure no exception or interrupt is pending */
7882 env->pending_interrupts = 0;
7883 s->exception_index = POWERPC_EXCP_NONE;
7884 env->error_code = 0;
7885 ppc_irq_reset(cpu);
7886
7887 /* tininess for underflow is detected before rounding */
7888 set_float_detect_tininess(float_tininess_before_rounding,
7889 &env->fp_status);
7890
7891 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7892 ppc_spr_t *spr = &env->spr_cb[i];
7893
7894 if (!spr->name) {
7895 continue;
7896 }
7897 env->spr[i] = spr->default_value;
7898 }
7899 }
7900
7901 #ifndef CONFIG_USER_ONLY
7902
7903 static bool ppc_cpu_is_big_endian(CPUState *cs)
7904 {
7905 PowerPCCPU *cpu = POWERPC_CPU(cs);
7906 CPUPPCState *env = &cpu->env;
7907
7908 cpu_synchronize_state(cs);
7909
7910 return !msr_le;
7911 }
7912
7913 #ifdef CONFIG_TCG
7914 static void ppc_cpu_exec_enter(CPUState *cs)
7915 {
7916 PowerPCCPU *cpu = POWERPC_CPU(cs);
7917
7918 if (cpu->vhyp) {
7919 PPCVirtualHypervisorClass *vhc =
7920 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7921 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7922 }
7923 }
7924
7925 static void ppc_cpu_exec_exit(CPUState *cs)
7926 {
7927 PowerPCCPU *cpu = POWERPC_CPU(cs);
7928
7929 if (cpu->vhyp) {
7930 PPCVirtualHypervisorClass *vhc =
7931 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7932 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7933 }
7934 }
7935 #endif /* CONFIG_TCG */
7936
7937 #endif /* !CONFIG_USER_ONLY */
7938
7939 static void ppc_cpu_instance_init(Object *obj)
7940 {
7941 PowerPCCPU *cpu = POWERPC_CPU(obj);
7942 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7943 CPUPPCState *env = &cpu->env;
7944
7945 cpu_set_cpustate_pointers(cpu);
7946 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7947
7948 env->msr_mask = pcc->msr_mask;
7949 env->mmu_model = pcc->mmu_model;
7950 env->excp_model = pcc->excp_model;
7951 env->bus_model = pcc->bus_model;
7952 env->insns_flags = pcc->insns_flags;
7953 env->insns_flags2 = pcc->insns_flags2;
7954 env->flags = pcc->flags;
7955 env->bfd_mach = pcc->bfd_mach;
7956 env->check_pow = pcc->check_pow;
7957
7958 /*
7959 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7960 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7961 * mode support will remain, thus enforcing that we cannot use
7962 * priv. instructions in guest in PAPR mode. For 970 we currently
7963 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7964 * 970. If we ever want to support 970 HV mode, we'll have to add
7965 * a processor attribute of some sort.
7966 */
7967 #if !defined(CONFIG_USER_ONLY)
7968 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7969 #endif
7970
7971 ppc_hash64_init(cpu);
7972 }
7973
7974 static void ppc_cpu_instance_finalize(Object *obj)
7975 {
7976 PowerPCCPU *cpu = POWERPC_CPU(obj);
7977
7978 ppc_hash64_finalize(cpu);
7979 }
7980
7981 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
7982 {
7983 return pcc->pvr == pvr;
7984 }
7985
7986 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7987 {
7988 PowerPCCPU *cpu = POWERPC_CPU(cs);
7989 CPUPPCState *env = &cpu->env;
7990
7991 if ((env->hflags >> MSR_LE) & 1) {
7992 info->endian = BFD_ENDIAN_LITTLE;
7993 }
7994 info->mach = env->bfd_mach;
7995 if (!env->bfd_mach) {
7996 #ifdef TARGET_PPC64
7997 info->mach = bfd_mach_ppc64;
7998 #else
7999 info->mach = bfd_mach_ppc;
8000 #endif
8001 }
8002 info->disassembler_options = (char *)"any";
8003 info->print_insn = print_insn_ppc;
8004
8005 info->cap_arch = CS_ARCH_PPC;
8006 #ifdef TARGET_PPC64
8007 info->cap_mode = CS_MODE_64;
8008 #endif
8009 }
8010
8011 static Property ppc_cpu_properties[] = {
8012 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
8013 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
8014 false),
8015 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
8016 false),
8017 DEFINE_PROP_END_OF_LIST(),
8018 };
8019
8020 #ifndef CONFIG_USER_ONLY
8021 #include "hw/core/sysemu-cpu-ops.h"
8022
8023 static const struct SysemuCPUOps ppc_sysemu_ops = {
8024 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
8025 .write_elf32_note = ppc32_cpu_write_elf32_note,
8026 .write_elf64_note = ppc64_cpu_write_elf64_note,
8027 .virtio_is_big_endian = ppc_cpu_is_big_endian,
8028 .legacy_vmsd = &vmstate_ppc_cpu,
8029 };
8030 #endif
8031
8032 #ifdef CONFIG_TCG
8033 #include "hw/core/tcg-cpu-ops.h"
8034
8035 static const struct TCGCPUOps ppc_tcg_ops = {
8036 .initialize = ppc_translate_init,
8037
8038 #ifdef CONFIG_USER_ONLY
8039 .record_sigsegv = ppc_cpu_record_sigsegv,
8040 #else
8041 .tlb_fill = ppc_cpu_tlb_fill,
8042 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
8043 .do_interrupt = ppc_cpu_do_interrupt,
8044 .cpu_exec_enter = ppc_cpu_exec_enter,
8045 .cpu_exec_exit = ppc_cpu_exec_exit,
8046 .do_unaligned_access = ppc_cpu_do_unaligned_access,
8047 #endif /* !CONFIG_USER_ONLY */
8048 };
8049 #endif /* CONFIG_TCG */
8050
8051 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8052 {
8053 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8054 CPUClass *cc = CPU_CLASS(oc);
8055 DeviceClass *dc = DEVICE_CLASS(oc);
8056
8057 device_class_set_parent_realize(dc, ppc_cpu_realize,
8058 &pcc->parent_realize);
8059 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
8060 &pcc->parent_unrealize);
8061 pcc->pvr_match = ppc_pvr_match_default;
8062 device_class_set_props(dc, ppc_cpu_properties);
8063
8064 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
8065
8066 cc->class_by_name = ppc_cpu_class_by_name;
8067 cc->has_work = ppc_cpu_has_work;
8068 cc->dump_state = ppc_cpu_dump_state;
8069 cc->set_pc = ppc_cpu_set_pc;
8070 cc->gdb_read_register = ppc_cpu_gdb_read_register;
8071 cc->gdb_write_register = ppc_cpu_gdb_write_register;
8072 #ifndef CONFIG_USER_ONLY
8073 cc->sysemu_ops = &ppc_sysemu_ops;
8074 #endif
8075
8076 cc->gdb_num_core_regs = 71;
8077 #ifndef CONFIG_USER_ONLY
8078 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
8079 #endif
8080 #ifdef USE_APPLE_GDB
8081 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
8082 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
8083 cc->gdb_num_core_regs = 71 + 32;
8084 #endif
8085
8086 cc->gdb_arch_name = ppc_gdb_arch_name;
8087 #if defined(TARGET_PPC64)
8088 cc->gdb_core_xml_file = "power64-core.xml";
8089 #else
8090 cc->gdb_core_xml_file = "power-core.xml";
8091 #endif
8092 cc->disas_set_info = ppc_disas_set_info;
8093
8094 dc->fw_name = "PowerPC,UNKNOWN";
8095
8096 #ifdef CONFIG_TCG
8097 cc->tcg_ops = &ppc_tcg_ops;
8098 #endif /* CONFIG_TCG */
8099 }
8100
8101 static const TypeInfo ppc_cpu_type_info = {
8102 .name = TYPE_POWERPC_CPU,
8103 .parent = TYPE_CPU,
8104 .instance_size = sizeof(PowerPCCPU),
8105 .instance_align = __alignof__(PowerPCCPU),
8106 .instance_init = ppc_cpu_instance_init,
8107 .instance_finalize = ppc_cpu_instance_finalize,
8108 .abstract = true,
8109 .class_size = sizeof(PowerPCCPUClass),
8110 .class_init = ppc_cpu_class_init,
8111 };
8112
8113 #ifndef CONFIG_USER_ONLY
8114 static const TypeInfo ppc_vhyp_type_info = {
8115 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
8116 .parent = TYPE_INTERFACE,
8117 .class_size = sizeof(PPCVirtualHypervisorClass),
8118 };
8119 #endif
8120
8121 static void ppc_cpu_register_types(void)
8122 {
8123 type_register_static(&ppc_cpu_type_info);
8124 #ifndef CONFIG_USER_ONLY
8125 type_register_static(&ppc_vhyp_type_info);
8126 #endif
8127 }
8128
8129 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
8130 {
8131 #define RGPL 4
8132 #define RFPL 4
8133
8134 PowerPCCPU *cpu = POWERPC_CPU(cs);
8135 CPUPPCState *env = &cpu->env;
8136 int i;
8137
8138 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
8139 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
8140 env->nip, env->lr, env->ctr, cpu_read_xer(env),
8141 cs->cpu_index);
8142 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
8143 "%08x iidx %d didx %d\n",
8144 env->msr, env->spr[SPR_HID0], env->hflags,
8145 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
8146 #if !defined(NO_TIMER_DUMP)
8147 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
8148 #if !defined(CONFIG_USER_ONLY)
8149 " DECR " TARGET_FMT_lu
8150 #endif
8151 "\n",
8152 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8153 #if !defined(CONFIG_USER_ONLY)
8154 , cpu_ppc_load_decr(env)
8155 #endif
8156 );
8157 #endif
8158 for (i = 0; i < 32; i++) {
8159 if ((i & (RGPL - 1)) == 0) {
8160 qemu_fprintf(f, "GPR%02d", i);
8161 }
8162 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
8163 if ((i & (RGPL - 1)) == (RGPL - 1)) {
8164 qemu_fprintf(f, "\n");
8165 }
8166 }
8167 qemu_fprintf(f, "CR ");
8168 for (i = 0; i < 8; i++)
8169 qemu_fprintf(f, "%01x", env->crf[i]);
8170 qemu_fprintf(f, " [");
8171 for (i = 0; i < 8; i++) {
8172 char a = '-';
8173 if (env->crf[i] & 0x08) {
8174 a = 'L';
8175 } else if (env->crf[i] & 0x04) {
8176 a = 'G';
8177 } else if (env->crf[i] & 0x02) {
8178 a = 'E';
8179 }
8180 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8181 }
8182 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
8183 env->reserve_addr);
8184
8185 if (flags & CPU_DUMP_FPU) {
8186 for (i = 0; i < 32; i++) {
8187 if ((i & (RFPL - 1)) == 0) {
8188 qemu_fprintf(f, "FPR%02d", i);
8189 }
8190 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
8191 if ((i & (RFPL - 1)) == (RFPL - 1)) {
8192 qemu_fprintf(f, "\n");
8193 }
8194 }
8195 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
8196 }
8197
8198 #if !defined(CONFIG_USER_ONLY)
8199 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
8200 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
8201 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
8202 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
8203
8204 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
8205 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
8206 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
8207 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
8208
8209 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
8210 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
8211 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
8212 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
8213
8214 switch (env->excp_model) {
8215 #if defined(TARGET_PPC64)
8216 case POWERPC_EXCP_POWER7:
8217 case POWERPC_EXCP_POWER8:
8218 case POWERPC_EXCP_POWER9:
8219 case POWERPC_EXCP_POWER10:
8220 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
8221 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
8222 break;
8223 #endif
8224 case POWERPC_EXCP_BOOKE:
8225 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
8226 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
8227 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
8228 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
8229
8230 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8231 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8232 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
8233 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
8234
8235 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
8236 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
8237 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
8238 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
8239
8240 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
8241 " EPR " TARGET_FMT_lx "\n",
8242 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
8243 env->spr[SPR_BOOKE_EPR]);
8244
8245 /* FSL-specific */
8246 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
8247 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
8248 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
8249 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
8250
8251 /*
8252 * IVORs are left out as they are large and do not change often --
8253 * they can be read with "p $ivor0", "p $ivor1", etc.
8254 */
8255 break;
8256 case POWERPC_EXCP_40x:
8257 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8258 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8259 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
8260 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
8261
8262 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
8263 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8264 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
8265 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
8266 break;
8267 default:
8268 break;
8269 }
8270
8271 #if defined(TARGET_PPC64)
8272 if (env->flags & POWERPC_FLAG_CFAR) {
8273 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
8274 }
8275 #endif
8276
8277 if (env->spr_cb[SPR_LPCR].name) {
8278 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
8279 }
8280
8281 switch (env->mmu_model) {
8282 case POWERPC_MMU_32B:
8283 case POWERPC_MMU_SOFT_6xx:
8284 #if defined(TARGET_PPC64)
8285 case POWERPC_MMU_64B:
8286 case POWERPC_MMU_2_03:
8287 case POWERPC_MMU_2_06:
8288 case POWERPC_MMU_2_07:
8289 case POWERPC_MMU_3_00:
8290 #endif
8291 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
8292 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
8293 }
8294 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
8295 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
8296 }
8297 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
8298 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
8299 break;
8300 case POWERPC_MMU_BOOKE206:
8301 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
8302 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
8303 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
8304 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
8305
8306 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
8307 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8308 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
8309 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
8310
8311 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
8312 " TLB1CFG " TARGET_FMT_lx "\n",
8313 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
8314 env->spr[SPR_BOOKE_TLB1CFG]);
8315 break;
8316 default:
8317 break;
8318 }
8319 #endif
8320
8321 #undef RGPL
8322 #undef RFPL
8323 }
8324 type_init(ppc_cpu_register_types)
QEmu