2 * QEMU Ultrasparc APB PCI host
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2012,2013 Artyom Tarasenko
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* XXX This file and most of its contents are somewhat misnamed. The
27 Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
28 the secondary PCI bridge. */
30 #include "qemu/osdep.h"
31 #include "hw/sysbus.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/pci/pci_bridge.h"
35 #include "hw/pci/pci_bus.h"
36 #include "hw/pci-host/apb.h"
37 #include "sysemu/sysemu.h"
38 #include "exec/address-spaces.h"
45 #define APB_DPRINTF(fmt, ...) \
46 do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
48 #define APB_DPRINTF(fmt, ...)
55 #define IOMMU_DPRINTF(fmt, ...) \
56 do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
58 #define IOMMU_DPRINTF(fmt, ...)
63 * PBM: "UltraSPARC IIi User's Manual",
64 * http://www.sun.com/processors/manuals/805-0087.pdf
66 * APB: "Advanced PCI Bridge (APB) User's Manual",
67 * http://www.sun.com/processors/manuals/805-1251.pdf
70 #define PBM_PCI_IMR_MASK 0x7fffffff
71 #define PBM_PCI_IMR_ENABLED 0x80000000
73 #define POR (1U << 31)
74 #define SOFT_POR (1U << 30)
75 #define SOFT_XIR (1U << 29)
76 #define BTN_POR (1U << 28)
77 #define BTN_XIR (1U << 27)
78 #define RESET_MASK 0xf8000000
79 #define RESET_WCMASK 0x98000000
80 #define RESET_WMASK 0x60000000
83 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
85 #define IOMMU_PAGE_SIZE_8K (1ULL << 13)
86 #define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1))
87 #define IOMMU_PAGE_SIZE_64K (1ULL << 16)
88 #define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1))
92 #define IOMMU_CTRL 0x0
93 #define IOMMU_CTRL_TBW_SIZE (1ULL << 2)
94 #define IOMMU_CTRL_MMU_EN (1ULL)
96 #define IOMMU_CTRL_TSB_SHIFT 16
98 #define IOMMU_BASE 0x8
99 #define IOMMU_FLUSH 0x10
101 #define IOMMU_TTE_DATA_V (1ULL << 63)
102 #define IOMMU_TTE_DATA_SIZE (1ULL << 61)
103 #define IOMMU_TTE_DATA_W (1ULL << 1)
105 #define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL
106 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
108 #define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL
109 #define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL
110 #define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL
111 #define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL
112 #define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL
113 #define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL
114 #define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL
115 #define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL
117 #define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL
118 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
119 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
120 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
121 #define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL
122 #define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL
124 typedef struct IOMMUState
{
125 AddressSpace iommu_as
;
126 IOMMUMemoryRegion iommu
;
128 uint64_t regs
[IOMMU_NREGS
];
131 #define TYPE_APB "pbm"
133 #define APB_DEVICE(obj) \
134 OBJECT_CHECK(APBState, (obj), TYPE_APB)
136 #define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region"
138 typedef struct APBState
{
139 PCIHostState parent_obj
;
141 MemoryRegion apb_config
;
142 MemoryRegion pci_config
;
143 MemoryRegion pci_mmio
;
144 MemoryRegion pci_ioport
;
147 uint32_t pci_control
[16];
148 uint32_t pci_irq_map
[8];
149 uint32_t pci_err_irq_map
[4];
150 uint32_t obio_irq_map
[32];
153 unsigned int irq_request
;
154 uint32_t reset_control
;
155 unsigned int nr_resets
;
158 #define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
159 #define PBM_PCI_BRIDGE(obj) \
160 OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
162 typedef struct PBMPCIBridge
{
164 PCIBridge parent_obj
;
166 /* Is this busA with in-built devices (ebus)? */
170 static inline void pbm_set_request(APBState
*s
, unsigned int irq_num
)
172 APB_DPRINTF("%s: request irq %d\n", __func__
, irq_num
);
174 s
->irq_request
= irq_num
;
175 qemu_set_irq(s
->ivec_irqs
[irq_num
], 1);
178 static inline void pbm_check_irqs(APBState
*s
)
183 /* Previous request is not acknowledged, resubmit */
184 if (s
->irq_request
!= NO_IRQ_REQUEST
) {
185 pbm_set_request(s
, s
->irq_request
);
188 /* no request pending */
189 if (s
->pci_irq_in
== 0ULL) {
192 for (i
= 0; i
< 32; i
++) {
193 if (s
->pci_irq_in
& (1ULL << i
)) {
194 if (s
->pci_irq_map
[i
>> 2] & PBM_PCI_IMR_ENABLED
) {
195 pbm_set_request(s
, i
);
200 for (i
= 32; i
< 64; i
++) {
201 if (s
->pci_irq_in
& (1ULL << i
)) {
202 if (s
->obio_irq_map
[i
- 32] & PBM_PCI_IMR_ENABLED
) {
203 pbm_set_request(s
, i
);
210 static inline void pbm_clear_request(APBState
*s
, unsigned int irq_num
)
212 APB_DPRINTF("%s: clear request irq %d\n", __func__
, irq_num
);
213 qemu_set_irq(s
->ivec_irqs
[irq_num
], 0);
214 s
->irq_request
= NO_IRQ_REQUEST
;
217 static AddressSpace
*pbm_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
219 IOMMUState
*is
= opaque
;
221 return &is
->iommu_as
;
224 /* Called from RCU critical section */
225 static IOMMUTLBEntry
pbm_translate_iommu(IOMMUMemoryRegion
*iommu
, hwaddr addr
,
226 IOMMUAccessFlags flag
)
228 IOMMUState
*is
= container_of(iommu
, IOMMUState
, iommu
);
229 hwaddr baseaddr
, offset
;
232 IOMMUTLBEntry ret
= {
233 .target_as
= &address_space_memory
,
235 .translated_addr
= 0,
236 .addr_mask
= ~(hwaddr
)0,
240 if (!(is
->regs
[IOMMU_CTRL
>> 3] & IOMMU_CTRL_MMU_EN
)) {
241 /* IOMMU disabled, passthrough using standard 8K page */
242 ret
.iova
= addr
& IOMMU_PAGE_MASK_8K
;
243 ret
.translated_addr
= addr
;
244 ret
.addr_mask
= IOMMU_PAGE_MASK_8K
;
250 baseaddr
= is
->regs
[IOMMU_BASE
>> 3];
251 tsbsize
= (is
->regs
[IOMMU_CTRL
>> 3] >> IOMMU_CTRL_TSB_SHIFT
) & 0x7;
253 if (is
->regs
[IOMMU_CTRL
>> 3] & IOMMU_CTRL_TBW_SIZE
) {
257 offset
= (addr
& IOMMU_TSB_64K_OFFSET_MASK_64M
) >> 13;
260 offset
= (addr
& IOMMU_TSB_64K_OFFSET_MASK_128M
) >> 13;
263 offset
= (addr
& IOMMU_TSB_64K_OFFSET_MASK_256M
) >> 13;
266 offset
= (addr
& IOMMU_TSB_64K_OFFSET_MASK_512M
) >> 13;
269 offset
= (addr
& IOMMU_TSB_64K_OFFSET_MASK_1G
) >> 13;
272 offset
= (addr
& IOMMU_TSB_64K_OFFSET_MASK_2G
) >> 13;
275 /* Not implemented, error */
282 offset
= (addr
& IOMMU_TSB_8K_OFFSET_MASK_8M
) >> 10;
285 offset
= (addr
& IOMMU_TSB_8K_OFFSET_MASK_16M
) >> 10;
288 offset
= (addr
& IOMMU_TSB_8K_OFFSET_MASK_32M
) >> 10;
291 offset
= (addr
& IOMMU_TSB_8K_OFFSET_MASK_64M
) >> 10;
294 offset
= (addr
& IOMMU_TSB_8K_OFFSET_MASK_128M
) >> 10;
297 offset
= (addr
& IOMMU_TSB_8K_OFFSET_MASK_256M
) >> 10;
300 offset
= (addr
& IOMMU_TSB_8K_OFFSET_MASK_512M
) >> 10;
303 offset
= (addr
& IOMMU_TSB_8K_OFFSET_MASK_1G
) >> 10;
308 tte
= address_space_ldq_be(&address_space_memory
, baseaddr
+ offset
,
309 MEMTXATTRS_UNSPECIFIED
, NULL
);
311 if (!(tte
& IOMMU_TTE_DATA_V
)) {
312 /* Invalid mapping */
316 if (tte
& IOMMU_TTE_DATA_W
) {
324 if (tte
& IOMMU_TTE_DATA_SIZE
) {
326 ret
.iova
= addr
& IOMMU_PAGE_MASK_64K
;
327 ret
.translated_addr
= tte
& IOMMU_TTE_PHYS_MASK_64K
;
328 ret
.addr_mask
= (IOMMU_PAGE_SIZE_64K
- 1);
331 ret
.iova
= addr
& IOMMU_PAGE_MASK_8K
;
332 ret
.translated_addr
= tte
& IOMMU_TTE_PHYS_MASK_8K
;
333 ret
.addr_mask
= (IOMMU_PAGE_SIZE_8K
- 1);
339 static void iommu_config_write(void *opaque
, hwaddr addr
,
340 uint64_t val
, unsigned size
)
342 IOMMUState
*is
= opaque
;
344 IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx
" val: %" PRIx64
345 " size: %d\n", addr
, val
, size
);
350 is
->regs
[IOMMU_CTRL
>> 3] &= 0xffffffffULL
;
351 is
->regs
[IOMMU_CTRL
>> 3] |= val
<< 32;
353 is
->regs
[IOMMU_CTRL
>> 3] = val
;
356 case IOMMU_CTRL
+ 0x4:
357 is
->regs
[IOMMU_CTRL
>> 3] &= 0xffffffff00000000ULL
;
358 is
->regs
[IOMMU_CTRL
>> 3] |= val
& 0xffffffffULL
;
362 is
->regs
[IOMMU_BASE
>> 3] &= 0xffffffffULL
;
363 is
->regs
[IOMMU_BASE
>> 3] |= val
<< 32;
365 is
->regs
[IOMMU_BASE
>> 3] = val
;
368 case IOMMU_BASE
+ 0x4:
369 is
->regs
[IOMMU_BASE
>> 3] &= 0xffffffff00000000ULL
;
370 is
->regs
[IOMMU_BASE
>> 3] |= val
& 0xffffffffULL
;
373 case IOMMU_FLUSH
+ 0x4:
376 qemu_log_mask(LOG_UNIMP
,
377 "apb iommu: Unimplemented register write "
378 "reg 0x%" HWADDR_PRIx
" size 0x%x value 0x%" PRIx64
"\n",
384 static uint64_t iommu_config_read(void *opaque
, hwaddr addr
, unsigned size
)
386 IOMMUState
*is
= opaque
;
392 val
= is
->regs
[IOMMU_CTRL
>> 3] >> 32;
394 val
= is
->regs
[IOMMU_CTRL
>> 3];
397 case IOMMU_CTRL
+ 0x4:
398 val
= is
->regs
[IOMMU_CTRL
>> 3] & 0xffffffffULL
;
402 val
= is
->regs
[IOMMU_BASE
>> 3] >> 32;
404 val
= is
->regs
[IOMMU_BASE
>> 3];
407 case IOMMU_BASE
+ 0x4:
408 val
= is
->regs
[IOMMU_BASE
>> 3] & 0xffffffffULL
;
411 case IOMMU_FLUSH
+ 0x4:
415 qemu_log_mask(LOG_UNIMP
,
416 "apb iommu: Unimplemented register read "
417 "reg 0x%" HWADDR_PRIx
" size 0x%x\n",
423 IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx
" val: %" PRIx64
424 " size: %d\n", addr
, val
, size
);
429 static void apb_config_writel (void *opaque
, hwaddr addr
,
430 uint64_t val
, unsigned size
)
432 APBState
*s
= opaque
;
433 IOMMUState
*is
= &s
->iommu
;
435 APB_DPRINTF("%s: addr " TARGET_FMT_plx
" val %" PRIx64
"\n", __func__
, addr
, val
);
437 switch (addr
& 0xffff) {
438 case 0x30 ... 0x4f: /* DMA error registers */
439 /* XXX: not implemented yet */
441 case 0x200 ... 0x217: /* IOMMU */
442 iommu_config_write(is
, (addr
& 0x1f), val
, size
);
444 case 0xc00 ... 0xc3f: /* PCI interrupt control */
446 unsigned int ino
= (addr
& 0x3f) >> 3;
447 s
->pci_irq_map
[ino
] &= PBM_PCI_IMR_MASK
;
448 s
->pci_irq_map
[ino
] |= val
& ~PBM_PCI_IMR_MASK
;
449 if ((s
->irq_request
== ino
) && !(val
& ~PBM_PCI_IMR_MASK
)) {
450 pbm_clear_request(s
, ino
);
455 case 0x1000 ... 0x107f: /* OBIO interrupt control */
457 unsigned int ino
= ((addr
& 0xff) >> 3);
458 s
->obio_irq_map
[ino
] &= PBM_PCI_IMR_MASK
;
459 s
->obio_irq_map
[ino
] |= val
& ~PBM_PCI_IMR_MASK
;
460 if ((s
->irq_request
== (ino
| 0x20))
461 && !(val
& ~PBM_PCI_IMR_MASK
)) {
462 pbm_clear_request(s
, ino
| 0x20);
467 case 0x1400 ... 0x14ff: /* PCI interrupt clear */
469 unsigned int ino
= (addr
& 0xff) >> 5;
470 if ((s
->irq_request
/ 4) == ino
) {
471 pbm_clear_request(s
, s
->irq_request
);
476 case 0x1800 ... 0x1860: /* OBIO interrupt clear */
478 unsigned int ino
= ((addr
& 0xff) >> 3) | 0x20;
479 if (s
->irq_request
== ino
) {
480 pbm_clear_request(s
, ino
);
485 case 0x2000 ... 0x202f: /* PCI control */
486 s
->pci_control
[(addr
& 0x3f) >> 2] = val
;
488 case 0xf020 ... 0xf027: /* Reset control */
491 s
->reset_control
&= ~(val
& RESET_WCMASK
);
492 s
->reset_control
|= val
& RESET_WMASK
;
493 if (val
& SOFT_POR
) {
495 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
496 } else if (val
& SOFT_XIR
) {
497 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
501 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
502 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
503 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
504 case 0xf000 ... 0xf01f: /* FFB config, memory control */
511 static uint64_t apb_config_readl (void *opaque
,
512 hwaddr addr
, unsigned size
)
514 APBState
*s
= opaque
;
515 IOMMUState
*is
= &s
->iommu
;
518 switch (addr
& 0xffff) {
519 case 0x30 ... 0x4f: /* DMA error registers */
521 /* XXX: not implemented yet */
523 case 0x200 ... 0x217: /* IOMMU */
524 val
= iommu_config_read(is
, (addr
& 0x1f), size
);
526 case 0xc00 ... 0xc3f: /* PCI interrupt control */
528 val
= s
->pci_irq_map
[(addr
& 0x3f) >> 3];
533 case 0x1000 ... 0x107f: /* OBIO interrupt control */
535 val
= s
->obio_irq_map
[(addr
& 0xff) >> 3];
540 case 0x1080 ... 0x108f: /* PCI bus error */
542 val
= s
->pci_err_irq_map
[(addr
& 0xf) >> 3];
547 case 0x2000 ... 0x202f: /* PCI control */
548 val
= s
->pci_control
[(addr
& 0x3f) >> 2];
550 case 0xf020 ... 0xf027: /* Reset control */
552 val
= s
->reset_control
;
557 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
558 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
559 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
560 case 0xf000 ... 0xf01f: /* FFB config, memory control */
566 APB_DPRINTF("%s: addr " TARGET_FMT_plx
" -> %x\n", __func__
, addr
, val
);
571 static const MemoryRegionOps apb_config_ops
= {
572 .read
= apb_config_readl
,
573 .write
= apb_config_writel
,
574 .endianness
= DEVICE_BIG_ENDIAN
,
577 static void apb_pci_config_write(void *opaque
, hwaddr addr
,
578 uint64_t val
, unsigned size
)
580 APBState
*s
= opaque
;
581 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
583 APB_DPRINTF("%s: addr " TARGET_FMT_plx
" val %" PRIx64
"\n", __func__
, addr
, val
);
584 pci_data_write(phb
->bus
, addr
, val
, size
);
587 static uint64_t apb_pci_config_read(void *opaque
, hwaddr addr
,
591 APBState
*s
= opaque
;
592 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
594 ret
= pci_data_read(phb
->bus
, addr
, size
);
595 APB_DPRINTF("%s: addr " TARGET_FMT_plx
" -> %x\n", __func__
, addr
, ret
);
599 /* The APB host has an IRQ line for each IRQ line of each slot. */
600 static int pci_apb_map_irq(PCIDevice
*pci_dev
, int irq_num
)
602 return ((pci_dev
->devfn
& 0x18) >> 1) + irq_num
;
605 static int pci_pbm_map_irq(PCIDevice
*pci_dev
, int irq_num
)
608 if (pci_dev
->devfn
& 1)
612 return (bus_offset
+ (PCI_SLOT(pci_dev
->devfn
) << 2) + irq_num
) & 0x1f;
615 static void pci_apb_set_irq(void *opaque
, int irq_num
, int level
)
617 APBState
*s
= opaque
;
619 APB_DPRINTF("%s: set irq_in %d level %d\n", __func__
, irq_num
, level
);
620 /* PCI IRQ map onto the first 32 INO. */
623 s
->pci_irq_in
|= 1ULL << irq_num
;
624 if (s
->pci_irq_map
[irq_num
>> 2] & PBM_PCI_IMR_ENABLED
) {
625 pbm_set_request(s
, irq_num
);
628 s
->pci_irq_in
&= ~(1ULL << irq_num
);
631 /* OBIO IRQ map onto the next 32 INO. */
633 APB_DPRINTF("%s: set irq %d level %d\n", __func__
, irq_num
, level
);
634 s
->pci_irq_in
|= 1ULL << irq_num
;
635 if ((s
->irq_request
== NO_IRQ_REQUEST
)
636 && (s
->obio_irq_map
[irq_num
- 32] & PBM_PCI_IMR_ENABLED
)) {
637 pbm_set_request(s
, irq_num
);
640 s
->pci_irq_in
&= ~(1ULL << irq_num
);
645 static void apb_pci_bridge_realize(PCIDevice
*dev
, Error
**errp
)
649 * According to PCI bridge spec, after reset
650 * bus master bit is off
651 * memory space enable bit is off
652 * According to manual (805-1251.pdf).
653 * the reset value should be zero unless the boot pin is tied high
654 * (which is true) and thus it should be PCI_COMMAND_MEMORY.
656 uint16_t cmd
= PCI_COMMAND_MEMORY
;
657 PBMPCIBridge
*br
= PBM_PCI_BRIDGE(dev
);
659 pci_bridge_initfn(dev
, TYPE_PCI_BUS
);
661 /* If initialising busA, ensure that we allow IO transactions so that
662 we get the early serial console until OpenBIOS configures the bridge */
664 cmd
|= PCI_COMMAND_IO
;
667 pci_set_word(dev
->config
+ PCI_COMMAND
, cmd
);
668 pci_set_word(dev
->config
+ PCI_STATUS
,
669 PCI_STATUS_FAST_BACK
| PCI_STATUS_66MHZ
|
670 PCI_STATUS_DEVSEL_MEDIUM
);
672 pci_bridge_update_mappings(PCI_BRIDGE(br
));
675 PCIBus
*pci_apb_init(hwaddr special_base
,
677 qemu_irq
*ivec_irqs
, PCIBus
**busA
, PCIBus
**busB
,
688 /* Ultrasparc PBM main bus */
689 dev
= qdev_create(NULL
, TYPE_APB
);
691 phb
= PCI_HOST_BRIDGE(dev
);
692 phb
->bus
= pci_register_bus(DEVICE(phb
), "pci",
693 pci_apb_set_irq
, pci_pbm_map_irq
, d
,
696 0, 32, TYPE_PCI_BUS
);
697 qdev_init_nofail(dev
);
698 s
= SYS_BUS_DEVICE(dev
);
700 sysbus_mmio_map(s
, 0, special_base
);
701 /* PCI configuration space */
702 sysbus_mmio_map(s
, 1, special_base
+ 0x1000000ULL
);
704 sysbus_mmio_map(s
, 2, special_base
+ 0x2000000ULL
);
706 memory_region_init(&d
->pci_mmio
, OBJECT(s
), "pci-mmio", 0x100000000ULL
);
707 memory_region_add_subregion(get_system_memory(), mem_base
, &d
->pci_mmio
);
709 *pbm_irqs
= d
->pbm_irqs
;
710 d
->ivec_irqs
= ivec_irqs
;
712 pci_create_simple(phb
->bus
, 0, "pbm-pci");
716 memset(is
, 0, sizeof(IOMMUState
));
718 memory_region_init_iommu(&is
->iommu
, sizeof(is
->iommu
),
719 TYPE_APB_IOMMU_MEMORY_REGION
, OBJECT(dev
),
720 "iommu-apb", UINT64_MAX
);
721 address_space_init(&is
->iommu_as
, MEMORY_REGION(&is
->iommu
), "pbm-as");
722 pci_setup_iommu(phb
->bus
, pbm_pci_dma_iommu
, is
);
724 /* APB secondary busses */
725 pci_dev
= pci_create_multifunction(phb
->bus
, PCI_DEVFN(1, 0), true,
726 TYPE_PBM_PCI_BRIDGE
);
727 br
= PCI_BRIDGE(pci_dev
);
728 pci_bridge_map_irq(br
, "pciB", pci_apb_map_irq
);
729 qdev_init_nofail(&pci_dev
->qdev
);
730 *busB
= pci_bridge_get_sec_bus(br
);
732 pci_dev
= pci_create_multifunction(phb
->bus
, PCI_DEVFN(1, 1), true,
733 TYPE_PBM_PCI_BRIDGE
);
734 br
= PCI_BRIDGE(pci_dev
);
735 pci_bridge_map_irq(br
, "pciA", pci_apb_map_irq
);
736 qdev_prop_set_bit(DEVICE(pci_dev
), "busA", true);
737 qdev_init_nofail(&pci_dev
->qdev
);
738 *busA
= pci_bridge_get_sec_bus(br
);
743 static void pci_pbm_reset(DeviceState
*d
)
746 APBState
*s
= APB_DEVICE(d
);
748 for (i
= 0; i
< 8; i
++) {
749 s
->pci_irq_map
[i
] &= PBM_PCI_IMR_MASK
;
751 for (i
= 0; i
< 32; i
++) {
752 s
->obio_irq_map
[i
] &= PBM_PCI_IMR_MASK
;
755 s
->irq_request
= NO_IRQ_REQUEST
;
756 s
->pci_irq_in
= 0ULL;
758 if (s
->nr_resets
++ == 0) {
760 s
->reset_control
= POR
;
764 static const MemoryRegionOps pci_config_ops
= {
765 .read
= apb_pci_config_read
,
766 .write
= apb_pci_config_write
,
767 .endianness
= DEVICE_LITTLE_ENDIAN
,
770 static int pci_pbm_init_device(SysBusDevice
*dev
)
776 for (i
= 0; i
< 8; i
++) {
777 s
->pci_irq_map
[i
] = (0x1f << 6) | (i
<< 2);
779 for (i
= 0; i
< 2; i
++) {
780 s
->pci_err_irq_map
[i
] = (0x1f << 6) | 0x30;
782 for (i
= 0; i
< 32; i
++) {
783 s
->obio_irq_map
[i
] = ((0x1f << 6) | 0x20) + i
;
785 s
->pbm_irqs
= qemu_allocate_irqs(pci_apb_set_irq
, s
, MAX_IVEC
);
786 s
->irq_request
= NO_IRQ_REQUEST
;
787 s
->pci_irq_in
= 0ULL;
790 memory_region_init_io(&s
->apb_config
, OBJECT(s
), &apb_config_ops
, s
,
791 "apb-config", 0x10000);
793 sysbus_init_mmio(dev
, &s
->apb_config
);
795 memory_region_init_io(&s
->pci_config
, OBJECT(s
), &pci_config_ops
, s
,
796 "apb-pci-config", 0x1000000);
798 sysbus_init_mmio(dev
, &s
->pci_config
);
801 memory_region_init_alias(&s
->pci_ioport
, OBJECT(s
), "apb-pci-ioport",
802 get_system_io(), 0, 0x10000);
804 sysbus_init_mmio(dev
, &s
->pci_ioport
);
809 static void pbm_pci_host_realize(PCIDevice
*d
, Error
**errp
)
811 pci_set_word(d
->config
+ PCI_COMMAND
,
812 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
813 pci_set_word(d
->config
+ PCI_STATUS
,
814 PCI_STATUS_FAST_BACK
| PCI_STATUS_66MHZ
|
815 PCI_STATUS_DEVSEL_MEDIUM
);
818 static void pbm_pci_host_class_init(ObjectClass
*klass
, void *data
)
820 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
821 DeviceClass
*dc
= DEVICE_CLASS(klass
);
823 k
->realize
= pbm_pci_host_realize
;
824 k
->vendor_id
= PCI_VENDOR_ID_SUN
;
825 k
->device_id
= PCI_DEVICE_ID_SUN_SABRE
;
826 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
828 * PCI-facing part of the host bridge, not usable without the
829 * host-facing part, which can't be device_add'ed, yet.
831 dc
->user_creatable
= false;
834 static const TypeInfo pbm_pci_host_info
= {
836 .parent
= TYPE_PCI_DEVICE
,
837 .instance_size
= sizeof(PCIDevice
),
838 .class_init
= pbm_pci_host_class_init
,
839 .interfaces
= (InterfaceInfo
[]) {
840 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
845 static void pbm_host_class_init(ObjectClass
*klass
, void *data
)
847 DeviceClass
*dc
= DEVICE_CLASS(klass
);
848 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
850 k
->init
= pci_pbm_init_device
;
851 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
852 dc
->reset
= pci_pbm_reset
;
855 static const TypeInfo pbm_host_info
= {
857 .parent
= TYPE_PCI_HOST_BRIDGE
,
858 .instance_size
= sizeof(APBState
),
859 .class_init
= pbm_host_class_init
,
862 static Property pbm_pci_properties
[] = {
863 DEFINE_PROP_BOOL("busA", PBMPCIBridge
, busA
, false),
864 DEFINE_PROP_END_OF_LIST(),
867 static void pbm_pci_bridge_class_init(ObjectClass
*klass
, void *data
)
869 DeviceClass
*dc
= DEVICE_CLASS(klass
);
870 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
872 k
->realize
= apb_pci_bridge_realize
;
873 k
->exit
= pci_bridge_exitfn
;
874 k
->vendor_id
= PCI_VENDOR_ID_SUN
;
875 k
->device_id
= PCI_DEVICE_ID_SUN_SIMBA
;
877 k
->config_write
= pci_bridge_write_config
;
879 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
880 dc
->reset
= pci_bridge_reset
;
881 dc
->vmsd
= &vmstate_pci_device
;
882 dc
->props
= pbm_pci_properties
;
885 static const TypeInfo pbm_pci_bridge_info
= {
886 .name
= TYPE_PBM_PCI_BRIDGE
,
887 .parent
= TYPE_PCI_BRIDGE
,
888 .class_init
= pbm_pci_bridge_class_init
,
889 .instance_size
= sizeof(PBMPCIBridge
),
890 .interfaces
= (InterfaceInfo
[]) {
891 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
896 static void pbm_iommu_memory_region_class_init(ObjectClass
*klass
, void *data
)
898 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
900 imrc
->translate
= pbm_translate_iommu
;
903 static const TypeInfo pbm_iommu_memory_region_info
= {
904 .parent
= TYPE_IOMMU_MEMORY_REGION
,
905 .name
= TYPE_APB_IOMMU_MEMORY_REGION
,
906 .class_init
= pbm_iommu_memory_region_class_init
,
909 static void pbm_register_types(void)
911 type_register_static(&pbm_host_info
);
912 type_register_static(&pbm_pci_host_info
);
913 type_register_static(&pbm_pci_bridge_info
);
914 type_register_static(&pbm_iommu_memory_region_info
);
917 type_init(pbm_register_types
)