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target-xtensa: implement ATOMCTL SR
[qemu.git] / target-xtensa / translate.c
blobdc08de51ba56ff04186e4dab9efafd77f1a87a1e
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <stdio.h>
32
33 #include "cpu.h"
34 #include "exec-all.h"
35 #include "disas.h"
36 #include "tcg-op.h"
37 #include "qemu-log.h"
38 #include "sysemu.h"
39
40 #include "helper.h"
41 #define GEN_HELPER 1
42 #include "helper.h"
43
44 typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
49 int cring;
50 int ring;
51 uint32_t lbeg;
52 uint32_t lend;
53 TCGv_i32 litbase;
54 int is_jmp;
55 int singlestep_enabled;
56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
61
62 uint32_t ccount_delta;
63 unsigned used_window;
64
65 bool debug;
66 bool icount;
67 TCGv_i32 next_icount;
68
69 unsigned cpenable;
70 } DisasContext;
71
72 static TCGv_ptr cpu_env;
73 static TCGv_i32 cpu_pc;
74 static TCGv_i32 cpu_R[16];
75 static TCGv_i32 cpu_FR[16];
76 static TCGv_i32 cpu_SR[256];
77 static TCGv_i32 cpu_UR[256];
78
79 #include "gen-icount.h"
80
81 static const char * const sregnames[256] = {
82 [LBEG] = "LBEG",
83 [LEND] = "LEND",
84 [LCOUNT] = "LCOUNT",
85 [SAR] = "SAR",
86 [BR] = "BR",
87 [LITBASE] = "LITBASE",
88 [SCOMPARE1] = "SCOMPARE1",
89 [ACCLO] = "ACCLO",
90 [ACCHI] = "ACCHI",
91 [MR] = "MR0",
92 [MR + 1] = "MR1",
93 [MR + 2] = "MR2",
94 [MR + 3] = "MR3",
95 [WINDOW_BASE] = "WINDOW_BASE",
96 [WINDOW_START] = "WINDOW_START",
97 [PTEVADDR] = "PTEVADDR",
98 [RASID] = "RASID",
99 [ITLBCFG] = "ITLBCFG",
100 [DTLBCFG] = "DTLBCFG",
101 [IBREAKENABLE] = "IBREAKENABLE",
102 [ATOMCTL] = "ATOMCTL",
103 [IBREAKA] = "IBREAKA0",
104 [IBREAKA + 1] = "IBREAKA1",
105 [DBREAKA] = "DBREAKA0",
106 [DBREAKA + 1] = "DBREAKA1",
107 [DBREAKC] = "DBREAKC0",
108 [DBREAKC + 1] = "DBREAKC1",
109 [EPC1] = "EPC1",
110 [EPC1 + 1] = "EPC2",
111 [EPC1 + 2] = "EPC3",
112 [EPC1 + 3] = "EPC4",
113 [EPC1 + 4] = "EPC5",
114 [EPC1 + 5] = "EPC6",
115 [EPC1 + 6] = "EPC7",
116 [DEPC] = "DEPC",
117 [EPS2] = "EPS2",
118 [EPS2 + 1] = "EPS3",
119 [EPS2 + 2] = "EPS4",
120 [EPS2 + 3] = "EPS5",
121 [EPS2 + 4] = "EPS6",
122 [EPS2 + 5] = "EPS7",
123 [EXCSAVE1] = "EXCSAVE1",
124 [EXCSAVE1 + 1] = "EXCSAVE2",
125 [EXCSAVE1 + 2] = "EXCSAVE3",
126 [EXCSAVE1 + 3] = "EXCSAVE4",
127 [EXCSAVE1 + 4] = "EXCSAVE5",
128 [EXCSAVE1 + 5] = "EXCSAVE6",
129 [EXCSAVE1 + 6] = "EXCSAVE7",
130 [CPENABLE] = "CPENABLE",
131 [INTSET] = "INTSET",
132 [INTCLEAR] = "INTCLEAR",
133 [INTENABLE] = "INTENABLE",
134 [PS] = "PS",
135 [VECBASE] = "VECBASE",
136 [EXCCAUSE] = "EXCCAUSE",
137 [DEBUGCAUSE] = "DEBUGCAUSE",
138 [CCOUNT] = "CCOUNT",
139 [PRID] = "PRID",
140 [ICOUNT] = "ICOUNT",
141 [ICOUNTLEVEL] = "ICOUNTLEVEL",
142 [EXCVADDR] = "EXCVADDR",
143 [CCOMPARE] = "CCOMPARE0",
144 [CCOMPARE + 1] = "CCOMPARE1",
145 [CCOMPARE + 2] = "CCOMPARE2",
146 };
147
148 static const char * const uregnames[256] = {
149 [THREADPTR] = "THREADPTR",
150 [FCR] = "FCR",
151 [FSR] = "FSR",
152 };
153
154 void xtensa_translate_init(void)
155 {
156 static const char * const regnames[] = {
157 "ar0", "ar1", "ar2", "ar3",
158 "ar4", "ar5", "ar6", "ar7",
159 "ar8", "ar9", "ar10", "ar11",
160 "ar12", "ar13", "ar14", "ar15",
161 };
162 static const char * const fregnames[] = {
163 "f0", "f1", "f2", "f3",
164 "f4", "f5", "f6", "f7",
165 "f8", "f9", "f10", "f11",
166 "f12", "f13", "f14", "f15",
167 };
168 int i;
169
170 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
171 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
172 offsetof(CPUXtensaState, pc), "pc");
173
174 for (i = 0; i < 16; i++) {
175 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUXtensaState, regs[i]),
177 regnames[i]);
178 }
179
180 for (i = 0; i < 16; i++) {
181 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
182 offsetof(CPUXtensaState, fregs[i]),
183 fregnames[i]);
184 }
185
186 for (i = 0; i < 256; ++i) {
187 if (sregnames[i]) {
188 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
189 offsetof(CPUXtensaState, sregs[i]),
190 sregnames[i]);
191 }
192 }
193
194 for (i = 0; i < 256; ++i) {
195 if (uregnames[i]) {
196 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
197 offsetof(CPUXtensaState, uregs[i]),
198 uregnames[i]);
199 }
200 }
201 #define GEN_HELPER 2
202 #include "helper.h"
203 }
204
205 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
206 {
207 return xtensa_option_bits_enabled(dc->config, opt);
208 }
209
210 static inline bool option_enabled(DisasContext *dc, int opt)
211 {
212 return xtensa_option_enabled(dc->config, opt);
213 }
214
215 static void init_litbase(DisasContext *dc)
216 {
217 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
218 dc->litbase = tcg_temp_local_new_i32();
219 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
220 }
221 }
222
223 static void reset_litbase(DisasContext *dc)
224 {
225 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
226 tcg_temp_free(dc->litbase);
227 }
228 }
229
230 static void init_sar_tracker(DisasContext *dc)
231 {
232 dc->sar_5bit = false;
233 dc->sar_m32_5bit = false;
234 dc->sar_m32_allocated = false;
235 }
236
237 static void reset_sar_tracker(DisasContext *dc)
238 {
239 if (dc->sar_m32_allocated) {
240 tcg_temp_free(dc->sar_m32);
241 }
242 }
243
244 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
245 {
246 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
247 if (dc->sar_m32_5bit) {
248 tcg_gen_discard_i32(dc->sar_m32);
249 }
250 dc->sar_5bit = true;
251 dc->sar_m32_5bit = false;
252 }
253
254 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
255 {
256 TCGv_i32 tmp = tcg_const_i32(32);
257 if (!dc->sar_m32_allocated) {
258 dc->sar_m32 = tcg_temp_local_new_i32();
259 dc->sar_m32_allocated = true;
260 }
261 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
262 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
263 dc->sar_5bit = false;
264 dc->sar_m32_5bit = true;
265 tcg_temp_free(tmp);
266 }
267
268 static void gen_advance_ccount(DisasContext *dc)
269 {
270 if (dc->ccount_delta > 0) {
271 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
272 dc->ccount_delta = 0;
273 gen_helper_advance_ccount(cpu_env, tmp);
274 tcg_temp_free(tmp);
275 }
276 }
277
278 static void reset_used_window(DisasContext *dc)
279 {
280 dc->used_window = 0;
281 }
282
283 static void gen_exception(DisasContext *dc, int excp)
284 {
285 TCGv_i32 tmp = tcg_const_i32(excp);
286 gen_advance_ccount(dc);
287 gen_helper_exception(cpu_env, tmp);
288 tcg_temp_free(tmp);
289 }
290
291 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
292 {
293 TCGv_i32 tpc = tcg_const_i32(dc->pc);
294 TCGv_i32 tcause = tcg_const_i32(cause);
295 gen_advance_ccount(dc);
296 gen_helper_exception_cause(cpu_env, tpc, tcause);
297 tcg_temp_free(tpc);
298 tcg_temp_free(tcause);
299 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
300 cause == SYSCALL_CAUSE) {
301 dc->is_jmp = DISAS_UPDATE;
302 }
303 }
304
305 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
306 TCGv_i32 vaddr)
307 {
308 TCGv_i32 tpc = tcg_const_i32(dc->pc);
309 TCGv_i32 tcause = tcg_const_i32(cause);
310 gen_advance_ccount(dc);
311 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
312 tcg_temp_free(tpc);
313 tcg_temp_free(tcause);
314 }
315
316 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
317 {
318 TCGv_i32 tpc = tcg_const_i32(dc->pc);
319 TCGv_i32 tcause = tcg_const_i32(cause);
320 gen_advance_ccount(dc);
321 gen_helper_debug_exception(cpu_env, tpc, tcause);
322 tcg_temp_free(tpc);
323 tcg_temp_free(tcause);
324 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
325 dc->is_jmp = DISAS_UPDATE;
326 }
327 }
328
329 static void gen_check_privilege(DisasContext *dc)
330 {
331 if (dc->cring) {
332 gen_exception_cause(dc, PRIVILEGED_CAUSE);
333 dc->is_jmp = DISAS_UPDATE;
334 }
335 }
336
337 static void gen_check_cpenable(DisasContext *dc, unsigned cp)
338 {
339 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
340 !(dc->cpenable & (1 << cp))) {
341 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
342 dc->is_jmp = DISAS_UPDATE;
343 }
344 }
345
346 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
347 {
348 tcg_gen_mov_i32(cpu_pc, dest);
349 gen_advance_ccount(dc);
350 if (dc->icount) {
351 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
352 }
353 if (dc->singlestep_enabled) {
354 gen_exception(dc, EXCP_DEBUG);
355 } else {
356 if (slot >= 0) {
357 tcg_gen_goto_tb(slot);
358 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
359 } else {
360 tcg_gen_exit_tb(0);
361 }
362 }
363 dc->is_jmp = DISAS_UPDATE;
364 }
365
366 static void gen_jump(DisasContext *dc, TCGv dest)
367 {
368 gen_jump_slot(dc, dest, -1);
369 }
370
371 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
372 {
373 TCGv_i32 tmp = tcg_const_i32(dest);
374 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
375 slot = -1;
376 }
377 gen_jump_slot(dc, tmp, slot);
378 tcg_temp_free(tmp);
379 }
380
381 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
382 int slot)
383 {
384 TCGv_i32 tcallinc = tcg_const_i32(callinc);
385
386 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
387 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
388 tcg_temp_free(tcallinc);
389 tcg_gen_movi_i32(cpu_R[callinc << 2],
390 (callinc << 30) | (dc->next_pc & 0x3fffffff));
391 gen_jump_slot(dc, dest, slot);
392 }
393
394 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
395 {
396 gen_callw_slot(dc, callinc, dest, -1);
397 }
398
399 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
400 {
401 TCGv_i32 tmp = tcg_const_i32(dest);
402 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
403 slot = -1;
404 }
405 gen_callw_slot(dc, callinc, tmp, slot);
406 tcg_temp_free(tmp);
407 }
408
409 static bool gen_check_loop_end(DisasContext *dc, int slot)
410 {
411 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
412 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
413 dc->next_pc == dc->lend) {
414 int label = gen_new_label();
415
416 gen_advance_ccount(dc);
417 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
418 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
419 gen_jumpi(dc, dc->lbeg, slot);
420 gen_set_label(label);
421 gen_jumpi(dc, dc->next_pc, -1);
422 return true;
423 }
424 return false;
425 }
426
427 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
428 {
429 if (!gen_check_loop_end(dc, slot)) {
430 gen_jumpi(dc, dc->next_pc, slot);
431 }
432 }
433
434 static void gen_brcond(DisasContext *dc, TCGCond cond,
435 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
436 {
437 int label = gen_new_label();
438
439 gen_advance_ccount(dc);
440 tcg_gen_brcond_i32(cond, t0, t1, label);
441 gen_jumpi_check_loop_end(dc, 0);
442 gen_set_label(label);
443 gen_jumpi(dc, dc->pc + offset, 1);
444 }
445
446 static void gen_brcondi(DisasContext *dc, TCGCond cond,
447 TCGv_i32 t0, uint32_t t1, uint32_t offset)
448 {
449 TCGv_i32 tmp = tcg_const_i32(t1);
450 gen_brcond(dc, cond, t0, tmp, offset);
451 tcg_temp_free(tmp);
452 }
453
454 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
455 {
456 gen_advance_ccount(dc);
457 tcg_gen_mov_i32(d, cpu_SR[sr]);
458 }
459
460 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
461 {
462 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
463 tcg_gen_or_i32(d, d, cpu_SR[sr]);
464 tcg_gen_andi_i32(d, d, 0xfffffffc);
465 }
466
467 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
468 {
469 static void (* const rsr_handler[256])(DisasContext *dc,
470 TCGv_i32 d, uint32_t sr) = {
471 [CCOUNT] = gen_rsr_ccount,
472 [PTEVADDR] = gen_rsr_ptevaddr,
473 };
474
475 if (sregnames[sr]) {
476 if (rsr_handler[sr]) {
477 rsr_handler[sr](dc, d, sr);
478 } else {
479 tcg_gen_mov_i32(d, cpu_SR[sr]);
480 }
481 } else {
482 qemu_log("RSR %d not implemented, ", sr);
483 }
484 }
485
486 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
487 {
488 gen_helper_wsr_lbeg(cpu_env, s);
489 gen_jumpi_check_loop_end(dc, 0);
490 }
491
492 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
493 {
494 gen_helper_wsr_lend(cpu_env, s);
495 gen_jumpi_check_loop_end(dc, 0);
496 }
497
498 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
499 {
500 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
501 if (dc->sar_m32_5bit) {
502 tcg_gen_discard_i32(dc->sar_m32);
503 }
504 dc->sar_5bit = false;
505 dc->sar_m32_5bit = false;
506 }
507
508 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
509 {
510 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
511 }
512
513 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
514 {
515 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
516 /* This can change tb->flags, so exit tb */
517 gen_jumpi_check_loop_end(dc, -1);
518 }
519
520 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
521 {
522 tcg_gen_ext8s_i32(cpu_SR[sr], s);
523 }
524
525 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
526 {
527 gen_helper_wsr_windowbase(cpu_env, v);
528 reset_used_window(dc);
529 }
530
531 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
532 {
533 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
534 reset_used_window(dc);
535 }
536
537 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
538 {
539 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
540 }
541
542 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
543 {
544 gen_helper_wsr_rasid(cpu_env, v);
545 /* This can change tb->flags, so exit tb */
546 gen_jumpi_check_loop_end(dc, -1);
547 }
548
549 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
550 {
551 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
552 }
553
554 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
555 {
556 gen_helper_wsr_ibreakenable(cpu_env, v);
557 gen_jumpi_check_loop_end(dc, 0);
558 }
559
560 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
561 {
562 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
563 }
564
565 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
566 {
567 unsigned id = sr - IBREAKA;
568
569 if (id < dc->config->nibreak) {
570 TCGv_i32 tmp = tcg_const_i32(id);
571 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
572 tcg_temp_free(tmp);
573 gen_jumpi_check_loop_end(dc, 0);
574 }
575 }
576
577 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
578 {
579 unsigned id = sr - DBREAKA;
580
581 if (id < dc->config->ndbreak) {
582 TCGv_i32 tmp = tcg_const_i32(id);
583 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
584 tcg_temp_free(tmp);
585 }
586 }
587
588 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
589 {
590 unsigned id = sr - DBREAKC;
591
592 if (id < dc->config->ndbreak) {
593 TCGv_i32 tmp = tcg_const_i32(id);
594 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
595 tcg_temp_free(tmp);
596 }
597 }
598
599 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
600 {
601 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
602 /* This can change tb->flags, so exit tb */
603 gen_jumpi_check_loop_end(dc, -1);
604 }
605
606 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
607 {
608 tcg_gen_andi_i32(cpu_SR[sr], v,
609 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
610 gen_helper_check_interrupts(cpu_env);
611 gen_jumpi_check_loop_end(dc, 0);
612 }
613
614 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
615 {
616 TCGv_i32 tmp = tcg_temp_new_i32();
617
618 tcg_gen_andi_i32(tmp, v,
619 dc->config->inttype_mask[INTTYPE_EDGE] |
620 dc->config->inttype_mask[INTTYPE_NMI] |
621 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
622 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
623 tcg_temp_free(tmp);
624 gen_helper_check_interrupts(cpu_env);
625 }
626
627 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
628 {
629 tcg_gen_mov_i32(cpu_SR[sr], v);
630 gen_helper_check_interrupts(cpu_env);
631 gen_jumpi_check_loop_end(dc, 0);
632 }
633
634 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
635 {
636 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
637 PS_UM | PS_EXCM | PS_INTLEVEL;
638
639 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
640 mask |= PS_RING;
641 }
642 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
643 reset_used_window(dc);
644 gen_helper_check_interrupts(cpu_env);
645 /* This can change mmu index and tb->flags, so exit tb */
646 gen_jumpi_check_loop_end(dc, -1);
647 }
648
649 static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v)
650 {
651 }
652
653 static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
654 {
655 }
656
657 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
658 {
659 if (dc->icount) {
660 tcg_gen_mov_i32(dc->next_icount, v);
661 } else {
662 tcg_gen_mov_i32(cpu_SR[sr], v);
663 }
664 }
665
666 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
667 {
668 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
669 /* This can change tb->flags, so exit tb */
670 gen_jumpi_check_loop_end(dc, -1);
671 }
672
673 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
674 {
675 uint32_t id = sr - CCOMPARE;
676 if (id < dc->config->nccompare) {
677 uint32_t int_bit = 1 << dc->config->timerint[id];
678 gen_advance_ccount(dc);
679 tcg_gen_mov_i32(cpu_SR[sr], v);
680 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
681 gen_helper_check_interrupts(cpu_env);
682 }
683 }
684
685 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
686 {
687 static void (* const wsr_handler[256])(DisasContext *dc,
688 uint32_t sr, TCGv_i32 v) = {
689 [LBEG] = gen_wsr_lbeg,
690 [LEND] = gen_wsr_lend,
691 [SAR] = gen_wsr_sar,
692 [BR] = gen_wsr_br,
693 [LITBASE] = gen_wsr_litbase,
694 [ACCHI] = gen_wsr_acchi,
695 [WINDOW_BASE] = gen_wsr_windowbase,
696 [WINDOW_START] = gen_wsr_windowstart,
697 [PTEVADDR] = gen_wsr_ptevaddr,
698 [RASID] = gen_wsr_rasid,
699 [ITLBCFG] = gen_wsr_tlbcfg,
700 [DTLBCFG] = gen_wsr_tlbcfg,
701 [IBREAKENABLE] = gen_wsr_ibreakenable,
702 [ATOMCTL] = gen_wsr_atomctl,
703 [IBREAKA] = gen_wsr_ibreaka,
704 [IBREAKA + 1] = gen_wsr_ibreaka,
705 [DBREAKA] = gen_wsr_dbreaka,
706 [DBREAKA + 1] = gen_wsr_dbreaka,
707 [DBREAKC] = gen_wsr_dbreakc,
708 [DBREAKC + 1] = gen_wsr_dbreakc,
709 [CPENABLE] = gen_wsr_cpenable,
710 [INTSET] = gen_wsr_intset,
711 [INTCLEAR] = gen_wsr_intclear,
712 [INTENABLE] = gen_wsr_intenable,
713 [PS] = gen_wsr_ps,
714 [DEBUGCAUSE] = gen_wsr_debugcause,
715 [PRID] = gen_wsr_prid,
716 [ICOUNT] = gen_wsr_icount,
717 [ICOUNTLEVEL] = gen_wsr_icountlevel,
718 [CCOMPARE] = gen_wsr_ccompare,
719 [CCOMPARE + 1] = gen_wsr_ccompare,
720 [CCOMPARE + 2] = gen_wsr_ccompare,
721 };
722
723 if (sregnames[sr]) {
724 if (wsr_handler[sr]) {
725 wsr_handler[sr](dc, sr, s);
726 } else {
727 tcg_gen_mov_i32(cpu_SR[sr], s);
728 }
729 } else {
730 qemu_log("WSR %d not implemented, ", sr);
731 }
732 }
733
734 static void gen_wur(uint32_t ur, TCGv_i32 s)
735 {
736 switch (ur) {
737 case FCR:
738 gen_helper_wur_fcr(cpu_env, s);
739 break;
740
741 case FSR:
742 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
743 break;
744
745 default:
746 tcg_gen_mov_i32(cpu_UR[ur], s);
747 break;
748 }
749 }
750
751 static void gen_load_store_alignment(DisasContext *dc, int shift,
752 TCGv_i32 addr, bool no_hw_alignment)
753 {
754 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
755 tcg_gen_andi_i32(addr, addr, ~0 << shift);
756 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
757 no_hw_alignment) {
758 int label = gen_new_label();
759 TCGv_i32 tmp = tcg_temp_new_i32();
760 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
761 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
762 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
763 gen_set_label(label);
764 tcg_temp_free(tmp);
765 }
766 }
767
768 static void gen_waiti(DisasContext *dc, uint32_t imm4)
769 {
770 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
771 TCGv_i32 intlevel = tcg_const_i32(imm4);
772 gen_advance_ccount(dc);
773 gen_helper_waiti(cpu_env, pc, intlevel);
774 tcg_temp_free(pc);
775 tcg_temp_free(intlevel);
776 }
777
778 static void gen_window_check1(DisasContext *dc, unsigned r1)
779 {
780 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
781 return;
782 }
783 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
784 r1 / 4 > dc->used_window) {
785 TCGv_i32 pc = tcg_const_i32(dc->pc);
786 TCGv_i32 w = tcg_const_i32(r1 / 4);
787
788 dc->used_window = r1 / 4;
789 gen_advance_ccount(dc);
790 gen_helper_window_check(cpu_env, pc, w);
791
792 tcg_temp_free(w);
793 tcg_temp_free(pc);
794 }
795 }
796
797 static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
798 {
799 gen_window_check1(dc, r1 > r2 ? r1 : r2);
800 }
801
802 static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
803 unsigned r3)
804 {
805 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
806 }
807
808 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
809 {
810 TCGv_i32 m = tcg_temp_new_i32();
811
812 if (hi) {
813 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
814 } else {
815 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
816 }
817 return m;
818 }
819
820 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
821 {
822 #define HAS_OPTION_BITS(opt) do { \
823 if (!option_bits_enabled(dc, opt)) { \
824 qemu_log("Option is not enabled %s:%d\n", \
825 __FILE__, __LINE__); \
826 goto invalid_opcode; \
827 } \
828 } while (0)
829
830 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
831
832 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
833 #define RESERVED() do { \
834 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
835 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
836 goto invalid_opcode; \
837 } while (0)
838
839
840 #ifdef TARGET_WORDS_BIGENDIAN
841 #define OP0 (((b0) & 0xf0) >> 4)
842 #define OP1 (((b2) & 0xf0) >> 4)
843 #define OP2 ((b2) & 0xf)
844 #define RRR_R ((b1) & 0xf)
845 #define RRR_S (((b1) & 0xf0) >> 4)
846 #define RRR_T ((b0) & 0xf)
847 #else
848 #define OP0 (((b0) & 0xf))
849 #define OP1 (((b2) & 0xf))
850 #define OP2 (((b2) & 0xf0) >> 4)
851 #define RRR_R (((b1) & 0xf0) >> 4)
852 #define RRR_S (((b1) & 0xf))
853 #define RRR_T (((b0) & 0xf0) >> 4)
854 #endif
855 #define RRR_X ((RRR_R & 0x4) >> 2)
856 #define RRR_Y ((RRR_T & 0x4) >> 2)
857 #define RRR_W (RRR_R & 0x3)
858
859 #define RRRN_R RRR_R
860 #define RRRN_S RRR_S
861 #define RRRN_T RRR_T
862
863 #define RRI8_R RRR_R
864 #define RRI8_S RRR_S
865 #define RRI8_T RRR_T
866 #define RRI8_IMM8 (b2)
867 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
868
869 #ifdef TARGET_WORDS_BIGENDIAN
870 #define RI16_IMM16 (((b1) << 8) | (b2))
871 #else
872 #define RI16_IMM16 (((b2) << 8) | (b1))
873 #endif
874
875 #ifdef TARGET_WORDS_BIGENDIAN
876 #define CALL_N (((b0) & 0xc) >> 2)
877 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
878 #else
879 #define CALL_N (((b0) & 0x30) >> 4)
880 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
881 #endif
882 #define CALL_OFFSET_SE \
883 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
884
885 #define CALLX_N CALL_N
886 #ifdef TARGET_WORDS_BIGENDIAN
887 #define CALLX_M ((b0) & 0x3)
888 #else
889 #define CALLX_M (((b0) & 0xc0) >> 6)
890 #endif
891 #define CALLX_S RRR_S
892
893 #define BRI12_M CALLX_M
894 #define BRI12_S RRR_S
895 #ifdef TARGET_WORDS_BIGENDIAN
896 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
897 #else
898 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
899 #endif
900 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
901
902 #define BRI8_M BRI12_M
903 #define BRI8_R RRI8_R
904 #define BRI8_S RRI8_S
905 #define BRI8_IMM8 RRI8_IMM8
906 #define BRI8_IMM8_SE RRI8_IMM8_SE
907
908 #define RSR_SR (b1)
909
910 uint8_t b0 = cpu_ldub_code(env, dc->pc);
911 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
912 uint8_t b2 = 0;
913
914 static const uint32_t B4CONST[] = {
915 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
916 };
917
918 static const uint32_t B4CONSTU[] = {
919 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
920 };
921
922 if (OP0 >= 8) {
923 dc->next_pc = dc->pc + 2;
924 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
925 } else {
926 dc->next_pc = dc->pc + 3;
927 b2 = cpu_ldub_code(env, dc->pc + 2);
928 }
929
930 switch (OP0) {
931 case 0: /*QRST*/
932 switch (OP1) {
933 case 0: /*RST0*/
934 switch (OP2) {
935 case 0: /*ST0*/
936 if ((RRR_R & 0xc) == 0x8) {
937 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
938 }
939
940 switch (RRR_R) {
941 case 0: /*SNM0*/
942 switch (CALLX_M) {
943 case 0: /*ILL*/
944 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
945 break;
946
947 case 1: /*reserved*/
948 RESERVED();
949 break;
950
951 case 2: /*JR*/
952 switch (CALLX_N) {
953 case 0: /*RET*/
954 case 2: /*JX*/
955 gen_window_check1(dc, CALLX_S);
956 gen_jump(dc, cpu_R[CALLX_S]);
957 break;
958
959 case 1: /*RETWw*/
960 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
961 {
962 TCGv_i32 tmp = tcg_const_i32(dc->pc);
963 gen_advance_ccount(dc);
964 gen_helper_retw(tmp, cpu_env, tmp);
965 gen_jump(dc, tmp);
966 tcg_temp_free(tmp);
967 }
968 break;
969
970 case 3: /*reserved*/
971 RESERVED();
972 break;
973 }
974 break;
975
976 case 3: /*CALLX*/
977 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
978 switch (CALLX_N) {
979 case 0: /*CALLX0*/
980 {
981 TCGv_i32 tmp = tcg_temp_new_i32();
982 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
983 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
984 gen_jump(dc, tmp);
985 tcg_temp_free(tmp);
986 }
987 break;
988
989 case 1: /*CALLX4w*/
990 case 2: /*CALLX8w*/
991 case 3: /*CALLX12w*/
992 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
993 {
994 TCGv_i32 tmp = tcg_temp_new_i32();
995
996 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
997 gen_callw(dc, CALLX_N, tmp);
998 tcg_temp_free(tmp);
999 }
1000 break;
1001 }
1002 break;
1003 }
1004 break;
1005
1006 case 1: /*MOVSPw*/
1007 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1008 gen_window_check2(dc, RRR_T, RRR_S);
1009 {
1010 TCGv_i32 pc = tcg_const_i32(dc->pc);
1011 gen_advance_ccount(dc);
1012 gen_helper_movsp(cpu_env, pc);
1013 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1014 tcg_temp_free(pc);
1015 }
1016 break;
1017
1018 case 2: /*SYNC*/
1019 switch (RRR_T) {
1020 case 0: /*ISYNC*/
1021 break;
1022
1023 case 1: /*RSYNC*/
1024 break;
1025
1026 case 2: /*ESYNC*/
1027 break;
1028
1029 case 3: /*DSYNC*/
1030 break;
1031
1032 case 8: /*EXCW*/
1033 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1034 break;
1035
1036 case 12: /*MEMW*/
1037 break;
1038
1039 case 13: /*EXTW*/
1040 break;
1041
1042 case 15: /*NOP*/
1043 break;
1044
1045 default: /*reserved*/
1046 RESERVED();
1047 break;
1048 }
1049 break;
1050
1051 case 3: /*RFEIx*/
1052 switch (RRR_T) {
1053 case 0: /*RFETx*/
1054 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1055 switch (RRR_S) {
1056 case 0: /*RFEx*/
1057 gen_check_privilege(dc);
1058 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1059 gen_helper_check_interrupts(cpu_env);
1060 gen_jump(dc, cpu_SR[EPC1]);
1061 break;
1062
1063 case 1: /*RFUEx*/
1064 RESERVED();
1065 break;
1066
1067 case 2: /*RFDEx*/
1068 gen_check_privilege(dc);
1069 gen_jump(dc, cpu_SR[
1070 dc->config->ndepc ? DEPC : EPC1]);
1071 break;
1072
1073 case 4: /*RFWOw*/
1074 case 5: /*RFWUw*/
1075 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1076 gen_check_privilege(dc);
1077 {
1078 TCGv_i32 tmp = tcg_const_i32(1);
1079
1080 tcg_gen_andi_i32(
1081 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1082 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1083
1084 if (RRR_S == 4) {
1085 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1086 cpu_SR[WINDOW_START], tmp);
1087 } else {
1088 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1089 cpu_SR[WINDOW_START], tmp);
1090 }
1091
1092 gen_helper_restore_owb(cpu_env);
1093 gen_helper_check_interrupts(cpu_env);
1094 gen_jump(dc, cpu_SR[EPC1]);
1095
1096 tcg_temp_free(tmp);
1097 }
1098 break;
1099
1100 default: /*reserved*/
1101 RESERVED();
1102 break;
1103 }
1104 break;
1105
1106 case 1: /*RFIx*/
1107 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1108 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1109 gen_check_privilege(dc);
1110 tcg_gen_mov_i32(cpu_SR[PS],
1111 cpu_SR[EPS2 + RRR_S - 2]);
1112 gen_helper_check_interrupts(cpu_env);
1113 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1114 } else {
1115 qemu_log("RFI %d is illegal\n", RRR_S);
1116 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1117 }
1118 break;
1119
1120 case 2: /*RFME*/
1121 TBD();
1122 break;
1123
1124 default: /*reserved*/
1125 RESERVED();
1126 break;
1127
1128 }
1129 break;
1130
1131 case 4: /*BREAKx*/
1132 HAS_OPTION(XTENSA_OPTION_DEBUG);
1133 if (dc->debug) {
1134 gen_debug_exception(dc, DEBUGCAUSE_BI);
1135 }
1136 break;
1137
1138 case 5: /*SYSCALLx*/
1139 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1140 switch (RRR_S) {
1141 case 0: /*SYSCALLx*/
1142 gen_exception_cause(dc, SYSCALL_CAUSE);
1143 break;
1144
1145 case 1: /*SIMCALL*/
1146 if (semihosting_enabled) {
1147 gen_check_privilege(dc);
1148 gen_helper_simcall(cpu_env);
1149 } else {
1150 qemu_log("SIMCALL but semihosting is disabled\n");
1151 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1152 }
1153 break;
1154
1155 default:
1156 RESERVED();
1157 break;
1158 }
1159 break;
1160
1161 case 6: /*RSILx*/
1162 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1163 gen_check_privilege(dc);
1164 gen_window_check1(dc, RRR_T);
1165 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1166 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1167 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1168 gen_helper_check_interrupts(cpu_env);
1169 gen_jumpi_check_loop_end(dc, 0);
1170 break;
1171
1172 case 7: /*WAITIx*/
1173 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1174 gen_check_privilege(dc);
1175 gen_waiti(dc, RRR_S);
1176 break;
1177
1178 case 8: /*ANY4p*/
1179 case 9: /*ALL4p*/
1180 case 10: /*ANY8p*/
1181 case 11: /*ALL8p*/
1182 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1183 {
1184 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1185 TCGv_i32 mask = tcg_const_i32(
1186 ((1 << shift) - 1) << RRR_S);
1187 TCGv_i32 tmp = tcg_temp_new_i32();
1188
1189 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1190 if (RRR_R & 1) { /*ALL*/
1191 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1192 } else { /*ANY*/
1193 tcg_gen_add_i32(tmp, tmp, mask);
1194 }
1195 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1196 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1197 tmp, RRR_T, 1);
1198 tcg_temp_free(mask);
1199 tcg_temp_free(tmp);
1200 }
1201 break;
1202
1203 default: /*reserved*/
1204 RESERVED();
1205 break;
1206
1207 }
1208 break;
1209
1210 case 1: /*AND*/
1211 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1212 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1213 break;
1214
1215 case 2: /*OR*/
1216 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1217 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1218 break;
1219
1220 case 3: /*XOR*/
1221 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1222 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1223 break;
1224
1225 case 4: /*ST1*/
1226 switch (RRR_R) {
1227 case 0: /*SSR*/
1228 gen_window_check1(dc, RRR_S);
1229 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1230 break;
1231
1232 case 1: /*SSL*/
1233 gen_window_check1(dc, RRR_S);
1234 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1235 break;
1236
1237 case 2: /*SSA8L*/
1238 gen_window_check1(dc, RRR_S);
1239 {
1240 TCGv_i32 tmp = tcg_temp_new_i32();
1241 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1242 gen_right_shift_sar(dc, tmp);
1243 tcg_temp_free(tmp);
1244 }
1245 break;
1246
1247 case 3: /*SSA8B*/
1248 gen_window_check1(dc, RRR_S);
1249 {
1250 TCGv_i32 tmp = tcg_temp_new_i32();
1251 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1252 gen_left_shift_sar(dc, tmp);
1253 tcg_temp_free(tmp);
1254 }
1255 break;
1256
1257 case 4: /*SSAI*/
1258 {
1259 TCGv_i32 tmp = tcg_const_i32(
1260 RRR_S | ((RRR_T & 1) << 4));
1261 gen_right_shift_sar(dc, tmp);
1262 tcg_temp_free(tmp);
1263 }
1264 break;
1265
1266 case 6: /*RER*/
1267 TBD();
1268 break;
1269
1270 case 7: /*WER*/
1271 TBD();
1272 break;
1273
1274 case 8: /*ROTWw*/
1275 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1276 gen_check_privilege(dc);
1277 {
1278 TCGv_i32 tmp = tcg_const_i32(
1279 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1280 gen_helper_rotw(cpu_env, tmp);
1281 tcg_temp_free(tmp);
1282 reset_used_window(dc);
1283 }
1284 break;
1285
1286 case 14: /*NSAu*/
1287 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1288 gen_window_check2(dc, RRR_S, RRR_T);
1289 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1290 break;
1291
1292 case 15: /*NSAUu*/
1293 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1294 gen_window_check2(dc, RRR_S, RRR_T);
1295 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1296 break;
1297
1298 default: /*reserved*/
1299 RESERVED();
1300 break;
1301 }
1302 break;
1303
1304 case 5: /*TLB*/
1305 HAS_OPTION_BITS(
1306 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1307 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1308 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1309 gen_check_privilege(dc);
1310 gen_window_check2(dc, RRR_S, RRR_T);
1311 {
1312 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1313
1314 switch (RRR_R & 7) {
1315 case 3: /*RITLB0*/ /*RDTLB0*/
1316 gen_helper_rtlb0(cpu_R[RRR_T],
1317 cpu_env, cpu_R[RRR_S], dtlb);
1318 break;
1319
1320 case 4: /*IITLB*/ /*IDTLB*/
1321 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1322 /* This could change memory mapping, so exit tb */
1323 gen_jumpi_check_loop_end(dc, -1);
1324 break;
1325
1326 case 5: /*PITLB*/ /*PDTLB*/
1327 tcg_gen_movi_i32(cpu_pc, dc->pc);
1328 gen_helper_ptlb(cpu_R[RRR_T],
1329 cpu_env, cpu_R[RRR_S], dtlb);
1330 break;
1331
1332 case 6: /*WITLB*/ /*WDTLB*/
1333 gen_helper_wtlb(
1334 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1335 /* This could change memory mapping, so exit tb */
1336 gen_jumpi_check_loop_end(dc, -1);
1337 break;
1338
1339 case 7: /*RITLB1*/ /*RDTLB1*/
1340 gen_helper_rtlb1(cpu_R[RRR_T],
1341 cpu_env, cpu_R[RRR_S], dtlb);
1342 break;
1343
1344 default:
1345 tcg_temp_free(dtlb);
1346 RESERVED();
1347 break;
1348 }
1349 tcg_temp_free(dtlb);
1350 }
1351 break;
1352
1353 case 6: /*RT0*/
1354 gen_window_check2(dc, RRR_R, RRR_T);
1355 switch (RRR_S) {
1356 case 0: /*NEG*/
1357 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1358 break;
1359
1360 case 1: /*ABS*/
1361 {
1362 int label = gen_new_label();
1363 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1364 tcg_gen_brcondi_i32(
1365 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1366 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1367 gen_set_label(label);
1368 }
1369 break;
1370
1371 default: /*reserved*/
1372 RESERVED();
1373 break;
1374 }
1375 break;
1376
1377 case 7: /*reserved*/
1378 RESERVED();
1379 break;
1380
1381 case 8: /*ADD*/
1382 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1383 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1384 break;
1385
1386 case 9: /*ADD**/
1387 case 10:
1388 case 11:
1389 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1390 {
1391 TCGv_i32 tmp = tcg_temp_new_i32();
1392 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1393 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1394 tcg_temp_free(tmp);
1395 }
1396 break;
1397
1398 case 12: /*SUB*/
1399 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1400 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1401 break;
1402
1403 case 13: /*SUB**/
1404 case 14:
1405 case 15:
1406 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1407 {
1408 TCGv_i32 tmp = tcg_temp_new_i32();
1409 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1410 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1411 tcg_temp_free(tmp);
1412 }
1413 break;
1414 }
1415 break;
1416
1417 case 1: /*RST1*/
1418 switch (OP2) {
1419 case 0: /*SLLI*/
1420 case 1:
1421 gen_window_check2(dc, RRR_R, RRR_S);
1422 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1423 32 - (RRR_T | ((OP2 & 1) << 4)));
1424 break;
1425
1426 case 2: /*SRAI*/
1427 case 3:
1428 gen_window_check2(dc, RRR_R, RRR_T);
1429 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1430 RRR_S | ((OP2 & 1) << 4));
1431 break;
1432
1433 case 4: /*SRLI*/
1434 gen_window_check2(dc, RRR_R, RRR_T);
1435 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1436 break;
1437
1438 case 6: /*XSR*/
1439 {
1440 TCGv_i32 tmp = tcg_temp_new_i32();
1441 if (RSR_SR >= 64) {
1442 gen_check_privilege(dc);
1443 }
1444 gen_window_check1(dc, RRR_T);
1445 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1446 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1447 gen_wsr(dc, RSR_SR, tmp);
1448 tcg_temp_free(tmp);
1449 if (!sregnames[RSR_SR]) {
1450 TBD();
1451 }
1452 }
1453 break;
1454
1455 /*
1456 * Note: 64 bit ops are used here solely because SAR values
1457 * have range 0..63
1458 */
1459 #define gen_shift_reg(cmd, reg) do { \
1460 TCGv_i64 tmp = tcg_temp_new_i64(); \
1461 tcg_gen_extu_i32_i64(tmp, reg); \
1462 tcg_gen_##cmd##_i64(v, v, tmp); \
1463 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1464 tcg_temp_free_i64(v); \
1465 tcg_temp_free_i64(tmp); \
1466 } while (0)
1467
1468 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1469
1470 case 8: /*SRC*/
1471 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1472 {
1473 TCGv_i64 v = tcg_temp_new_i64();
1474 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1475 gen_shift(shr);
1476 }
1477 break;
1478
1479 case 9: /*SRL*/
1480 gen_window_check2(dc, RRR_R, RRR_T);
1481 if (dc->sar_5bit) {
1482 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1483 } else {
1484 TCGv_i64 v = tcg_temp_new_i64();
1485 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1486 gen_shift(shr);
1487 }
1488 break;
1489
1490 case 10: /*SLL*/
1491 gen_window_check2(dc, RRR_R, RRR_S);
1492 if (dc->sar_m32_5bit) {
1493 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1494 } else {
1495 TCGv_i64 v = tcg_temp_new_i64();
1496 TCGv_i32 s = tcg_const_i32(32);
1497 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1498 tcg_gen_andi_i32(s, s, 0x3f);
1499 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1500 gen_shift_reg(shl, s);
1501 tcg_temp_free(s);
1502 }
1503 break;
1504
1505 case 11: /*SRA*/
1506 gen_window_check2(dc, RRR_R, RRR_T);
1507 if (dc->sar_5bit) {
1508 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1509 } else {
1510 TCGv_i64 v = tcg_temp_new_i64();
1511 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1512 gen_shift(sar);
1513 }
1514 break;
1515 #undef gen_shift
1516 #undef gen_shift_reg
1517
1518 case 12: /*MUL16U*/
1519 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1520 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1521 {
1522 TCGv_i32 v1 = tcg_temp_new_i32();
1523 TCGv_i32 v2 = tcg_temp_new_i32();
1524 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1525 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1526 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1527 tcg_temp_free(v2);
1528 tcg_temp_free(v1);
1529 }
1530 break;
1531
1532 case 13: /*MUL16S*/
1533 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1534 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1535 {
1536 TCGv_i32 v1 = tcg_temp_new_i32();
1537 TCGv_i32 v2 = tcg_temp_new_i32();
1538 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1539 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1540 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1541 tcg_temp_free(v2);
1542 tcg_temp_free(v1);
1543 }
1544 break;
1545
1546 default: /*reserved*/
1547 RESERVED();
1548 break;
1549 }
1550 break;
1551
1552 case 2: /*RST2*/
1553 if (OP2 >= 8) {
1554 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1555 }
1556
1557 if (OP2 >= 12) {
1558 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1559 int label = gen_new_label();
1560 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1561 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1562 gen_set_label(label);
1563 }
1564
1565 switch (OP2) {
1566 #define BOOLEAN_LOGIC(fn, r, s, t) \
1567 do { \
1568 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1569 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1570 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1571 \
1572 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1573 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1574 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1575 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1576 tcg_temp_free(tmp1); \
1577 tcg_temp_free(tmp2); \
1578 } while (0)
1579
1580 case 0: /*ANDBp*/
1581 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1582 break;
1583
1584 case 1: /*ANDBCp*/
1585 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1586 break;
1587
1588 case 2: /*ORBp*/
1589 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1590 break;
1591
1592 case 3: /*ORBCp*/
1593 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1594 break;
1595
1596 case 4: /*XORBp*/
1597 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1598 break;
1599
1600 #undef BOOLEAN_LOGIC
1601
1602 case 8: /*MULLi*/
1603 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1604 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1605 break;
1606
1607 case 10: /*MULUHi*/
1608 case 11: /*MULSHi*/
1609 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1610 {
1611 TCGv_i64 r = tcg_temp_new_i64();
1612 TCGv_i64 s = tcg_temp_new_i64();
1613 TCGv_i64 t = tcg_temp_new_i64();
1614
1615 if (OP2 == 10) {
1616 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1617 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1618 } else {
1619 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1620 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1621 }
1622 tcg_gen_mul_i64(r, s, t);
1623 tcg_gen_shri_i64(r, r, 32);
1624 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1625
1626 tcg_temp_free_i64(r);
1627 tcg_temp_free_i64(s);
1628 tcg_temp_free_i64(t);
1629 }
1630 break;
1631
1632 case 12: /*QUOUi*/
1633 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1634 break;
1635
1636 case 13: /*QUOSi*/
1637 case 15: /*REMSi*/
1638 {
1639 int label1 = gen_new_label();
1640 int label2 = gen_new_label();
1641
1642 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1643 label1);
1644 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1645 label1);
1646 tcg_gen_movi_i32(cpu_R[RRR_R],
1647 OP2 == 13 ? 0x80000000 : 0);
1648 tcg_gen_br(label2);
1649 gen_set_label(label1);
1650 if (OP2 == 13) {
1651 tcg_gen_div_i32(cpu_R[RRR_R],
1652 cpu_R[RRR_S], cpu_R[RRR_T]);
1653 } else {
1654 tcg_gen_rem_i32(cpu_R[RRR_R],
1655 cpu_R[RRR_S], cpu_R[RRR_T]);
1656 }
1657 gen_set_label(label2);
1658 }
1659 break;
1660
1661 case 14: /*REMUi*/
1662 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1663 break;
1664
1665 default: /*reserved*/
1666 RESERVED();
1667 break;
1668 }
1669 break;
1670
1671 case 3: /*RST3*/
1672 switch (OP2) {
1673 case 0: /*RSR*/
1674 if (RSR_SR >= 64) {
1675 gen_check_privilege(dc);
1676 }
1677 gen_window_check1(dc, RRR_T);
1678 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1679 if (!sregnames[RSR_SR]) {
1680 TBD();
1681 }
1682 break;
1683
1684 case 1: /*WSR*/
1685 if (RSR_SR >= 64) {
1686 gen_check_privilege(dc);
1687 }
1688 gen_window_check1(dc, RRR_T);
1689 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1690 if (!sregnames[RSR_SR]) {
1691 TBD();
1692 }
1693 break;
1694
1695 case 2: /*SEXTu*/
1696 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1697 gen_window_check2(dc, RRR_R, RRR_S);
1698 {
1699 int shift = 24 - RRR_T;
1700
1701 if (shift == 24) {
1702 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1703 } else if (shift == 16) {
1704 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1705 } else {
1706 TCGv_i32 tmp = tcg_temp_new_i32();
1707 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1708 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1709 tcg_temp_free(tmp);
1710 }
1711 }
1712 break;
1713
1714 case 3: /*CLAMPSu*/
1715 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1716 gen_window_check2(dc, RRR_R, RRR_S);
1717 {
1718 TCGv_i32 tmp1 = tcg_temp_new_i32();
1719 TCGv_i32 tmp2 = tcg_temp_new_i32();
1720 int label = gen_new_label();
1721
1722 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1723 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1724 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1725 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1726 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1727
1728 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1729 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1730 0xffffffff >> (25 - RRR_T));
1731
1732 gen_set_label(label);
1733
1734 tcg_temp_free(tmp1);
1735 tcg_temp_free(tmp2);
1736 }
1737 break;
1738
1739 case 4: /*MINu*/
1740 case 5: /*MAXu*/
1741 case 6: /*MINUu*/
1742 case 7: /*MAXUu*/
1743 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1744 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1745 {
1746 static const TCGCond cond[] = {
1747 TCG_COND_LE,
1748 TCG_COND_GE,
1749 TCG_COND_LEU,
1750 TCG_COND_GEU
1751 };
1752 int label = gen_new_label();
1753
1754 if (RRR_R != RRR_T) {
1755 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1756 tcg_gen_brcond_i32(cond[OP2 - 4],
1757 cpu_R[RRR_S], cpu_R[RRR_T], label);
1758 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1759 } else {
1760 tcg_gen_brcond_i32(cond[OP2 - 4],
1761 cpu_R[RRR_T], cpu_R[RRR_S], label);
1762 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1763 }
1764 gen_set_label(label);
1765 }
1766 break;
1767
1768 case 8: /*MOVEQZ*/
1769 case 9: /*MOVNEZ*/
1770 case 10: /*MOVLTZ*/
1771 case 11: /*MOVGEZ*/
1772 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1773 {
1774 static const TCGCond cond[] = {
1775 TCG_COND_NE,
1776 TCG_COND_EQ,
1777 TCG_COND_GE,
1778 TCG_COND_LT
1779 };
1780 int label = gen_new_label();
1781 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1782 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1783 gen_set_label(label);
1784 }
1785 break;
1786
1787 case 12: /*MOVFp*/
1788 case 13: /*MOVTp*/
1789 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1790 gen_window_check2(dc, RRR_R, RRR_S);
1791 {
1792 int label = gen_new_label();
1793 TCGv_i32 tmp = tcg_temp_new_i32();
1794
1795 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1796 tcg_gen_brcondi_i32(
1797 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
1798 tmp, 0, label);
1799 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1800 gen_set_label(label);
1801 tcg_temp_free(tmp);
1802 }
1803 break;
1804
1805 case 14: /*RUR*/
1806 gen_window_check1(dc, RRR_R);
1807 {
1808 int st = (RRR_S << 4) + RRR_T;
1809 if (uregnames[st]) {
1810 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1811 } else {
1812 qemu_log("RUR %d not implemented, ", st);
1813 TBD();
1814 }
1815 }
1816 break;
1817
1818 case 15: /*WUR*/
1819 gen_window_check1(dc, RRR_T);
1820 if (uregnames[RSR_SR]) {
1821 gen_wur(RSR_SR, cpu_R[RRR_T]);
1822 } else {
1823 qemu_log("WUR %d not implemented, ", RSR_SR);
1824 TBD();
1825 }
1826 break;
1827
1828 }
1829 break;
1830
1831 case 4: /*EXTUI*/
1832 case 5:
1833 gen_window_check2(dc, RRR_R, RRR_T);
1834 {
1835 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1836 int maskimm = (1 << (OP2 + 1)) - 1;
1837
1838 TCGv_i32 tmp = tcg_temp_new_i32();
1839 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1840 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1841 tcg_temp_free(tmp);
1842 }
1843 break;
1844
1845 case 6: /*CUST0*/
1846 RESERVED();
1847 break;
1848
1849 case 7: /*CUST1*/
1850 RESERVED();
1851 break;
1852
1853 case 8: /*LSCXp*/
1854 switch (OP2) {
1855 case 0: /*LSXf*/
1856 case 1: /*LSXUf*/
1857 case 4: /*SSXf*/
1858 case 5: /*SSXUf*/
1859 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1860 gen_window_check2(dc, RRR_S, RRR_T);
1861 gen_check_cpenable(dc, 0);
1862 {
1863 TCGv_i32 addr = tcg_temp_new_i32();
1864 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1865 gen_load_store_alignment(dc, 2, addr, false);
1866 if (OP2 & 0x4) {
1867 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1868 } else {
1869 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1870 }
1871 if (OP2 & 0x1) {
1872 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1873 }
1874 tcg_temp_free(addr);
1875 }
1876 break;
1877
1878 default: /*reserved*/
1879 RESERVED();
1880 break;
1881 }
1882 break;
1883
1884 case 9: /*LSC4*/
1885 gen_window_check2(dc, RRR_S, RRR_T);
1886 switch (OP2) {
1887 case 0: /*L32E*/
1888 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1889 gen_check_privilege(dc);
1890 {
1891 TCGv_i32 addr = tcg_temp_new_i32();
1892 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1893 (0xffffffc0 | (RRR_R << 2)));
1894 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1895 tcg_temp_free(addr);
1896 }
1897 break;
1898
1899 case 4: /*S32E*/
1900 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1901 gen_check_privilege(dc);
1902 {
1903 TCGv_i32 addr = tcg_temp_new_i32();
1904 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1905 (0xffffffc0 | (RRR_R << 2)));
1906 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1907 tcg_temp_free(addr);
1908 }
1909 break;
1910
1911 default:
1912 RESERVED();
1913 break;
1914 }
1915 break;
1916
1917 case 10: /*FP0*/
1918 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1919 switch (OP2) {
1920 case 0: /*ADD.Sf*/
1921 gen_check_cpenable(dc, 0);
1922 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
1923 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1924 break;
1925
1926 case 1: /*SUB.Sf*/
1927 gen_check_cpenable(dc, 0);
1928 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
1929 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1930 break;
1931
1932 case 2: /*MUL.Sf*/
1933 gen_check_cpenable(dc, 0);
1934 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
1935 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1936 break;
1937
1938 case 4: /*MADD.Sf*/
1939 gen_check_cpenable(dc, 0);
1940 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
1941 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1942 break;
1943
1944 case 5: /*MSUB.Sf*/
1945 gen_check_cpenable(dc, 0);
1946 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
1947 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1948 break;
1949
1950 case 8: /*ROUND.Sf*/
1951 case 9: /*TRUNC.Sf*/
1952 case 10: /*FLOOR.Sf*/
1953 case 11: /*CEIL.Sf*/
1954 case 14: /*UTRUNC.Sf*/
1955 gen_window_check1(dc, RRR_R);
1956 gen_check_cpenable(dc, 0);
1957 {
1958 static const unsigned rounding_mode_const[] = {
1959 float_round_nearest_even,
1960 float_round_to_zero,
1961 float_round_down,
1962 float_round_up,
1963 [6] = float_round_to_zero,
1964 };
1965 TCGv_i32 rounding_mode = tcg_const_i32(
1966 rounding_mode_const[OP2 & 7]);
1967 TCGv_i32 scale = tcg_const_i32(RRR_T);
1968
1969 if (OP2 == 14) {
1970 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
1971 rounding_mode, scale);
1972 } else {
1973 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
1974 rounding_mode, scale);
1975 }
1976
1977 tcg_temp_free(rounding_mode);
1978 tcg_temp_free(scale);
1979 }
1980 break;
1981
1982 case 12: /*FLOAT.Sf*/
1983 case 13: /*UFLOAT.Sf*/
1984 gen_window_check1(dc, RRR_S);
1985 gen_check_cpenable(dc, 0);
1986 {
1987 TCGv_i32 scale = tcg_const_i32(-RRR_T);
1988
1989 if (OP2 == 13) {
1990 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
1991 cpu_R[RRR_S], scale);
1992 } else {
1993 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
1994 cpu_R[RRR_S], scale);
1995 }
1996 tcg_temp_free(scale);
1997 }
1998 break;
1999
2000 case 15: /*FP1OP*/
2001 switch (RRR_T) {
2002 case 0: /*MOV.Sf*/
2003 gen_check_cpenable(dc, 0);
2004 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2005 break;
2006
2007 case 1: /*ABS.Sf*/
2008 gen_check_cpenable(dc, 0);
2009 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2010 break;
2011
2012 case 4: /*RFRf*/
2013 gen_window_check1(dc, RRR_R);
2014 gen_check_cpenable(dc, 0);
2015 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2016 break;
2017
2018 case 5: /*WFRf*/
2019 gen_window_check1(dc, RRR_S);
2020 gen_check_cpenable(dc, 0);
2021 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2022 break;
2023
2024 case 6: /*NEG.Sf*/
2025 gen_check_cpenable(dc, 0);
2026 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2027 break;
2028
2029 default: /*reserved*/
2030 RESERVED();
2031 break;
2032 }
2033 break;
2034
2035 default: /*reserved*/
2036 RESERVED();
2037 break;
2038 }
2039 break;
2040
2041 case 11: /*FP1*/
2042 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2043
2044 #define gen_compare(rel, br, a, b) \
2045 do { \
2046 TCGv_i32 bit = tcg_const_i32(1 << br); \
2047 \
2048 gen_check_cpenable(dc, 0); \
2049 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2050 tcg_temp_free(bit); \
2051 } while (0)
2052
2053 switch (OP2) {
2054 case 1: /*UN.Sf*/
2055 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2056 break;
2057
2058 case 2: /*OEQ.Sf*/
2059 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2060 break;
2061
2062 case 3: /*UEQ.Sf*/
2063 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2064 break;
2065
2066 case 4: /*OLT.Sf*/
2067 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2068 break;
2069
2070 case 5: /*ULT.Sf*/
2071 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2072 break;
2073
2074 case 6: /*OLE.Sf*/
2075 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2076 break;
2077
2078 case 7: /*ULE.Sf*/
2079 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2080 break;
2081
2082 #undef gen_compare
2083
2084 case 8: /*MOVEQZ.Sf*/
2085 case 9: /*MOVNEZ.Sf*/
2086 case 10: /*MOVLTZ.Sf*/
2087 case 11: /*MOVGEZ.Sf*/
2088 gen_window_check1(dc, RRR_T);
2089 gen_check_cpenable(dc, 0);
2090 {
2091 static const TCGCond cond[] = {
2092 TCG_COND_NE,
2093 TCG_COND_EQ,
2094 TCG_COND_GE,
2095 TCG_COND_LT
2096 };
2097 int label = gen_new_label();
2098 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
2099 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2100 gen_set_label(label);
2101 }
2102 break;
2103
2104 case 12: /*MOVF.Sf*/
2105 case 13: /*MOVT.Sf*/
2106 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2107 gen_check_cpenable(dc, 0);
2108 {
2109 int label = gen_new_label();
2110 TCGv_i32 tmp = tcg_temp_new_i32();
2111
2112 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2113 tcg_gen_brcondi_i32(
2114 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
2115 tmp, 0, label);
2116 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2117 gen_set_label(label);
2118 tcg_temp_free(tmp);
2119 }
2120 break;
2121
2122 default: /*reserved*/
2123 RESERVED();
2124 break;
2125 }
2126 break;
2127
2128 default: /*reserved*/
2129 RESERVED();
2130 break;
2131 }
2132 break;
2133
2134 case 1: /*L32R*/
2135 gen_window_check1(dc, RRR_T);
2136 {
2137 TCGv_i32 tmp = tcg_const_i32(
2138 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2139 0 : ((dc->pc + 3) & ~3)) +
2140 (0xfffc0000 | (RI16_IMM16 << 2)));
2141
2142 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2143 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2144 }
2145 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
2146 tcg_temp_free(tmp);
2147 }
2148 break;
2149
2150 case 2: /*LSAI*/
2151 #define gen_load_store(type, shift) do { \
2152 TCGv_i32 addr = tcg_temp_new_i32(); \
2153 gen_window_check2(dc, RRI8_S, RRI8_T); \
2154 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2155 if (shift) { \
2156 gen_load_store_alignment(dc, shift, addr, false); \
2157 } \
2158 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2159 tcg_temp_free(addr); \
2160 } while (0)
2161
2162 switch (RRI8_R) {
2163 case 0: /*L8UI*/
2164 gen_load_store(ld8u, 0);
2165 break;
2166
2167 case 1: /*L16UI*/
2168 gen_load_store(ld16u, 1);
2169 break;
2170
2171 case 2: /*L32I*/
2172 gen_load_store(ld32u, 2);
2173 break;
2174
2175 case 4: /*S8I*/
2176 gen_load_store(st8, 0);
2177 break;
2178
2179 case 5: /*S16I*/
2180 gen_load_store(st16, 1);
2181 break;
2182
2183 case 6: /*S32I*/
2184 gen_load_store(st32, 2);
2185 break;
2186
2187 case 7: /*CACHEc*/
2188 if (RRI8_T < 8) {
2189 HAS_OPTION(XTENSA_OPTION_DCACHE);
2190 }
2191
2192 switch (RRI8_T) {
2193 case 0: /*DPFRc*/
2194 break;
2195
2196 case 1: /*DPFWc*/
2197 break;
2198
2199 case 2: /*DPFROc*/
2200 break;
2201
2202 case 3: /*DPFWOc*/
2203 break;
2204
2205 case 4: /*DHWBc*/
2206 break;
2207
2208 case 5: /*DHWBIc*/
2209 break;
2210
2211 case 6: /*DHIc*/
2212 break;
2213
2214 case 7: /*DIIc*/
2215 break;
2216
2217 case 8: /*DCEc*/
2218 switch (OP1) {
2219 case 0: /*DPFLl*/
2220 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2221 break;
2222
2223 case 2: /*DHUl*/
2224 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2225 break;
2226
2227 case 3: /*DIUl*/
2228 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2229 break;
2230
2231 case 4: /*DIWBc*/
2232 HAS_OPTION(XTENSA_OPTION_DCACHE);
2233 break;
2234
2235 case 5: /*DIWBIc*/
2236 HAS_OPTION(XTENSA_OPTION_DCACHE);
2237 break;
2238
2239 default: /*reserved*/
2240 RESERVED();
2241 break;
2242
2243 }
2244 break;
2245
2246 case 12: /*IPFc*/
2247 HAS_OPTION(XTENSA_OPTION_ICACHE);
2248 break;
2249
2250 case 13: /*ICEc*/
2251 switch (OP1) {
2252 case 0: /*IPFLl*/
2253 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2254 break;
2255
2256 case 2: /*IHUl*/
2257 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2258 break;
2259
2260 case 3: /*IIUl*/
2261 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2262 break;
2263
2264 default: /*reserved*/
2265 RESERVED();
2266 break;
2267 }
2268 break;
2269
2270 case 14: /*IHIc*/
2271 HAS_OPTION(XTENSA_OPTION_ICACHE);
2272 break;
2273
2274 case 15: /*IIIc*/
2275 HAS_OPTION(XTENSA_OPTION_ICACHE);
2276 break;
2277
2278 default: /*reserved*/
2279 RESERVED();
2280 break;
2281 }
2282 break;
2283
2284 case 9: /*L16SI*/
2285 gen_load_store(ld16s, 1);
2286 break;
2287 #undef gen_load_store
2288
2289 case 10: /*MOVI*/
2290 gen_window_check1(dc, RRI8_T);
2291 tcg_gen_movi_i32(cpu_R[RRI8_T],
2292 RRI8_IMM8 | (RRI8_S << 8) |
2293 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2294 break;
2295
2296 #define gen_load_store_no_hw_align(type) do { \
2297 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2298 gen_window_check2(dc, RRI8_S, RRI8_T); \
2299 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2300 gen_load_store_alignment(dc, 2, addr, true); \
2301 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2302 tcg_temp_free(addr); \
2303 } while (0)
2304
2305 case 11: /*L32AIy*/
2306 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2307 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
2308 break;
2309
2310 case 12: /*ADDI*/
2311 gen_window_check2(dc, RRI8_S, RRI8_T);
2312 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2313 break;
2314
2315 case 13: /*ADDMI*/
2316 gen_window_check2(dc, RRI8_S, RRI8_T);
2317 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
2318 break;
2319
2320 case 14: /*S32C1Iy*/
2321 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2322 gen_window_check2(dc, RRI8_S, RRI8_T);
2323 {
2324 int label = gen_new_label();
2325 TCGv_i32 tmp = tcg_temp_local_new_i32();
2326 TCGv_i32 addr = tcg_temp_local_new_i32();
2327 TCGv_i32 tpc;
2328
2329 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2330 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2331 gen_load_store_alignment(dc, 2, addr, true);
2332
2333 gen_advance_ccount(dc);
2334 tpc = tcg_const_i32(dc->pc);
2335 gen_helper_check_atomctl(cpu_env, tpc, addr);
2336 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2337 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2338 cpu_SR[SCOMPARE1], label);
2339
2340 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2341
2342 gen_set_label(label);
2343 tcg_temp_free(tpc);
2344 tcg_temp_free(addr);
2345 tcg_temp_free(tmp);
2346 }
2347 break;
2348
2349 case 15: /*S32RIy*/
2350 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2351 gen_load_store_no_hw_align(st32); /*TODO release?*/
2352 break;
2353 #undef gen_load_store_no_hw_align
2354
2355 default: /*reserved*/
2356 RESERVED();
2357 break;
2358 }
2359 break;
2360
2361 case 3: /*LSCIp*/
2362 switch (RRI8_R) {
2363 case 0: /*LSIf*/
2364 case 4: /*SSIf*/
2365 case 8: /*LSIUf*/
2366 case 12: /*SSIUf*/
2367 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2368 gen_window_check1(dc, RRI8_S);
2369 gen_check_cpenable(dc, 0);
2370 {
2371 TCGv_i32 addr = tcg_temp_new_i32();
2372 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2373 gen_load_store_alignment(dc, 2, addr, false);
2374 if (RRI8_R & 0x4) {
2375 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2376 } else {
2377 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2378 }
2379 if (RRI8_R & 0x8) {
2380 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2381 }
2382 tcg_temp_free(addr);
2383 }
2384 break;
2385
2386 default: /*reserved*/
2387 RESERVED();
2388 break;
2389 }
2390 break;
2391
2392 case 4: /*MAC16d*/
2393 HAS_OPTION(XTENSA_OPTION_MAC16);
2394 {
2395 enum {
2396 MAC16_UMUL = 0x0,
2397 MAC16_MUL = 0x4,
2398 MAC16_MULA = 0x8,
2399 MAC16_MULS = 0xc,
2400 MAC16_NONE = 0xf,
2401 } op = OP1 & 0xc;
2402 bool is_m1_sr = (OP2 & 0x3) == 2;
2403 bool is_m2_sr = (OP2 & 0xc) == 0;
2404 uint32_t ld_offset = 0;
2405
2406 if (OP2 > 9) {
2407 RESERVED();
2408 }
2409
2410 switch (OP2 & 2) {
2411 case 0: /*MACI?/MACC?*/
2412 is_m1_sr = true;
2413 ld_offset = (OP2 & 1) ? -4 : 4;
2414
2415 if (OP2 >= 8) { /*MACI/MACC*/
2416 if (OP1 == 0) { /*LDINC/LDDEC*/
2417 op = MAC16_NONE;
2418 } else {
2419 RESERVED();
2420 }
2421 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2422 RESERVED();
2423 }
2424 break;
2425
2426 case 2: /*MACD?/MACA?*/
2427 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2428 RESERVED();
2429 }
2430 break;
2431 }
2432
2433 if (op != MAC16_NONE) {
2434 if (!is_m1_sr) {
2435 gen_window_check1(dc, RRR_S);
2436 }
2437 if (!is_m2_sr) {
2438 gen_window_check1(dc, RRR_T);
2439 }
2440 }
2441
2442 {
2443 TCGv_i32 vaddr = tcg_temp_new_i32();
2444 TCGv_i32 mem32 = tcg_temp_new_i32();
2445
2446 if (ld_offset) {
2447 gen_window_check1(dc, RRR_S);
2448 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2449 gen_load_store_alignment(dc, 2, vaddr, false);
2450 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2451 }
2452 if (op != MAC16_NONE) {
2453 TCGv_i32 m1 = gen_mac16_m(
2454 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2455 OP1 & 1, op == MAC16_UMUL);
2456 TCGv_i32 m2 = gen_mac16_m(
2457 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2458 OP1 & 2, op == MAC16_UMUL);
2459
2460 if (op == MAC16_MUL || op == MAC16_UMUL) {
2461 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2462 if (op == MAC16_UMUL) {
2463 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2464 } else {
2465 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2466 }
2467 } else {
2468 TCGv_i32 res = tcg_temp_new_i32();
2469 TCGv_i64 res64 = tcg_temp_new_i64();
2470 TCGv_i64 tmp = tcg_temp_new_i64();
2471
2472 tcg_gen_mul_i32(res, m1, m2);
2473 tcg_gen_ext_i32_i64(res64, res);
2474 tcg_gen_concat_i32_i64(tmp,
2475 cpu_SR[ACCLO], cpu_SR[ACCHI]);
2476 if (op == MAC16_MULA) {
2477 tcg_gen_add_i64(tmp, tmp, res64);
2478 } else {
2479 tcg_gen_sub_i64(tmp, tmp, res64);
2480 }
2481 tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
2482 tcg_gen_shri_i64(tmp, tmp, 32);
2483 tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
2484 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2485
2486 tcg_temp_free(res);
2487 tcg_temp_free_i64(res64);
2488 tcg_temp_free_i64(tmp);
2489 }
2490 tcg_temp_free(m1);
2491 tcg_temp_free(m2);
2492 }
2493 if (ld_offset) {
2494 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2495 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2496 }
2497 tcg_temp_free(vaddr);
2498 tcg_temp_free(mem32);
2499 }
2500 }
2501 break;
2502
2503 case 5: /*CALLN*/
2504 switch (CALL_N) {
2505 case 0: /*CALL0*/
2506 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2507 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2508 break;
2509
2510 case 1: /*CALL4w*/
2511 case 2: /*CALL8w*/
2512 case 3: /*CALL12w*/
2513 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2514 gen_window_check1(dc, CALL_N << 2);
2515 gen_callwi(dc, CALL_N,
2516 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2517 break;
2518 }
2519 break;
2520
2521 case 6: /*SI*/
2522 switch (CALL_N) {
2523 case 0: /*J*/
2524 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2525 break;
2526
2527 case 1: /*BZ*/
2528 gen_window_check1(dc, BRI12_S);
2529 {
2530 static const TCGCond cond[] = {
2531 TCG_COND_EQ, /*BEQZ*/
2532 TCG_COND_NE, /*BNEZ*/
2533 TCG_COND_LT, /*BLTZ*/
2534 TCG_COND_GE, /*BGEZ*/
2535 };
2536
2537 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2538 4 + BRI12_IMM12_SE);
2539 }
2540 break;
2541
2542 case 2: /*BI0*/
2543 gen_window_check1(dc, BRI8_S);
2544 {
2545 static const TCGCond cond[] = {
2546 TCG_COND_EQ, /*BEQI*/
2547 TCG_COND_NE, /*BNEI*/
2548 TCG_COND_LT, /*BLTI*/
2549 TCG_COND_GE, /*BGEI*/
2550 };
2551
2552 gen_brcondi(dc, cond[BRI8_M & 3],
2553 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2554 }
2555 break;
2556
2557 case 3: /*BI1*/
2558 switch (BRI8_M) {
2559 case 0: /*ENTRYw*/
2560 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2561 {
2562 TCGv_i32 pc = tcg_const_i32(dc->pc);
2563 TCGv_i32 s = tcg_const_i32(BRI12_S);
2564 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2565 gen_advance_ccount(dc);
2566 gen_helper_entry(cpu_env, pc, s, imm);
2567 tcg_temp_free(imm);
2568 tcg_temp_free(s);
2569 tcg_temp_free(pc);
2570 reset_used_window(dc);
2571 }
2572 break;
2573
2574 case 1: /*B1*/
2575 switch (BRI8_R) {
2576 case 0: /*BFp*/
2577 case 1: /*BTp*/
2578 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2579 {
2580 TCGv_i32 tmp = tcg_temp_new_i32();
2581 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2582 gen_brcondi(dc,
2583 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2584 tmp, 0, 4 + RRI8_IMM8_SE);
2585 tcg_temp_free(tmp);
2586 }
2587 break;
2588
2589 case 8: /*LOOP*/
2590 case 9: /*LOOPNEZ*/
2591 case 10: /*LOOPGTZ*/
2592 HAS_OPTION(XTENSA_OPTION_LOOP);
2593 gen_window_check1(dc, RRI8_S);
2594 {
2595 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2596 TCGv_i32 tmp = tcg_const_i32(lend);
2597
2598 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2599 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2600 gen_helper_wsr_lend(cpu_env, tmp);
2601 tcg_temp_free(tmp);
2602
2603 if (BRI8_R > 8) {
2604 int label = gen_new_label();
2605 tcg_gen_brcondi_i32(
2606 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2607 cpu_R[RRI8_S], 0, label);
2608 gen_jumpi(dc, lend, 1);
2609 gen_set_label(label);
2610 }
2611
2612 gen_jumpi(dc, dc->next_pc, 0);
2613 }
2614 break;
2615
2616 default: /*reserved*/
2617 RESERVED();
2618 break;
2619
2620 }
2621 break;
2622
2623 case 2: /*BLTUI*/
2624 case 3: /*BGEUI*/
2625 gen_window_check1(dc, BRI8_S);
2626 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2627 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2628 break;
2629 }
2630 break;
2631
2632 }
2633 break;
2634
2635 case 7: /*B*/
2636 {
2637 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2638
2639 switch (RRI8_R & 7) {
2640 case 0: /*BNONE*/ /*BANY*/
2641 gen_window_check2(dc, RRI8_S, RRI8_T);
2642 {
2643 TCGv_i32 tmp = tcg_temp_new_i32();
2644 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2645 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2646 tcg_temp_free(tmp);
2647 }
2648 break;
2649
2650 case 1: /*BEQ*/ /*BNE*/
2651 case 2: /*BLT*/ /*BGE*/
2652 case 3: /*BLTU*/ /*BGEU*/
2653 gen_window_check2(dc, RRI8_S, RRI8_T);
2654 {
2655 static const TCGCond cond[] = {
2656 [1] = TCG_COND_EQ,
2657 [2] = TCG_COND_LT,
2658 [3] = TCG_COND_LTU,
2659 [9] = TCG_COND_NE,
2660 [10] = TCG_COND_GE,
2661 [11] = TCG_COND_GEU,
2662 };
2663 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2664 4 + RRI8_IMM8_SE);
2665 }
2666 break;
2667
2668 case 4: /*BALL*/ /*BNALL*/
2669 gen_window_check2(dc, RRI8_S, RRI8_T);
2670 {
2671 TCGv_i32 tmp = tcg_temp_new_i32();
2672 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2673 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2674 4 + RRI8_IMM8_SE);
2675 tcg_temp_free(tmp);
2676 }
2677 break;
2678
2679 case 5: /*BBC*/ /*BBS*/
2680 gen_window_check2(dc, RRI8_S, RRI8_T);
2681 {
2682 #ifdef TARGET_WORDS_BIGENDIAN
2683 TCGv_i32 bit = tcg_const_i32(0x80000000);
2684 #else
2685 TCGv_i32 bit = tcg_const_i32(0x00000001);
2686 #endif
2687 TCGv_i32 tmp = tcg_temp_new_i32();
2688 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2689 #ifdef TARGET_WORDS_BIGENDIAN
2690 tcg_gen_shr_i32(bit, bit, tmp);
2691 #else
2692 tcg_gen_shl_i32(bit, bit, tmp);
2693 #endif
2694 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2695 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2696 tcg_temp_free(tmp);
2697 tcg_temp_free(bit);
2698 }
2699 break;
2700
2701 case 6: /*BBCI*/ /*BBSI*/
2702 case 7:
2703 gen_window_check1(dc, RRI8_S);
2704 {
2705 TCGv_i32 tmp = tcg_temp_new_i32();
2706 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2707 #ifdef TARGET_WORDS_BIGENDIAN
2708 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2709 #else
2710 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2711 #endif
2712 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2713 tcg_temp_free(tmp);
2714 }
2715 break;
2716
2717 }
2718 }
2719 break;
2720
2721 #define gen_narrow_load_store(type) do { \
2722 TCGv_i32 addr = tcg_temp_new_i32(); \
2723 gen_window_check2(dc, RRRN_S, RRRN_T); \
2724 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2725 gen_load_store_alignment(dc, 2, addr, false); \
2726 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2727 tcg_temp_free(addr); \
2728 } while (0)
2729
2730 case 8: /*L32I.Nn*/
2731 gen_narrow_load_store(ld32u);
2732 break;
2733
2734 case 9: /*S32I.Nn*/
2735 gen_narrow_load_store(st32);
2736 break;
2737 #undef gen_narrow_load_store
2738
2739 case 10: /*ADD.Nn*/
2740 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
2741 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2742 break;
2743
2744 case 11: /*ADDI.Nn*/
2745 gen_window_check2(dc, RRRN_R, RRRN_S);
2746 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
2747 break;
2748
2749 case 12: /*ST2n*/
2750 gen_window_check1(dc, RRRN_S);
2751 if (RRRN_T < 8) { /*MOVI.Nn*/
2752 tcg_gen_movi_i32(cpu_R[RRRN_S],
2753 RRRN_R | (RRRN_T << 4) |
2754 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2755 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2756 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2757
2758 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2759 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2760 }
2761 break;
2762
2763 case 13: /*ST3n*/
2764 switch (RRRN_R) {
2765 case 0: /*MOV.Nn*/
2766 gen_window_check2(dc, RRRN_S, RRRN_T);
2767 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2768 break;
2769
2770 case 15: /*S3*/
2771 switch (RRRN_T) {
2772 case 0: /*RET.Nn*/
2773 gen_jump(dc, cpu_R[0]);
2774 break;
2775
2776 case 1: /*RETW.Nn*/
2777 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2778 {
2779 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2780 gen_advance_ccount(dc);
2781 gen_helper_retw(tmp, cpu_env, tmp);
2782 gen_jump(dc, tmp);
2783 tcg_temp_free(tmp);
2784 }
2785 break;
2786
2787 case 2: /*BREAK.Nn*/
2788 HAS_OPTION(XTENSA_OPTION_DEBUG);
2789 if (dc->debug) {
2790 gen_debug_exception(dc, DEBUGCAUSE_BN);
2791 }
2792 break;
2793
2794 case 3: /*NOP.Nn*/
2795 break;
2796
2797 case 6: /*ILL.Nn*/
2798 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2799 break;
2800
2801 default: /*reserved*/
2802 RESERVED();
2803 break;
2804 }
2805 break;
2806
2807 default: /*reserved*/
2808 RESERVED();
2809 break;
2810 }
2811 break;
2812
2813 default: /*reserved*/
2814 RESERVED();
2815 break;
2816 }
2817
2818 if (dc->is_jmp == DISAS_NEXT) {
2819 gen_check_loop_end(dc, 0);
2820 }
2821 dc->pc = dc->next_pc;
2822
2823 return;
2824
2825 invalid_opcode:
2826 qemu_log("INVALID(pc = %08x)\n", dc->pc);
2827 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2828 #undef HAS_OPTION
2829 }
2830
2831 static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
2832 {
2833 CPUBreakpoint *bp;
2834
2835 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2836 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2837 if (bp->pc == dc->pc) {
2838 tcg_gen_movi_i32(cpu_pc, dc->pc);
2839 gen_exception(dc, EXCP_DEBUG);
2840 dc->is_jmp = DISAS_UPDATE;
2841 }
2842 }
2843 }
2844 }
2845
2846 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
2847 {
2848 unsigned i;
2849
2850 for (i = 0; i < dc->config->nibreak; ++i) {
2851 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2852 env->sregs[IBREAKA + i] == dc->pc) {
2853 gen_debug_exception(dc, DEBUGCAUSE_IB);
2854 break;
2855 }
2856 }
2857 }
2858
2859 static void gen_intermediate_code_internal(
2860 CPUXtensaState *env, TranslationBlock *tb, int search_pc)
2861 {
2862 DisasContext dc;
2863 int insn_count = 0;
2864 int j, lj = -1;
2865 uint16_t *gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
2866 int max_insns = tb->cflags & CF_COUNT_MASK;
2867 uint32_t pc_start = tb->pc;
2868 uint32_t next_page_start =
2869 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2870
2871 if (max_insns == 0) {
2872 max_insns = CF_COUNT_MASK;
2873 }
2874
2875 dc.config = env->config;
2876 dc.singlestep_enabled = env->singlestep_enabled;
2877 dc.tb = tb;
2878 dc.pc = pc_start;
2879 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2880 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
2881 dc.lbeg = env->sregs[LBEG];
2882 dc.lend = env->sregs[LEND];
2883 dc.is_jmp = DISAS_NEXT;
2884 dc.ccount_delta = 0;
2885 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
2886 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
2887 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
2888 XTENSA_TBFLAG_CPENABLE_SHIFT;
2889
2890 init_litbase(&dc);
2891 init_sar_tracker(&dc);
2892 reset_used_window(&dc);
2893 if (dc.icount) {
2894 dc.next_icount = tcg_temp_local_new_i32();
2895 }
2896
2897 gen_icount_start();
2898
2899 if (env->singlestep_enabled && env->exception_taken) {
2900 env->exception_taken = 0;
2901 tcg_gen_movi_i32(cpu_pc, dc.pc);
2902 gen_exception(&dc, EXCP_DEBUG);
2903 }
2904
2905 do {
2906 check_breakpoint(env, &dc);
2907
2908 if (search_pc) {
2909 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
2910 if (lj < j) {
2911 lj++;
2912 while (lj < j) {
2913 tcg_ctx.gen_opc_instr_start[lj++] = 0;
2914 }
2915 }
2916 tcg_ctx.gen_opc_pc[lj] = dc.pc;
2917 tcg_ctx.gen_opc_instr_start[lj] = 1;
2918 tcg_ctx.gen_opc_icount[lj] = insn_count;
2919 }
2920
2921 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
2922 tcg_gen_debug_insn_start(dc.pc);
2923 }
2924
2925 ++dc.ccount_delta;
2926
2927 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2928 gen_io_start();
2929 }
2930
2931 if (dc.icount) {
2932 int label = gen_new_label();
2933
2934 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
2935 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
2936 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
2937 if (dc.debug) {
2938 gen_debug_exception(&dc, DEBUGCAUSE_IC);
2939 }
2940 gen_set_label(label);
2941 }
2942
2943 if (dc.debug) {
2944 gen_ibreak_check(env, &dc);
2945 }
2946
2947 disas_xtensa_insn(env, &dc);
2948 ++insn_count;
2949 if (dc.icount) {
2950 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
2951 }
2952 if (env->singlestep_enabled) {
2953 tcg_gen_movi_i32(cpu_pc, dc.pc);
2954 gen_exception(&dc, EXCP_DEBUG);
2955 break;
2956 }
2957 } while (dc.is_jmp == DISAS_NEXT &&
2958 insn_count < max_insns &&
2959 dc.pc < next_page_start &&
2960 tcg_ctx.gen_opc_ptr < gen_opc_end);
2961
2962 reset_litbase(&dc);
2963 reset_sar_tracker(&dc);
2964 if (dc.icount) {
2965 tcg_temp_free(dc.next_icount);
2966 }
2967
2968 if (tb->cflags & CF_LAST_IO) {
2969 gen_io_end();
2970 }
2971
2972 if (dc.is_jmp == DISAS_NEXT) {
2973 gen_jumpi(&dc, dc.pc, 0);
2974 }
2975 gen_icount_end(tb, insn_count);
2976 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
2977
2978 if (!search_pc) {
2979 tb->size = dc.pc - pc_start;
2980 tb->icount = insn_count;
2981 }
2982 }
2983
2984 void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
2985 {
2986 gen_intermediate_code_internal(env, tb, 0);
2987 }
2988
2989 void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
2990 {
2991 gen_intermediate_code_internal(env, tb, 1);
2992 }
2993
2994 void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
2995 int flags)
2996 {
2997 int i, j;
2998
2999 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3000
3001 for (i = j = 0; i < 256; ++i) {
3002 if (sregnames[i]) {
3003 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
3004 (j++ % 4) == 3 ? '\n' : ' ');
3005 }
3006 }
3007
3008 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3009
3010 for (i = j = 0; i < 256; ++i) {
3011 if (uregnames[i]) {
3012 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
3013 (j++ % 4) == 3 ? '\n' : ' ');
3014 }
3015 }
3016
3017 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3018
3019 for (i = 0; i < 16; ++i) {
3020 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
3021 (i % 4) == 3 ? '\n' : ' ');
3022 }
3023
3024 cpu_fprintf(f, "\n");
3025
3026 for (i = 0; i < env->config->nareg; ++i) {
3027 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3028 (i % 4) == 3 ? '\n' : ' ');
3029 }
3030
3031 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3032 cpu_fprintf(f, "\n");
3033
3034 for (i = 0; i < 16; ++i) {
3035 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3036 float32_val(env->fregs[i]),
3037 *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
3038 }
3039 }
3040 }
3041
3042 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
3043 {
3044 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3045 }
QEmu