2 * USB UHCI controller emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "hw/usb/uhci-regs.h"
31 #include "hw/pci/pci.h"
32 #include "qemu/timer.h"
34 #include "sysemu/dma.h"
36 #include "qemu/main-loop.h"
38 #define FRAME_TIMER_FREQ 1000
40 #define FRAME_MAX_LOOPS 256
42 /* Must be large enough to handle 10 frame delay for initial isoc requests */
45 #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
50 TD_RESULT_STOP_FRAME
= 10,
53 TD_RESULT_ASYNC_START
,
57 typedef struct UHCIState UHCIState
;
58 typedef struct UHCIAsync UHCIAsync
;
59 typedef struct UHCIQueue UHCIQueue
;
60 typedef struct UHCIInfo UHCIInfo
;
61 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass
;
69 void (*realize
)(PCIDevice
*dev
, Error
**errp
);
73 struct UHCIPCIDeviceClass
{
74 PCIDeviceClass parent_class
;
79 * Pending async transaction.
80 * 'packet' must be the first field because completion
81 * handler does "(UHCIAsync *) pkt" cast.
86 uint8_t static_buf
[64]; /* 64 bytes is enough, except for isoc packets */
89 QTAILQ_ENTRY(UHCIAsync
) next
;
99 QTAILQ_ENTRY(UHCIQueue
) next
;
100 QTAILQ_HEAD(asyncs_head
, UHCIAsync
) asyncs
;
104 typedef struct UHCIPort
{
112 USBBus bus
; /* Note unused when we're a companion controller */
113 uint16_t cmd
; /* cmd register */
115 uint16_t intr
; /* interrupt enable register */
116 uint16_t frnum
; /* frame number */
117 uint32_t fl_base_addr
; /* frame list base address */
119 uint8_t status2
; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
121 QEMUTimer
*frame_timer
;
123 uint32_t frame_bytes
;
124 uint32_t frame_bandwidth
;
125 bool completions_only
;
126 UHCIPort ports
[NB_PORTS
];
128 /* Interrupts that should be raised at the end of the current frame. */
129 uint32_t pending_int_mask
;
132 QTAILQ_HEAD(, UHCIQueue
) queues
;
133 uint8_t num_ports_vmstate
;
141 typedef struct UHCI_TD
{
143 uint32_t ctrl
; /* see TD_CTRL_xxx */
148 typedef struct UHCI_QH
{
153 static void uhci_async_cancel(UHCIAsync
*async
);
154 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
);
155 static void uhci_resume(void *opaque
);
157 #define TYPE_UHCI "pci-uhci-usb"
158 #define UHCI(obj) OBJECT_CHECK(UHCIState, (obj), TYPE_UHCI)
160 static inline int32_t uhci_queue_token(UHCI_TD
*td
)
162 if ((td
->token
& (0xf << 15)) == 0) {
163 /* ctrl ep, cover ep and dev, not pid! */
164 return td
->token
& 0x7ff00;
166 /* covers ep, dev, pid -> identifies the endpoint */
167 return td
->token
& 0x7ffff;
171 static UHCIQueue
*uhci_queue_new(UHCIState
*s
, uint32_t qh_addr
, UHCI_TD
*td
,
176 queue
= g_new0(UHCIQueue
, 1);
178 queue
->qh_addr
= qh_addr
;
179 queue
->token
= uhci_queue_token(td
);
181 QTAILQ_INIT(&queue
->asyncs
);
182 QTAILQ_INSERT_HEAD(&s
->queues
, queue
, next
);
183 queue
->valid
= QH_VALID
;
184 trace_usb_uhci_queue_add(queue
->token
);
188 static void uhci_queue_free(UHCIQueue
*queue
, const char *reason
)
190 UHCIState
*s
= queue
->uhci
;
193 while (!QTAILQ_EMPTY(&queue
->asyncs
)) {
194 async
= QTAILQ_FIRST(&queue
->asyncs
);
195 uhci_async_cancel(async
);
197 usb_device_ep_stopped(queue
->ep
->dev
, queue
->ep
);
199 trace_usb_uhci_queue_del(queue
->token
, reason
);
200 QTAILQ_REMOVE(&s
->queues
, queue
, next
);
204 static UHCIQueue
*uhci_queue_find(UHCIState
*s
, UHCI_TD
*td
)
206 uint32_t token
= uhci_queue_token(td
);
209 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
210 if (queue
->token
== token
) {
217 static bool uhci_queue_verify(UHCIQueue
*queue
, uint32_t qh_addr
, UHCI_TD
*td
,
218 uint32_t td_addr
, bool queuing
)
220 UHCIAsync
*first
= QTAILQ_FIRST(&queue
->asyncs
);
221 uint32_t queue_token_addr
= (queue
->token
>> 8) & 0x7f;
223 return queue
->qh_addr
== qh_addr
&&
224 queue
->token
== uhci_queue_token(td
) &&
225 queue_token_addr
== queue
->ep
->dev
->addr
&&
226 (queuing
|| !(td
->ctrl
& TD_CTRL_ACTIVE
) || first
== NULL
||
227 first
->td_addr
== td_addr
);
230 static UHCIAsync
*uhci_async_alloc(UHCIQueue
*queue
, uint32_t td_addr
)
232 UHCIAsync
*async
= g_new0(UHCIAsync
, 1);
234 async
->queue
= queue
;
235 async
->td_addr
= td_addr
;
236 usb_packet_init(&async
->packet
);
237 trace_usb_uhci_packet_add(async
->queue
->token
, async
->td_addr
);
242 static void uhci_async_free(UHCIAsync
*async
)
244 trace_usb_uhci_packet_del(async
->queue
->token
, async
->td_addr
);
245 usb_packet_cleanup(&async
->packet
);
246 if (async
->buf
!= async
->static_buf
) {
252 static void uhci_async_link(UHCIAsync
*async
)
254 UHCIQueue
*queue
= async
->queue
;
255 QTAILQ_INSERT_TAIL(&queue
->asyncs
, async
, next
);
256 trace_usb_uhci_packet_link_async(async
->queue
->token
, async
->td_addr
);
259 static void uhci_async_unlink(UHCIAsync
*async
)
261 UHCIQueue
*queue
= async
->queue
;
262 QTAILQ_REMOVE(&queue
->asyncs
, async
, next
);
263 trace_usb_uhci_packet_unlink_async(async
->queue
->token
, async
->td_addr
);
266 static void uhci_async_cancel(UHCIAsync
*async
)
268 uhci_async_unlink(async
);
269 trace_usb_uhci_packet_cancel(async
->queue
->token
, async
->td_addr
,
272 usb_cancel_packet(&async
->packet
);
273 uhci_async_free(async
);
277 * Mark all outstanding async packets as invalid.
278 * This is used for canceling them when TDs are removed by the HCD.
280 static void uhci_async_validate_begin(UHCIState
*s
)
284 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
290 * Cancel async packets that are no longer valid
292 static void uhci_async_validate_end(UHCIState
*s
)
294 UHCIQueue
*queue
, *n
;
296 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
298 uhci_queue_free(queue
, "validate-end");
303 static void uhci_async_cancel_device(UHCIState
*s
, USBDevice
*dev
)
305 UHCIQueue
*queue
, *n
;
307 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
308 if (queue
->ep
->dev
== dev
) {
309 uhci_queue_free(queue
, "cancel-device");
314 static void uhci_async_cancel_all(UHCIState
*s
)
316 UHCIQueue
*queue
, *nq
;
318 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, nq
) {
319 uhci_queue_free(queue
, "cancel-all");
323 static UHCIAsync
*uhci_async_find_td(UHCIState
*s
, uint32_t td_addr
)
328 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
329 QTAILQ_FOREACH(async
, &queue
->asyncs
, next
) {
330 if (async
->td_addr
== td_addr
) {
338 static void uhci_update_irq(UHCIState
*s
)
341 if (((s
->status2
& 1) && (s
->intr
& (1 << 2))) ||
342 ((s
->status2
& 2) && (s
->intr
& (1 << 3))) ||
343 ((s
->status
& UHCI_STS_USBERR
) && (s
->intr
& (1 << 0))) ||
344 ((s
->status
& UHCI_STS_RD
) && (s
->intr
& (1 << 1))) ||
345 (s
->status
& UHCI_STS_HSERR
) ||
346 (s
->status
& UHCI_STS_HCPERR
)) {
351 pci_set_irq(&s
->dev
, level
);
354 static void uhci_reset(DeviceState
*dev
)
356 PCIDevice
*d
= PCI_DEVICE(dev
);
357 UHCIState
*s
= UHCI(d
);
362 trace_usb_uhci_reset();
364 pci_conf
= s
->dev
.config
;
366 pci_conf
[0x6a] = 0x01; /* usb clock */
367 pci_conf
[0x6b] = 0x00;
369 s
->status
= UHCI_STS_HCHALTED
;
375 for(i
= 0; i
< NB_PORTS
; i
++) {
378 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
379 usb_port_reset(&port
->port
);
383 uhci_async_cancel_all(s
);
384 qemu_bh_cancel(s
->bh
);
388 static const VMStateDescription vmstate_uhci_port
= {
391 .minimum_version_id
= 1,
392 .fields
= (VMStateField
[]) {
393 VMSTATE_UINT16(ctrl
, UHCIPort
),
394 VMSTATE_END_OF_LIST()
398 static int uhci_post_load(void *opaque
, int version_id
)
400 UHCIState
*s
= opaque
;
402 if (version_id
< 2) {
403 s
->expire_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
404 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
409 static const VMStateDescription vmstate_uhci
= {
412 .minimum_version_id
= 1,
413 .post_load
= uhci_post_load
,
414 .fields
= (VMStateField
[]) {
415 VMSTATE_PCI_DEVICE(dev
, UHCIState
),
416 VMSTATE_UINT8_EQUAL(num_ports_vmstate
, UHCIState
),
417 VMSTATE_STRUCT_ARRAY(ports
, UHCIState
, NB_PORTS
, 1,
418 vmstate_uhci_port
, UHCIPort
),
419 VMSTATE_UINT16(cmd
, UHCIState
),
420 VMSTATE_UINT16(status
, UHCIState
),
421 VMSTATE_UINT16(intr
, UHCIState
),
422 VMSTATE_UINT16(frnum
, UHCIState
),
423 VMSTATE_UINT32(fl_base_addr
, UHCIState
),
424 VMSTATE_UINT8(sof_timing
, UHCIState
),
425 VMSTATE_UINT8(status2
, UHCIState
),
426 VMSTATE_TIMER_PTR(frame_timer
, UHCIState
),
427 VMSTATE_INT64_V(expire_time
, UHCIState
, 2),
428 VMSTATE_UINT32_V(pending_int_mask
, UHCIState
, 3),
429 VMSTATE_END_OF_LIST()
433 static void uhci_port_write(void *opaque
, hwaddr addr
,
434 uint64_t val
, unsigned size
)
436 UHCIState
*s
= opaque
;
438 trace_usb_uhci_mmio_writew(addr
, val
);
442 if ((val
& UHCI_CMD_RS
) && !(s
->cmd
& UHCI_CMD_RS
)) {
443 /* start frame processing */
444 trace_usb_uhci_schedule_start();
445 s
->expire_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
446 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
447 timer_mod(s
->frame_timer
, s
->expire_time
);
448 s
->status
&= ~UHCI_STS_HCHALTED
;
449 } else if (!(val
& UHCI_CMD_RS
)) {
450 s
->status
|= UHCI_STS_HCHALTED
;
452 if (val
& UHCI_CMD_GRESET
) {
456 /* send reset on the USB bus */
457 for(i
= 0; i
< NB_PORTS
; i
++) {
459 usb_device_reset(port
->port
.dev
);
461 uhci_reset(DEVICE(s
));
464 if (val
& UHCI_CMD_HCRESET
) {
465 uhci_reset(DEVICE(s
));
469 if (val
& UHCI_CMD_EGSM
) {
470 if ((s
->ports
[0].ctrl
& UHCI_PORT_RD
) ||
471 (s
->ports
[1].ctrl
& UHCI_PORT_RD
)) {
478 /* XXX: the chip spec is not coherent, so we add a hidden
479 register to distinguish between IOC and SPD */
480 if (val
& UHCI_STS_USBINT
)
489 if (s
->status
& UHCI_STS_HCHALTED
)
490 s
->frnum
= val
& 0x7ff;
493 s
->fl_base_addr
&= 0xffff0000;
494 s
->fl_base_addr
|= val
& ~0xfff;
497 s
->fl_base_addr
&= 0x0000ffff;
498 s
->fl_base_addr
|= (val
<< 16);
501 s
->sof_timing
= val
& 0xff;
513 dev
= port
->port
.dev
;
514 if (dev
&& dev
->attached
) {
516 if ( (val
& UHCI_PORT_RESET
) &&
517 !(port
->ctrl
& UHCI_PORT_RESET
) ) {
518 usb_device_reset(dev
);
521 port
->ctrl
&= UHCI_PORT_READ_ONLY
;
522 /* enabled may only be set if a device is connected */
523 if (!(port
->ctrl
& UHCI_PORT_CCS
)) {
524 val
&= ~UHCI_PORT_EN
;
526 port
->ctrl
|= (val
& ~UHCI_PORT_READ_ONLY
);
527 /* some bits are reset when a '1' is written to them */
528 port
->ctrl
&= ~(val
& UHCI_PORT_WRITE_CLEAR
);
534 static uint64_t uhci_port_read(void *opaque
, hwaddr addr
, unsigned size
)
536 UHCIState
*s
= opaque
;
553 val
= s
->fl_base_addr
& 0xffff;
556 val
= (s
->fl_base_addr
>> 16) & 0xffff;
574 val
= 0xff7f; /* disabled port */
578 trace_usb_uhci_mmio_readw(addr
, val
);
583 /* signal resume if controller suspended */
584 static void uhci_resume (void *opaque
)
586 UHCIState
*s
= (UHCIState
*)opaque
;
591 if (s
->cmd
& UHCI_CMD_EGSM
) {
592 s
->cmd
|= UHCI_CMD_FGR
;
593 s
->status
|= UHCI_STS_RD
;
598 static void uhci_attach(USBPort
*port1
)
600 UHCIState
*s
= port1
->opaque
;
601 UHCIPort
*port
= &s
->ports
[port1
->index
];
603 /* set connect status */
604 port
->ctrl
|= UHCI_PORT_CCS
| UHCI_PORT_CSC
;
607 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
608 port
->ctrl
|= UHCI_PORT_LSDA
;
610 port
->ctrl
&= ~UHCI_PORT_LSDA
;
616 static void uhci_detach(USBPort
*port1
)
618 UHCIState
*s
= port1
->opaque
;
619 UHCIPort
*port
= &s
->ports
[port1
->index
];
621 uhci_async_cancel_device(s
, port1
->dev
);
623 /* set connect status */
624 if (port
->ctrl
& UHCI_PORT_CCS
) {
625 port
->ctrl
&= ~UHCI_PORT_CCS
;
626 port
->ctrl
|= UHCI_PORT_CSC
;
629 if (port
->ctrl
& UHCI_PORT_EN
) {
630 port
->ctrl
&= ~UHCI_PORT_EN
;
631 port
->ctrl
|= UHCI_PORT_ENC
;
637 static void uhci_child_detach(USBPort
*port1
, USBDevice
*child
)
639 UHCIState
*s
= port1
->opaque
;
641 uhci_async_cancel_device(s
, child
);
644 static void uhci_wakeup(USBPort
*port1
)
646 UHCIState
*s
= port1
->opaque
;
647 UHCIPort
*port
= &s
->ports
[port1
->index
];
649 if (port
->ctrl
& UHCI_PORT_SUSPEND
&& !(port
->ctrl
& UHCI_PORT_RD
)) {
650 port
->ctrl
|= UHCI_PORT_RD
;
655 static USBDevice
*uhci_find_device(UHCIState
*s
, uint8_t addr
)
660 for (i
= 0; i
< NB_PORTS
; i
++) {
661 UHCIPort
*port
= &s
->ports
[i
];
662 if (!(port
->ctrl
& UHCI_PORT_EN
)) {
665 dev
= usb_find_device(&port
->port
, addr
);
673 static void uhci_read_td(UHCIState
*s
, UHCI_TD
*td
, uint32_t link
)
675 pci_dma_read(&s
->dev
, link
& ~0xf, td
, sizeof(*td
));
676 le32_to_cpus(&td
->link
);
677 le32_to_cpus(&td
->ctrl
);
678 le32_to_cpus(&td
->token
);
679 le32_to_cpus(&td
->buffer
);
682 static int uhci_handle_td_error(UHCIState
*s
, UHCI_TD
*td
, uint32_t td_addr
,
683 int status
, uint32_t *int_mask
)
685 uint32_t queue_token
= uhci_queue_token(td
);
690 td
->ctrl
|= TD_CTRL_NAK
;
691 return TD_RESULT_NEXT_QH
;
694 td
->ctrl
|= TD_CTRL_STALL
;
695 trace_usb_uhci_packet_complete_stall(queue_token
, td_addr
);
696 ret
= TD_RESULT_NEXT_QH
;
700 td
->ctrl
|= TD_CTRL_BABBLE
| TD_CTRL_STALL
;
701 /* frame interrupted */
702 trace_usb_uhci_packet_complete_babble(queue_token
, td_addr
);
703 ret
= TD_RESULT_STOP_FRAME
;
706 case USB_RET_IOERROR
:
709 td
->ctrl
|= TD_CTRL_TIMEOUT
;
710 td
->ctrl
&= ~(3 << TD_CTRL_ERROR_SHIFT
);
711 trace_usb_uhci_packet_complete_error(queue_token
, td_addr
);
712 ret
= TD_RESULT_NEXT_QH
;
716 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
717 s
->status
|= UHCI_STS_USBERR
;
718 if (td
->ctrl
& TD_CTRL_IOC
) {
725 static int uhci_complete_td(UHCIState
*s
, UHCI_TD
*td
, UHCIAsync
*async
, uint32_t *int_mask
)
727 int len
= 0, max_len
;
730 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
731 pid
= td
->token
& 0xff;
733 if (td
->ctrl
& TD_CTRL_IOS
)
734 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
736 if (async
->packet
.status
!= USB_RET_SUCCESS
) {
737 return uhci_handle_td_error(s
, td
, async
->td_addr
,
738 async
->packet
.status
, int_mask
);
741 len
= async
->packet
.actual_length
;
742 td
->ctrl
= (td
->ctrl
& ~0x7ff) | ((len
- 1) & 0x7ff);
744 /* The NAK bit may have been set by a previous frame, so clear it
745 here. The docs are somewhat unclear, but win2k relies on this
747 td
->ctrl
&= ~(TD_CTRL_ACTIVE
| TD_CTRL_NAK
);
748 if (td
->ctrl
& TD_CTRL_IOC
)
751 if (pid
== USB_TOKEN_IN
) {
752 pci_dma_write(&s
->dev
, td
->buffer
, async
->buf
, len
);
753 if ((td
->ctrl
& TD_CTRL_SPD
) && len
< max_len
) {
755 /* short packet: do not update QH */
756 trace_usb_uhci_packet_complete_shortxfer(async
->queue
->token
,
758 return TD_RESULT_NEXT_QH
;
763 trace_usb_uhci_packet_complete_success(async
->queue
->token
,
765 return TD_RESULT_COMPLETE
;
768 static int uhci_handle_td(UHCIState
*s
, UHCIQueue
*q
, uint32_t qh_addr
,
769 UHCI_TD
*td
, uint32_t td_addr
, uint32_t *int_mask
)
773 bool queuing
= (q
!= NULL
);
774 uint8_t pid
= td
->token
& 0xff;
775 UHCIAsync
*async
= uhci_async_find_td(s
, td_addr
);
778 if (uhci_queue_verify(async
->queue
, qh_addr
, td
, td_addr
, queuing
)) {
779 assert(q
== NULL
|| q
== async
->queue
);
782 uhci_queue_free(async
->queue
, "guest re-used pending td");
788 q
= uhci_queue_find(s
, td
);
789 if (q
&& !uhci_queue_verify(q
, qh_addr
, td
, td_addr
, queuing
)) {
790 uhci_queue_free(q
, "guest re-used qh");
800 if (!(td
->ctrl
& TD_CTRL_ACTIVE
)) {
802 /* Guest marked a pending td non-active, cancel the queue */
803 uhci_queue_free(async
->queue
, "pending td non-active");
806 * ehci11d spec page 22: "Even if the Active bit in the TD is already
807 * cleared when the TD is fetched ... an IOC interrupt is generated"
809 if (td
->ctrl
& TD_CTRL_IOC
) {
812 return TD_RESULT_NEXT_QH
;
817 /* we are busy filling the queue, we are not prepared
818 to consume completed packages then, just leave them
820 return TD_RESULT_ASYNC_CONT
;
824 UHCIAsync
*last
= QTAILQ_LAST(&async
->queue
->asyncs
, asyncs_head
);
826 * While we are waiting for the current td to complete, the guest
827 * may have added more tds to the queue. Note we re-read the td
828 * rather then caching it, as we want to see guest made changes!
830 uhci_read_td(s
, &last_td
, last
->td_addr
);
831 uhci_queue_fill(async
->queue
, &last_td
);
833 return TD_RESULT_ASYNC_CONT
;
835 uhci_async_unlink(async
);
839 if (s
->completions_only
) {
840 return TD_RESULT_ASYNC_CONT
;
843 /* Allocate new packet */
845 USBDevice
*dev
= uhci_find_device(s
, (td
->token
>> 8) & 0x7f);
846 USBEndpoint
*ep
= usb_ep_get(dev
, pid
, (td
->token
>> 15) & 0xf);
849 return uhci_handle_td_error(s
, td
, td_addr
, USB_RET_NODEV
,
852 q
= uhci_queue_new(s
, qh_addr
, td
, ep
);
854 async
= uhci_async_alloc(q
, td_addr
);
856 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
857 spd
= (pid
== USB_TOKEN_IN
&& (td
->ctrl
& TD_CTRL_SPD
) != 0);
858 usb_packet_setup(&async
->packet
, pid
, q
->ep
, 0, td_addr
, spd
,
859 (td
->ctrl
& TD_CTRL_IOC
) != 0);
860 if (max_len
<= sizeof(async
->static_buf
)) {
861 async
->buf
= async
->static_buf
;
863 async
->buf
= g_malloc(max_len
);
865 usb_packet_addbuf(&async
->packet
, async
->buf
, max_len
);
869 case USB_TOKEN_SETUP
:
870 pci_dma_read(&s
->dev
, td
->buffer
, async
->buf
, max_len
);
871 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
872 if (async
->packet
.status
== USB_RET_SUCCESS
) {
873 async
->packet
.actual_length
= max_len
;
878 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
882 /* invalid pid : frame interrupted */
883 uhci_async_free(async
);
884 s
->status
|= UHCI_STS_HCPERR
;
886 return TD_RESULT_STOP_FRAME
;
889 if (async
->packet
.status
== USB_RET_ASYNC
) {
890 uhci_async_link(async
);
892 uhci_queue_fill(q
, td
);
894 return TD_RESULT_ASYNC_START
;
898 ret
= uhci_complete_td(s
, td
, async
, int_mask
);
899 uhci_async_free(async
);
903 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
)
905 UHCIAsync
*async
= container_of(packet
, UHCIAsync
, packet
);
906 UHCIState
*s
= async
->queue
->uhci
;
908 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
909 uhci_async_cancel(async
);
914 /* Force processing of this packet *now*, needed for migration */
915 s
->completions_only
= true;
916 qemu_bh_schedule(s
->bh
);
919 static int is_valid(uint32_t link
)
921 return (link
& 1) == 0;
924 static int is_qh(uint32_t link
)
926 return (link
& 2) != 0;
929 static int depth_first(uint32_t link
)
931 return (link
& 4) != 0;
934 /* QH DB used for detecting QH loops */
935 #define UHCI_MAX_QUEUES 128
937 uint32_t addr
[UHCI_MAX_QUEUES
];
941 static void qhdb_reset(QhDb
*db
)
946 /* Add QH to DB. Returns 1 if already present or DB is full. */
947 static int qhdb_insert(QhDb
*db
, uint32_t addr
)
950 for (i
= 0; i
< db
->count
; i
++)
951 if (db
->addr
[i
] == addr
)
954 if (db
->count
>= UHCI_MAX_QUEUES
)
957 db
->addr
[db
->count
++] = addr
;
961 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
)
963 uint32_t int_mask
= 0;
964 uint32_t plink
= td
->link
;
968 while (is_valid(plink
)) {
969 uhci_read_td(q
->uhci
, &ptd
, plink
);
970 if (!(ptd
.ctrl
& TD_CTRL_ACTIVE
)) {
973 if (uhci_queue_token(&ptd
) != q
->token
) {
976 trace_usb_uhci_td_queue(plink
& ~0xf, ptd
.ctrl
, ptd
.token
);
977 ret
= uhci_handle_td(q
->uhci
, q
, q
->qh_addr
, &ptd
, plink
, &int_mask
);
978 if (ret
== TD_RESULT_ASYNC_CONT
) {
981 assert(ret
== TD_RESULT_ASYNC_START
);
982 assert(int_mask
== 0);
985 usb_device_flush_ep_queue(q
->ep
->dev
, q
->ep
);
988 static void uhci_process_frame(UHCIState
*s
)
990 uint32_t frame_addr
, link
, old_td_ctrl
, val
, int_mask
;
991 uint32_t curr_qh
, td_count
= 0;
997 frame_addr
= s
->fl_base_addr
+ ((s
->frnum
& 0x3ff) << 2);
999 pci_dma_read(&s
->dev
, frame_addr
, &link
, 4);
1000 le32_to_cpus(&link
);
1007 for (cnt
= FRAME_MAX_LOOPS
; is_valid(link
) && cnt
; cnt
--) {
1008 if (!s
->completions_only
&& s
->frame_bytes
>= s
->frame_bandwidth
) {
1009 /* We've reached the usb 1.1 bandwidth, which is
1010 1280 bytes/frame, stop processing */
1011 trace_usb_uhci_frame_stop_bandwidth();
1016 trace_usb_uhci_qh_load(link
& ~0xf);
1018 if (qhdb_insert(&qhdb
, link
)) {
1020 * We're going in circles. Which is not a bug because
1021 * HCD is allowed to do that as part of the BW management.
1023 * Stop processing here if no transaction has been done
1024 * since we've been here last time.
1026 if (td_count
== 0) {
1027 trace_usb_uhci_frame_loop_stop_idle();
1030 trace_usb_uhci_frame_loop_continue();
1033 qhdb_insert(&qhdb
, link
);
1037 pci_dma_read(&s
->dev
, link
& ~0xf, &qh
, sizeof(qh
));
1038 le32_to_cpus(&qh
.link
);
1039 le32_to_cpus(&qh
.el_link
);
1041 if (!is_valid(qh
.el_link
)) {
1042 /* QH w/o elements */
1046 /* QH with elements */
1054 uhci_read_td(s
, &td
, link
);
1055 trace_usb_uhci_td_load(curr_qh
& ~0xf, link
& ~0xf, td
.ctrl
, td
.token
);
1057 old_td_ctrl
= td
.ctrl
;
1058 ret
= uhci_handle_td(s
, NULL
, curr_qh
, &td
, link
, &int_mask
);
1059 if (old_td_ctrl
!= td
.ctrl
) {
1060 /* update the status bits of the TD */
1061 val
= cpu_to_le32(td
.ctrl
);
1062 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
1066 case TD_RESULT_STOP_FRAME
: /* interrupted frame */
1069 case TD_RESULT_NEXT_QH
:
1070 case TD_RESULT_ASYNC_CONT
:
1071 trace_usb_uhci_td_nextqh(curr_qh
& ~0xf, link
& ~0xf);
1072 link
= curr_qh
? qh
.link
: td
.link
;
1075 case TD_RESULT_ASYNC_START
:
1076 trace_usb_uhci_td_async(curr_qh
& ~0xf, link
& ~0xf);
1077 link
= curr_qh
? qh
.link
: td
.link
;
1080 case TD_RESULT_COMPLETE
:
1081 trace_usb_uhci_td_complete(curr_qh
& ~0xf, link
& ~0xf);
1084 s
->frame_bytes
+= (td
.ctrl
& 0x7ff) + 1;
1087 /* update QH element link */
1089 val
= cpu_to_le32(qh
.el_link
);
1090 pci_dma_write(&s
->dev
, (curr_qh
& ~0xf) + 4, &val
, sizeof(val
));
1092 if (!depth_first(link
)) {
1093 /* done with this QH */
1101 assert(!"unknown return code");
1104 /* go to the next entry */
1108 s
->pending_int_mask
|= int_mask
;
1111 static void uhci_bh(void *opaque
)
1113 UHCIState
*s
= opaque
;
1114 uhci_process_frame(s
);
1117 static void uhci_frame_timer(void *opaque
)
1119 UHCIState
*s
= opaque
;
1120 uint64_t t_now
, t_last_run
;
1122 const uint64_t frame_t
= get_ticks_per_sec() / FRAME_TIMER_FREQ
;
1124 s
->completions_only
= false;
1125 qemu_bh_cancel(s
->bh
);
1127 if (!(s
->cmd
& UHCI_CMD_RS
)) {
1129 trace_usb_uhci_schedule_stop();
1130 timer_del(s
->frame_timer
);
1131 uhci_async_cancel_all(s
);
1132 /* set hchalted bit in status - UHCI11D 2.1.2 */
1133 s
->status
|= UHCI_STS_HCHALTED
;
1137 /* We still store expire_time in our state, for migration */
1138 t_last_run
= s
->expire_time
- frame_t
;
1139 t_now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1141 /* Process up to MAX_FRAMES_PER_TICK frames */
1142 frames
= (t_now
- t_last_run
) / frame_t
;
1143 if (frames
> s
->maxframes
) {
1144 int skipped
= frames
- s
->maxframes
;
1145 s
->expire_time
+= skipped
* frame_t
;
1146 s
->frnum
= (s
->frnum
+ skipped
) & 0x7ff;
1149 if (frames
> MAX_FRAMES_PER_TICK
) {
1150 frames
= MAX_FRAMES_PER_TICK
;
1153 for (i
= 0; i
< frames
; i
++) {
1155 trace_usb_uhci_frame_start(s
->frnum
);
1156 uhci_async_validate_begin(s
);
1157 uhci_process_frame(s
);
1158 uhci_async_validate_end(s
);
1159 /* The spec says frnum is the frame currently being processed, and
1160 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1161 s
->frnum
= (s
->frnum
+ 1) & 0x7ff;
1162 s
->expire_time
+= frame_t
;
1165 /* Complete the previous frame(s) */
1166 if (s
->pending_int_mask
) {
1167 s
->status2
|= s
->pending_int_mask
;
1168 s
->status
|= UHCI_STS_USBINT
;
1171 s
->pending_int_mask
= 0;
1173 timer_mod(s
->frame_timer
, t_now
+ frame_t
);
1176 static const MemoryRegionOps uhci_ioport_ops
= {
1177 .read
= uhci_port_read
,
1178 .write
= uhci_port_write
,
1179 .valid
.min_access_size
= 1,
1180 .valid
.max_access_size
= 4,
1181 .impl
.min_access_size
= 2,
1182 .impl
.max_access_size
= 2,
1183 .endianness
= DEVICE_LITTLE_ENDIAN
,
1186 static USBPortOps uhci_port_ops
= {
1187 .attach
= uhci_attach
,
1188 .detach
= uhci_detach
,
1189 .child_detach
= uhci_child_detach
,
1190 .wakeup
= uhci_wakeup
,
1191 .complete
= uhci_async_complete
,
1194 static USBBusOps uhci_bus_ops
= {
1197 static void usb_uhci_common_realize(PCIDevice
*dev
, Error
**errp
)
1200 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1201 UHCIPCIDeviceClass
*u
= container_of(pc
, UHCIPCIDeviceClass
, parent_class
);
1202 UHCIState
*s
= UHCI(dev
);
1203 uint8_t *pci_conf
= s
->dev
.config
;
1206 pci_conf
[PCI_CLASS_PROG
] = 0x00;
1207 /* TODO: reset value should be 0. */
1208 pci_conf
[USB_SBRN
] = USB_RELEASE_1
; // release number
1210 pci_config_set_interrupt_pin(pci_conf
, u
->info
.irq_pin
+ 1);
1213 USBPort
*ports
[NB_PORTS
];
1214 for(i
= 0; i
< NB_PORTS
; i
++) {
1215 ports
[i
] = &s
->ports
[i
].port
;
1217 usb_register_companion(s
->masterbus
, ports
, NB_PORTS
,
1218 s
->firstport
, s
, &uhci_port_ops
,
1219 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
,
1222 error_propagate(errp
, err
);
1226 usb_bus_new(&s
->bus
, sizeof(s
->bus
), &uhci_bus_ops
, DEVICE(dev
));
1227 for (i
= 0; i
< NB_PORTS
; i
++) {
1228 usb_register_port(&s
->bus
, &s
->ports
[i
].port
, s
, i
, &uhci_port_ops
,
1229 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1232 s
->bh
= qemu_bh_new(uhci_bh
, s
);
1233 s
->frame_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, uhci_frame_timer
, s
);
1234 s
->num_ports_vmstate
= NB_PORTS
;
1235 QTAILQ_INIT(&s
->queues
);
1237 memory_region_init_io(&s
->io_bar
, OBJECT(s
), &uhci_ioport_ops
, s
,
1240 /* Use region 4 for consistency with real hardware. BSD guests seem
1242 pci_register_bar(&s
->dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1245 static void usb_uhci_vt82c686b_realize(PCIDevice
*dev
, Error
**errp
)
1247 UHCIState
*s
= UHCI(dev
);
1248 uint8_t *pci_conf
= s
->dev
.config
;
1250 /* USB misc control 1/2 */
1251 pci_set_long(pci_conf
+ 0x40,0x00001000);
1253 pci_set_long(pci_conf
+ 0x80,0x00020001);
1254 /* USB legacy support */
1255 pci_set_long(pci_conf
+ 0xc0,0x00002000);
1257 usb_uhci_common_realize(dev
, errp
);
1260 static void usb_uhci_exit(PCIDevice
*dev
)
1262 UHCIState
*s
= UHCI(dev
);
1264 trace_usb_uhci_exit();
1266 if (s
->frame_timer
) {
1267 timer_del(s
->frame_timer
);
1268 timer_free(s
->frame_timer
);
1269 s
->frame_timer
= NULL
;
1273 qemu_bh_delete(s
->bh
);
1276 uhci_async_cancel_all(s
);
1278 if (!s
->masterbus
) {
1279 usb_bus_release(&s
->bus
);
1283 static Property uhci_properties_companion
[] = {
1284 DEFINE_PROP_STRING("masterbus", UHCIState
, masterbus
),
1285 DEFINE_PROP_UINT32("firstport", UHCIState
, firstport
, 0),
1286 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1287 DEFINE_PROP_UINT32("maxframes", UHCIState
, maxframes
, 128),
1288 DEFINE_PROP_END_OF_LIST(),
1290 static Property uhci_properties_standalone
[] = {
1291 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1292 DEFINE_PROP_UINT32("maxframes", UHCIState
, maxframes
, 128),
1293 DEFINE_PROP_END_OF_LIST(),
1296 static void uhci_class_init(ObjectClass
*klass
, void *data
)
1298 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1299 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1301 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1302 dc
->vmsd
= &vmstate_uhci
;
1303 dc
->reset
= uhci_reset
;
1304 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
1307 static const TypeInfo uhci_pci_type_info
= {
1309 .parent
= TYPE_PCI_DEVICE
,
1310 .instance_size
= sizeof(UHCIState
),
1311 .class_size
= sizeof(UHCIPCIDeviceClass
),
1313 .class_init
= uhci_class_init
,
1316 static void uhci_data_class_init(ObjectClass
*klass
, void *data
)
1318 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1319 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1320 UHCIPCIDeviceClass
*u
= container_of(k
, UHCIPCIDeviceClass
, parent_class
);
1321 UHCIInfo
*info
= data
;
1323 k
->realize
= info
->realize
? info
->realize
: usb_uhci_common_realize
;
1324 k
->exit
= info
->unplug
? usb_uhci_exit
: NULL
;
1325 k
->vendor_id
= info
->vendor_id
;
1326 k
->device_id
= info
->device_id
;
1327 k
->revision
= info
->revision
;
1328 if (!info
->unplug
) {
1329 /* uhci controllers in companion setups can't be hotplugged */
1330 dc
->hotpluggable
= false;
1331 dc
->props
= uhci_properties_companion
;
1333 dc
->props
= uhci_properties_standalone
;
1338 static UHCIInfo uhci_info
[] = {
1340 .name
= "piix3-usb-uhci",
1341 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1342 .device_id
= PCI_DEVICE_ID_INTEL_82371SB_2
,
1347 .name
= "piix4-usb-uhci",
1348 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1349 .device_id
= PCI_DEVICE_ID_INTEL_82371AB_2
,
1354 .name
= "vt82c686b-usb-uhci",
1355 .vendor_id
= PCI_VENDOR_ID_VIA
,
1356 .device_id
= PCI_DEVICE_ID_VIA_UHCI
,
1359 .realize
= usb_uhci_vt82c686b_realize
,
1362 .name
= "ich9-usb-uhci1", /* 00:1d.0 */
1363 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1364 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI1
,
1369 .name
= "ich9-usb-uhci2", /* 00:1d.1 */
1370 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1371 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI2
,
1376 .name
= "ich9-usb-uhci3", /* 00:1d.2 */
1377 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1378 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI3
,
1383 .name
= "ich9-usb-uhci4", /* 00:1a.0 */
1384 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1385 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI4
,
1390 .name
= "ich9-usb-uhci5", /* 00:1a.1 */
1391 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1392 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI5
,
1397 .name
= "ich9-usb-uhci6", /* 00:1a.2 */
1398 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1399 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI6
,
1406 static void uhci_register_types(void)
1408 TypeInfo uhci_type_info
= {
1409 .parent
= TYPE_UHCI
,
1410 .class_init
= uhci_data_class_init
,
1414 type_register_static(&uhci_pci_type_info
);
1416 for (i
= 0; i
< ARRAY_SIZE(uhci_info
); i
++) {
1417 uhci_type_info
.name
= uhci_info
[i
].name
;
1418 uhci_type_info
.class_data
= uhci_info
+ i
;
1419 type_register(&uhci_type_info
);
1423 type_init(uhci_register_types
)