4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #include "libqos/libqos-pc.h"
33 #include "libqos/ahci.h"
34 #include "libqos/pci-pc.h"
36 #include "qemu-common.h"
37 #include "qemu/host-utils.h"
39 #include "hw/pci/pci_ids.h"
40 #include "hw/pci/pci_regs.h"
42 /* Test-specific defines. */
43 #define TEST_IMAGE_SIZE (64 * 1024 * 1024)
46 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
47 static bool ahci_pedantic
;
49 /*** Function Declarations ***/
50 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
);
51 static void ahci_test_pci_spec(AHCIQState
*ahci
);
52 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
54 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
);
55 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
);
56 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
);
60 static void string_bswap16(uint16_t *s
, size_t bytes
)
62 g_assert_cmphex((bytes
& 1), ==, 0);
71 /*** Test Setup & Teardown ***/
74 * Start a Q35 machine and bookmark a handle to the AHCI device.
76 static AHCIQState
*ahci_boot(void)
81 s
= g_malloc0(sizeof(AHCIQState
));
83 cli
= "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
86 "-device ide-hd,drive=drive0 "
87 "-global ide-hd.ver=%s";
88 s
->parent
= qtest_pc_boot(cli
, tmp_path
, "testdisk", "version");
89 alloc_set_flags(s
->parent
->alloc
, ALLOC_LEAK_ASSERT
);
91 /* Verify that we have an AHCI device present. */
92 s
->dev
= get_ahci_device(&s
->fingerprint
);
98 * Clean up the PCI device, then terminate the QEMU instance.
100 static void ahci_shutdown(AHCIQState
*ahci
)
102 QOSState
*qs
= ahci
->parent
;
104 ahci_clean_mem(ahci
);
105 free_ahci_device(ahci
->dev
);
111 * Boot and fully enable the HBA device.
112 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
114 static AHCIQState
*ahci_boot_and_enable(void)
119 ahci_pci_enable(ahci
);
120 ahci_hba_enable(ahci
);
125 /*** Specification Adherence Tests ***/
128 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
130 static void ahci_test_pci_spec(AHCIQState
*ahci
)
136 /* Most of these bits should start cleared until we turn them on. */
137 data
= qpci_config_readw(ahci
->dev
, PCI_COMMAND
);
138 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MEMORY
);
139 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MASTER
);
140 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SPECIAL
); /* Reserved */
141 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_VGA_PALETTE
); /* Reserved */
142 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_PARITY
);
143 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_WAIT
); /* Reserved */
144 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SERR
);
145 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_FAST_BACK
);
146 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_INTX_DISABLE
);
147 ASSERT_BIT_CLEAR(data
, 0xF800); /* Reserved */
149 data
= qpci_config_readw(ahci
->dev
, PCI_STATUS
);
150 ASSERT_BIT_CLEAR(data
, 0x01 | 0x02 | 0x04); /* Reserved */
151 ASSERT_BIT_CLEAR(data
, PCI_STATUS_INTERRUPT
);
152 ASSERT_BIT_SET(data
, PCI_STATUS_CAP_LIST
); /* must be set */
153 ASSERT_BIT_CLEAR(data
, PCI_STATUS_UDF
); /* Reserved */
154 ASSERT_BIT_CLEAR(data
, PCI_STATUS_PARITY
);
155 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_TARGET_ABORT
);
156 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_TARGET_ABORT
);
157 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_MASTER_ABORT
);
158 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_SYSTEM_ERROR
);
159 ASSERT_BIT_CLEAR(data
, PCI_STATUS_DETECTED_PARITY
);
161 /* RID occupies the low byte, CCs occupy the high three. */
162 datal
= qpci_config_readl(ahci
->dev
, PCI_CLASS_REVISION
);
164 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
165 * Though in practice this is likely seldom true. */
166 ASSERT_BIT_CLEAR(datal
, 0xFF);
169 /* BCC *must* equal 0x01. */
170 g_assert_cmphex(PCI_BCC(datal
), ==, 0x01);
171 if (PCI_SCC(datal
) == 0x01) {
173 ASSERT_BIT_SET(0x80000000, datal
);
174 ASSERT_BIT_CLEAR(0x60000000, datal
);
175 } else if (PCI_SCC(datal
) == 0x04) {
177 g_assert_cmphex(PCI_PI(datal
), ==, 0);
178 } else if (PCI_SCC(datal
) == 0x06) {
180 g_assert_cmphex(PCI_PI(datal
), ==, 0x01);
182 g_assert_not_reached();
185 datab
= qpci_config_readb(ahci
->dev
, PCI_CACHE_LINE_SIZE
);
186 g_assert_cmphex(datab
, ==, 0);
188 datab
= qpci_config_readb(ahci
->dev
, PCI_LATENCY_TIMER
);
189 g_assert_cmphex(datab
, ==, 0);
191 /* Only the bottom 7 bits must be off. */
192 datab
= qpci_config_readb(ahci
->dev
, PCI_HEADER_TYPE
);
193 ASSERT_BIT_CLEAR(datab
, 0x7F);
195 /* BIST is optional, but the low 7 bits must always start off regardless. */
196 datab
= qpci_config_readb(ahci
->dev
, PCI_BIST
);
197 ASSERT_BIT_CLEAR(datab
, 0x7F);
199 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
200 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
201 g_assert_cmphex(datal
, ==, 0);
203 qpci_config_writel(ahci
->dev
, PCI_BASE_ADDRESS_5
, 0xFFFFFFFF);
204 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
205 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
206 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
207 ASSERT_BIT_CLEAR(datal
, 0xFF);
209 /* Capability list MUST be present, */
210 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
);
211 /* But these bits are reserved. */
212 ASSERT_BIT_CLEAR(datal
, ~0xFF);
213 g_assert_cmphex(datal
, !=, 0);
215 /* Check specification adherence for capability extenstions. */
216 data
= qpci_config_readw(ahci
->dev
, datal
);
218 switch (ahci
->fingerprint
) {
219 case AHCI_INTEL_ICH9
:
220 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
221 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_MSI
);
224 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
225 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_PM
);
228 ahci_test_pci_caps(ahci
, data
, (uint8_t)datal
);
231 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
+ 4);
232 g_assert_cmphex(datal
, ==, 0);
234 /* IPIN might vary, but ILINE must be off. */
235 datab
= qpci_config_readb(ahci
->dev
, PCI_INTERRUPT_LINE
);
236 g_assert_cmphex(datab
, ==, 0);
240 * Test PCI capabilities for AHCI specification adherence.
242 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
245 uint8_t cid
= header
& 0xFF;
246 uint8_t next
= header
>> 8;
248 g_test_message("CID: %02x; next: %02x", cid
, next
);
252 ahci_test_pmcap(ahci
, offset
);
255 ahci_test_msicap(ahci
, offset
);
257 case PCI_CAP_ID_SATA
:
258 ahci_test_satacap(ahci
, offset
);
262 g_test_message("Unknown CAP 0x%02x", cid
);
266 ahci_test_pci_caps(ahci
, qpci_config_readw(ahci
->dev
, next
), next
);
271 * Test SATA PCI capabilitity for AHCI specification adherence.
273 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
)
278 g_test_message("Verifying SATACAP");
280 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
281 dataw
= qpci_config_readw(ahci
->dev
, offset
+ 2);
282 g_assert_cmphex(dataw
, ==, 0x10);
284 /* Grab the SATACR1 register. */
285 datal
= qpci_config_readw(ahci
->dev
, offset
+ 4);
287 switch (datal
& 0x0F) {
288 case 0x04: /* BAR0 */
289 case 0x05: /* BAR1 */
293 case 0x09: /* BAR5 */
294 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
297 /* Invalid BARLOC for the Index Data Pair. */
298 g_assert_not_reached();
302 g_assert_cmphex((datal
>> 24), ==, 0x00);
306 * Test MSI PCI capability for AHCI specification adherence.
308 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
)
313 g_test_message("Verifying MSICAP");
315 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_FLAGS
);
316 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_ENABLE
);
317 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_QSIZE
);
318 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_RESERVED
);
320 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_LO
);
321 g_assert_cmphex(datal
, ==, 0);
323 if (dataw
& PCI_MSI_FLAGS_64BIT
) {
324 g_test_message("MSICAP is 64bit");
325 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_HI
);
326 g_assert_cmphex(datal
, ==, 0);
327 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_64
);
328 g_assert_cmphex(dataw
, ==, 0);
330 g_test_message("MSICAP is 32bit");
331 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_32
);
332 g_assert_cmphex(dataw
, ==, 0);
337 * Test Power Management PCI capability for AHCI specification adherence.
339 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
)
343 g_test_message("Verifying PMCAP");
345 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_PMC
);
346 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_PME_CLOCK
);
347 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_RESERVED
);
348 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D1
);
349 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D2
);
351 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_CTRL
);
352 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_STATE_MASK
);
353 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_RESERVED
);
354 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SEL_MASK
);
355 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SCALE_MASK
);
358 static void ahci_test_hba_spec(AHCIQState
*ahci
)
366 g_assert(ahci
!= NULL
);
369 * Note that the AHCI spec does expect the BIOS to set up a few things:
370 * CAP.SSS - Support for staggered spin-up (t/f)
371 * CAP.SMPS - Support for mechanical presence switches (t/f)
372 * PI - Ports Implemented (1-32)
373 * PxCMD.HPCP - Hot Plug Capable Port
374 * PxCMD.MPSP - Mechanical Presence Switch Present
375 * PxCMD.CPD - Cold Presence Detection support
377 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
378 * Foreach Port Implemented:
379 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
380 * -PxCLB/U and PxFB/U are set to valid regions in memory
381 * -PxSUD is set to 1.
382 * -PxSSTS.DET is polled for presence; if detected, we continue:
383 * -PxSERR is cleared with 1's.
384 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
385 * the device is ready.
388 /* 1 CAP - Capabilities Register */
389 ahci
->cap
= ahci_rreg(ahci
, AHCI_CAP
);
390 ASSERT_BIT_CLEAR(ahci
->cap
, AHCI_CAP_RESERVED
);
392 /* 2 GHC - Global Host Control */
393 reg
= ahci_rreg(ahci
, AHCI_GHC
);
394 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_HR
);
395 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_IE
);
396 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_MRSM
);
397 if (BITSET(ahci
->cap
, AHCI_CAP_SAM
)) {
398 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
399 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
401 g_test_message("Supports AHCI/Legacy mix.");
402 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_AE
);
405 /* 3 IS - Interrupt Status */
406 reg
= ahci_rreg(ahci
, AHCI_IS
);
407 g_assert_cmphex(reg
, ==, 0);
409 /* 4 PI - Ports Implemented */
410 ports
= ahci_rreg(ahci
, AHCI_PI
);
411 /* Ports Implemented must be non-zero. */
412 g_assert_cmphex(ports
, !=, 0);
413 /* Ports Implemented must be <= Number of Ports. */
414 nports_impl
= ctpopl(ports
);
415 g_assert_cmpuint(((AHCI_CAP_NP
& ahci
->cap
) + 1), >=, nports_impl
);
417 /* Ports must be within the proper range. Given a mapping of SIZE,
418 * 256 bytes are used for global HBA control, and the rest is used
419 * for ports data, at 0x80 bytes each. */
420 g_assert_cmphex(ahci
->barsize
, >, 0);
421 maxports
= (ahci
->barsize
- HBA_DATA_REGION_SIZE
) / HBA_PORT_DATA_SIZE
;
422 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
423 g_assert_cmphex((reg
>> maxports
), ==, 0);
426 reg
= ahci_rreg(ahci
, AHCI_VS
);
428 case AHCI_VERSION_0_95
:
429 case AHCI_VERSION_1_0
:
430 case AHCI_VERSION_1_1
:
431 case AHCI_VERSION_1_2
:
432 case AHCI_VERSION_1_3
:
435 g_assert_not_reached();
438 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
439 reg
= ahci_rreg(ahci
, AHCI_CCCCTL
);
440 if (BITSET(ahci
->cap
, AHCI_CAP_CCCS
)) {
441 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_EN
);
442 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_RESERVED
);
443 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_CC
);
444 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_TV
);
446 g_assert_cmphex(reg
, ==, 0);
450 reg
= ahci_rreg(ahci
, AHCI_CCCPORTS
);
451 /* Must be zeroes initially regardless of CAP.CCCS */
452 g_assert_cmphex(reg
, ==, 0);
455 reg
= ahci_rreg(ahci
, AHCI_EMLOC
);
456 if (BITCLR(ahci
->cap
, AHCI_CAP_EMS
)) {
457 g_assert_cmphex(reg
, ==, 0);
461 reg
= ahci_rreg(ahci
, AHCI_EMCTL
);
462 if (BITSET(ahci
->cap
, AHCI_CAP_EMS
)) {
463 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_STSMR
);
464 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLTM
);
465 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLRST
);
466 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_RESERVED
);
468 g_assert_cmphex(reg
, ==, 0);
471 /* 10 CAP2 -- Capabilities Extended */
472 ahci
->cap2
= ahci_rreg(ahci
, AHCI_CAP2
);
473 ASSERT_BIT_CLEAR(ahci
->cap2
, AHCI_CAP2_RESERVED
);
475 /* 11 BOHC -- Bios/OS Handoff Control */
476 reg
= ahci_rreg(ahci
, AHCI_BOHC
);
477 g_assert_cmphex(reg
, ==, 0);
479 /* 12 -- 23: Reserved */
480 g_test_message("Verifying HBA reserved area is empty.");
481 for (i
= AHCI_RESERVED
; i
< AHCI_NVMHCI
; ++i
) {
482 reg
= ahci_rreg(ahci
, i
);
483 g_assert_cmphex(reg
, ==, 0);
486 /* 24 -- 39: NVMHCI */
487 if (BITCLR(ahci
->cap2
, AHCI_CAP2_NVMP
)) {
488 g_test_message("Verifying HBA/NVMHCI area is empty.");
489 for (i
= AHCI_NVMHCI
; i
< AHCI_VENDOR
; ++i
) {
490 reg
= ahci_rreg(ahci
, i
);
491 g_assert_cmphex(reg
, ==, 0);
495 /* 40 -- 63: Vendor */
496 g_test_message("Verifying HBA/Vendor area is empty.");
497 for (i
= AHCI_VENDOR
; i
< AHCI_PORTS
; ++i
) {
498 reg
= ahci_rreg(ahci
, i
);
499 g_assert_cmphex(reg
, ==, 0);
502 /* 64 -- XX: Port Space */
503 for (i
= 0; ports
|| (i
< maxports
); ports
>>= 1, ++i
) {
504 if (BITSET(ports
, 0x1)) {
505 g_test_message("Testing port %u for spec", i
);
506 ahci_test_port_spec(ahci
, i
);
509 uint16_t low
= AHCI_PORTS
+ (32 * i
);
510 uint16_t high
= AHCI_PORTS
+ (32 * (i
+ 1));
511 g_test_message("Asserting unimplemented port %u "
512 "(reg [%u-%u]) is empty.",
514 for (j
= low
; j
< high
; ++j
) {
515 reg
= ahci_rreg(ahci
, j
);
516 g_assert_cmphex(reg
, ==, 0);
523 * Test the memory space for one port for specification adherence.
525 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
)
531 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLB
);
532 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CLB_RESERVED
);
535 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
536 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLBU
);
537 g_assert_cmphex(reg
, ==, 0);
541 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FB
);
542 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FB_RESERVED
);
545 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
546 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBU
);
547 g_assert_cmphex(reg
, ==, 0);
551 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
552 g_assert_cmphex(reg
, ==, 0);
555 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IE
);
556 g_assert_cmphex(reg
, ==, 0);
559 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CMD
);
560 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FRE
);
561 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_RESERVED
);
562 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CCS
);
563 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
564 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
565 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_PMA
); /* And RW only if CAP.SPM */
566 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_APSTE
); /* RW only if CAP2.APST */
567 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ATAPI
);
568 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_DLAE
);
569 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ALPE
); /* RW only if CAP.SALP */
570 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ASP
); /* RW only if CAP.SALP */
571 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ICC
);
572 /* If CPDetect support does not exist, CPState must be off. */
573 if (BITCLR(reg
, AHCI_PX_CMD_CPD
)) {
574 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CPS
);
576 /* If MPSPresence is not set, MPSState must be off. */
577 if (BITCLR(reg
, AHCI_PX_CMD_MPSP
)) {
578 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
580 /* If we do not support MPS, MPSS and MPSP must be off. */
581 if (BITCLR(ahci
->cap
, AHCI_CAP_SMPS
)) {
582 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
583 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSP
);
585 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
586 if (BITANY(reg
, AHCI_PX_CMD_CPD
|| AHCI_PX_CMD_MPSP
)) {
587 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_HPCP
);
589 /* HPCP and ESP cannot both be active. */
590 g_assert(!BITSET(reg
, AHCI_PX_CMD_HPCP
| AHCI_PX_CMD_ESP
));
591 /* If CAP.FBSS is not set, FBSCP must not be set. */
592 if (BITCLR(ahci
->cap
, AHCI_CAP_FBSS
)) {
593 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FBSCP
);
597 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_RES1
);
598 g_assert_cmphex(reg
, ==, 0);
601 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
602 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
603 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
604 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_ERR
);
605 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS1
);
606 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_DRQ
);
607 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS2
);
608 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
609 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
610 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_RESERVED
);
613 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
614 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
615 * D2H register FIS and update the signature asynchronously,
616 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
618 /* (10) SSTS / SCR0: SStatus */
619 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SSTS
);
620 ASSERT_BIT_CLEAR(reg
, AHCI_PX_SSTS_RESERVED
);
621 /* Even though the register should be 0 at boot, it is asynchronous and
622 * prone to change, so we cannot test any well known value. */
624 /* (11) SCTL / SCR2: SControl */
625 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SCTL
);
626 g_assert_cmphex(reg
, ==, 0);
628 /* (12) SERR / SCR1: SError */
629 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SERR
);
630 g_assert_cmphex(reg
, ==, 0);
632 /* (13) SACT / SCR3: SActive */
633 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SACT
);
634 g_assert_cmphex(reg
, ==, 0);
637 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CI
);
638 g_assert_cmphex(reg
, ==, 0);
641 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SNTF
);
642 g_assert_cmphex(reg
, ==, 0);
645 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBS
);
646 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_EN
);
647 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEC
);
648 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_SDE
);
649 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEV
);
650 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DWE
);
651 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_RESERVED
);
652 if (BITSET(ahci
->cap
, AHCI_CAP_FBSS
)) {
653 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
654 g_assert((reg
& AHCI_PX_FBS_ADO
) >> ctzl(AHCI_PX_FBS_ADO
) >= 2);
657 /* [17 -- 27] RESERVED */
658 for (i
= AHCI_PX_RES2
; i
< AHCI_PX_VS
; ++i
) {
659 reg
= ahci_px_rreg(ahci
, port
, i
);
660 g_assert_cmphex(reg
, ==, 0);
663 /* [28 -- 31] Vendor-Specific */
664 for (i
= AHCI_PX_VS
; i
< 32; ++i
) {
665 reg
= ahci_px_rreg(ahci
, port
, i
);
667 g_test_message("INFO: Vendor register %u non-empty", i
);
673 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
674 * device we see, then read and check the response.
676 static void ahci_test_identify(AHCIQState
*ahci
)
682 const size_t buffsize
= 512;
684 g_assert(ahci
!= NULL
);
687 * This serves as a bit of a tutorial on AHCI device programming:
689 * (1) Create a data buffer for the IDENTIFY response to be sent to
690 * (2) Create a Command Table buffer, where we will store the
691 * command and PRDT (Physical Region Descriptor Table)
692 * (3) Construct an FIS host-to-device command structure, and write it to
693 * the top of the Command Table buffer.
694 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
695 * a location in memory where data may be stored/retrieved.
696 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
697 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
698 * header that points to a Command Table buffer. Pick an unused slot
699 * and update it to point to the Command Table we have built.
700 * (7) Now: Command #n points to our Command Table, and our Command Table
701 * contains the FIS (that describes our command) and the PRDTL, which
702 * describes our buffer.
703 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
704 * #n is ready for processing.
707 /* Pick the first implemented and running port */
708 px
= ahci_port_select(ahci
);
709 g_test_message("Selected port %u for test", px
);
711 /* Clear out the FIS Receive area and any pending interrupts. */
712 ahci_port_clear(ahci
, px
);
714 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
715 ahci_io(ahci
, px
, CMD_IDENTIFY
, &buff
, buffsize
);
717 /* Check serial number/version in the buffer */
718 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
719 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
720 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
721 * as a consequence, only needs to unchunk the data on LE machines. */
722 string_bswap16(&buff
[10], 20);
723 rc
= memcmp(&buff
[10], "testdisk ", 20);
724 g_assert_cmphex(rc
, ==, 0);
726 string_bswap16(&buff
[23], 8);
727 rc
= memcmp(&buff
[23], "version ", 8);
728 g_assert_cmphex(rc
, ==, 0);
730 sect_size
= le16_to_cpu(*((uint16_t *)(&buff
[5])));
731 g_assert_cmphex(sect_size
, ==, 0x200);
734 static void ahci_test_io_rw_simple(AHCIQState
*ahci
, unsigned bufsize
,
735 uint8_t read_cmd
, uint8_t write_cmd
)
740 unsigned char *tx
= g_malloc(bufsize
);
741 unsigned char *rx
= g_malloc0(bufsize
);
743 g_assert(ahci
!= NULL
);
745 /* Pick the first running port and clear it. */
746 port
= ahci_port_select(ahci
);
747 ahci_port_clear(ahci
, port
);
749 /*** Create pattern and transfer to guest ***/
750 /* Data buffer in the guest */
751 ptr
= ahci_alloc(ahci
, bufsize
);
754 /* Write some indicative pattern to our buffer. */
755 for (i
= 0; i
< bufsize
; i
++) {
756 tx
[i
] = (bufsize
- i
);
758 memwrite(ptr
, tx
, bufsize
);
760 /* Write this buffer to disk, then read it back to the DMA buffer. */
761 ahci_guest_io(ahci
, port
, write_cmd
, ptr
, bufsize
);
762 qmemset(ptr
, 0x00, bufsize
);
763 ahci_guest_io(ahci
, port
, read_cmd
, ptr
, bufsize
);
765 /*** Read back the Data ***/
766 memread(ptr
, rx
, bufsize
);
767 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
769 ahci_free(ahci
, ptr
);
774 /******************************************************************************/
775 /* Test Interfaces */
776 /******************************************************************************/
779 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
781 static void test_sanity(void)
789 * Ensure that the PCI configuration space for the AHCI device is in-line with
790 * the AHCI 1.3 specification for initial values.
792 static void test_pci_spec(void)
796 ahci_test_pci_spec(ahci
);
801 * Engage the PCI AHCI device and sanity check the response.
802 * Perform additional PCI config space bringup for the HBA.
804 static void test_pci_enable(void)
809 ahci_pci_enable(ahci
);
814 * Investigate the memory mapped regions of the HBA,
815 * and test them for AHCI specification adherence.
817 static void test_hba_spec(void)
822 ahci_pci_enable(ahci
);
823 ahci_test_hba_spec(ahci
);
828 * Engage the HBA functionality of the AHCI PCI device,
829 * and bring it into a functional idle state.
831 static void test_hba_enable(void)
836 ahci_pci_enable(ahci
);
837 ahci_hba_enable(ahci
);
842 * Bring up the device and issue an IDENTIFY command.
843 * Inspect the state of the HBA device and the data returned.
845 static void test_identify(void)
849 ahci
= ahci_boot_and_enable();
850 ahci_test_identify(ahci
);
855 * Fragmented DMA test: Perform a standard 4K DMA read/write
856 * test, but make sure the physical regions are fragmented to
857 * be very small, each just 32 bytes, to see how AHCI performs
858 * with chunks defined to be much less than a sector.
860 static void test_dma_fragmented(void)
865 size_t bufsize
= 4096;
866 unsigned char *tx
= g_malloc(bufsize
);
867 unsigned char *rx
= g_malloc0(bufsize
);
871 ahci
= ahci_boot_and_enable();
872 px
= ahci_port_select(ahci
);
873 ahci_port_clear(ahci
, px
);
876 for (i
= 0; i
< bufsize
; i
++) {
877 tx
[i
] = (bufsize
- i
);
880 /* Create a DMA buffer in guest memory, and write our pattern to it. */
881 ptr
= guest_alloc(ahci
->parent
->alloc
, bufsize
);
883 memwrite(ptr
, tx
, bufsize
);
885 cmd
= ahci_command_create(CMD_WRITE_DMA
);
886 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
887 ahci_command_commit(ahci
, cmd
, px
);
888 ahci_command_issue(ahci
, cmd
);
889 ahci_command_verify(ahci
, cmd
);
892 cmd
= ahci_command_create(CMD_READ_DMA
);
893 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
894 ahci_command_commit(ahci
, cmd
, px
);
895 ahci_command_issue(ahci
, cmd
);
896 ahci_command_verify(ahci
, cmd
);
899 /* Read back the guest's receive buffer into local memory */
900 memread(ptr
, rx
, bufsize
);
901 guest_free(ahci
->parent
->alloc
, ptr
);
903 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
911 /******************************************************************************/
912 /* AHCI I/O Test Matrix Definitions */
916 LEN_SIMPLE
= LEN_BEGIN
,
923 static const char *buff_len_str
[NUM_LENGTHS
] = { "simple", "double",
928 ADDR_MODE_LBA28
= ADDR_MODE_BEGIN
,
933 static const char *addr_mode_str
[NUM_ADDR_MODES
] = { "lba28", "lba48" };
937 MODE_PIO
= MODE_BEGIN
,
942 static const char *io_mode_str
[NUM_MODES
] = { "pio", "dma" };
951 typedef struct AHCIIOTestOptions
{
953 enum AddrMode address_type
;
958 * Table of possible I/O ATA commands given a set of enumerations.
960 static const uint8_t io_cmds
[NUM_MODES
][NUM_ADDR_MODES
][NUM_IO_OPS
] = {
962 [ADDR_MODE_LBA28
] = {
963 [IO_READ
] = CMD_READ_PIO
,
964 [IO_WRITE
] = CMD_WRITE_PIO
},
965 [ADDR_MODE_LBA48
] = {
966 [IO_READ
] = CMD_READ_PIO_EXT
,
967 [IO_WRITE
] = CMD_WRITE_PIO_EXT
}
970 [ADDR_MODE_LBA28
] = {
971 [IO_READ
] = CMD_READ_DMA
,
972 [IO_WRITE
] = CMD_WRITE_DMA
},
973 [ADDR_MODE_LBA48
] = {
974 [IO_READ
] = CMD_READ_DMA_EXT
,
975 [IO_WRITE
] = CMD_WRITE_DMA_EXT
}
980 * Test a Read/Write pattern using various commands, addressing modes,
981 * transfer modes, and buffer sizes.
983 static void test_io_rw_interface(enum AddrMode lba48
, enum IOMode dma
,
988 ahci
= ahci_boot_and_enable();
989 ahci_test_io_rw_simple(ahci
, bufsize
,
990 io_cmds
[dma
][lba48
][IO_READ
],
991 io_cmds
[dma
][lba48
][IO_WRITE
]);
996 * Demultiplex the test data and invoke the actual test routine.
998 static void test_io_interface(gconstpointer opaque
)
1000 AHCIIOTestOptions
*opts
= (AHCIIOTestOptions
*)opaque
;
1003 switch (opts
->length
) {
1011 bufsize
= 4096 * 64;
1017 g_assert_not_reached();
1020 test_io_rw_interface(opts
->address_type
, opts
->io_type
, bufsize
);
1025 static void create_ahci_io_test(enum IOMode type
, enum AddrMode addr
,
1028 static const char *arch
;
1030 AHCIIOTestOptions
*opts
= g_malloc(sizeof(AHCIIOTestOptions
));
1033 opts
->address_type
= addr
;
1034 opts
->io_type
= type
;
1037 arch
= qtest_get_arch();
1040 name
= g_strdup_printf("/%s/ahci/io/%s/%s/%s", arch
,
1042 addr_mode_str
[addr
],
1045 g_test_add_data_func(name
, opts
, test_io_interface
);
1049 /******************************************************************************/
1051 int main(int argc
, char **argv
)
1059 static struct option long_options
[] = {
1060 {"pedantic", no_argument
, 0, 'p' },
1064 /* Should be first to utilize g_test functionality, So we can see errors. */
1065 g_test_init(&argc
, &argv
, NULL
);
1068 c
= getopt_long(argc
, argv
, "", long_options
, NULL
);
1079 fprintf(stderr
, "Unrecognized ahci_test option.\n");
1080 g_assert_not_reached();
1084 /* Check architecture */
1085 arch
= qtest_get_arch();
1086 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
1087 g_test_message("Skipping test for non-x86");
1091 /* Create a temporary raw image */
1092 fd
= mkstemp(tmp_path
);
1094 ret
= ftruncate(fd
, TEST_IMAGE_SIZE
);
1099 qtest_add_func("/ahci/sanity", test_sanity
);
1100 qtest_add_func("/ahci/pci_spec", test_pci_spec
);
1101 qtest_add_func("/ahci/pci_enable", test_pci_enable
);
1102 qtest_add_func("/ahci/hba_spec", test_hba_spec
);
1103 qtest_add_func("/ahci/hba_enable", test_hba_enable
);
1104 qtest_add_func("/ahci/identify", test_identify
);
1106 for (i
= MODE_BEGIN
; i
< NUM_MODES
; i
++) {
1107 for (j
= ADDR_MODE_BEGIN
; j
< NUM_ADDR_MODES
; j
++) {
1108 for (k
= LEN_BEGIN
; k
< NUM_LENGTHS
; k
++) {
1109 create_ahci_io_test(i
, j
, k
);
1114 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented
);