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exec/memop: Adding signedness to quad definitions
[qemu.git] / include / tcg / tcg-op.h
blobcaa0a636125dea30c0e2e1873b3877cf11d74cd6
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef TCG_TCG_OP_H
26 #define TCG_TCG_OP_H
27
28 #include "tcg/tcg.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 /* Basic output routines. Not for general consumption. */
33
34 void tcg_gen_op1(TCGOpcode, TCGArg);
35 void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
36 void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
37 void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
38 void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
39 void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
40
41 void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
42 void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
43 void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
44
45 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
46 {
47 tcg_gen_op1(opc, tcgv_i32_arg(a1));
48 }
49
50 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
51 {
52 tcg_gen_op1(opc, tcgv_i64_arg(a1));
53 }
54
55 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
56 {
57 tcg_gen_op1(opc, a1);
58 }
59
60 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
61 {
62 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
63 }
64
65 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
66 {
67 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
68 }
69
70 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
71 {
72 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
73 }
74
75 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
76 {
77 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
78 }
79
80 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
81 {
82 tcg_gen_op2(opc, a1, a2);
83 }
84
85 static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
86 TCGv_i32 a2, TCGv_i32 a3)
87 {
88 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
89 }
90
91 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
92 TCGv_i64 a2, TCGv_i64 a3)
93 {
94 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
95 }
96
97 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
98 TCGv_i32 a2, TCGArg a3)
99 {
100 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
101 }
102
103 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
104 TCGv_i64 a2, TCGArg a3)
105 {
106 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
107 }
108
109 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
110 TCGv_ptr base, TCGArg offset)
111 {
112 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
113 }
114
115 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
116 TCGv_ptr base, TCGArg offset)
117 {
118 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
119 }
120
121 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
122 TCGv_i32 a3, TCGv_i32 a4)
123 {
124 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
125 tcgv_i32_arg(a3), tcgv_i32_arg(a4));
126 }
127
128 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
129 TCGv_i64 a3, TCGv_i64 a4)
130 {
131 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
132 tcgv_i64_arg(a3), tcgv_i64_arg(a4));
133 }
134
135 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
136 TCGv_i32 a3, TCGArg a4)
137 {
138 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
139 tcgv_i32_arg(a3), a4);
140 }
141
142 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
143 TCGv_i64 a3, TCGArg a4)
144 {
145 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
146 tcgv_i64_arg(a3), a4);
147 }
148
149 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
150 TCGArg a3, TCGArg a4)
151 {
152 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
153 }
154
155 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
156 TCGArg a3, TCGArg a4)
157 {
158 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
159 }
160
161 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
162 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
163 {
164 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
165 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
166 }
167
168 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
169 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
170 {
171 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
172 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
173 }
174
175 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
176 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
177 {
178 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
179 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
180 }
181
182 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
183 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
184 {
185 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
186 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
187 }
188
189 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
190 TCGv_i32 a3, TCGArg a4, TCGArg a5)
191 {
192 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
193 tcgv_i32_arg(a3), a4, a5);
194 }
195
196 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
197 TCGv_i64 a3, TCGArg a4, TCGArg a5)
198 {
199 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
200 tcgv_i64_arg(a3), a4, a5);
201 }
202
203 static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
204 TCGv_i32 a3, TCGv_i32 a4,
205 TCGv_i32 a5, TCGv_i32 a6)
206 {
207 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
208 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
209 tcgv_i32_arg(a6));
210 }
211
212 static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
213 TCGv_i64 a3, TCGv_i64 a4,
214 TCGv_i64 a5, TCGv_i64 a6)
215 {
216 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
217 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
218 tcgv_i64_arg(a6));
219 }
220
221 static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
222 TCGv_i32 a3, TCGv_i32 a4,
223 TCGv_i32 a5, TCGArg a6)
224 {
225 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
226 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
227 }
228
229 static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
230 TCGv_i64 a3, TCGv_i64 a4,
231 TCGv_i64 a5, TCGArg a6)
232 {
233 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
234 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
235 }
236
237 static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
238 TCGv_i32 a3, TCGv_i32 a4,
239 TCGArg a5, TCGArg a6)
240 {
241 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
242 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
243 }
244
245 static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
246 TCGv_i64 a3, TCGv_i64 a4,
247 TCGArg a5, TCGArg a6)
248 {
249 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
250 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
251 }
252
253
254 /* Generic ops. */
255
256 static inline void gen_set_label(TCGLabel *l)
257 {
258 l->present = 1;
259 tcg_gen_op1(INDEX_op_set_label, label_arg(l));
260 }
261
262 static inline void tcg_gen_br(TCGLabel *l)
263 {
264 l->refs++;
265 tcg_gen_op1(INDEX_op_br, label_arg(l));
266 }
267
268 void tcg_gen_mb(TCGBar);
269
270 /* Helper calls. */
271
272 /* 32 bit ops */
273
274 void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg);
275 void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
276 void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
277 void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
278 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
279 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
280 void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
281 void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
282 void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
283 void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
284 void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
285 void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286 void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287 void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
288 void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289 void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290 void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
291 void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
292 void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
293 void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
294 void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
295 void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
296 void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
297 void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
298 void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
299 void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
300 void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
301 void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
302 void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
303 void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
304 void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
305 unsigned int ofs, unsigned int len);
306 void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
307 unsigned int ofs, unsigned int len);
308 void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
309 unsigned int ofs, unsigned int len);
310 void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
311 unsigned int ofs, unsigned int len);
312 void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
313 unsigned int ofs);
314 void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
315 void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
316 void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
317 TCGv_i32 arg1, TCGv_i32 arg2);
318 void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
319 TCGv_i32 arg1, int32_t arg2);
320 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
321 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
322 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
323 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
324 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
325 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
326 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
327 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
328 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
329 void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
330 void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
331 void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
332 void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
333 void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags);
334 void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
335 void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
336 void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
337 void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
338 void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
339 void tcg_gen_abs_i32(TCGv_i32, TCGv_i32);
340
341 /* Replicate a value of size @vece from @in to all the lanes in @out */
342 void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in);
343
344 static inline void tcg_gen_discard_i32(TCGv_i32 arg)
345 {
346 tcg_gen_op1_i32(INDEX_op_discard, arg);
347 }
348
349 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
350 {
351 if (ret != arg) {
352 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
353 }
354 }
355
356 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
357 tcg_target_long offset)
358 {
359 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
360 }
361
362 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
363 tcg_target_long offset)
364 {
365 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
366 }
367
368 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
369 tcg_target_long offset)
370 {
371 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
372 }
373
374 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
375 tcg_target_long offset)
376 {
377 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
378 }
379
380 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
381 tcg_target_long offset)
382 {
383 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
384 }
385
386 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
387 tcg_target_long offset)
388 {
389 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
390 }
391
392 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
393 tcg_target_long offset)
394 {
395 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
396 }
397
398 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
399 tcg_target_long offset)
400 {
401 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
402 }
403
404 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
405 {
406 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
407 }
408
409 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
410 {
411 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
412 }
413
414 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
415 {
416 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
417 }
418
419 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
420 {
421 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
422 }
423
424 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
425 {
426 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
427 }
428
429 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
430 {
431 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
432 }
433
434 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
435 {
436 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
437 }
438
439 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
440 {
441 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
442 }
443
444 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
445 {
446 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
447 }
448
449 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
450 {
451 if (TCG_TARGET_HAS_neg_i32) {
452 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
453 } else {
454 tcg_gen_subfi_i32(ret, 0, arg);
455 }
456 }
457
458 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
459 {
460 if (TCG_TARGET_HAS_not_i32) {
461 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
462 } else {
463 tcg_gen_xori_i32(ret, arg, -1);
464 }
465 }
466
467 /* 64 bit ops */
468
469 void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
470 void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
471 void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
472 void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
473 void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474 void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
475 void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
476 void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
477 void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
478 void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
479 void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
480 void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
481 void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
482 void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
483 void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
484 void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
485 void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
486 void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
487 void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
488 void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
489 void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
490 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
491 void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
492 void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
493 void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
494 void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
495 void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
496 void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
497 void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
498 void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
499 void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
500 unsigned int ofs, unsigned int len);
501 void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
502 unsigned int ofs, unsigned int len);
503 void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
504 unsigned int ofs, unsigned int len);
505 void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
506 unsigned int ofs, unsigned int len);
507 void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
508 unsigned int ofs);
509 void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
510 void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
511 void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
512 TCGv_i64 arg1, TCGv_i64 arg2);
513 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
514 TCGv_i64 arg1, int64_t arg2);
515 void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
516 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
517 void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
518 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
519 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
520 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
521 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
522 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
523 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
524 void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
525 void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
526 void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
527 void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
528 void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
529 void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
530 void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
531 void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
532 void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
533 void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
534 void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
535 void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
536 void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
537 void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
538 void tcg_gen_abs_i64(TCGv_i64, TCGv_i64);
539
540 /* Replicate a value of size @vece from @in to all the lanes in @out */
541 void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in);
542
543 #if TCG_TARGET_REG_BITS == 64
544 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
545 {
546 tcg_gen_op1_i64(INDEX_op_discard, arg);
547 }
548
549 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
550 {
551 if (ret != arg) {
552 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
553 }
554 }
555
556 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
557 tcg_target_long offset)
558 {
559 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
560 }
561
562 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
563 tcg_target_long offset)
564 {
565 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
566 }
567
568 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
569 tcg_target_long offset)
570 {
571 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
572 }
573
574 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
575 tcg_target_long offset)
576 {
577 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
578 }
579
580 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
581 tcg_target_long offset)
582 {
583 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
584 }
585
586 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
587 tcg_target_long offset)
588 {
589 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
590 }
591
592 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
593 tcg_target_long offset)
594 {
595 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
596 }
597
598 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
599 tcg_target_long offset)
600 {
601 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
602 }
603
604 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
605 tcg_target_long offset)
606 {
607 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
608 }
609
610 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
611 tcg_target_long offset)
612 {
613 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
614 }
615
616 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
617 tcg_target_long offset)
618 {
619 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
620 }
621
622 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
623 {
624 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
625 }
626
627 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
628 {
629 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
630 }
631
632 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
633 {
634 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
635 }
636
637 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
638 {
639 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
640 }
641
642 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
643 {
644 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
645 }
646
647 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
648 {
649 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
650 }
651
652 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
653 {
654 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
655 }
656
657 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
658 {
659 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
660 }
661
662 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
663 {
664 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
665 }
666 #else /* TCG_TARGET_REG_BITS == 32 */
667 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
668 tcg_target_long offset)
669 {
670 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
671 }
672
673 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
674 tcg_target_long offset)
675 {
676 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
677 }
678
679 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
680 tcg_target_long offset)
681 {
682 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
683 }
684
685 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
686 {
687 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
688 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
689 }
690
691 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
692 {
693 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
694 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
695 }
696
697 void tcg_gen_discard_i64(TCGv_i64 arg);
698 void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
699 void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
700 void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
701 void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
702 void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
703 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
704 void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
705 void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
706 void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
707 void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
708 void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
709 void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
710 void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
711 void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
712 void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
713 void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
714 #endif /* TCG_TARGET_REG_BITS */
715
716 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
717 {
718 if (TCG_TARGET_HAS_neg_i64) {
719 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
720 } else {
721 tcg_gen_subfi_i64(ret, 0, arg);
722 }
723 }
724
725 /* Size changing operations. */
726
727 void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
728 void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
729 void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
730 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
731 void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
732 void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
733 void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
734
735 static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
736 {
737 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
738 }
739
740 /* QEMU specific operations. */
741
742 #ifndef TARGET_LONG_BITS
743 #error must include QEMU headers
744 #endif
745
746 #if TARGET_INSN_START_WORDS == 1
747 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
748 static inline void tcg_gen_insn_start(target_ulong pc)
749 {
750 tcg_gen_op1(INDEX_op_insn_start, pc);
751 }
752 # else
753 static inline void tcg_gen_insn_start(target_ulong pc)
754 {
755 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
756 }
757 # endif
758 #elif TARGET_INSN_START_WORDS == 2
759 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
760 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
761 {
762 tcg_gen_op2(INDEX_op_insn_start, pc, a1);
763 }
764 # else
765 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
766 {
767 tcg_gen_op4(INDEX_op_insn_start,
768 (uint32_t)pc, (uint32_t)(pc >> 32),
769 (uint32_t)a1, (uint32_t)(a1 >> 32));
770 }
771 # endif
772 #elif TARGET_INSN_START_WORDS == 3
773 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
774 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
775 target_ulong a2)
776 {
777 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
778 }
779 # else
780 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
781 target_ulong a2)
782 {
783 tcg_gen_op6(INDEX_op_insn_start,
784 (uint32_t)pc, (uint32_t)(pc >> 32),
785 (uint32_t)a1, (uint32_t)(a1 >> 32),
786 (uint32_t)a2, (uint32_t)(a2 >> 32));
787 }
788 # endif
789 #else
790 # error "Unhandled number of operands to insn_start"
791 #endif
792
793 /**
794 * tcg_gen_exit_tb() - output exit_tb TCG operation
795 * @tb: The TranslationBlock from which we are exiting
796 * @idx: Direct jump slot index, or exit request
797 *
798 * See tcg/README for more info about this TCG operation.
799 * See also tcg.h and the block comment above TB_EXIT_MASK.
800 *
801 * For a normal exit from the TB, back to the main loop, @tb should
802 * be NULL and @idx should be 0. Otherwise, @tb should be valid and
803 * @idx should be one of the TB_EXIT_ values.
804 */
805 void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx);
806
807 /**
808 * tcg_gen_goto_tb() - output goto_tb TCG operation
809 * @idx: Direct jump slot index (0 or 1)
810 *
811 * See tcg/README for more info about this TCG operation.
812 *
813 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
814 * the pages this TB resides in because we don't take care of direct jumps when
815 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
816 * static address translation, so the destination address is always valid, TBs
817 * are always invalidated properly, and direct jumps are reset when mapping
818 * changes.
819 */
820 void tcg_gen_goto_tb(unsigned idx);
821
822 /**
823 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
824 * @addr: Guest address of the target TB
825 *
826 * If the TB is not valid, jump to the epilogue.
827 *
828 * This operation is optional. If the TCG backend does not implement goto_ptr,
829 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
830 */
831 void tcg_gen_lookup_and_goto_ptr(void);
832
833 static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type,
834 unsigned wr)
835 {
836 tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr);
837 }
838
839 static inline void tcg_gen_plugin_cb_end(void)
840 {
841 tcg_emit_op(INDEX_op_plugin_cb_end);
842 }
843
844 #if TARGET_LONG_BITS == 32
845 #define tcg_temp_new() tcg_temp_new_i32()
846 #define tcg_global_mem_new tcg_global_mem_new_i32
847 #define tcg_temp_local_new() tcg_temp_local_new_i32()
848 #define tcg_temp_free tcg_temp_free_i32
849 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
850 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
851 #else
852 #define tcg_temp_new() tcg_temp_new_i64()
853 #define tcg_global_mem_new tcg_global_mem_new_i64
854 #define tcg_temp_local_new() tcg_temp_local_new_i64()
855 #define tcg_temp_free tcg_temp_free_i64
856 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
857 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
858 #endif
859
860 void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp);
861 void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp);
862 void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp);
863 void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp);
864
865 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
866 {
867 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
868 }
869
870 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
871 {
872 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
873 }
874
875 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
876 {
877 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
878 }
879
880 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
881 {
882 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
883 }
884
885 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
886 {
887 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
888 }
889
890 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
891 {
892 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
893 }
894
895 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
896 {
897 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEUQ);
898 }
899
900 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
901 {
902 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
903 }
904
905 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
906 {
907 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
908 }
909
910 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
911 {
912 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
913 }
914
915 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
916 {
917 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEUQ);
918 }
919
920 void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
921 TCGArg, MemOp);
922 void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
923 TCGArg, MemOp);
924
925 void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
926 void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
927
928 void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
929 void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
930 void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
931 void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
932 void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
933 void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
934 void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
935 void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
936 void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
937 void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
938 void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
939 void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
940 void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
941 void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
942 void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
943 void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
944
945 void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
946 void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
947 void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
948 void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
949 void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
950 void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
951 void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
952 void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
953 void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
954 void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
955 void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
956 void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
957 void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
958 void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
959 void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
960 void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
961
962 void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
963 void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
964 void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
965 void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long);
966 void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
967 void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
968 void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
969 void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
970 void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
971 void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
972 void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
973 void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
974 void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
975 void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
976 void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
977 void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
978 void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
979 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
980 void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
981 void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
982 void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
983 void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
984 void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
985 void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
986 void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
987 void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
988 void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
989
990 void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
991 void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
992 void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
993 void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
994 void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
995
996 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
997 void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
998 void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
999 void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
1000
1001 void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
1002 void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
1003 void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
1004 void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
1005 void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
1006
1007 void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
1008 TCGv_vec a, TCGv_vec b);
1009
1010 void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
1011 TCGv_vec b, TCGv_vec c);
1012 void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r,
1013 TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d);
1014
1015 void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
1016 void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
1017 void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
1018
1019 #if TARGET_LONG_BITS == 64
1020 #define tcg_gen_movi_tl tcg_gen_movi_i64
1021 #define tcg_gen_mov_tl tcg_gen_mov_i64
1022 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
1023 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1024 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1025 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1026 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1027 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1028 #define tcg_gen_ld_tl tcg_gen_ld_i64
1029 #define tcg_gen_st8_tl tcg_gen_st8_i64
1030 #define tcg_gen_st16_tl tcg_gen_st16_i64
1031 #define tcg_gen_st32_tl tcg_gen_st32_i64
1032 #define tcg_gen_st_tl tcg_gen_st_i64
1033 #define tcg_gen_add_tl tcg_gen_add_i64
1034 #define tcg_gen_addi_tl tcg_gen_addi_i64
1035 #define tcg_gen_sub_tl tcg_gen_sub_i64
1036 #define tcg_gen_neg_tl tcg_gen_neg_i64
1037 #define tcg_gen_abs_tl tcg_gen_abs_i64
1038 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
1039 #define tcg_gen_subi_tl tcg_gen_subi_i64
1040 #define tcg_gen_and_tl tcg_gen_and_i64
1041 #define tcg_gen_andi_tl tcg_gen_andi_i64
1042 #define tcg_gen_or_tl tcg_gen_or_i64
1043 #define tcg_gen_ori_tl tcg_gen_ori_i64
1044 #define tcg_gen_xor_tl tcg_gen_xor_i64
1045 #define tcg_gen_xori_tl tcg_gen_xori_i64
1046 #define tcg_gen_not_tl tcg_gen_not_i64
1047 #define tcg_gen_shl_tl tcg_gen_shl_i64
1048 #define tcg_gen_shli_tl tcg_gen_shli_i64
1049 #define tcg_gen_shr_tl tcg_gen_shr_i64
1050 #define tcg_gen_shri_tl tcg_gen_shri_i64
1051 #define tcg_gen_sar_tl tcg_gen_sar_i64
1052 #define tcg_gen_sari_tl tcg_gen_sari_i64
1053 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
1054 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
1055 #define tcg_gen_setcond_tl tcg_gen_setcond_i64
1056 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
1057 #define tcg_gen_mul_tl tcg_gen_mul_i64
1058 #define tcg_gen_muli_tl tcg_gen_muli_i64
1059 #define tcg_gen_div_tl tcg_gen_div_i64
1060 #define tcg_gen_rem_tl tcg_gen_rem_i64
1061 #define tcg_gen_divu_tl tcg_gen_divu_i64
1062 #define tcg_gen_remu_tl tcg_gen_remu_i64
1063 #define tcg_gen_discard_tl tcg_gen_discard_i64
1064 #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
1065 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1066 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1067 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1068 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1069 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
1070 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
1071 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
1072 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
1073 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
1074 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
1075 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
1076 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
1077 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
1078 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
1079 #define tcg_gen_bswap_tl tcg_gen_bswap64_i64
1080 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
1081 #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
1082 #define tcg_gen_andc_tl tcg_gen_andc_i64
1083 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
1084 #define tcg_gen_nand_tl tcg_gen_nand_i64
1085 #define tcg_gen_nor_tl tcg_gen_nor_i64
1086 #define tcg_gen_orc_tl tcg_gen_orc_i64
1087 #define tcg_gen_clz_tl tcg_gen_clz_i64
1088 #define tcg_gen_ctz_tl tcg_gen_ctz_i64
1089 #define tcg_gen_clzi_tl tcg_gen_clzi_i64
1090 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
1091 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
1092 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
1093 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
1094 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
1095 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
1096 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
1097 #define tcg_gen_deposit_tl tcg_gen_deposit_i64
1098 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
1099 #define tcg_gen_extract_tl tcg_gen_extract_i64
1100 #define tcg_gen_sextract_tl tcg_gen_sextract_i64
1101 #define tcg_gen_extract2_tl tcg_gen_extract2_i64
1102 #define tcg_const_tl tcg_const_i64
1103 #define tcg_constant_tl tcg_constant_i64
1104 #define tcg_const_local_tl tcg_const_local_i64
1105 #define tcg_gen_movcond_tl tcg_gen_movcond_i64
1106 #define tcg_gen_add2_tl tcg_gen_add2_i64
1107 #define tcg_gen_sub2_tl tcg_gen_sub2_i64
1108 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1109 #define tcg_gen_muls2_tl tcg_gen_muls2_i64
1110 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
1111 #define tcg_gen_smin_tl tcg_gen_smin_i64
1112 #define tcg_gen_umin_tl tcg_gen_umin_i64
1113 #define tcg_gen_smax_tl tcg_gen_smax_i64
1114 #define tcg_gen_umax_tl tcg_gen_umax_i64
1115 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1116 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1117 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1118 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1119 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1120 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
1121 #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64
1122 #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64
1123 #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64
1124 #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64
1125 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1126 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1127 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1128 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
1129 #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64
1130 #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64
1131 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64
1132 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64
1133 #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
1134 #define tcg_gen_dup_tl tcg_gen_dup_i64
1135 #else
1136 #define tcg_gen_movi_tl tcg_gen_movi_i32
1137 #define tcg_gen_mov_tl tcg_gen_mov_i32
1138 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1139 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1140 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1141 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1142 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
1143 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
1144 #define tcg_gen_ld_tl tcg_gen_ld_i32
1145 #define tcg_gen_st8_tl tcg_gen_st8_i32
1146 #define tcg_gen_st16_tl tcg_gen_st16_i32
1147 #define tcg_gen_st32_tl tcg_gen_st_i32
1148 #define tcg_gen_st_tl tcg_gen_st_i32
1149 #define tcg_gen_add_tl tcg_gen_add_i32
1150 #define tcg_gen_addi_tl tcg_gen_addi_i32
1151 #define tcg_gen_sub_tl tcg_gen_sub_i32
1152 #define tcg_gen_neg_tl tcg_gen_neg_i32
1153 #define tcg_gen_abs_tl tcg_gen_abs_i32
1154 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
1155 #define tcg_gen_subi_tl tcg_gen_subi_i32
1156 #define tcg_gen_and_tl tcg_gen_and_i32
1157 #define tcg_gen_andi_tl tcg_gen_andi_i32
1158 #define tcg_gen_or_tl tcg_gen_or_i32
1159 #define tcg_gen_ori_tl tcg_gen_ori_i32
1160 #define tcg_gen_xor_tl tcg_gen_xor_i32
1161 #define tcg_gen_xori_tl tcg_gen_xori_i32
1162 #define tcg_gen_not_tl tcg_gen_not_i32
1163 #define tcg_gen_shl_tl tcg_gen_shl_i32
1164 #define tcg_gen_shli_tl tcg_gen_shli_i32
1165 #define tcg_gen_shr_tl tcg_gen_shr_i32
1166 #define tcg_gen_shri_tl tcg_gen_shri_i32
1167 #define tcg_gen_sar_tl tcg_gen_sar_i32
1168 #define tcg_gen_sari_tl tcg_gen_sari_i32
1169 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
1170 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
1171 #define tcg_gen_setcond_tl tcg_gen_setcond_i32
1172 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
1173 #define tcg_gen_mul_tl tcg_gen_mul_i32
1174 #define tcg_gen_muli_tl tcg_gen_muli_i32
1175 #define tcg_gen_div_tl tcg_gen_div_i32
1176 #define tcg_gen_rem_tl tcg_gen_rem_i32
1177 #define tcg_gen_divu_tl tcg_gen_divu_i32
1178 #define tcg_gen_remu_tl tcg_gen_remu_i32
1179 #define tcg_gen_discard_tl tcg_gen_discard_i32
1180 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
1181 #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
1182 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1183 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1184 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1185 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
1186 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1187 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1188 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1189 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1190 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
1191 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
1192 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1193 #define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S)
1194 #define tcg_gen_bswap_tl tcg_gen_bswap32_i32
1195 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
1196 #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
1197 #define tcg_gen_andc_tl tcg_gen_andc_i32
1198 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
1199 #define tcg_gen_nand_tl tcg_gen_nand_i32
1200 #define tcg_gen_nor_tl tcg_gen_nor_i32
1201 #define tcg_gen_orc_tl tcg_gen_orc_i32
1202 #define tcg_gen_clz_tl tcg_gen_clz_i32
1203 #define tcg_gen_ctz_tl tcg_gen_ctz_i32
1204 #define tcg_gen_clzi_tl tcg_gen_clzi_i32
1205 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
1206 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
1207 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
1208 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
1209 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
1210 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
1211 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
1212 #define tcg_gen_deposit_tl tcg_gen_deposit_i32
1213 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
1214 #define tcg_gen_extract_tl tcg_gen_extract_i32
1215 #define tcg_gen_sextract_tl tcg_gen_sextract_i32
1216 #define tcg_gen_extract2_tl tcg_gen_extract2_i32
1217 #define tcg_const_tl tcg_const_i32
1218 #define tcg_constant_tl tcg_constant_i32
1219 #define tcg_const_local_tl tcg_const_local_i32
1220 #define tcg_gen_movcond_tl tcg_gen_movcond_i32
1221 #define tcg_gen_add2_tl tcg_gen_add2_i32
1222 #define tcg_gen_sub2_tl tcg_gen_sub2_i32
1223 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1224 #define tcg_gen_muls2_tl tcg_gen_muls2_i32
1225 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
1226 #define tcg_gen_smin_tl tcg_gen_smin_i32
1227 #define tcg_gen_umin_tl tcg_gen_umin_i32
1228 #define tcg_gen_smax_tl tcg_gen_smax_i32
1229 #define tcg_gen_umax_tl tcg_gen_umax_i32
1230 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1231 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1232 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1233 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1234 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1235 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
1236 #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32
1237 #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32
1238 #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32
1239 #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32
1240 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1241 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1242 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1243 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
1244 #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32
1245 #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32
1246 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32
1247 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32
1248 #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
1249 #define tcg_gen_dup_tl tcg_gen_dup_i32
1250 #endif
1251
1252 #if UINTPTR_MAX == UINT32_MAX
1253 # define PTR i32
1254 # define NAT TCGv_i32
1255 #else
1256 # define PTR i64
1257 # define NAT TCGv_i64
1258 #endif
1259
1260 static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1261 {
1262 glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
1263 }
1264
1265 static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1266 {
1267 glue(tcg_gen_st_, PTR)((NAT)r, a, o);
1268 }
1269
1270 static inline void tcg_gen_discard_ptr(TCGv_ptr a)
1271 {
1272 glue(tcg_gen_discard_,PTR)((NAT)a);
1273 }
1274
1275 static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
1276 {
1277 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
1278 }
1279
1280 static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
1281 {
1282 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
1283 }
1284
1285 static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
1286 intptr_t b, TCGLabel *label)
1287 {
1288 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
1289 }
1290
1291 static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
1292 {
1293 #if UINTPTR_MAX == UINT32_MAX
1294 tcg_gen_mov_i32((NAT)r, a);
1295 #else
1296 tcg_gen_ext_i32_i64((NAT)r, a);
1297 #endif
1298 }
1299
1300 static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
1301 {
1302 #if UINTPTR_MAX == UINT32_MAX
1303 tcg_gen_extrl_i64_i32((NAT)r, a);
1304 #else
1305 tcg_gen_mov_i64((NAT)r, a);
1306 #endif
1307 }
1308
1309 static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
1310 {
1311 #if UINTPTR_MAX == UINT32_MAX
1312 tcg_gen_extu_i32_i64(r, (NAT)a);
1313 #else
1314 tcg_gen_mov_i64(r, (NAT)a);
1315 #endif
1316 }
1317
1318 static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
1319 {
1320 #if UINTPTR_MAX == UINT32_MAX
1321 tcg_gen_mov_i32(r, (NAT)a);
1322 #else
1323 tcg_gen_extrl_i64_i32(r, (NAT)a);
1324 #endif
1325 }
1326
1327 #undef PTR
1328 #undef NAT
1329
1330 #endif /* TCG_TCG_OP_H */
QEmu