target/avr/helper.c

   1 /*
   2  * QEMU AVR CPU helpers
   3  *
   4  * Copyright (c) 2016-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "cpu.h"
  24 #include "hw/core/tcg-cpu-ops.h"
  25 #include "exec/exec-all.h"
  26 #include "exec/address-spaces.h"
  27 #include "exec/helper-proto.h"
  28
  29 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  30 {
  31     bool ret = false;
  32     CPUClass *cc = CPU_GET_CLASS(cs);
  33     AVRCPU *cpu = AVR_CPU(cs);
  34     CPUAVRState *env = &cpu->env;
  35
  36     if (interrupt_request & CPU_INTERRUPT_RESET) {
  37         if (cpu_interrupts_enabled(env)) {
  38             cs->exception_index = EXCP_RESET;
  39             cc->tcg_ops->do_interrupt(cs);
  40
  41             cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
  42
  43             ret = true;
  44         }
  45     }
  46     if (interrupt_request & CPU_INTERRUPT_HARD) {
  47         if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
  48             int index = ctz32(env->intsrc);
  49             cs->exception_index = EXCP_INT(index);
  50             cc->tcg_ops->do_interrupt(cs);
  51
  52             env->intsrc &= env->intsrc - 1; /* clear the interrupt */
  53             if (!env->intsrc) {
  54                 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
  55             }
  56
  57             ret = true;
  58         }
  59     }
  60     return ret;
  61 }
  62
  63 void avr_cpu_do_interrupt(CPUState *cs)
  64 {
  65     AVRCPU *cpu = AVR_CPU(cs);
  66     CPUAVRState *env = &cpu->env;
  67
  68     uint32_t ret = env->pc_w;
  69     int vector = 0;
  70     int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
  71     int base = 0;
  72
  73     if (cs->exception_index == EXCP_RESET) {
  74         vector = 0;
  75     } else if (env->intsrc != 0) {
  76         vector = ctz32(env->intsrc) + 1;
  77     }
  78
  79     if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
  80         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  81         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
  82         cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
  83     } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
  84         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  85         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
  86     } else {
  87         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  88     }
  89
  90     env->pc_w = base + vector * size;
  91     env->sregI = 0; /* clear Global Interrupt Flag */
  92
  93     cs->exception_index = -1;
  94 }
  95
  96 int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
  97                             int len, bool is_write)
  98 {
  99     return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
 100 }
 101
 102 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 103 {
 104     return addr; /* I assume 1:1 address correspondence */
 105 }
 106
 107 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 108                       MMUAccessType access_type, int mmu_idx,
 109                       bool probe, uintptr_t retaddr)
 110 {
 111     int prot = 0;
 112     MemTxAttrs attrs = {};
 113     uint32_t paddr;
 114
 115     address &= TARGET_PAGE_MASK;
 116
 117     if (mmu_idx == MMU_CODE_IDX) {
 118         /* access to code in flash */
 119         paddr = OFFSET_CODE + address;
 120         prot = PAGE_READ | PAGE_EXEC;
 121         if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
 122             error_report("execution left flash memory");
 123             abort();
 124         }
 125     } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 126         /*
 127          * access to CPU registers, exit and rebuilt this TB to use full access
 128          * incase it touches specially handled registers like SREG or SP
 129          */
 130         AVRCPU *cpu = AVR_CPU(cs);
 131         CPUAVRState *env = &cpu->env;
 132         env->fullacc = 1;
 133         cpu_loop_exit_restore(cs, retaddr);
 134     } else {
 135         /* access to memory. nothing special */
 136         paddr = OFFSET_DATA + address;
 137         prot = PAGE_READ | PAGE_WRITE;
 138     }
 139
 140     tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
 141                             mmu_idx, TARGET_PAGE_SIZE);
 142
 143     return true;
 144 }
 145
 146 /*
 147  *  helpers
 148  */
 149
 150 void helper_sleep(CPUAVRState *env)
 151 {
 152     CPUState *cs = env_cpu(env);
 153
 154     cs->exception_index = EXCP_HLT;
 155     cpu_loop_exit(cs);
 156 }
 157
 158 void helper_unsupported(CPUAVRState *env)
 159 {
 160     CPUState *cs = env_cpu(env);
 161
 162     /*
 163      *  I count not find what happens on the real platform, so
 164      *  it's EXCP_DEBUG for meanwhile
 165      */
 166     cs->exception_index = EXCP_DEBUG;
 167     if (qemu_loglevel_mask(LOG_UNIMP)) {
 168         qemu_log("UNSUPPORTED\n");
 169         cpu_dump_state(cs, stderr, 0);
 170     }
 171     cpu_loop_exit(cs);
 172 }
 173
 174 void helper_debug(CPUAVRState *env)
 175 {
 176     CPUState *cs = env_cpu(env);
 177
 178     cs->exception_index = EXCP_DEBUG;
 179     cpu_loop_exit(cs);
 180 }
 181
 182 void helper_break(CPUAVRState *env)
 183 {
 184     CPUState *cs = env_cpu(env);
 185
 186     cs->exception_index = EXCP_DEBUG;
 187     cpu_loop_exit(cs);
 188 }
 189
 190 void helper_wdr(CPUAVRState *env)
 191 {
 192     qemu_log_mask(LOG_UNIMP, "WDG reset (not implemented)\n");
 193 }
 194
 195 /*
 196  * This function implements IN instruction
 197  *
 198  * It does the following
 199  * a.  if an IO register belongs to CPU, its value is read and returned
 200  * b.  otherwise io address is translated to mem address and physical memory
 201  *     is read.
 202  * c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
 203  *
 204  */
 205 target_ulong helper_inb(CPUAVRState *env, uint32_t port)
 206 {
 207     target_ulong data = 0;
 208
 209     switch (port) {
 210     case 0x38: /* RAMPD */
 211         data = 0xff & (env->rampD >> 16);
 212         break;
 213     case 0x39: /* RAMPX */
 214         data = 0xff & (env->rampX >> 16);
 215         break;
 216     case 0x3a: /* RAMPY */
 217         data = 0xff & (env->rampY >> 16);
 218         break;
 219     case 0x3b: /* RAMPZ */
 220         data = 0xff & (env->rampZ >> 16);
 221         break;
 222     case 0x3c: /* EIND */
 223         data = 0xff & (env->eind >> 16);
 224         break;
 225     case 0x3d: /* SPL */
 226         data = env->sp & 0x00ff;
 227         break;
 228     case 0x3e: /* SPH */
 229         data = env->sp >> 8;
 230         break;
 231     case 0x3f: /* SREG */
 232         data = cpu_get_sreg(env);
 233         break;
 234     default:
 235         /* not a special register, pass to normal memory access */
 236         data = address_space_ldub(&address_space_memory,
 237                                   OFFSET_IO_REGISTERS + port,
 238                                   MEMTXATTRS_UNSPECIFIED, NULL);
 239     }
 240
 241     return data;
 242 }
 243
 244 /*
 245  *  This function implements OUT instruction
 246  *
 247  *  It does the following
 248  *  a.  if an IO register belongs to CPU, its value is written into the register
 249  *  b.  otherwise io address is translated to mem address and physical memory
 250  *      is written.
 251  *  c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
 252  *
 253  */
 254 void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
 255 {
 256     data &= 0x000000ff;
 257
 258     switch (port) {
 259     case 0x38: /* RAMPD */
 260         if (avr_feature(env, AVR_FEATURE_RAMPD)) {
 261             env->rampD = (data & 0xff) << 16;
 262         }
 263         break;
 264     case 0x39: /* RAMPX */
 265         if (avr_feature(env, AVR_FEATURE_RAMPX)) {
 266             env->rampX = (data & 0xff) << 16;
 267         }
 268         break;
 269     case 0x3a: /* RAMPY */
 270         if (avr_feature(env, AVR_FEATURE_RAMPY)) {
 271             env->rampY = (data & 0xff) << 16;
 272         }
 273         break;
 274     case 0x3b: /* RAMPZ */
 275         if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
 276             env->rampZ = (data & 0xff) << 16;
 277         }
 278         break;
 279     case 0x3c: /* EIDN */
 280         env->eind = (data & 0xff) << 16;
 281         break;
 282     case 0x3d: /* SPL */
 283         env->sp = (env->sp & 0xff00) | (data);
 284         break;
 285     case 0x3e: /* SPH */
 286         if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
 287             env->sp = (env->sp & 0x00ff) | (data << 8);
 288         }
 289         break;
 290     case 0x3f: /* SREG */
 291         cpu_set_sreg(env, data);
 292         break;
 293     default:
 294         /* not a special register, pass to normal memory access */
 295         address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port,
 296                           data, MEMTXATTRS_UNSPECIFIED, NULL);
 297     }
 298 }
 299
 300 /*
 301  *  this function implements LD instruction when there is a possibility to read
 302  *  from a CPU register
 303  */
 304 target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
 305 {
 306     uint8_t data;
 307
 308     env->fullacc = false;
 309
 310     if (addr < NUMBER_OF_CPU_REGISTERS) {
 311         /* CPU registers */
 312         data = env->r[addr];
 313     } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 314         /* IO registers */
 315         data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS);
 316     } else {
 317         /* memory */
 318         data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr,
 319                                   MEMTXATTRS_UNSPECIFIED, NULL);
 320     }
 321     return data;
 322 }
 323
 324 /*
 325  *  this function implements ST instruction when there is a possibility to write
 326  *  into a CPU register
 327  */
 328 void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
 329 {
 330     env->fullacc = false;
 331
 332     /* Following logic assumes this: */
 333     assert(OFFSET_CPU_REGISTERS == OFFSET_DATA);
 334     assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS +
 335                                   NUMBER_OF_CPU_REGISTERS);
 336
 337     if (addr < NUMBER_OF_CPU_REGISTERS) {
 338         /* CPU registers */
 339         env->r[addr] = data;
 340     } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 341         /* IO registers */
 342         helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data);
 343     } else {
 344         /* memory */
 345         address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
 346                           MEMTXATTRS_UNSPECIFIED, NULL);
 347     }
 348 }