tests/ahci-test.c

   1 /*
   2  * AHCI test cases
   3  *
   4  * Copyright (c) 2014 John Snow <jsnow@redhat.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <stdio.h>
  28 #include <getopt.h>
  29 #include <glib.h>
  30
  31 #include "libqtest.h"
  32 #include "libqos/libqos-pc.h"
  33 #include "libqos/ahci.h"
  34 #include "libqos/pci-pc.h"
  35
  36 #include "qemu-common.h"
  37 #include "qemu/host-utils.h"
  38
  39 #include "hw/pci/pci_ids.h"
  40 #include "hw/pci/pci_regs.h"
  41
  42 /* Test-specific defines. */
  43 #define TEST_IMAGE_SIZE    (64 * 1024 * 1024)
  44
  45 /*** Globals ***/
  46 static char tmp_path[] = "/tmp/qtest.XXXXXX";
  47 static bool ahci_pedantic;
  48
  49 /*** Function Declarations ***/
  50 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
  51 static void ahci_test_pci_spec(AHCIQState *ahci);
  52 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
  53                                uint8_t offset);
  54 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
  55 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
  56 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
  57
  58 /*** Utilities ***/
  59
  60 static void string_bswap16(uint16_t *s, size_t bytes)
  61 {
  62     g_assert_cmphex((bytes & 1), ==, 0);
  63     bytes /= 2;
  64
  65     while (bytes--) {
  66         *s = bswap16(*s);
  67         s++;
  68     }
  69 }
  70
  71 static void generate_pattern(void *buffer, size_t len, size_t cycle_len)
  72 {
  73     int i, j;
  74     unsigned char *tx = (unsigned char *)buffer;
  75     unsigned char p;
  76     size_t *sx;
  77
  78     /* Write an indicative pattern that varies and is unique per-cycle */
  79     p = rand() % 256;
  80     for (i = j = 0; i < len; i++, j++) {
  81         tx[i] = p;
  82         if (j % cycle_len == 0) {
  83             p = rand() % 256;
  84         }
  85     }
  86
  87     /* force uniqueness by writing an id per-cycle */
  88     for (i = 0; i < len / cycle_len; i++) {
  89         j = i * cycle_len;
  90         if (j + sizeof(*sx) <= len) {
  91             sx = (size_t *)&tx[j];
  92             *sx = i;
  93         }
  94     }
  95 }
  96
  97 /*** Test Setup & Teardown ***/
  98
  99 /**
 100  * Start a Q35 machine and bookmark a handle to the AHCI device.
 101  */
 102 static AHCIQState *ahci_boot(void)
 103 {
 104     AHCIQState *s;
 105     const char *cli;
 106
 107     s = g_malloc0(sizeof(AHCIQState));
 108
 109     cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
 110         ",format=raw"
 111         " -M q35 "
 112         "-device ide-hd,drive=drive0 "
 113         "-global ide-hd.ver=%s";
 114     s->parent = qtest_pc_boot(cli, tmp_path, "testdisk", "version");
 115     alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
 116
 117     /* Verify that we have an AHCI device present. */
 118     s->dev = get_ahci_device(&s->fingerprint);
 119
 120     return s;
 121 }
 122
 123 /**
 124  * Clean up the PCI device, then terminate the QEMU instance.
 125  */
 126 static void ahci_shutdown(AHCIQState *ahci)
 127 {
 128     QOSState *qs = ahci->parent;
 129
 130     ahci_clean_mem(ahci);
 131     free_ahci_device(ahci->dev);
 132     g_free(ahci);
 133     qtest_shutdown(qs);
 134 }
 135
 136 /**
 137  * Boot and fully enable the HBA device.
 138  * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
 139  */
 140 static AHCIQState *ahci_boot_and_enable(void)
 141 {
 142     AHCIQState *ahci;
 143     ahci = ahci_boot();
 144
 145     ahci_pci_enable(ahci);
 146     ahci_hba_enable(ahci);
 147
 148     return ahci;
 149 }
 150
 151 /*** Specification Adherence Tests ***/
 152
 153 /**
 154  * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
 155  */
 156 static void ahci_test_pci_spec(AHCIQState *ahci)
 157 {
 158     uint8_t datab;
 159     uint16_t data;
 160     uint32_t datal;
 161
 162     /* Most of these bits should start cleared until we turn them on. */
 163     data = qpci_config_readw(ahci->dev, PCI_COMMAND);
 164     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
 165     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
 166     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);     /* Reserved */
 167     ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
 168     ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
 169     ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);        /* Reserved */
 170     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
 171     ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
 172     ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
 173     ASSERT_BIT_CLEAR(data, 0xF800);                  /* Reserved */
 174
 175     data = qpci_config_readw(ahci->dev, PCI_STATUS);
 176     ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);     /* Reserved */
 177     ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
 178     ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);      /* must be set */
 179     ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);         /* Reserved */
 180     ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
 181     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
 182     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
 183     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
 184     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
 185     ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
 186
 187     /* RID occupies the low byte, CCs occupy the high three. */
 188     datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
 189     if (ahci_pedantic) {
 190         /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
 191          * Though in practice this is likely seldom true. */
 192         ASSERT_BIT_CLEAR(datal, 0xFF);
 193     }
 194
 195     /* BCC *must* equal 0x01. */
 196     g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
 197     if (PCI_SCC(datal) == 0x01) {
 198         /* IDE */
 199         ASSERT_BIT_SET(0x80000000, datal);
 200         ASSERT_BIT_CLEAR(0x60000000, datal);
 201     } else if (PCI_SCC(datal) == 0x04) {
 202         /* RAID */
 203         g_assert_cmphex(PCI_PI(datal), ==, 0);
 204     } else if (PCI_SCC(datal) == 0x06) {
 205         /* AHCI */
 206         g_assert_cmphex(PCI_PI(datal), ==, 0x01);
 207     } else {
 208         g_assert_not_reached();
 209     }
 210
 211     datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
 212     g_assert_cmphex(datab, ==, 0);
 213
 214     datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
 215     g_assert_cmphex(datab, ==, 0);
 216
 217     /* Only the bottom 7 bits must be off. */
 218     datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
 219     ASSERT_BIT_CLEAR(datab, 0x7F);
 220
 221     /* BIST is optional, but the low 7 bits must always start off regardless. */
 222     datab = qpci_config_readb(ahci->dev, PCI_BIST);
 223     ASSERT_BIT_CLEAR(datab, 0x7F);
 224
 225     /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
 226     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 227     g_assert_cmphex(datal, ==, 0);
 228
 229     qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
 230     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 231     /* ABAR must be 32-bit, memory mapped, non-prefetchable and
 232      * must be >= 512 bytes. To that end, bits 0-8 must be off. */
 233     ASSERT_BIT_CLEAR(datal, 0xFF);
 234
 235     /* Capability list MUST be present, */
 236     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
 237     /* But these bits are reserved. */
 238     ASSERT_BIT_CLEAR(datal, ~0xFF);
 239     g_assert_cmphex(datal, !=, 0);
 240
 241     /* Check specification adherence for capability extenstions. */
 242     data = qpci_config_readw(ahci->dev, datal);
 243
 244     switch (ahci->fingerprint) {
 245     case AHCI_INTEL_ICH9:
 246         /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
 247         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
 248         break;
 249     default:
 250         /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
 251         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
 252     }
 253
 254     ahci_test_pci_caps(ahci, data, (uint8_t)datal);
 255
 256     /* Reserved. */
 257     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
 258     g_assert_cmphex(datal, ==, 0);
 259
 260     /* IPIN might vary, but ILINE must be off. */
 261     datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
 262     g_assert_cmphex(datab, ==, 0);
 263 }
 264
 265 /**
 266  * Test PCI capabilities for AHCI specification adherence.
 267  */
 268 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
 269                                uint8_t offset)
 270 {
 271     uint8_t cid = header & 0xFF;
 272     uint8_t next = header >> 8;
 273
 274     g_test_message("CID: %02x; next: %02x", cid, next);
 275
 276     switch (cid) {
 277     case PCI_CAP_ID_PM:
 278         ahci_test_pmcap(ahci, offset);
 279         break;
 280     case PCI_CAP_ID_MSI:
 281         ahci_test_msicap(ahci, offset);
 282         break;
 283     case PCI_CAP_ID_SATA:
 284         ahci_test_satacap(ahci, offset);
 285         break;
 286
 287     default:
 288         g_test_message("Unknown CAP 0x%02x", cid);
 289     }
 290
 291     if (next) {
 292         ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
 293     }
 294 }
 295
 296 /**
 297  * Test SATA PCI capabilitity for AHCI specification adherence.
 298  */
 299 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
 300 {
 301     uint16_t dataw;
 302     uint32_t datal;
 303
 304     g_test_message("Verifying SATACAP");
 305
 306     /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
 307     dataw = qpci_config_readw(ahci->dev, offset + 2);
 308     g_assert_cmphex(dataw, ==, 0x10);
 309
 310     /* Grab the SATACR1 register. */
 311     datal = qpci_config_readw(ahci->dev, offset + 4);
 312
 313     switch (datal & 0x0F) {
 314     case 0x04: /* BAR0 */
 315     case 0x05: /* BAR1 */
 316     case 0x06:
 317     case 0x07:
 318     case 0x08:
 319     case 0x09: /* BAR5 */
 320     case 0x0F: /* Immediately following SATACR1 in PCI config space. */
 321         break;
 322     default:
 323         /* Invalid BARLOC for the Index Data Pair. */
 324         g_assert_not_reached();
 325     }
 326
 327     /* Reserved. */
 328     g_assert_cmphex((datal >> 24), ==, 0x00);
 329 }
 330
 331 /**
 332  * Test MSI PCI capability for AHCI specification adherence.
 333  */
 334 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
 335 {
 336     uint16_t dataw;
 337     uint32_t datal;
 338
 339     g_test_message("Verifying MSICAP");
 340
 341     dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
 342     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
 343     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
 344     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
 345
 346     datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
 347     g_assert_cmphex(datal, ==, 0);
 348
 349     if (dataw & PCI_MSI_FLAGS_64BIT) {
 350         g_test_message("MSICAP is 64bit");
 351         datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
 352         g_assert_cmphex(datal, ==, 0);
 353         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
 354         g_assert_cmphex(dataw, ==, 0);
 355     } else {
 356         g_test_message("MSICAP is 32bit");
 357         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
 358         g_assert_cmphex(dataw, ==, 0);
 359     }
 360 }
 361
 362 /**
 363  * Test Power Management PCI capability for AHCI specification adherence.
 364  */
 365 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
 366 {
 367     uint16_t dataw;
 368
 369     g_test_message("Verifying PMCAP");
 370
 371     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
 372     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
 373     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
 374     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
 375     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
 376
 377     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
 378     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
 379     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
 380     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
 381     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
 382 }
 383
 384 static void ahci_test_hba_spec(AHCIQState *ahci)
 385 {
 386     unsigned i;
 387     uint32_t reg;
 388     uint32_t ports;
 389     uint8_t nports_impl;
 390     uint8_t maxports;
 391
 392     g_assert(ahci != NULL);
 393
 394     /*
 395      * Note that the AHCI spec does expect the BIOS to set up a few things:
 396      * CAP.SSS    - Support for staggered spin-up            (t/f)
 397      * CAP.SMPS   - Support for mechanical presence switches (t/f)
 398      * PI         - Ports Implemented                        (1-32)
 399      * PxCMD.HPCP - Hot Plug Capable Port
 400      * PxCMD.MPSP - Mechanical Presence Switch Present
 401      * PxCMD.CPD  - Cold Presence Detection support
 402      *
 403      * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
 404      * Foreach Port Implemented:
 405      * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
 406      * -PxCLB/U and PxFB/U are set to valid regions in memory
 407      * -PxSUD is set to 1.
 408      * -PxSSTS.DET is polled for presence; if detected, we continue:
 409      * -PxSERR is cleared with 1's.
 410      * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
 411      *  the device is ready.
 412      */
 413
 414     /* 1 CAP - Capabilities Register */
 415     ahci->cap = ahci_rreg(ahci, AHCI_CAP);
 416     ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
 417
 418     /* 2 GHC - Global Host Control */
 419     reg = ahci_rreg(ahci, AHCI_GHC);
 420     ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
 421     ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
 422     ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
 423     if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
 424         g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
 425         ASSERT_BIT_SET(reg, AHCI_GHC_AE);
 426     } else {
 427         g_test_message("Supports AHCI/Legacy mix.");
 428         ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
 429     }
 430
 431     /* 3 IS - Interrupt Status */
 432     reg = ahci_rreg(ahci, AHCI_IS);
 433     g_assert_cmphex(reg, ==, 0);
 434
 435     /* 4 PI - Ports Implemented */
 436     ports = ahci_rreg(ahci, AHCI_PI);
 437     /* Ports Implemented must be non-zero. */
 438     g_assert_cmphex(ports, !=, 0);
 439     /* Ports Implemented must be <= Number of Ports. */
 440     nports_impl = ctpopl(ports);
 441     g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
 442
 443     /* Ports must be within the proper range. Given a mapping of SIZE,
 444      * 256 bytes are used for global HBA control, and the rest is used
 445      * for ports data, at 0x80 bytes each. */
 446     g_assert_cmphex(ahci->barsize, >, 0);
 447     maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
 448     /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
 449     g_assert_cmphex((reg >> maxports), ==, 0);
 450
 451     /* 5 AHCI Version */
 452     reg = ahci_rreg(ahci, AHCI_VS);
 453     switch (reg) {
 454     case AHCI_VERSION_0_95:
 455     case AHCI_VERSION_1_0:
 456     case AHCI_VERSION_1_1:
 457     case AHCI_VERSION_1_2:
 458     case AHCI_VERSION_1_3:
 459         break;
 460     default:
 461         g_assert_not_reached();
 462     }
 463
 464     /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
 465     reg = ahci_rreg(ahci, AHCI_CCCCTL);
 466     if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
 467         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
 468         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
 469         ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
 470         ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
 471     } else {
 472         g_assert_cmphex(reg, ==, 0);
 473     }
 474
 475     /* 7 CCC_PORTS */
 476     reg = ahci_rreg(ahci, AHCI_CCCPORTS);
 477     /* Must be zeroes initially regardless of CAP.CCCS */
 478     g_assert_cmphex(reg, ==, 0);
 479
 480     /* 8 EM_LOC */
 481     reg = ahci_rreg(ahci, AHCI_EMLOC);
 482     if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
 483         g_assert_cmphex(reg, ==, 0);
 484     }
 485
 486     /* 9 EM_CTL */
 487     reg = ahci_rreg(ahci, AHCI_EMCTL);
 488     if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
 489         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
 490         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
 491         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
 492         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
 493     } else {
 494         g_assert_cmphex(reg, ==, 0);
 495     }
 496
 497     /* 10 CAP2 -- Capabilities Extended */
 498     ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
 499     ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
 500
 501     /* 11 BOHC -- Bios/OS Handoff Control */
 502     reg = ahci_rreg(ahci, AHCI_BOHC);
 503     g_assert_cmphex(reg, ==, 0);
 504
 505     /* 12 -- 23: Reserved */
 506     g_test_message("Verifying HBA reserved area is empty.");
 507     for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
 508         reg = ahci_rreg(ahci, i);
 509         g_assert_cmphex(reg, ==, 0);
 510     }
 511
 512     /* 24 -- 39: NVMHCI */
 513     if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
 514         g_test_message("Verifying HBA/NVMHCI area is empty.");
 515         for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
 516             reg = ahci_rreg(ahci, i);
 517             g_assert_cmphex(reg, ==, 0);
 518         }
 519     }
 520
 521     /* 40 -- 63: Vendor */
 522     g_test_message("Verifying HBA/Vendor area is empty.");
 523     for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
 524         reg = ahci_rreg(ahci, i);
 525         g_assert_cmphex(reg, ==, 0);
 526     }
 527
 528     /* 64 -- XX: Port Space */
 529     for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
 530         if (BITSET(ports, 0x1)) {
 531             g_test_message("Testing port %u for spec", i);
 532             ahci_test_port_spec(ahci, i);
 533         } else {
 534             uint16_t j;
 535             uint16_t low = AHCI_PORTS + (32 * i);
 536             uint16_t high = AHCI_PORTS + (32 * (i + 1));
 537             g_test_message("Asserting unimplemented port %u "
 538                            "(reg [%u-%u]) is empty.",
 539                            i, low, high - 1);
 540             for (j = low; j < high; ++j) {
 541                 reg = ahci_rreg(ahci, j);
 542                 g_assert_cmphex(reg, ==, 0);
 543             }
 544         }
 545     }
 546 }
 547
 548 /**
 549  * Test the memory space for one port for specification adherence.
 550  */
 551 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
 552 {
 553     uint32_t reg;
 554     unsigned i;
 555
 556     /* (0) CLB */
 557     reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
 558     ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
 559
 560     /* (1) CLBU */
 561     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 562         reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
 563         g_assert_cmphex(reg, ==, 0);
 564     }
 565
 566     /* (2) FB */
 567     reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
 568     ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
 569
 570     /* (3) FBU */
 571     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 572         reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
 573         g_assert_cmphex(reg, ==, 0);
 574     }
 575
 576     /* (4) IS */
 577     reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
 578     g_assert_cmphex(reg, ==, 0);
 579
 580     /* (5) IE */
 581     reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
 582     g_assert_cmphex(reg, ==, 0);
 583
 584     /* (6) CMD */
 585     reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
 586     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
 587     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
 588     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
 589     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
 590     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
 591     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
 592     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
 593     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
 594     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
 595     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);  /* RW only if CAP.SALP */
 596     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);   /* RW only if CAP.SALP */
 597     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
 598     /* If CPDetect support does not exist, CPState must be off. */
 599     if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
 600         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
 601     }
 602     /* If MPSPresence is not set, MPSState must be off. */
 603     if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
 604         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 605     }
 606     /* If we do not support MPS, MPSS and MPSP must be off. */
 607     if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
 608         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 609         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
 610     }
 611     /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
 612     if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
 613         ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
 614     }
 615     /* HPCP and ESP cannot both be active. */
 616     g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
 617     /* If CAP.FBSS is not set, FBSCP must not be set. */
 618     if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
 619         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
 620     }
 621
 622     /* (7) RESERVED */
 623     reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
 624     g_assert_cmphex(reg, ==, 0);
 625
 626     /* (8) TFD */
 627     reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
 628     /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
 629      * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
 630     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
 631     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
 632     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
 633     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
 634     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
 635     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
 636     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
 637
 638     /* (9) SIG */
 639     /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
 640      * Even when GHC.ST is zero, the AHCI HBA may receive the initial
 641      * D2H register FIS and update the signature asynchronously,
 642      * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
 643
 644     /* (10) SSTS / SCR0: SStatus */
 645     reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
 646     ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
 647     /* Even though the register should be 0 at boot, it is asynchronous and
 648      * prone to change, so we cannot test any well known value. */
 649
 650     /* (11) SCTL / SCR2: SControl */
 651     reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
 652     g_assert_cmphex(reg, ==, 0);
 653
 654     /* (12) SERR / SCR1: SError */
 655     reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
 656     g_assert_cmphex(reg, ==, 0);
 657
 658     /* (13) SACT / SCR3: SActive */
 659     reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
 660     g_assert_cmphex(reg, ==, 0);
 661
 662     /* (14) CI */
 663     reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
 664     g_assert_cmphex(reg, ==, 0);
 665
 666     /* (15) SNTF */
 667     reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
 668     g_assert_cmphex(reg, ==, 0);
 669
 670     /* (16) FBS */
 671     reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
 672     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
 673     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
 674     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
 675     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
 676     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
 677     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
 678     if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
 679         /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
 680         g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
 681     }
 682
 683     /* [17 -- 27] RESERVED */
 684     for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
 685         reg = ahci_px_rreg(ahci, port, i);
 686         g_assert_cmphex(reg, ==, 0);
 687     }
 688
 689     /* [28 -- 31] Vendor-Specific */
 690     for (i = AHCI_PX_VS; i < 32; ++i) {
 691         reg = ahci_px_rreg(ahci, port, i);
 692         if (reg) {
 693             g_test_message("INFO: Vendor register %u non-empty", i);
 694         }
 695     }
 696 }
 697
 698 /**
 699  * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
 700  * device we see, then read and check the response.
 701  */
 702 static void ahci_test_identify(AHCIQState *ahci)
 703 {
 704     uint16_t buff[256];
 705     unsigned px;
 706     int rc;
 707     uint16_t sect_size;
 708     const size_t buffsize = 512;
 709
 710     g_assert(ahci != NULL);
 711
 712     /**
 713      * This serves as a bit of a tutorial on AHCI device programming:
 714      *
 715      * (1) Create a data buffer for the IDENTIFY response to be sent to
 716      * (2) Create a Command Table buffer, where we will store the
 717      *     command and PRDT (Physical Region Descriptor Table)
 718      * (3) Construct an FIS host-to-device command structure, and write it to
 719      *     the top of the Command Table buffer.
 720      * (4) Create one or more Physical Region Descriptors (PRDs) that describe
 721      *     a location in memory where data may be stored/retrieved.
 722      * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
 723      * (6) Each AHCI port has up to 32 command slots. Each slot contains a
 724      *     header that points to a Command Table buffer. Pick an unused slot
 725      *     and update it to point to the Command Table we have built.
 726      * (7) Now: Command #n points to our Command Table, and our Command Table
 727      *     contains the FIS (that describes our command) and the PRDTL, which
 728      *     describes our buffer.
 729      * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
 730      *     #n is ready for processing.
 731      */
 732
 733     /* Pick the first implemented and running port */
 734     px = ahci_port_select(ahci);
 735     g_test_message("Selected port %u for test", px);
 736
 737     /* Clear out the FIS Receive area and any pending interrupts. */
 738     ahci_port_clear(ahci, px);
 739
 740     /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
 741     ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize);
 742
 743     /* Check serial number/version in the buffer */
 744     /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
 745      * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
 746      * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
 747      * as a consequence, only needs to unchunk the data on LE machines. */
 748     string_bswap16(&buff[10], 20);
 749     rc = memcmp(&buff[10], "testdisk            ", 20);
 750     g_assert_cmphex(rc, ==, 0);
 751
 752     string_bswap16(&buff[23], 8);
 753     rc = memcmp(&buff[23], "version ", 8);
 754     g_assert_cmphex(rc, ==, 0);
 755
 756     sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
 757     g_assert_cmphex(sect_size, ==, 0x200);
 758 }
 759
 760 static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
 761                                    uint8_t read_cmd, uint8_t write_cmd)
 762 {
 763     uint64_t ptr;
 764     uint8_t port;
 765     unsigned char *tx = g_malloc(bufsize);
 766     unsigned char *rx = g_malloc0(bufsize);
 767
 768     g_assert(ahci != NULL);
 769
 770     /* Pick the first running port and clear it. */
 771     port = ahci_port_select(ahci);
 772     ahci_port_clear(ahci, port);
 773
 774     /*** Create pattern and transfer to guest ***/
 775     /* Data buffer in the guest */
 776     ptr = ahci_alloc(ahci, bufsize);
 777     g_assert(ptr);
 778
 779     /* Write some indicative pattern to our buffer. */
 780     generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
 781     memwrite(ptr, tx, bufsize);
 782
 783     /* Write this buffer to disk, then read it back to the DMA buffer. */
 784     ahci_guest_io(ahci, port, write_cmd, ptr, bufsize);
 785     qmemset(ptr, 0x00, bufsize);
 786     ahci_guest_io(ahci, port, read_cmd, ptr, bufsize);
 787
 788     /*** Read back the Data ***/
 789     memread(ptr, rx, bufsize);
 790     g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
 791
 792     ahci_free(ahci, ptr);
 793     g_free(tx);
 794     g_free(rx);
 795 }
 796
 797 /******************************************************************************/
 798 /* Test Interfaces                                                            */
 799 /******************************************************************************/
 800
 801 /**
 802  * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
 803  */
 804 static void test_sanity(void)
 805 {
 806     AHCIQState *ahci;
 807     ahci = ahci_boot();
 808     ahci_shutdown(ahci);
 809 }
 810
 811 /**
 812  * Ensure that the PCI configuration space for the AHCI device is in-line with
 813  * the AHCI 1.3 specification for initial values.
 814  */
 815 static void test_pci_spec(void)
 816 {
 817     AHCIQState *ahci;
 818     ahci = ahci_boot();
 819     ahci_test_pci_spec(ahci);
 820     ahci_shutdown(ahci);
 821 }
 822
 823 /**
 824  * Engage the PCI AHCI device and sanity check the response.
 825  * Perform additional PCI config space bringup for the HBA.
 826  */
 827 static void test_pci_enable(void)
 828 {
 829     AHCIQState *ahci;
 830
 831     ahci = ahci_boot();
 832     ahci_pci_enable(ahci);
 833     ahci_shutdown(ahci);
 834 }
 835
 836 /**
 837  * Investigate the memory mapped regions of the HBA,
 838  * and test them for AHCI specification adherence.
 839  */
 840 static void test_hba_spec(void)
 841 {
 842     AHCIQState *ahci;
 843
 844     ahci = ahci_boot();
 845     ahci_pci_enable(ahci);
 846     ahci_test_hba_spec(ahci);
 847     ahci_shutdown(ahci);
 848 }
 849
 850 /**
 851  * Engage the HBA functionality of the AHCI PCI device,
 852  * and bring it into a functional idle state.
 853  */
 854 static void test_hba_enable(void)
 855 {
 856     AHCIQState *ahci;
 857
 858     ahci = ahci_boot();
 859     ahci_pci_enable(ahci);
 860     ahci_hba_enable(ahci);
 861     ahci_shutdown(ahci);
 862 }
 863
 864 /**
 865  * Bring up the device and issue an IDENTIFY command.
 866  * Inspect the state of the HBA device and the data returned.
 867  */
 868 static void test_identify(void)
 869 {
 870     AHCIQState *ahci;
 871
 872     ahci = ahci_boot_and_enable();
 873     ahci_test_identify(ahci);
 874     ahci_shutdown(ahci);
 875 }
 876
 877 /**
 878  * Fragmented DMA test: Perform a standard 4K DMA read/write
 879  * test, but make sure the physical regions are fragmented to
 880  * be very small, each just 32 bytes, to see how AHCI performs
 881  * with chunks defined to be much less than a sector.
 882  */
 883 static void test_dma_fragmented(void)
 884 {
 885     AHCIQState *ahci;
 886     AHCICommand *cmd;
 887     uint8_t px;
 888     size_t bufsize = 4096;
 889     unsigned char *tx = g_malloc(bufsize);
 890     unsigned char *rx = g_malloc0(bufsize);
 891     uint64_t ptr;
 892
 893     ahci = ahci_boot_and_enable();
 894     px = ahci_port_select(ahci);
 895     ahci_port_clear(ahci, px);
 896
 897     /* create pattern */
 898     generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
 899
 900     /* Create a DMA buffer in guest memory, and write our pattern to it. */
 901     ptr = guest_alloc(ahci->parent->alloc, bufsize);
 902     g_assert(ptr);
 903     memwrite(ptr, tx, bufsize);
 904
 905     cmd = ahci_command_create(CMD_WRITE_DMA);
 906     ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
 907     ahci_command_commit(ahci, cmd, px);
 908     ahci_command_issue(ahci, cmd);
 909     ahci_command_verify(ahci, cmd);
 910     g_free(cmd);
 911
 912     cmd = ahci_command_create(CMD_READ_DMA);
 913     ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
 914     ahci_command_commit(ahci, cmd, px);
 915     ahci_command_issue(ahci, cmd);
 916     ahci_command_verify(ahci, cmd);
 917     g_free(cmd);
 918
 919     /* Read back the guest's receive buffer into local memory */
 920     memread(ptr, rx, bufsize);
 921     guest_free(ahci->parent->alloc, ptr);
 922
 923     g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
 924
 925     ahci_shutdown(ahci);
 926
 927     g_free(rx);
 928     g_free(tx);
 929 }
 930
 931 /******************************************************************************/
 932 /* AHCI I/O Test Matrix Definitions                                           */
 933
 934 enum BuffLen {
 935     LEN_BEGIN = 0,
 936     LEN_SIMPLE = LEN_BEGIN,
 937     LEN_DOUBLE,
 938     LEN_LONG,
 939     LEN_SHORT,
 940     NUM_LENGTHS
 941 };
 942
 943 static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
 944                                                  "long", "short" };
 945
 946 enum AddrMode {
 947     ADDR_MODE_BEGIN = 0,
 948     ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
 949     ADDR_MODE_LBA48,
 950     NUM_ADDR_MODES
 951 };
 952
 953 static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
 954
 955 enum IOMode {
 956     MODE_BEGIN = 0,
 957     MODE_PIO = MODE_BEGIN,
 958     MODE_DMA,
 959     NUM_MODES
 960 };
 961
 962 static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
 963
 964 enum IOOps {
 965     IO_BEGIN = 0,
 966     IO_READ = IO_BEGIN,
 967     IO_WRITE,
 968     NUM_IO_OPS
 969 };
 970
 971 typedef struct AHCIIOTestOptions {
 972     enum BuffLen length;
 973     enum AddrMode address_type;
 974     enum IOMode io_type;
 975 } AHCIIOTestOptions;
 976
 977 /**
 978  * Table of possible I/O ATA commands given a set of enumerations.
 979  */
 980 static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
 981     [MODE_PIO] = {
 982         [ADDR_MODE_LBA28] = {
 983             [IO_READ] = CMD_READ_PIO,
 984             [IO_WRITE] = CMD_WRITE_PIO },
 985         [ADDR_MODE_LBA48] = {
 986             [IO_READ] = CMD_READ_PIO_EXT,
 987             [IO_WRITE] = CMD_WRITE_PIO_EXT }
 988     },
 989     [MODE_DMA] = {
 990         [ADDR_MODE_LBA28] = {
 991             [IO_READ] = CMD_READ_DMA,
 992             [IO_WRITE] = CMD_WRITE_DMA },
 993         [ADDR_MODE_LBA48] = {
 994             [IO_READ] = CMD_READ_DMA_EXT,
 995             [IO_WRITE] = CMD_WRITE_DMA_EXT }
 996     }
 997 };
 998
 999 /**
1000  * Test a Read/Write pattern using various commands, addressing modes,
1001  * transfer modes, and buffer sizes.
1002  */
1003 static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
1004                                  unsigned bufsize)
1005 {
1006     AHCIQState *ahci;
1007
1008     ahci = ahci_boot_and_enable();
1009     ahci_test_io_rw_simple(ahci, bufsize,
1010                            io_cmds[dma][lba48][IO_READ],
1011                            io_cmds[dma][lba48][IO_WRITE]);
1012     ahci_shutdown(ahci);
1013 }
1014
1015 /**
1016  * Demultiplex the test data and invoke the actual test routine.
1017  */
1018 static void test_io_interface(gconstpointer opaque)
1019 {
1020     AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1021     unsigned bufsize;
1022
1023     switch (opts->length) {
1024     case LEN_SIMPLE:
1025         bufsize = 4096;
1026         break;
1027     case LEN_DOUBLE:
1028         bufsize = 8192;
1029         break;
1030     case LEN_LONG:
1031         bufsize = 4096 * 64;
1032         break;
1033     case LEN_SHORT:
1034         bufsize = 512;
1035         break;
1036     default:
1037         g_assert_not_reached();
1038     }
1039
1040     test_io_rw_interface(opts->address_type, opts->io_type, bufsize);
1041     g_free(opts);
1042     return;
1043 }
1044
1045 static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
1046                                 enum BuffLen len)
1047 {
1048     static const char *arch;
1049     char *name;
1050     AHCIIOTestOptions *opts = g_malloc(sizeof(AHCIIOTestOptions));
1051
1052     opts->length = len;
1053     opts->address_type = addr;
1054     opts->io_type = type;
1055
1056     if (!arch) {
1057         arch = qtest_get_arch();
1058     }
1059
1060     name = g_strdup_printf("/%s/ahci/io/%s/%s/%s", arch,
1061                            io_mode_str[type],
1062                            addr_mode_str[addr],
1063                            buff_len_str[len]);
1064
1065     g_test_add_data_func(name, opts, test_io_interface);
1066     g_free(name);
1067 }
1068
1069 /******************************************************************************/
1070
1071 int main(int argc, char **argv)
1072 {
1073     const char *arch;
1074     int fd;
1075     int ret;
1076     int c;
1077     int i, j, k;
1078
1079     static struct option long_options[] = {
1080         {"pedantic", no_argument, 0, 'p' },
1081         {0, 0, 0, 0},
1082     };
1083
1084     /* Should be first to utilize g_test functionality, So we can see errors. */
1085     g_test_init(&argc, &argv, NULL);
1086
1087     while (1) {
1088         c = getopt_long(argc, argv, "", long_options, NULL);
1089         if (c == -1) {
1090             break;
1091         }
1092         switch (c) {
1093         case -1:
1094             break;
1095         case 'p':
1096             ahci_pedantic = 1;
1097             break;
1098         default:
1099             fprintf(stderr, "Unrecognized ahci_test option.\n");
1100             g_assert_not_reached();
1101         }
1102     }
1103
1104     /* Check architecture */
1105     arch = qtest_get_arch();
1106     if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1107         g_test_message("Skipping test for non-x86");
1108         return 0;
1109     }
1110
1111     /* Create a temporary raw image */
1112     fd = mkstemp(tmp_path);
1113     g_assert(fd >= 0);
1114     ret = ftruncate(fd, TEST_IMAGE_SIZE);
1115     g_assert(ret == 0);
1116     close(fd);
1117
1118     /* Run the tests */
1119     qtest_add_func("/ahci/sanity",     test_sanity);
1120     qtest_add_func("/ahci/pci_spec",   test_pci_spec);
1121     qtest_add_func("/ahci/pci_enable", test_pci_enable);
1122     qtest_add_func("/ahci/hba_spec",   test_hba_spec);
1123     qtest_add_func("/ahci/hba_enable", test_hba_enable);
1124     qtest_add_func("/ahci/identify",   test_identify);
1125
1126     for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1127         for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1128             for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
1129                 create_ahci_io_test(i, j, k);
1130             }
1131         }
1132     }
1133
1134     qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1135
1136     ret = g_test_run();
1137
1138     /* Cleanup */
1139     unlink(tmp_path);
1140
1141     return ret;
1142 }