hw/intc/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20 #include "hw/i386/apic.h"
  21 #include "hw/i386/apic_internal.h"
  22 #include "trace.h"
  23 #include "sysemu/kvm.h"
  24 #include "hw/qdev.h"
  25 #include "hw/sysbus.h"
  26
  27 static int apic_irq_delivered;
  28 bool apic_report_tpr_access;
  29
  30 void cpu_set_apic_base(DeviceState *dev, uint64_t val)
  31 {
  32     trace_cpu_set_apic_base(val);
  33
  34     if (dev) {
  35         APICCommonState *s = APIC_COMMON(dev);
  36         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  37         info->set_base(s, val);
  38     }
  39 }
  40
  41 uint64_t cpu_get_apic_base(DeviceState *dev)
  42 {
  43     if (dev) {
  44         APICCommonState *s = APIC_COMMON(dev);
  45         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  46         return s->apicbase;
  47     } else {
  48         trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
  49         return MSR_IA32_APICBASE_BSP;
  50     }
  51 }
  52
  53 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
  54 {
  55     APICCommonState *s;
  56     APICCommonClass *info;
  57
  58     if (!dev) {
  59         return;
  60     }
  61
  62     s = APIC_COMMON(dev);
  63     info = APIC_COMMON_GET_CLASS(s);
  64
  65     info->set_tpr(s, val);
  66 }
  67
  68 uint8_t cpu_get_apic_tpr(DeviceState *dev)
  69 {
  70     APICCommonState *s;
  71     APICCommonClass *info;
  72
  73     if (!dev) {
  74         return 0;
  75     }
  76
  77     s = APIC_COMMON(dev);
  78     info = APIC_COMMON_GET_CLASS(s);
  79
  80     return info->get_tpr(s);
  81 }
  82
  83 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
  84 {
  85     APICCommonState *s = APIC_COMMON(dev);
  86     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  87
  88     apic_report_tpr_access = enable;
  89     if (info->enable_tpr_reporting) {
  90         info->enable_tpr_reporting(s, enable);
  91     }
  92 }
  93
  94 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
  95 {
  96     APICCommonState *s = APIC_COMMON(dev);
  97     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  98
  99     s->vapic_paddr = paddr;
 100     info->vapic_base_update(s);
 101 }
 102
 103 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
 104                                    TPRAccess access)
 105 {
 106     APICCommonState *s = APIC_COMMON(dev);
 107
 108     vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
 109 }
 110
 111 void apic_report_irq_delivered(int delivered)
 112 {
 113     apic_irq_delivered += delivered;
 114
 115     trace_apic_report_irq_delivered(apic_irq_delivered);
 116 }
 117
 118 void apic_reset_irq_delivered(void)
 119 {
 120     /* Copy this into a local variable to encourage gcc to emit a plain
 121      * register for a sys/sdt.h marker.  For details on this workaround, see:
 122      * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
 123      */
 124     volatile int a_i_d = apic_irq_delivered;
 125     trace_apic_reset_irq_delivered(a_i_d);
 126
 127     apic_irq_delivered = 0;
 128 }
 129
 130 int apic_get_irq_delivered(void)
 131 {
 132     trace_apic_get_irq_delivered(apic_irq_delivered);
 133
 134     return apic_irq_delivered;
 135 }
 136
 137 void apic_deliver_nmi(DeviceState *dev)
 138 {
 139     APICCommonState *s = APIC_COMMON(dev);
 140     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 141
 142     info->external_nmi(s);
 143 }
 144
 145 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 146 {
 147     int64_t d;
 148
 149     /* We need to store the timer state separately to support APIC
 150      * implementations that maintain a non-QEMU timer, e.g. inside the
 151      * host kernel. This open-coded state allows us to migrate between
 152      * both models. */
 153     s->timer_expiry = -1;
 154
 155     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 156         return false;
 157     }
 158
 159     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 160
 161     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 162         if (!s->initial_count) {
 163             return false;
 164         }
 165         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 166             ((uint64_t)s->initial_count + 1);
 167     } else {
 168         if (d >= s->initial_count) {
 169             return false;
 170         }
 171         d = (uint64_t)s->initial_count + 1;
 172     }
 173     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 174     s->timer_expiry = s->next_time;
 175     return true;
 176 }
 177
 178 void apic_init_reset(DeviceState *dev)
 179 {
 180     APICCommonState *s = APIC_COMMON(dev);
 181     int i;
 182
 183     if (!s) {
 184         return;
 185     }
 186     s->tpr = 0;
 187     s->spurious_vec = 0xff;
 188     s->log_dest = 0;
 189     s->dest_mode = 0xf;
 190     memset(s->isr, 0, sizeof(s->isr));
 191     memset(s->tmr, 0, sizeof(s->tmr));
 192     memset(s->irr, 0, sizeof(s->irr));
 193     for (i = 0; i < APIC_LVT_NB; i++) {
 194         s->lvt[i] = APIC_LVT_MASKED;
 195     }
 196     s->esr = 0;
 197     memset(s->icr, 0, sizeof(s->icr));
 198     s->divide_conf = 0;
 199     s->count_shift = 0;
 200     s->initial_count = 0;
 201     s->initial_count_load_time = 0;
 202     s->next_time = 0;
 203     s->wait_for_sipi = !cpu_is_bsp(s->cpu);
 204
 205     if (s->timer) {
 206         timer_del(s->timer);
 207     }
 208     s->timer_expiry = -1;
 209 }
 210
 211 void apic_designate_bsp(DeviceState *dev)
 212 {
 213     if (dev == NULL) {
 214         return;
 215     }
 216
 217     APICCommonState *s = APIC_COMMON(dev);
 218     s->apicbase |= MSR_IA32_APICBASE_BSP;
 219 }
 220
 221 static void apic_reset_common(DeviceState *dev)
 222 {
 223     APICCommonState *s = APIC_COMMON(dev);
 224     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 225     bool bsp;
 226
 227     bsp = cpu_is_bsp(s->cpu);
 228     s->apicbase = APIC_DEFAULT_ADDRESS |
 229         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
 230
 231     s->vapic_paddr = 0;
 232     info->vapic_base_update(s);
 233
 234     apic_init_reset(dev);
 235
 236     if (bsp) {
 237         /*
 238          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 239          * time typically by BIOS, so PIC interrupt can be delivered to the
 240          * processor when local APIC is enabled.
 241          */
 242         s->lvt[APIC_LVT_LINT0] = 0x700;
 243     }
 244 }
 245
 246 /* This function is only used for old state version 1 and 2 */
 247 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 248 {
 249     APICCommonState *s = opaque;
 250     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 251     int i;
 252
 253     if (version_id > 2) {
 254         return -EINVAL;
 255     }
 256
 257     /* XXX: what if the base changes? (registered memory regions) */
 258     qemu_get_be32s(f, &s->apicbase);
 259     qemu_get_8s(f, &s->id);
 260     qemu_get_8s(f, &s->arb_id);
 261     qemu_get_8s(f, &s->tpr);
 262     qemu_get_be32s(f, &s->spurious_vec);
 263     qemu_get_8s(f, &s->log_dest);
 264     qemu_get_8s(f, &s->dest_mode);
 265     for (i = 0; i < 8; i++) {
 266         qemu_get_be32s(f, &s->isr[i]);
 267         qemu_get_be32s(f, &s->tmr[i]);
 268         qemu_get_be32s(f, &s->irr[i]);
 269     }
 270     for (i = 0; i < APIC_LVT_NB; i++) {
 271         qemu_get_be32s(f, &s->lvt[i]);
 272     }
 273     qemu_get_be32s(f, &s->esr);
 274     qemu_get_be32s(f, &s->icr[0]);
 275     qemu_get_be32s(f, &s->icr[1]);
 276     qemu_get_be32s(f, &s->divide_conf);
 277     s->count_shift = qemu_get_be32(f);
 278     qemu_get_be32s(f, &s->initial_count);
 279     s->initial_count_load_time = qemu_get_be64(f);
 280     s->next_time = qemu_get_be64(f);
 281
 282     if (version_id >= 2) {
 283         s->timer_expiry = qemu_get_be64(f);
 284     }
 285
 286     if (info->post_load) {
 287         info->post_load(s);
 288     }
 289     return 0;
 290 }
 291
 292 static void apic_common_realize(DeviceState *dev, Error **errp)
 293 {
 294     APICCommonState *s = APIC_COMMON(dev);
 295     APICCommonClass *info;
 296     static DeviceState *vapic;
 297     static int apic_no;
 298     static bool mmio_registered;
 299
 300     if (apic_no >= MAX_APICS) {
 301         error_setg(errp, "%s initialization failed.",
 302                    object_get_typename(OBJECT(dev)));
 303         return;
 304     }
 305     s->idx = apic_no++;
 306
 307     info = APIC_COMMON_GET_CLASS(s);
 308     info->realize(dev, errp);
 309     if (!mmio_registered) {
 310         ICCBus *b = ICC_BUS(qdev_get_parent_bus(dev));
 311         memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory);
 312         mmio_registered = true;
 313     }
 314
 315     /* Note: We need at least 1M to map the VAPIC option ROM */
 316     if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
 317         ram_size >= 1024 * 1024) {
 318         vapic = sysbus_create_simple("kvmvapic", -1, NULL);
 319     }
 320     s->vapic = vapic;
 321     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 322         info->enable_tpr_reporting(s, true);
 323     }
 324
 325 }
 326
 327 static void apic_dispatch_pre_save(void *opaque)
 328 {
 329     APICCommonState *s = APIC_COMMON(opaque);
 330     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 331
 332     if (info->pre_save) {
 333         info->pre_save(s);
 334     }
 335 }
 336
 337 static int apic_dispatch_post_load(void *opaque, int version_id)
 338 {
 339     APICCommonState *s = APIC_COMMON(opaque);
 340     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 341
 342     if (info->post_load) {
 343         info->post_load(s);
 344     }
 345     return 0;
 346 }
 347
 348 static const VMStateDescription vmstate_apic_common = {
 349     .name = "apic",
 350     .version_id = 3,
 351     .minimum_version_id = 3,
 352     .minimum_version_id_old = 1,
 353     .load_state_old = apic_load_old,
 354     .pre_save = apic_dispatch_pre_save,
 355     .post_load = apic_dispatch_post_load,
 356     .fields = (VMStateField[]) {
 357         VMSTATE_UINT32(apicbase, APICCommonState),
 358         VMSTATE_UINT8(id, APICCommonState),
 359         VMSTATE_UINT8(arb_id, APICCommonState),
 360         VMSTATE_UINT8(tpr, APICCommonState),
 361         VMSTATE_UINT32(spurious_vec, APICCommonState),
 362         VMSTATE_UINT8(log_dest, APICCommonState),
 363         VMSTATE_UINT8(dest_mode, APICCommonState),
 364         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 365         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 366         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 367         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 368         VMSTATE_UINT32(esr, APICCommonState),
 369         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 370         VMSTATE_UINT32(divide_conf, APICCommonState),
 371         VMSTATE_INT32(count_shift, APICCommonState),
 372         VMSTATE_UINT32(initial_count, APICCommonState),
 373         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 374         VMSTATE_INT64(next_time, APICCommonState),
 375         VMSTATE_INT64(timer_expiry,
 376                       APICCommonState), /* open-coded timer state */
 377         VMSTATE_END_OF_LIST()
 378     }
 379 };
 380
 381 static Property apic_properties_common[] = {
 382     DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
 383     DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
 384     DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
 385                     true),
 386     DEFINE_PROP_END_OF_LIST(),
 387 };
 388
 389 static void apic_common_class_init(ObjectClass *klass, void *data)
 390 {
 391     ICCDeviceClass *idc = ICC_DEVICE_CLASS(klass);
 392     DeviceClass *dc = DEVICE_CLASS(klass);
 393
 394     dc->vmsd = &vmstate_apic_common;
 395     dc->reset = apic_reset_common;
 396     dc->props = apic_properties_common;
 397     idc->realize = apic_common_realize;
 398     /*
 399      * Reason: APIC and CPU need to be wired up by
 400      * x86_cpu_apic_create()
 401      */
 402     dc->cannot_instantiate_with_device_add_yet = true;
 403 }
 404
 405 static const TypeInfo apic_common_type = {
 406     .name = TYPE_APIC_COMMON,
 407     .parent = TYPE_ICC_DEVICE,
 408     .instance_size = sizeof(APICCommonState),
 409     .class_size = sizeof(APICCommonClass),
 410     .class_init = apic_common_class_init,
 411     .abstract = true,
 412 };
 413
 414 static void apic_common_register_types(void)
 415 {
 416     type_register_static(&apic_common_type);
 417 }
 418
 419 type_init(apic_common_register_types)