?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
nbd: implement TLS support in the protocol negotiation
[qemu.git] / target-ppc / cpu.h
blob892f4dc94941b0f569b057a12932603cab1bbb10
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 #define TARGET_IS_BIENDIAN 1
33
34 /* Note that the official physical address space bits is 62-M where M
35 is implementation dependent. I've not looked up M for the set of
36 cpus we emulate at the system level. */
37 #define TARGET_PHYS_ADDR_SPACE_BITS 62
38
39 /* Note that the PPC environment architecture talks about 80 bit virtual
40 addresses, with segmentation. Obviously that's not all visible to a
41 single process, which is all we're concerned with here. */
42 #ifdef TARGET_ABI32
43 # define TARGET_VIRT_ADDR_SPACE_BITS 32
44 #else
45 # define TARGET_VIRT_ADDR_SPACE_BITS 64
46 #endif
47
48 #define TARGET_PAGE_BITS_64K 16
49 #define TARGET_PAGE_BITS_16M 24
50
51 #else /* defined (TARGET_PPC64) */
52 /* PowerPC 32 definitions */
53 #define TARGET_LONG_BITS 32
54
55 #if defined(TARGET_PPCEMB)
56 /* Specific definitions for PowerPC embedded */
57 /* BookE have 36 bits physical address space */
58 #if defined(CONFIG_USER_ONLY)
59 /* It looks like a lot of Linux programs assume page size
60 * is 4kB long. This is evil, but we have to deal with it...
61 */
62 #define TARGET_PAGE_BITS 12
63 #else /* defined(CONFIG_USER_ONLY) */
64 /* Pages can be 1 kB small */
65 #define TARGET_PAGE_BITS 10
66 #endif /* defined(CONFIG_USER_ONLY) */
67 #else /* defined(TARGET_PPCEMB) */
68 /* "standard" PowerPC 32 definitions */
69 #define TARGET_PAGE_BITS 12
70 #endif /* defined(TARGET_PPCEMB) */
71
72 #define TARGET_PHYS_ADDR_SPACE_BITS 36
73 #define TARGET_VIRT_ADDR_SPACE_BITS 32
74
75 #endif /* defined (TARGET_PPC64) */
76
77 #define CPUArchState struct CPUPPCState
78
79 #include "exec/cpu-defs.h"
80
81 #include "fpu/softfloat.h"
82
83 #if defined (TARGET_PPC64)
84 #define PPC_ELF_MACHINE EM_PPC64
85 #else
86 #define PPC_ELF_MACHINE EM_PPC
87 #endif
88
89 /*****************************************************************************/
90 /* MMU model */
91 typedef enum powerpc_mmu_t powerpc_mmu_t;
92 enum powerpc_mmu_t {
93 POWERPC_MMU_UNKNOWN = 0x00000000,
94 /* Standard 32 bits PowerPC MMU */
95 POWERPC_MMU_32B = 0x00000001,
96 /* PowerPC 6xx MMU with software TLB */
97 POWERPC_MMU_SOFT_6xx = 0x00000002,
98 /* PowerPC 74xx MMU with software TLB */
99 POWERPC_MMU_SOFT_74xx = 0x00000003,
100 /* PowerPC 4xx MMU with software TLB */
101 POWERPC_MMU_SOFT_4xx = 0x00000004,
102 /* PowerPC 4xx MMU with software TLB and zones protections */
103 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
104 /* PowerPC MMU in real mode only */
105 POWERPC_MMU_REAL = 0x00000006,
106 /* Freescale MPC8xx MMU model */
107 POWERPC_MMU_MPC8xx = 0x00000007,
108 /* BookE MMU model */
109 POWERPC_MMU_BOOKE = 0x00000008,
110 /* BookE 2.06 MMU model */
111 POWERPC_MMU_BOOKE206 = 0x00000009,
112 /* PowerPC 601 MMU model (specific BATs format) */
113 POWERPC_MMU_601 = 0x0000000A,
114 #if defined(TARGET_PPC64)
115 #define POWERPC_MMU_64 0x00010000
116 #define POWERPC_MMU_1TSEG 0x00020000
117 #define POWERPC_MMU_AMR 0x00040000
118 /* 64 bits PowerPC MMU */
119 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
120 /* Architecture 2.03 and later (has LPCR) */
121 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
122 /* Architecture 2.06 variant */
123 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
124 | POWERPC_MMU_AMR | 0x00000003,
125 /* Architecture 2.06 "degraded" (no 1T segments) */
126 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
127 | 0x00000003,
128 /* Architecture 2.07 variant */
129 POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
130 | POWERPC_MMU_AMR | 0x00000004,
131 /* Architecture 2.07 "degraded" (no 1T segments) */
132 POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
133 | 0x00000004,
134 #endif /* defined(TARGET_PPC64) */
135 };
136
137 /*****************************************************************************/
138 /* Exception model */
139 typedef enum powerpc_excp_t powerpc_excp_t;
140 enum powerpc_excp_t {
141 POWERPC_EXCP_UNKNOWN = 0,
142 /* Standard PowerPC exception model */
143 POWERPC_EXCP_STD,
144 /* PowerPC 40x exception model */
145 POWERPC_EXCP_40x,
146 /* PowerPC 601 exception model */
147 POWERPC_EXCP_601,
148 /* PowerPC 602 exception model */
149 POWERPC_EXCP_602,
150 /* PowerPC 603 exception model */
151 POWERPC_EXCP_603,
152 /* PowerPC 603e exception model */
153 POWERPC_EXCP_603E,
154 /* PowerPC G2 exception model */
155 POWERPC_EXCP_G2,
156 /* PowerPC 604 exception model */
157 POWERPC_EXCP_604,
158 /* PowerPC 7x0 exception model */
159 POWERPC_EXCP_7x0,
160 /* PowerPC 7x5 exception model */
161 POWERPC_EXCP_7x5,
162 /* PowerPC 74xx exception model */
163 POWERPC_EXCP_74xx,
164 /* BookE exception model */
165 POWERPC_EXCP_BOOKE,
166 #if defined(TARGET_PPC64)
167 /* PowerPC 970 exception model */
168 POWERPC_EXCP_970,
169 /* POWER7 exception model */
170 POWERPC_EXCP_POWER7,
171 #endif /* defined(TARGET_PPC64) */
172 };
173
174 /*****************************************************************************/
175 /* Exception vectors definitions */
176 enum {
177 POWERPC_EXCP_NONE = -1,
178 /* The 64 first entries are used by the PowerPC embedded specification */
179 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
180 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
181 POWERPC_EXCP_DSI = 2, /* Data storage exception */
182 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
183 POWERPC_EXCP_EXTERNAL = 4, /* External input */
184 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
185 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
186 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
187 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
188 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
189 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
190 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
191 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
192 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
193 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
194 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
195 /* Vectors 16 to 31 are reserved */
196 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
197 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
198 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
199 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
200 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
201 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
202 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
203 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
204 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
205 /* Vectors 42 to 63 are reserved */
206 /* Exceptions defined in the PowerPC server specification */
207 POWERPC_EXCP_RESET = 64, /* System reset exception */
208 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
209 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
210 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
211 POWERPC_EXCP_TRACE = 68, /* Trace exception */
212 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
213 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
214 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
215 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
216 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
217 /* 40x specific exceptions */
218 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
219 /* 601 specific exceptions */
220 POWERPC_EXCP_IO = 75, /* IO error exception */
221 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
222 /* 602 specific exceptions */
223 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
224 /* 602/603 specific exceptions */
225 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
226 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
227 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
228 /* Exceptions available on most PowerPC */
229 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
230 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
231 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
232 POWERPC_EXCP_SMI = 84, /* System management interrupt */
233 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
234 /* 7xx/74xx specific exceptions */
235 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
236 /* 74xx specific exceptions */
237 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
238 /* 970FX specific exceptions */
239 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
240 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
241 /* Freescale embedded cores specific exceptions */
242 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
243 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
244 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
245 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
246 /* VSX Unavailable (Power ISA 2.06 and later) */
247 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
248 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
249 /* EOL */
250 POWERPC_EXCP_NB = 96,
251 /* QEMU exceptions: used internally during code translation */
252 POWERPC_EXCP_STOP = 0x200, /* stop translation */
253 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
254 /* QEMU exceptions: special cases we want to stop translation */
255 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
256 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
257 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
258 };
259
260 /* Exceptions error codes */
261 enum {
262 /* Exception subtypes for POWERPC_EXCP_ALIGN */
263 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
264 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
265 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
266 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
267 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
268 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
269 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
270 /* FP exceptions */
271 POWERPC_EXCP_FP = 0x10,
272 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
273 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
274 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
275 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
276 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
277 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
278 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
279 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
280 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
281 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
282 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
283 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
284 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
285 /* Invalid instruction */
286 POWERPC_EXCP_INVAL = 0x20,
287 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
288 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
289 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
290 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
291 /* Privileged instruction */
292 POWERPC_EXCP_PRIV = 0x30,
293 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
294 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
295 /* Trap */
296 POWERPC_EXCP_TRAP = 0x40,
297 };
298
299 /*****************************************************************************/
300 /* Input pins model */
301 typedef enum powerpc_input_t powerpc_input_t;
302 enum powerpc_input_t {
303 PPC_FLAGS_INPUT_UNKNOWN = 0,
304 /* PowerPC 6xx bus */
305 PPC_FLAGS_INPUT_6xx,
306 /* BookE bus */
307 PPC_FLAGS_INPUT_BookE,
308 /* PowerPC 405 bus */
309 PPC_FLAGS_INPUT_405,
310 /* PowerPC 970 bus */
311 PPC_FLAGS_INPUT_970,
312 /* PowerPC POWER7 bus */
313 PPC_FLAGS_INPUT_POWER7,
314 /* PowerPC 401 bus */
315 PPC_FLAGS_INPUT_401,
316 /* Freescale RCPU bus */
317 PPC_FLAGS_INPUT_RCPU,
318 };
319
320 #define PPC_INPUT(env) (env->bus_model)
321
322 /*****************************************************************************/
323 typedef struct opc_handler_t opc_handler_t;
324
325 /*****************************************************************************/
326 /* Types used to describe some PowerPC registers */
327 typedef struct CPUPPCState CPUPPCState;
328 typedef struct DisasContext DisasContext;
329 typedef struct ppc_tb_t ppc_tb_t;
330 typedef struct ppc_spr_t ppc_spr_t;
331 typedef struct ppc_dcr_t ppc_dcr_t;
332 typedef union ppc_avr_t ppc_avr_t;
333 typedef union ppc_tlb_t ppc_tlb_t;
334
335 /* SPR access micro-ops generations callbacks */
336 struct ppc_spr_t {
337 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
338 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
339 #if !defined(CONFIG_USER_ONLY)
340 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
341 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
342 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
343 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
344 #endif
345 const char *name;
346 target_ulong default_value;
347 #ifdef CONFIG_KVM
348 /* We (ab)use the fact that all the SPRs will have ids for the
349 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
350 * don't sync this */
351 uint64_t one_reg_id;
352 #endif
353 };
354
355 /* Altivec registers (128 bits) */
356 union ppc_avr_t {
357 float32 f[4];
358 uint8_t u8[16];
359 uint16_t u16[8];
360 uint32_t u32[4];
361 int8_t s8[16];
362 int16_t s16[8];
363 int32_t s32[4];
364 uint64_t u64[2];
365 int64_t s64[2];
366 #ifdef CONFIG_INT128
367 __uint128_t u128;
368 #endif
369 };
370
371 #if !defined(CONFIG_USER_ONLY)
372 /* Software TLB cache */
373 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
374 struct ppc6xx_tlb_t {
375 target_ulong pte0;
376 target_ulong pte1;
377 target_ulong EPN;
378 };
379
380 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
381 struct ppcemb_tlb_t {
382 uint64_t RPN;
383 target_ulong EPN;
384 target_ulong PID;
385 target_ulong size;
386 uint32_t prot;
387 uint32_t attr; /* Storage attributes */
388 };
389
390 typedef struct ppcmas_tlb_t {
391 uint32_t mas8;
392 uint32_t mas1;
393 uint64_t mas2;
394 uint64_t mas7_3;
395 } ppcmas_tlb_t;
396
397 union ppc_tlb_t {
398 ppc6xx_tlb_t *tlb6;
399 ppcemb_tlb_t *tlbe;
400 ppcmas_tlb_t *tlbm;
401 };
402
403 /* possible TLB variants */
404 #define TLB_NONE 0
405 #define TLB_6XX 1
406 #define TLB_EMB 2
407 #define TLB_MAS 3
408 #endif
409
410 #define SDR_32_HTABORG 0xFFFF0000UL
411 #define SDR_32_HTABMASK 0x000001FFUL
412
413 #if defined(TARGET_PPC64)
414 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
415 #define SDR_64_HTABSIZE 0x000000000000001FULL
416 #endif /* defined(TARGET_PPC64 */
417
418 typedef struct ppc_slb_t ppc_slb_t;
419 struct ppc_slb_t {
420 uint64_t esid;
421 uint64_t vsid;
422 const struct ppc_one_seg_page_size *sps;
423 };
424
425 #define MAX_SLB_ENTRIES 64
426 #define SEGMENT_SHIFT_256M 28
427 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
428
429 #define SEGMENT_SHIFT_1T 40
430 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
431
432
433 /*****************************************************************************/
434 /* Machine state register bits definition */
435 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
436 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
437 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
438 #define MSR_SHV 60 /* hypervisor state hflags */
439 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
440 #define MSR_TS1 33
441 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
442 #define MSR_CM 31 /* Computation mode for BookE hflags */
443 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
444 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
445 #define MSR_GS 28 /* guest state for BookE */
446 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
447 #define MSR_VR 25 /* altivec available x hflags */
448 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
449 #define MSR_AP 23 /* Access privilege state on 602 hflags */
450 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
451 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
452 #define MSR_KEY 19 /* key bit on 603e */
453 #define MSR_POW 18 /* Power management */
454 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
455 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
456 #define MSR_ILE 16 /* Interrupt little-endian mode */
457 #define MSR_EE 15 /* External interrupt enable */
458 #define MSR_PR 14 /* Problem state hflags */
459 #define MSR_FP 13 /* Floating point available hflags */
460 #define MSR_ME 12 /* Machine check interrupt enable */
461 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
462 #define MSR_SE 10 /* Single-step trace enable x hflags */
463 #define MSR_DWE 10 /* Debug wait enable on 405 x */
464 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
465 #define MSR_BE 9 /* Branch trace enable x hflags */
466 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
467 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
468 #define MSR_AL 7 /* AL bit on POWER */
469 #define MSR_EP 6 /* Exception prefix on 601 */
470 #define MSR_IR 5 /* Instruction relocate */
471 #define MSR_DR 4 /* Data relocate */
472 #define MSR_PE 3 /* Protection enable on 403 */
473 #define MSR_PX 2 /* Protection exclusive on 403 x */
474 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
475 #define MSR_RI 1 /* Recoverable interrupt 1 */
476 #define MSR_LE 0 /* Little-endian mode 1 hflags */
477
478 #define LPCR_ILE (1 << (63-38))
479 #define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
480 #define LPCR_AIL (3 << LPCR_AIL_SHIFT)
481
482 #define msr_sf ((env->msr >> MSR_SF) & 1)
483 #define msr_isf ((env->msr >> MSR_ISF) & 1)
484 #define msr_shv ((env->msr >> MSR_SHV) & 1)
485 #define msr_cm ((env->msr >> MSR_CM) & 1)
486 #define msr_icm ((env->msr >> MSR_ICM) & 1)
487 #define msr_thv ((env->msr >> MSR_THV) & 1)
488 #define msr_gs ((env->msr >> MSR_GS) & 1)
489 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
490 #define msr_vr ((env->msr >> MSR_VR) & 1)
491 #define msr_spe ((env->msr >> MSR_SPE) & 1)
492 #define msr_ap ((env->msr >> MSR_AP) & 1)
493 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
494 #define msr_sa ((env->msr >> MSR_SA) & 1)
495 #define msr_key ((env->msr >> MSR_KEY) & 1)
496 #define msr_pow ((env->msr >> MSR_POW) & 1)
497 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
498 #define msr_ce ((env->msr >> MSR_CE) & 1)
499 #define msr_ile ((env->msr >> MSR_ILE) & 1)
500 #define msr_ee ((env->msr >> MSR_EE) & 1)
501 #define msr_pr ((env->msr >> MSR_PR) & 1)
502 #define msr_fp ((env->msr >> MSR_FP) & 1)
503 #define msr_me ((env->msr >> MSR_ME) & 1)
504 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
505 #define msr_se ((env->msr >> MSR_SE) & 1)
506 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
507 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
508 #define msr_be ((env->msr >> MSR_BE) & 1)
509 #define msr_de ((env->msr >> MSR_DE) & 1)
510 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
511 #define msr_al ((env->msr >> MSR_AL) & 1)
512 #define msr_ep ((env->msr >> MSR_EP) & 1)
513 #define msr_ir ((env->msr >> MSR_IR) & 1)
514 #define msr_dr ((env->msr >> MSR_DR) & 1)
515 #define msr_pe ((env->msr >> MSR_PE) & 1)
516 #define msr_px ((env->msr >> MSR_PX) & 1)
517 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
518 #define msr_ri ((env->msr >> MSR_RI) & 1)
519 #define msr_le ((env->msr >> MSR_LE) & 1)
520 #define msr_ts ((env->msr >> MSR_TS1) & 3)
521 #define msr_tm ((env->msr >> MSR_TM) & 1)
522
523 /* Hypervisor bit is more specific */
524 #if defined(TARGET_PPC64)
525 #define MSR_HVB (1ULL << MSR_SHV)
526 #define msr_hv msr_shv
527 #else
528 #if defined(PPC_EMULATE_32BITS_HYPV)
529 #define MSR_HVB (1ULL << MSR_THV)
530 #define msr_hv msr_thv
531 #else
532 #define MSR_HVB (0ULL)
533 #define msr_hv (0)
534 #endif
535 #endif
536
537 /* Facility Status and Control (FSCR) bits */
538 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
539 #define FSCR_TAR (63 - 55) /* Target Address Register */
540 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
541 #define FSCR_IC_MASK (0xFFULL)
542 #define FSCR_IC_POS (63 - 7)
543 #define FSCR_IC_DSCR_SPR3 2
544 #define FSCR_IC_PMU 3
545 #define FSCR_IC_BHRB 4
546 #define FSCR_IC_TM 5
547 #define FSCR_IC_EBB 7
548 #define FSCR_IC_TAR 8
549
550 /* Exception state register bits definition */
551 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
552 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
553 #define ESR_PTR (1 << (63 - 38)) /* Trap */
554 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
555 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
556 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
557 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
558 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
559 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
560 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
561 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
562 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
563 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
564 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
565 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
566 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
567
568 /* Transaction EXception And Summary Register bits */
569 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
570 #define TEXASR_DISALLOWED (63 - 8)
571 #define TEXASR_NESTING_OVERFLOW (63 - 9)
572 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
573 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
574 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
575 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
576 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
577 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
578 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
579 #define TEXASR_ABORT (63 - 31)
580 #define TEXASR_SUSPENDED (63 - 32)
581 #define TEXASR_PRIVILEGE_HV (63 - 34)
582 #define TEXASR_PRIVILEGE_PR (63 - 35)
583 #define TEXASR_FAILURE_SUMMARY (63 - 36)
584 #define TEXASR_TFIAR_EXACT (63 - 37)
585 #define TEXASR_ROT (63 - 38)
586 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
587
588 enum {
589 POWERPC_FLAG_NONE = 0x00000000,
590 /* Flag for MSR bit 25 signification (VRE/SPE) */
591 POWERPC_FLAG_SPE = 0x00000001,
592 POWERPC_FLAG_VRE = 0x00000002,
593 /* Flag for MSR bit 17 signification (TGPR/CE) */
594 POWERPC_FLAG_TGPR = 0x00000004,
595 POWERPC_FLAG_CE = 0x00000008,
596 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
597 POWERPC_FLAG_SE = 0x00000010,
598 POWERPC_FLAG_DWE = 0x00000020,
599 POWERPC_FLAG_UBLE = 0x00000040,
600 /* Flag for MSR bit 9 signification (BE/DE) */
601 POWERPC_FLAG_BE = 0x00000080,
602 POWERPC_FLAG_DE = 0x00000100,
603 /* Flag for MSR bit 2 signification (PX/PMM) */
604 POWERPC_FLAG_PX = 0x00000200,
605 POWERPC_FLAG_PMM = 0x00000400,
606 /* Flag for special features */
607 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
608 POWERPC_FLAG_RTC_CLK = 0x00010000,
609 POWERPC_FLAG_BUS_CLK = 0x00020000,
610 /* Has CFAR */
611 POWERPC_FLAG_CFAR = 0x00040000,
612 /* Has VSX */
613 POWERPC_FLAG_VSX = 0x00080000,
614 /* Has Transaction Memory (ISA 2.07) */
615 POWERPC_FLAG_TM = 0x00100000,
616 };
617
618 /*****************************************************************************/
619 /* Floating point status and control register */
620 #define FPSCR_FX 31 /* Floating-point exception summary */
621 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
622 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
623 #define FPSCR_OX 28 /* Floating-point overflow exception */
624 #define FPSCR_UX 27 /* Floating-point underflow exception */
625 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
626 #define FPSCR_XX 25 /* Floating-point inexact exception */
627 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
628 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
629 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
630 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
631 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
632 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
633 #define FPSCR_FR 18 /* Floating-point fraction rounded */
634 #define FPSCR_FI 17 /* Floating-point fraction inexact */
635 #define FPSCR_C 16 /* Floating-point result class descriptor */
636 #define FPSCR_FL 15 /* Floating-point less than or negative */
637 #define FPSCR_FG 14 /* Floating-point greater than or negative */
638 #define FPSCR_FE 13 /* Floating-point equal or zero */
639 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
640 #define FPSCR_FPCC 12 /* Floating-point condition code */
641 #define FPSCR_FPRF 12 /* Floating-point result flags */
642 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
643 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
644 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
645 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
646 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
647 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
648 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
649 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
650 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
651 #define FPSCR_RN1 1
652 #define FPSCR_RN 0 /* Floating-point rounding control */
653 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
654 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
655 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
656 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
657 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
658 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
659 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
660 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
661 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
662 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
663 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
664 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
665 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
666 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
667 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
668 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
669 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
670 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
671 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
672 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
673 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
674 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
675 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
676 /* Invalid operation exception summary */
677 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
678 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
679 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
680 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
681 (1 << FPSCR_VXCVI)))
682 /* exception summary */
683 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
684 /* enabled exception summary */
685 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
686 0x1F)
687
688 #define FP_FX (1ull << FPSCR_FX)
689 #define FP_FEX (1ull << FPSCR_FEX)
690 #define FP_VX (1ull << FPSCR_VX)
691 #define FP_OX (1ull << FPSCR_OX)
692 #define FP_UX (1ull << FPSCR_UX)
693 #define FP_ZX (1ull << FPSCR_ZX)
694 #define FP_XX (1ull << FPSCR_XX)
695 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
696 #define FP_VXISI (1ull << FPSCR_VXISI)
697 #define FP_VXIDI (1ull << FPSCR_VXIDI)
698 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
699 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
700 #define FP_VXVC (1ull << FPSCR_VXVC)
701 #define FP_FR (1ull << FSPCR_FR)
702 #define FP_FI (1ull << FPSCR_FI)
703 #define FP_C (1ull << FPSCR_C)
704 #define FP_FL (1ull << FPSCR_FL)
705 #define FP_FG (1ull << FPSCR_FG)
706 #define FP_FE (1ull << FPSCR_FE)
707 #define FP_FU (1ull << FPSCR_FU)
708 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
709 #define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
710 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
711 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
712 #define FP_VXCVI (1ull << FPSCR_VXCVI)
713 #define FP_VE (1ull << FPSCR_VE)
714 #define FP_OE (1ull << FPSCR_OE)
715 #define FP_UE (1ull << FPSCR_UE)
716 #define FP_ZE (1ull << FPSCR_ZE)
717 #define FP_XE (1ull << FPSCR_XE)
718 #define FP_NI (1ull << FPSCR_NI)
719 #define FP_RN1 (1ull << FPSCR_RN1)
720 #define FP_RN (1ull << FPSCR_RN)
721
722 /* the exception bits which can be cleared by mcrfs - includes FX */
723 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
724 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
725 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
726 FP_VXSQRT | FP_VXCVI)
727
728 /*****************************************************************************/
729 /* Vector status and control register */
730 #define VSCR_NJ 16 /* Vector non-java */
731 #define VSCR_SAT 0 /* Vector saturation */
732 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
733 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
734
735 /*****************************************************************************/
736 /* BookE e500 MMU registers */
737
738 #define MAS0_NV_SHIFT 0
739 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
740
741 #define MAS0_WQ_SHIFT 12
742 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
743 /* Write TLB entry regardless of reservation */
744 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
745 /* Write TLB entry only already in use */
746 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
747 /* Clear TLB entry */
748 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
749
750 #define MAS0_HES_SHIFT 14
751 #define MAS0_HES (1 << MAS0_HES_SHIFT)
752
753 #define MAS0_ESEL_SHIFT 16
754 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
755
756 #define MAS0_TLBSEL_SHIFT 28
757 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
758 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
759 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
760 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
761 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
762
763 #define MAS0_ATSEL_SHIFT 31
764 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
765 #define MAS0_ATSEL_TLB 0
766 #define MAS0_ATSEL_LRAT MAS0_ATSEL
767
768 #define MAS1_TSIZE_SHIFT 7
769 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
770
771 #define MAS1_TS_SHIFT 12
772 #define MAS1_TS (1 << MAS1_TS_SHIFT)
773
774 #define MAS1_IND_SHIFT 13
775 #define MAS1_IND (1 << MAS1_IND_SHIFT)
776
777 #define MAS1_TID_SHIFT 16
778 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
779
780 #define MAS1_IPROT_SHIFT 30
781 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
782
783 #define MAS1_VALID_SHIFT 31
784 #define MAS1_VALID 0x80000000
785
786 #define MAS2_EPN_SHIFT 12
787 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
788
789 #define MAS2_ACM_SHIFT 6
790 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
791
792 #define MAS2_VLE_SHIFT 5
793 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
794
795 #define MAS2_W_SHIFT 4
796 #define MAS2_W (1 << MAS2_W_SHIFT)
797
798 #define MAS2_I_SHIFT 3
799 #define MAS2_I (1 << MAS2_I_SHIFT)
800
801 #define MAS2_M_SHIFT 2
802 #define MAS2_M (1 << MAS2_M_SHIFT)
803
804 #define MAS2_G_SHIFT 1
805 #define MAS2_G (1 << MAS2_G_SHIFT)
806
807 #define MAS2_E_SHIFT 0
808 #define MAS2_E (1 << MAS2_E_SHIFT)
809
810 #define MAS3_RPN_SHIFT 12
811 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
812
813 #define MAS3_U0 0x00000200
814 #define MAS3_U1 0x00000100
815 #define MAS3_U2 0x00000080
816 #define MAS3_U3 0x00000040
817 #define MAS3_UX 0x00000020
818 #define MAS3_SX 0x00000010
819 #define MAS3_UW 0x00000008
820 #define MAS3_SW 0x00000004
821 #define MAS3_UR 0x00000002
822 #define MAS3_SR 0x00000001
823 #define MAS3_SPSIZE_SHIFT 1
824 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
825
826 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
827 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
828 #define MAS4_TIDSELD_MASK 0x00030000
829 #define MAS4_TIDSELD_PID0 0x00000000
830 #define MAS4_TIDSELD_PID1 0x00010000
831 #define MAS4_TIDSELD_PID2 0x00020000
832 #define MAS4_TIDSELD_PIDZ 0x00030000
833 #define MAS4_INDD 0x00008000 /* Default IND */
834 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
835 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
836 #define MAS4_ACMD 0x00000040
837 #define MAS4_VLED 0x00000020
838 #define MAS4_WD 0x00000010
839 #define MAS4_ID 0x00000008
840 #define MAS4_MD 0x00000004
841 #define MAS4_GD 0x00000002
842 #define MAS4_ED 0x00000001
843 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
844 #define MAS4_WIMGED_SHIFT 0
845
846 #define MAS5_SGS 0x80000000
847 #define MAS5_SLPID_MASK 0x00000fff
848
849 #define MAS6_SPID0 0x3fff0000
850 #define MAS6_SPID1 0x00007ffe
851 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
852 #define MAS6_SAS 0x00000001
853 #define MAS6_SPID MAS6_SPID0
854 #define MAS6_SIND 0x00000002 /* Indirect page */
855 #define MAS6_SIND_SHIFT 1
856 #define MAS6_SPID_MASK 0x3fff0000
857 #define MAS6_SPID_SHIFT 16
858 #define MAS6_ISIZE_MASK 0x00000f80
859 #define MAS6_ISIZE_SHIFT 7
860
861 #define MAS7_RPN 0xffffffff
862
863 #define MAS8_TGS 0x80000000
864 #define MAS8_VF 0x40000000
865 #define MAS8_TLBPID 0x00000fff
866
867 /* Bit definitions for MMUCFG */
868 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
869 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
870 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
871 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
872 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
873 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
874 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
875 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
876 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
877
878 /* Bit definitions for MMUCSR0 */
879 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
880 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
881 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
882 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
883 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
884 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
885 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
886 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
887 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
888 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
889
890 /* TLBnCFG encoding */
891 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
892 #define TLBnCFG_HES 0x00002000 /* HW select supported */
893 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
894 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
895 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
896 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
897 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
898 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
899 #define TLBnCFG_MINSIZE_SHIFT 20
900 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
901 #define TLBnCFG_MAXSIZE_SHIFT 16
902 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
903 #define TLBnCFG_ASSOC_SHIFT 24
904
905 /* TLBnPS encoding */
906 #define TLBnPS_4K 0x00000004
907 #define TLBnPS_8K 0x00000008
908 #define TLBnPS_16K 0x00000010
909 #define TLBnPS_32K 0x00000020
910 #define TLBnPS_64K 0x00000040
911 #define TLBnPS_128K 0x00000080
912 #define TLBnPS_256K 0x00000100
913 #define TLBnPS_512K 0x00000200
914 #define TLBnPS_1M 0x00000400
915 #define TLBnPS_2M 0x00000800
916 #define TLBnPS_4M 0x00001000
917 #define TLBnPS_8M 0x00002000
918 #define TLBnPS_16M 0x00004000
919 #define TLBnPS_32M 0x00008000
920 #define TLBnPS_64M 0x00010000
921 #define TLBnPS_128M 0x00020000
922 #define TLBnPS_256M 0x00040000
923 #define TLBnPS_512M 0x00080000
924 #define TLBnPS_1G 0x00100000
925 #define TLBnPS_2G 0x00200000
926 #define TLBnPS_4G 0x00400000
927 #define TLBnPS_8G 0x00800000
928 #define TLBnPS_16G 0x01000000
929 #define TLBnPS_32G 0x02000000
930 #define TLBnPS_64G 0x04000000
931 #define TLBnPS_128G 0x08000000
932 #define TLBnPS_256G 0x10000000
933
934 /* tlbilx action encoding */
935 #define TLBILX_T_ALL 0
936 #define TLBILX_T_TID 1
937 #define TLBILX_T_FULLMATCH 3
938 #define TLBILX_T_CLASS0 4
939 #define TLBILX_T_CLASS1 5
940 #define TLBILX_T_CLASS2 6
941 #define TLBILX_T_CLASS3 7
942
943 /* BookE 2.06 helper defines */
944
945 #define BOOKE206_FLUSH_TLB0 (1 << 0)
946 #define BOOKE206_FLUSH_TLB1 (1 << 1)
947 #define BOOKE206_FLUSH_TLB2 (1 << 2)
948 #define BOOKE206_FLUSH_TLB3 (1 << 3)
949
950 /* number of possible TLBs */
951 #define BOOKE206_MAX_TLBN 4
952
953 /*****************************************************************************/
954 /* Embedded.Processor Control */
955
956 #define DBELL_TYPE_SHIFT 27
957 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
958 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
959 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
960 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
961 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
962 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
963
964 #define DBELL_BRDCAST (1 << 26)
965 #define DBELL_LPIDTAG_SHIFT 14
966 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
967 #define DBELL_PIRTAG_MASK 0x3fff
968
969 /*****************************************************************************/
970 /* Segment page size information, used by recent hash MMUs
971 * The format of this structure mirrors kvm_ppc_smmu_info
972 */
973
974 #define PPC_PAGE_SIZES_MAX_SZ 8
975
976 struct ppc_one_page_size {
977 uint32_t page_shift; /* Page shift (or 0) */
978 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
979 };
980
981 struct ppc_one_seg_page_size {
982 uint32_t page_shift; /* Base page shift of segment (or 0) */
983 uint32_t slb_enc; /* SLB encoding for BookS */
984 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
985 };
986
987 struct ppc_segment_page_sizes {
988 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
989 };
990
991
992 /*****************************************************************************/
993 /* The whole PowerPC CPU context */
994 #define NB_MMU_MODES 3
995
996 #define PPC_CPU_OPCODES_LEN 0x40
997 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
998
999 struct CPUPPCState {
1000 /* First are the most commonly used resources
1001 * during translated code execution
1002 */
1003 /* general purpose registers */
1004 target_ulong gpr[32];
1005 /* Storage for GPR MSB, used by the SPE extension */
1006 target_ulong gprh[32];
1007 /* LR */
1008 target_ulong lr;
1009 /* CTR */
1010 target_ulong ctr;
1011 /* condition register */
1012 uint32_t crf[8];
1013 #if defined(TARGET_PPC64)
1014 /* CFAR */
1015 target_ulong cfar;
1016 #endif
1017 /* XER (with SO, OV, CA split out) */
1018 target_ulong xer;
1019 target_ulong so;
1020 target_ulong ov;
1021 target_ulong ca;
1022 /* Reservation address */
1023 target_ulong reserve_addr;
1024 /* Reservation value */
1025 target_ulong reserve_val;
1026 target_ulong reserve_val2;
1027 /* Reservation store address */
1028 target_ulong reserve_ea;
1029 /* Reserved store source register and size */
1030 target_ulong reserve_info;
1031
1032 /* Those ones are used in supervisor mode only */
1033 /* machine state register */
1034 target_ulong msr;
1035 /* temporary general purpose registers */
1036 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1037
1038 /* Floating point execution context */
1039 float_status fp_status;
1040 /* floating point registers */
1041 float64 fpr[32];
1042 /* floating point status and control register */
1043 target_ulong fpscr;
1044
1045 /* Next instruction pointer */
1046 target_ulong nip;
1047
1048 int access_type; /* when a memory exception occurs, the access
1049 type is stored here */
1050
1051 CPU_COMMON
1052
1053 /* MMU context - only relevant for full system emulation */
1054 #if !defined(CONFIG_USER_ONLY)
1055 #if defined(TARGET_PPC64)
1056 /* PowerPC 64 SLB area */
1057 ppc_slb_t slb[MAX_SLB_ENTRIES];
1058 int32_t slb_nr;
1059 #endif
1060 /* segment registers */
1061 hwaddr htab_base;
1062 /* mask used to normalize hash value to PTEG index */
1063 hwaddr htab_mask;
1064 target_ulong sr[32];
1065 /* externally stored hash table */
1066 uint8_t *external_htab;
1067 /* BATs */
1068 uint32_t nb_BATs;
1069 target_ulong DBAT[2][8];
1070 target_ulong IBAT[2][8];
1071 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1072 int32_t nb_tlb; /* Total number of TLB */
1073 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1074 int nb_ways; /* Number of ways in the TLB set */
1075 int last_way; /* Last used way used to allocate TLB in a LRU way */
1076 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1077 int nb_pids; /* Number of available PID registers */
1078 int tlb_type; /* Type of TLB we're dealing with */
1079 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1080 /* 403 dedicated access protection registers */
1081 target_ulong pb[4];
1082 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1083 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1084 #endif
1085
1086 /* Other registers */
1087 /* Special purpose registers */
1088 target_ulong spr[1024];
1089 ppc_spr_t spr_cb[1024];
1090 /* Altivec registers */
1091 ppc_avr_t avr[32];
1092 uint32_t vscr;
1093 /* VSX registers */
1094 uint64_t vsr[32];
1095 /* SPE registers */
1096 uint64_t spe_acc;
1097 uint32_t spe_fscr;
1098 /* SPE and Altivec can share a status since they will never be used
1099 * simultaneously */
1100 float_status vec_status;
1101
1102 /* Internal devices resources */
1103 /* Time base and decrementer */
1104 ppc_tb_t *tb_env;
1105 /* Device control registers */
1106 ppc_dcr_t *dcr_env;
1107
1108 int dcache_line_size;
1109 int icache_line_size;
1110
1111 /* Those resources are used during exception processing */
1112 /* CPU model definition */
1113 target_ulong msr_mask;
1114 powerpc_mmu_t mmu_model;
1115 powerpc_excp_t excp_model;
1116 powerpc_input_t bus_model;
1117 int bfd_mach;
1118 uint32_t flags;
1119 uint64_t insns_flags;
1120 uint64_t insns_flags2;
1121 #if defined(TARGET_PPC64)
1122 struct ppc_segment_page_sizes sps;
1123 bool ci_large_pages;
1124 #endif
1125
1126 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1127 uint64_t vpa_addr;
1128 uint64_t slb_shadow_addr, slb_shadow_size;
1129 uint64_t dtl_addr, dtl_size;
1130 #endif /* TARGET_PPC64 */
1131
1132 int error_code;
1133 uint32_t pending_interrupts;
1134 #if !defined(CONFIG_USER_ONLY)
1135 /* This is the IRQ controller, which is implementation dependent
1136 * and only relevant when emulating a complete machine.
1137 */
1138 uint32_t irq_input_state;
1139 void **irq_inputs;
1140 /* Exception vectors */
1141 target_ulong excp_vectors[POWERPC_EXCP_NB];
1142 target_ulong excp_prefix;
1143 target_ulong ivor_mask;
1144 target_ulong ivpr_mask;
1145 target_ulong hreset_vector;
1146 hwaddr mpic_iack;
1147 /* true when the external proxy facility mode is enabled */
1148 bool mpic_proxy;
1149 #endif
1150
1151 /* Those resources are used only during code translation */
1152 /* opcode handlers */
1153 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1154
1155 /* Those resources are used only in QEMU core */
1156 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1157 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1158 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1159
1160 /* Power management */
1161 int (*check_pow)(CPUPPCState *env);
1162
1163 #if !defined(CONFIG_USER_ONLY)
1164 void *load_info; /* Holds boot loading state. */
1165 #endif
1166
1167 /* booke timers */
1168
1169 /* Specifies bit locations of the Time Base used to signal a fixed timer
1170 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1171 *
1172 * 0 selects the least significant bit.
1173 * 63 selects the most significant bit.
1174 */
1175 uint8_t fit_period[4];
1176 uint8_t wdt_period[4];
1177
1178 /* Transactional memory state */
1179 target_ulong tm_gpr[32];
1180 ppc_avr_t tm_vsr[64];
1181 uint64_t tm_cr;
1182 uint64_t tm_lr;
1183 uint64_t tm_ctr;
1184 uint64_t tm_fpscr;
1185 uint64_t tm_amr;
1186 uint64_t tm_ppr;
1187 uint64_t tm_vrsave;
1188 uint32_t tm_vscr;
1189 uint64_t tm_dscr;
1190 uint64_t tm_tar;
1191 };
1192
1193 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1194 do { \
1195 env->fit_period[0] = (a_); \
1196 env->fit_period[1] = (b_); \
1197 env->fit_period[2] = (c_); \
1198 env->fit_period[3] = (d_); \
1199 } while (0)
1200
1201 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1202 do { \
1203 env->wdt_period[0] = (a_); \
1204 env->wdt_period[1] = (b_); \
1205 env->wdt_period[2] = (c_); \
1206 env->wdt_period[3] = (d_); \
1207 } while (0)
1208
1209 #include "cpu-qom.h"
1210
1211 /*****************************************************************************/
1212 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1213 void ppc_translate_init(void);
1214 void gen_update_current_nip(void *opaque);
1215 int cpu_ppc_exec (CPUState *s);
1216 /* you can call this signal handler from your SIGBUS and SIGSEGV
1217 signal handlers to inform the virtual CPU of exceptions. non zero
1218 is returned if the signal was handled by the virtual CPU. */
1219 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1220 void *puc);
1221 #if defined(CONFIG_USER_ONLY)
1222 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1223 int mmu_idx);
1224 #endif
1225
1226 #if !defined(CONFIG_USER_ONLY)
1227 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1228 #endif /* !defined(CONFIG_USER_ONLY) */
1229 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1230
1231 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1232 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1233 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
1234
1235 /* Time-base and decrementer management */
1236 #ifndef NO_CPU_IO_DEFS
1237 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1238 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1239 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1240 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1241 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1242 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1243 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1244 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1245 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1246 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1247 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1248 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1249 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1250 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1251 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1252 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1253 #if !defined(CONFIG_USER_ONLY)
1254 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1255 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1256 target_ulong load_40x_pit (CPUPPCState *env);
1257 void store_40x_pit (CPUPPCState *env, target_ulong val);
1258 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1259 void store_40x_sler (CPUPPCState *env, uint32_t val);
1260 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1261 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1262 void ppc_tlb_invalidate_all (CPUPPCState *env);
1263 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1264 #endif
1265 #endif
1266
1267 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1268
1269 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1270 {
1271 uint64_t gprv;
1272
1273 gprv = env->gpr[gprn];
1274 if (env->flags & POWERPC_FLAG_SPE) {
1275 /* If the CPU implements the SPE extension, we have to get the
1276 * high bits of the GPR from the gprh storage area
1277 */
1278 gprv &= 0xFFFFFFFFULL;
1279 gprv |= (uint64_t)env->gprh[gprn] << 32;
1280 }
1281
1282 return gprv;
1283 }
1284
1285 /* Device control registers */
1286 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1287 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1288
1289 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1290
1291 #define cpu_exec cpu_ppc_exec
1292 #define cpu_signal_handler cpu_ppc_signal_handler
1293 #define cpu_list ppc_cpu_list
1294
1295 /* MMU modes definitions */
1296 #define MMU_MODE0_SUFFIX _user
1297 #define MMU_MODE1_SUFFIX _kernel
1298 #define MMU_MODE2_SUFFIX _hypv
1299 #define MMU_USER_IDX 0
1300 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1301 {
1302 return env->mmu_idx;
1303 }
1304
1305 #include "exec/cpu-all.h"
1306
1307 /*****************************************************************************/
1308 /* CRF definitions */
1309 #define CRF_LT 3
1310 #define CRF_GT 2
1311 #define CRF_EQ 1
1312 #define CRF_SO 0
1313 #define CRF_CH (1 << CRF_LT)
1314 #define CRF_CL (1 << CRF_GT)
1315 #define CRF_CH_OR_CL (1 << CRF_EQ)
1316 #define CRF_CH_AND_CL (1 << CRF_SO)
1317
1318 /* XER definitions */
1319 #define XER_SO 31
1320 #define XER_OV 30
1321 #define XER_CA 29
1322 #define XER_CMP 8
1323 #define XER_BC 0
1324 #define xer_so (env->so)
1325 #define xer_ov (env->ov)
1326 #define xer_ca (env->ca)
1327 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1328 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1329
1330 /* SPR definitions */
1331 #define SPR_MQ (0x000)
1332 #define SPR_XER (0x001)
1333 #define SPR_601_VRTCU (0x004)
1334 #define SPR_601_VRTCL (0x005)
1335 #define SPR_601_UDECR (0x006)
1336 #define SPR_LR (0x008)
1337 #define SPR_CTR (0x009)
1338 #define SPR_UAMR (0x00C)
1339 #define SPR_DSCR (0x011)
1340 #define SPR_DSISR (0x012)
1341 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1342 #define SPR_601_RTCU (0x014)
1343 #define SPR_601_RTCL (0x015)
1344 #define SPR_DECR (0x016)
1345 #define SPR_SDR1 (0x019)
1346 #define SPR_SRR0 (0x01A)
1347 #define SPR_SRR1 (0x01B)
1348 #define SPR_CFAR (0x01C)
1349 #define SPR_AMR (0x01D)
1350 #define SPR_BOOKE_PID (0x030)
1351 #define SPR_BOOKE_DECAR (0x036)
1352 #define SPR_BOOKE_CSRR0 (0x03A)
1353 #define SPR_BOOKE_CSRR1 (0x03B)
1354 #define SPR_BOOKE_DEAR (0x03D)
1355 #define SPR_BOOKE_ESR (0x03E)
1356 #define SPR_BOOKE_IVPR (0x03F)
1357 #define SPR_MPC_EIE (0x050)
1358 #define SPR_MPC_EID (0x051)
1359 #define SPR_MPC_NRI (0x052)
1360 #define SPR_TFHAR (0x080)
1361 #define SPR_TFIAR (0x081)
1362 #define SPR_TEXASR (0x082)
1363 #define SPR_TEXASRU (0x083)
1364 #define SPR_UCTRL (0x088)
1365 #define SPR_MPC_CMPA (0x090)
1366 #define SPR_MPC_CMPB (0x091)
1367 #define SPR_MPC_CMPC (0x092)
1368 #define SPR_MPC_CMPD (0x093)
1369 #define SPR_MPC_ECR (0x094)
1370 #define SPR_MPC_DER (0x095)
1371 #define SPR_MPC_COUNTA (0x096)
1372 #define SPR_MPC_COUNTB (0x097)
1373 #define SPR_CTRL (0x098)
1374 #define SPR_MPC_CMPE (0x098)
1375 #define SPR_MPC_CMPF (0x099)
1376 #define SPR_FSCR (0x099)
1377 #define SPR_MPC_CMPG (0x09A)
1378 #define SPR_MPC_CMPH (0x09B)
1379 #define SPR_MPC_LCTRL1 (0x09C)
1380 #define SPR_MPC_LCTRL2 (0x09D)
1381 #define SPR_UAMOR (0x09D)
1382 #define SPR_MPC_ICTRL (0x09E)
1383 #define SPR_MPC_BAR (0x09F)
1384 #define SPR_VRSAVE (0x100)
1385 #define SPR_USPRG0 (0x100)
1386 #define SPR_USPRG1 (0x101)
1387 #define SPR_USPRG2 (0x102)
1388 #define SPR_USPRG3 (0x103)
1389 #define SPR_USPRG4 (0x104)
1390 #define SPR_USPRG5 (0x105)
1391 #define SPR_USPRG6 (0x106)
1392 #define SPR_USPRG7 (0x107)
1393 #define SPR_VTBL (0x10C)
1394 #define SPR_VTBU (0x10D)
1395 #define SPR_SPRG0 (0x110)
1396 #define SPR_SPRG1 (0x111)
1397 #define SPR_SPRG2 (0x112)
1398 #define SPR_SPRG3 (0x113)
1399 #define SPR_SPRG4 (0x114)
1400 #define SPR_SCOMC (0x114)
1401 #define SPR_SPRG5 (0x115)
1402 #define SPR_SCOMD (0x115)
1403 #define SPR_SPRG6 (0x116)
1404 #define SPR_SPRG7 (0x117)
1405 #define SPR_ASR (0x118)
1406 #define SPR_EAR (0x11A)
1407 #define SPR_TBL (0x11C)
1408 #define SPR_TBU (0x11D)
1409 #define SPR_TBU40 (0x11E)
1410 #define SPR_SVR (0x11E)
1411 #define SPR_BOOKE_PIR (0x11E)
1412 #define SPR_PVR (0x11F)
1413 #define SPR_HSPRG0 (0x130)
1414 #define SPR_BOOKE_DBSR (0x130)
1415 #define SPR_HSPRG1 (0x131)
1416 #define SPR_HDSISR (0x132)
1417 #define SPR_HDAR (0x133)
1418 #define SPR_BOOKE_EPCR (0x133)
1419 #define SPR_SPURR (0x134)
1420 #define SPR_BOOKE_DBCR0 (0x134)
1421 #define SPR_IBCR (0x135)
1422 #define SPR_PURR (0x135)
1423 #define SPR_BOOKE_DBCR1 (0x135)
1424 #define SPR_DBCR (0x136)
1425 #define SPR_HDEC (0x136)
1426 #define SPR_BOOKE_DBCR2 (0x136)
1427 #define SPR_HIOR (0x137)
1428 #define SPR_MBAR (0x137)
1429 #define SPR_RMOR (0x138)
1430 #define SPR_BOOKE_IAC1 (0x138)
1431 #define SPR_HRMOR (0x139)
1432 #define SPR_BOOKE_IAC2 (0x139)
1433 #define SPR_HSRR0 (0x13A)
1434 #define SPR_BOOKE_IAC3 (0x13A)
1435 #define SPR_HSRR1 (0x13B)
1436 #define SPR_BOOKE_IAC4 (0x13B)
1437 #define SPR_BOOKE_DAC1 (0x13C)
1438 #define SPR_LPIDR (0x13D)
1439 #define SPR_DABR2 (0x13D)
1440 #define SPR_BOOKE_DAC2 (0x13D)
1441 #define SPR_BOOKE_DVC1 (0x13E)
1442 #define SPR_LPCR (0x13E)
1443 #define SPR_BOOKE_DVC2 (0x13F)
1444 #define SPR_BOOKE_TSR (0x150)
1445 #define SPR_PCR (0x152)
1446 #define SPR_BOOKE_TCR (0x154)
1447 #define SPR_BOOKE_TLB0PS (0x158)
1448 #define SPR_BOOKE_TLB1PS (0x159)
1449 #define SPR_BOOKE_TLB2PS (0x15A)
1450 #define SPR_BOOKE_TLB3PS (0x15B)
1451 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1452 #define SPR_BOOKE_IVOR0 (0x190)
1453 #define SPR_BOOKE_IVOR1 (0x191)
1454 #define SPR_BOOKE_IVOR2 (0x192)
1455 #define SPR_BOOKE_IVOR3 (0x193)
1456 #define SPR_BOOKE_IVOR4 (0x194)
1457 #define SPR_BOOKE_IVOR5 (0x195)
1458 #define SPR_BOOKE_IVOR6 (0x196)
1459 #define SPR_BOOKE_IVOR7 (0x197)
1460 #define SPR_BOOKE_IVOR8 (0x198)
1461 #define SPR_BOOKE_IVOR9 (0x199)
1462 #define SPR_BOOKE_IVOR10 (0x19A)
1463 #define SPR_BOOKE_IVOR11 (0x19B)
1464 #define SPR_BOOKE_IVOR12 (0x19C)
1465 #define SPR_BOOKE_IVOR13 (0x19D)
1466 #define SPR_BOOKE_IVOR14 (0x19E)
1467 #define SPR_BOOKE_IVOR15 (0x19F)
1468 #define SPR_BOOKE_IVOR38 (0x1B0)
1469 #define SPR_BOOKE_IVOR39 (0x1B1)
1470 #define SPR_BOOKE_IVOR40 (0x1B2)
1471 #define SPR_BOOKE_IVOR41 (0x1B3)
1472 #define SPR_BOOKE_IVOR42 (0x1B4)
1473 #define SPR_BOOKE_GIVOR2 (0x1B8)
1474 #define SPR_BOOKE_GIVOR3 (0x1B9)
1475 #define SPR_BOOKE_GIVOR4 (0x1BA)
1476 #define SPR_BOOKE_GIVOR8 (0x1BB)
1477 #define SPR_BOOKE_GIVOR13 (0x1BC)
1478 #define SPR_BOOKE_GIVOR14 (0x1BD)
1479 #define SPR_TIR (0x1BE)
1480 #define SPR_BOOKE_SPEFSCR (0x200)
1481 #define SPR_Exxx_BBEAR (0x201)
1482 #define SPR_Exxx_BBTAR (0x202)
1483 #define SPR_Exxx_L1CFG0 (0x203)
1484 #define SPR_Exxx_L1CFG1 (0x204)
1485 #define SPR_Exxx_NPIDR (0x205)
1486 #define SPR_ATBL (0x20E)
1487 #define SPR_ATBU (0x20F)
1488 #define SPR_IBAT0U (0x210)
1489 #define SPR_BOOKE_IVOR32 (0x210)
1490 #define SPR_RCPU_MI_GRA (0x210)
1491 #define SPR_IBAT0L (0x211)
1492 #define SPR_BOOKE_IVOR33 (0x211)
1493 #define SPR_IBAT1U (0x212)
1494 #define SPR_BOOKE_IVOR34 (0x212)
1495 #define SPR_IBAT1L (0x213)
1496 #define SPR_BOOKE_IVOR35 (0x213)
1497 #define SPR_IBAT2U (0x214)
1498 #define SPR_BOOKE_IVOR36 (0x214)
1499 #define SPR_IBAT2L (0x215)
1500 #define SPR_BOOKE_IVOR37 (0x215)
1501 #define SPR_IBAT3U (0x216)
1502 #define SPR_IBAT3L (0x217)
1503 #define SPR_DBAT0U (0x218)
1504 #define SPR_RCPU_L2U_GRA (0x218)
1505 #define SPR_DBAT0L (0x219)
1506 #define SPR_DBAT1U (0x21A)
1507 #define SPR_DBAT1L (0x21B)
1508 #define SPR_DBAT2U (0x21C)
1509 #define SPR_DBAT2L (0x21D)
1510 #define SPR_DBAT3U (0x21E)
1511 #define SPR_DBAT3L (0x21F)
1512 #define SPR_IBAT4U (0x230)
1513 #define SPR_RPCU_BBCMCR (0x230)
1514 #define SPR_MPC_IC_CST (0x230)
1515 #define SPR_Exxx_CTXCR (0x230)
1516 #define SPR_IBAT4L (0x231)
1517 #define SPR_MPC_IC_ADR (0x231)
1518 #define SPR_Exxx_DBCR3 (0x231)
1519 #define SPR_IBAT5U (0x232)
1520 #define SPR_MPC_IC_DAT (0x232)
1521 #define SPR_Exxx_DBCNT (0x232)
1522 #define SPR_IBAT5L (0x233)
1523 #define SPR_IBAT6U (0x234)
1524 #define SPR_IBAT6L (0x235)
1525 #define SPR_IBAT7U (0x236)
1526 #define SPR_IBAT7L (0x237)
1527 #define SPR_DBAT4U (0x238)
1528 #define SPR_RCPU_L2U_MCR (0x238)
1529 #define SPR_MPC_DC_CST (0x238)
1530 #define SPR_Exxx_ALTCTXCR (0x238)
1531 #define SPR_DBAT4L (0x239)
1532 #define SPR_MPC_DC_ADR (0x239)
1533 #define SPR_DBAT5U (0x23A)
1534 #define SPR_BOOKE_MCSRR0 (0x23A)
1535 #define SPR_MPC_DC_DAT (0x23A)
1536 #define SPR_DBAT5L (0x23B)
1537 #define SPR_BOOKE_MCSRR1 (0x23B)
1538 #define SPR_DBAT6U (0x23C)
1539 #define SPR_BOOKE_MCSR (0x23C)
1540 #define SPR_DBAT6L (0x23D)
1541 #define SPR_Exxx_MCAR (0x23D)
1542 #define SPR_DBAT7U (0x23E)
1543 #define SPR_BOOKE_DSRR0 (0x23E)
1544 #define SPR_DBAT7L (0x23F)
1545 #define SPR_BOOKE_DSRR1 (0x23F)
1546 #define SPR_BOOKE_SPRG8 (0x25C)
1547 #define SPR_BOOKE_SPRG9 (0x25D)
1548 #define SPR_BOOKE_MAS0 (0x270)
1549 #define SPR_BOOKE_MAS1 (0x271)
1550 #define SPR_BOOKE_MAS2 (0x272)
1551 #define SPR_BOOKE_MAS3 (0x273)
1552 #define SPR_BOOKE_MAS4 (0x274)
1553 #define SPR_BOOKE_MAS5 (0x275)
1554 #define SPR_BOOKE_MAS6 (0x276)
1555 #define SPR_BOOKE_PID1 (0x279)
1556 #define SPR_BOOKE_PID2 (0x27A)
1557 #define SPR_MPC_DPDR (0x280)
1558 #define SPR_MPC_IMMR (0x288)
1559 #define SPR_BOOKE_TLB0CFG (0x2B0)
1560 #define SPR_BOOKE_TLB1CFG (0x2B1)
1561 #define SPR_BOOKE_TLB2CFG (0x2B2)
1562 #define SPR_BOOKE_TLB3CFG (0x2B3)
1563 #define SPR_BOOKE_EPR (0x2BE)
1564 #define SPR_PERF0 (0x300)
1565 #define SPR_RCPU_MI_RBA0 (0x300)
1566 #define SPR_MPC_MI_CTR (0x300)
1567 #define SPR_PERF1 (0x301)
1568 #define SPR_RCPU_MI_RBA1 (0x301)
1569 #define SPR_POWER_UMMCR2 (0x301)
1570 #define SPR_PERF2 (0x302)
1571 #define SPR_RCPU_MI_RBA2 (0x302)
1572 #define SPR_MPC_MI_AP (0x302)
1573 #define SPR_POWER_UMMCRA (0x302)
1574 #define SPR_PERF3 (0x303)
1575 #define SPR_RCPU_MI_RBA3 (0x303)
1576 #define SPR_MPC_MI_EPN (0x303)
1577 #define SPR_POWER_UPMC1 (0x303)
1578 #define SPR_PERF4 (0x304)
1579 #define SPR_POWER_UPMC2 (0x304)
1580 #define SPR_PERF5 (0x305)
1581 #define SPR_MPC_MI_TWC (0x305)
1582 #define SPR_POWER_UPMC3 (0x305)
1583 #define SPR_PERF6 (0x306)
1584 #define SPR_MPC_MI_RPN (0x306)
1585 #define SPR_POWER_UPMC4 (0x306)
1586 #define SPR_PERF7 (0x307)
1587 #define SPR_POWER_UPMC5 (0x307)
1588 #define SPR_PERF8 (0x308)
1589 #define SPR_RCPU_L2U_RBA0 (0x308)
1590 #define SPR_MPC_MD_CTR (0x308)
1591 #define SPR_POWER_UPMC6 (0x308)
1592 #define SPR_PERF9 (0x309)
1593 #define SPR_RCPU_L2U_RBA1 (0x309)
1594 #define SPR_MPC_MD_CASID (0x309)
1595 #define SPR_970_UPMC7 (0X309)
1596 #define SPR_PERFA (0x30A)
1597 #define SPR_RCPU_L2U_RBA2 (0x30A)
1598 #define SPR_MPC_MD_AP (0x30A)
1599 #define SPR_970_UPMC8 (0X30A)
1600 #define SPR_PERFB (0x30B)
1601 #define SPR_RCPU_L2U_RBA3 (0x30B)
1602 #define SPR_MPC_MD_EPN (0x30B)
1603 #define SPR_POWER_UMMCR0 (0X30B)
1604 #define SPR_PERFC (0x30C)
1605 #define SPR_MPC_MD_TWB (0x30C)
1606 #define SPR_POWER_USIAR (0X30C)
1607 #define SPR_PERFD (0x30D)
1608 #define SPR_MPC_MD_TWC (0x30D)
1609 #define SPR_POWER_USDAR (0X30D)
1610 #define SPR_PERFE (0x30E)
1611 #define SPR_MPC_MD_RPN (0x30E)
1612 #define SPR_POWER_UMMCR1 (0X30E)
1613 #define SPR_PERFF (0x30F)
1614 #define SPR_MPC_MD_TW (0x30F)
1615 #define SPR_UPERF0 (0x310)
1616 #define SPR_UPERF1 (0x311)
1617 #define SPR_POWER_MMCR2 (0x311)
1618 #define SPR_UPERF2 (0x312)
1619 #define SPR_POWER_MMCRA (0X312)
1620 #define SPR_UPERF3 (0x313)
1621 #define SPR_POWER_PMC1 (0X313)
1622 #define SPR_UPERF4 (0x314)
1623 #define SPR_POWER_PMC2 (0X314)
1624 #define SPR_UPERF5 (0x315)
1625 #define SPR_POWER_PMC3 (0X315)
1626 #define SPR_UPERF6 (0x316)
1627 #define SPR_POWER_PMC4 (0X316)
1628 #define SPR_UPERF7 (0x317)
1629 #define SPR_POWER_PMC5 (0X317)
1630 #define SPR_UPERF8 (0x318)
1631 #define SPR_POWER_PMC6 (0X318)
1632 #define SPR_UPERF9 (0x319)
1633 #define SPR_970_PMC7 (0X319)
1634 #define SPR_UPERFA (0x31A)
1635 #define SPR_970_PMC8 (0X31A)
1636 #define SPR_UPERFB (0x31B)
1637 #define SPR_POWER_MMCR0 (0X31B)
1638 #define SPR_UPERFC (0x31C)
1639 #define SPR_POWER_SIAR (0X31C)
1640 #define SPR_UPERFD (0x31D)
1641 #define SPR_POWER_SDAR (0X31D)
1642 #define SPR_UPERFE (0x31E)
1643 #define SPR_POWER_MMCR1 (0X31E)
1644 #define SPR_UPERFF (0x31F)
1645 #define SPR_RCPU_MI_RA0 (0x320)
1646 #define SPR_MPC_MI_DBCAM (0x320)
1647 #define SPR_BESCRS (0x320)
1648 #define SPR_RCPU_MI_RA1 (0x321)
1649 #define SPR_MPC_MI_DBRAM0 (0x321)
1650 #define SPR_BESCRSU (0x321)
1651 #define SPR_RCPU_MI_RA2 (0x322)
1652 #define SPR_MPC_MI_DBRAM1 (0x322)
1653 #define SPR_BESCRR (0x322)
1654 #define SPR_RCPU_MI_RA3 (0x323)
1655 #define SPR_BESCRRU (0x323)
1656 #define SPR_EBBHR (0x324)
1657 #define SPR_EBBRR (0x325)
1658 #define SPR_BESCR (0x326)
1659 #define SPR_RCPU_L2U_RA0 (0x328)
1660 #define SPR_MPC_MD_DBCAM (0x328)
1661 #define SPR_RCPU_L2U_RA1 (0x329)
1662 #define SPR_MPC_MD_DBRAM0 (0x329)
1663 #define SPR_RCPU_L2U_RA2 (0x32A)
1664 #define SPR_MPC_MD_DBRAM1 (0x32A)
1665 #define SPR_RCPU_L2U_RA3 (0x32B)
1666 #define SPR_TAR (0x32F)
1667 #define SPR_VTB (0x351)
1668 #define SPR_440_INV0 (0x370)
1669 #define SPR_440_INV1 (0x371)
1670 #define SPR_440_INV2 (0x372)
1671 #define SPR_440_INV3 (0x373)
1672 #define SPR_440_ITV0 (0x374)
1673 #define SPR_440_ITV1 (0x375)
1674 #define SPR_440_ITV2 (0x376)
1675 #define SPR_440_ITV3 (0x377)
1676 #define SPR_440_CCR1 (0x378)
1677 #define SPR_DCRIPR (0x37B)
1678 #define SPR_POWER_MMCRS (0x37E)
1679 #define SPR_PPR (0x380)
1680 #define SPR_750_GQR0 (0x390)
1681 #define SPR_440_DNV0 (0x390)
1682 #define SPR_750_GQR1 (0x391)
1683 #define SPR_440_DNV1 (0x391)
1684 #define SPR_750_GQR2 (0x392)
1685 #define SPR_440_DNV2 (0x392)
1686 #define SPR_750_GQR3 (0x393)
1687 #define SPR_440_DNV3 (0x393)
1688 #define SPR_750_GQR4 (0x394)
1689 #define SPR_440_DTV0 (0x394)
1690 #define SPR_750_GQR5 (0x395)
1691 #define SPR_440_DTV1 (0x395)
1692 #define SPR_750_GQR6 (0x396)
1693 #define SPR_440_DTV2 (0x396)
1694 #define SPR_750_GQR7 (0x397)
1695 #define SPR_440_DTV3 (0x397)
1696 #define SPR_750_THRM4 (0x398)
1697 #define SPR_750CL_HID2 (0x398)
1698 #define SPR_440_DVLIM (0x398)
1699 #define SPR_750_WPAR (0x399)
1700 #define SPR_440_IVLIM (0x399)
1701 #define SPR_750_DMAU (0x39A)
1702 #define SPR_750_DMAL (0x39B)
1703 #define SPR_440_RSTCFG (0x39B)
1704 #define SPR_BOOKE_DCDBTRL (0x39C)
1705 #define SPR_BOOKE_DCDBTRH (0x39D)
1706 #define SPR_BOOKE_ICDBTRL (0x39E)
1707 #define SPR_BOOKE_ICDBTRH (0x39F)
1708 #define SPR_74XX_UMMCR2 (0x3A0)
1709 #define SPR_7XX_UPMC5 (0x3A1)
1710 #define SPR_7XX_UPMC6 (0x3A2)
1711 #define SPR_UBAMR (0x3A7)
1712 #define SPR_7XX_UMMCR0 (0x3A8)
1713 #define SPR_7XX_UPMC1 (0x3A9)
1714 #define SPR_7XX_UPMC2 (0x3AA)
1715 #define SPR_7XX_USIAR (0x3AB)
1716 #define SPR_7XX_UMMCR1 (0x3AC)
1717 #define SPR_7XX_UPMC3 (0x3AD)
1718 #define SPR_7XX_UPMC4 (0x3AE)
1719 #define SPR_USDA (0x3AF)
1720 #define SPR_40x_ZPR (0x3B0)
1721 #define SPR_BOOKE_MAS7 (0x3B0)
1722 #define SPR_74XX_MMCR2 (0x3B0)
1723 #define SPR_7XX_PMC5 (0x3B1)
1724 #define SPR_40x_PID (0x3B1)
1725 #define SPR_7XX_PMC6 (0x3B2)
1726 #define SPR_440_MMUCR (0x3B2)
1727 #define SPR_4xx_CCR0 (0x3B3)
1728 #define SPR_BOOKE_EPLC (0x3B3)
1729 #define SPR_405_IAC3 (0x3B4)
1730 #define SPR_BOOKE_EPSC (0x3B4)
1731 #define SPR_405_IAC4 (0x3B5)
1732 #define SPR_405_DVC1 (0x3B6)
1733 #define SPR_405_DVC2 (0x3B7)
1734 #define SPR_BAMR (0x3B7)
1735 #define SPR_7XX_MMCR0 (0x3B8)
1736 #define SPR_7XX_PMC1 (0x3B9)
1737 #define SPR_40x_SGR (0x3B9)
1738 #define SPR_7XX_PMC2 (0x3BA)
1739 #define SPR_40x_DCWR (0x3BA)
1740 #define SPR_7XX_SIAR (0x3BB)
1741 #define SPR_405_SLER (0x3BB)
1742 #define SPR_7XX_MMCR1 (0x3BC)
1743 #define SPR_405_SU0R (0x3BC)
1744 #define SPR_401_SKR (0x3BC)
1745 #define SPR_7XX_PMC3 (0x3BD)
1746 #define SPR_405_DBCR1 (0x3BD)
1747 #define SPR_7XX_PMC4 (0x3BE)
1748 #define SPR_SDA (0x3BF)
1749 #define SPR_403_VTBL (0x3CC)
1750 #define SPR_403_VTBU (0x3CD)
1751 #define SPR_DMISS (0x3D0)
1752 #define SPR_DCMP (0x3D1)
1753 #define SPR_HASH1 (0x3D2)
1754 #define SPR_HASH2 (0x3D3)
1755 #define SPR_BOOKE_ICDBDR (0x3D3)
1756 #define SPR_TLBMISS (0x3D4)
1757 #define SPR_IMISS (0x3D4)
1758 #define SPR_40x_ESR (0x3D4)
1759 #define SPR_PTEHI (0x3D5)
1760 #define SPR_ICMP (0x3D5)
1761 #define SPR_40x_DEAR (0x3D5)
1762 #define SPR_PTELO (0x3D6)
1763 #define SPR_RPA (0x3D6)
1764 #define SPR_40x_EVPR (0x3D6)
1765 #define SPR_L3PM (0x3D7)
1766 #define SPR_403_CDBCR (0x3D7)
1767 #define SPR_L3ITCR0 (0x3D8)
1768 #define SPR_TCR (0x3D8)
1769 #define SPR_40x_TSR (0x3D8)
1770 #define SPR_IBR (0x3DA)
1771 #define SPR_40x_TCR (0x3DA)
1772 #define SPR_ESASRR (0x3DB)
1773 #define SPR_40x_PIT (0x3DB)
1774 #define SPR_403_TBL (0x3DC)
1775 #define SPR_403_TBU (0x3DD)
1776 #define SPR_SEBR (0x3DE)
1777 #define SPR_40x_SRR2 (0x3DE)
1778 #define SPR_SER (0x3DF)
1779 #define SPR_40x_SRR3 (0x3DF)
1780 #define SPR_L3OHCR (0x3E8)
1781 #define SPR_L3ITCR1 (0x3E9)
1782 #define SPR_L3ITCR2 (0x3EA)
1783 #define SPR_L3ITCR3 (0x3EB)
1784 #define SPR_HID0 (0x3F0)
1785 #define SPR_40x_DBSR (0x3F0)
1786 #define SPR_HID1 (0x3F1)
1787 #define SPR_IABR (0x3F2)
1788 #define SPR_40x_DBCR0 (0x3F2)
1789 #define SPR_601_HID2 (0x3F2)
1790 #define SPR_Exxx_L1CSR0 (0x3F2)
1791 #define SPR_ICTRL (0x3F3)
1792 #define SPR_HID2 (0x3F3)
1793 #define SPR_750CL_HID4 (0x3F3)
1794 #define SPR_Exxx_L1CSR1 (0x3F3)
1795 #define SPR_440_DBDR (0x3F3)
1796 #define SPR_LDSTDB (0x3F4)
1797 #define SPR_750_TDCL (0x3F4)
1798 #define SPR_40x_IAC1 (0x3F4)
1799 #define SPR_MMUCSR0 (0x3F4)
1800 #define SPR_970_HID4 (0x3F4)
1801 #define SPR_DABR (0x3F5)
1802 #define DABR_MASK (~(target_ulong)0x7)
1803 #define SPR_Exxx_BUCSR (0x3F5)
1804 #define SPR_40x_IAC2 (0x3F5)
1805 #define SPR_601_HID5 (0x3F5)
1806 #define SPR_40x_DAC1 (0x3F6)
1807 #define SPR_MSSCR0 (0x3F6)
1808 #define SPR_970_HID5 (0x3F6)
1809 #define SPR_MSSSR0 (0x3F7)
1810 #define SPR_MSSCR1 (0x3F7)
1811 #define SPR_DABRX (0x3F7)
1812 #define SPR_40x_DAC2 (0x3F7)
1813 #define SPR_MMUCFG (0x3F7)
1814 #define SPR_LDSTCR (0x3F8)
1815 #define SPR_L2PMCR (0x3F8)
1816 #define SPR_750FX_HID2 (0x3F8)
1817 #define SPR_Exxx_L1FINV0 (0x3F8)
1818 #define SPR_L2CR (0x3F9)
1819 #define SPR_L3CR (0x3FA)
1820 #define SPR_750_TDCH (0x3FA)
1821 #define SPR_IABR2 (0x3FA)
1822 #define SPR_40x_DCCR (0x3FA)
1823 #define SPR_ICTC (0x3FB)
1824 #define SPR_40x_ICCR (0x3FB)
1825 #define SPR_THRM1 (0x3FC)
1826 #define SPR_403_PBL1 (0x3FC)
1827 #define SPR_SP (0x3FD)
1828 #define SPR_THRM2 (0x3FD)
1829 #define SPR_403_PBU1 (0x3FD)
1830 #define SPR_604_HID13 (0x3FD)
1831 #define SPR_LT (0x3FE)
1832 #define SPR_THRM3 (0x3FE)
1833 #define SPR_RCPU_FPECR (0x3FE)
1834 #define SPR_403_PBL2 (0x3FE)
1835 #define SPR_PIR (0x3FF)
1836 #define SPR_403_PBU2 (0x3FF)
1837 #define SPR_601_HID15 (0x3FF)
1838 #define SPR_604_HID15 (0x3FF)
1839 #define SPR_E500_SVR (0x3FF)
1840
1841 /* Disable MAS Interrupt Updates for Hypervisor */
1842 #define EPCR_DMIUH (1 << 22)
1843 /* Disable Guest TLB Management Instructions */
1844 #define EPCR_DGTMI (1 << 23)
1845 /* Guest Interrupt Computation Mode */
1846 #define EPCR_GICM (1 << 24)
1847 /* Interrupt Computation Mode */
1848 #define EPCR_ICM (1 << 25)
1849 /* Disable Embedded Hypervisor Debug */
1850 #define EPCR_DUVD (1 << 26)
1851 /* Instruction Storage Interrupt Directed to Guest State */
1852 #define EPCR_ISIGS (1 << 27)
1853 /* Data Storage Interrupt Directed to Guest State */
1854 #define EPCR_DSIGS (1 << 28)
1855 /* Instruction TLB Error Interrupt Directed to Guest State */
1856 #define EPCR_ITLBGS (1 << 29)
1857 /* Data TLB Error Interrupt Directed to Guest State */
1858 #define EPCR_DTLBGS (1 << 30)
1859 /* External Input Interrupt Directed to Guest State */
1860 #define EPCR_EXTGS (1 << 31)
1861
1862 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1863 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1864 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1865 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1866 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1867
1868 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1869 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1870 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1871 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1872 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1873
1874 /* HID0 bits */
1875 #define HID0_DEEPNAP (1 << 24)
1876 #define HID0_DOZE (1 << 23)
1877 #define HID0_NAP (1 << 22)
1878
1879 /*****************************************************************************/
1880 /* PowerPC Instructions types definitions */
1881 enum {
1882 PPC_NONE = 0x0000000000000000ULL,
1883 /* PowerPC base instructions set */
1884 PPC_INSNS_BASE = 0x0000000000000001ULL,
1885 /* integer operations instructions */
1886 #define PPC_INTEGER PPC_INSNS_BASE
1887 /* flow control instructions */
1888 #define PPC_FLOW PPC_INSNS_BASE
1889 /* virtual memory instructions */
1890 #define PPC_MEM PPC_INSNS_BASE
1891 /* ld/st with reservation instructions */
1892 #define PPC_RES PPC_INSNS_BASE
1893 /* spr/msr access instructions */
1894 #define PPC_MISC PPC_INSNS_BASE
1895 /* Deprecated instruction sets */
1896 /* Original POWER instruction set */
1897 PPC_POWER = 0x0000000000000002ULL,
1898 /* POWER2 instruction set extension */
1899 PPC_POWER2 = 0x0000000000000004ULL,
1900 /* Power RTC support */
1901 PPC_POWER_RTC = 0x0000000000000008ULL,
1902 /* Power-to-PowerPC bridge (601) */
1903 PPC_POWER_BR = 0x0000000000000010ULL,
1904 /* 64 bits PowerPC instruction set */
1905 PPC_64B = 0x0000000000000020ULL,
1906 /* New 64 bits extensions (PowerPC 2.0x) */
1907 PPC_64BX = 0x0000000000000040ULL,
1908 /* 64 bits hypervisor extensions */
1909 PPC_64H = 0x0000000000000080ULL,
1910 /* New wait instruction (PowerPC 2.0x) */
1911 PPC_WAIT = 0x0000000000000100ULL,
1912 /* Time base mftb instruction */
1913 PPC_MFTB = 0x0000000000000200ULL,
1914
1915 /* Fixed-point unit extensions */
1916 /* PowerPC 602 specific */
1917 PPC_602_SPEC = 0x0000000000000400ULL,
1918 /* isel instruction */
1919 PPC_ISEL = 0x0000000000000800ULL,
1920 /* popcntb instruction */
1921 PPC_POPCNTB = 0x0000000000001000ULL,
1922 /* string load / store */
1923 PPC_STRING = 0x0000000000002000ULL,
1924
1925 /* Floating-point unit extensions */
1926 /* Optional floating point instructions */
1927 PPC_FLOAT = 0x0000000000010000ULL,
1928 /* New floating-point extensions (PowerPC 2.0x) */
1929 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1930 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1931 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1932 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1933 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1934 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1935 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1936
1937 /* Vector/SIMD extensions */
1938 /* Altivec support */
1939 PPC_ALTIVEC = 0x0000000001000000ULL,
1940 /* PowerPC 2.03 SPE extension */
1941 PPC_SPE = 0x0000000002000000ULL,
1942 /* PowerPC 2.03 SPE single-precision floating-point extension */
1943 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1944 /* PowerPC 2.03 SPE double-precision floating-point extension */
1945 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1946
1947 /* Optional memory control instructions */
1948 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1949 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1950 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1951 /* sync instruction */
1952 PPC_MEM_SYNC = 0x0000000080000000ULL,
1953 /* eieio instruction */
1954 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1955
1956 /* Cache control instructions */
1957 PPC_CACHE = 0x0000000200000000ULL,
1958 /* icbi instruction */
1959 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1960 /* dcbz instruction */
1961 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1962 /* dcba instruction */
1963 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1964 /* Freescale cache locking instructions */
1965 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1966
1967 /* MMU related extensions */
1968 /* external control instructions */
1969 PPC_EXTERN = 0x0000010000000000ULL,
1970 /* segment register access instructions */
1971 PPC_SEGMENT = 0x0000020000000000ULL,
1972 /* PowerPC 6xx TLB management instructions */
1973 PPC_6xx_TLB = 0x0000040000000000ULL,
1974 /* PowerPC 74xx TLB management instructions */
1975 PPC_74xx_TLB = 0x0000080000000000ULL,
1976 /* PowerPC 40x TLB management instructions */
1977 PPC_40x_TLB = 0x0000100000000000ULL,
1978 /* segment register access instructions for PowerPC 64 "bridge" */
1979 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1980 /* SLB management */
1981 PPC_SLBI = 0x0000400000000000ULL,
1982
1983 /* Embedded PowerPC dedicated instructions */
1984 PPC_WRTEE = 0x0001000000000000ULL,
1985 /* PowerPC 40x exception model */
1986 PPC_40x_EXCP = 0x0002000000000000ULL,
1987 /* PowerPC 405 Mac instructions */
1988 PPC_405_MAC = 0x0004000000000000ULL,
1989 /* PowerPC 440 specific instructions */
1990 PPC_440_SPEC = 0x0008000000000000ULL,
1991 /* BookE (embedded) PowerPC specification */
1992 PPC_BOOKE = 0x0010000000000000ULL,
1993 /* mfapidi instruction */
1994 PPC_MFAPIDI = 0x0020000000000000ULL,
1995 /* tlbiva instruction */
1996 PPC_TLBIVA = 0x0040000000000000ULL,
1997 /* tlbivax instruction */
1998 PPC_TLBIVAX = 0x0080000000000000ULL,
1999 /* PowerPC 4xx dedicated instructions */
2000 PPC_4xx_COMMON = 0x0100000000000000ULL,
2001 /* PowerPC 40x ibct instructions */
2002 PPC_40x_ICBT = 0x0200000000000000ULL,
2003 /* rfmci is not implemented in all BookE PowerPC */
2004 PPC_RFMCI = 0x0400000000000000ULL,
2005 /* rfdi instruction */
2006 PPC_RFDI = 0x0800000000000000ULL,
2007 /* DCR accesses */
2008 PPC_DCR = 0x1000000000000000ULL,
2009 /* DCR extended accesse */
2010 PPC_DCRX = 0x2000000000000000ULL,
2011 /* user-mode DCR access, implemented in PowerPC 460 */
2012 PPC_DCRUX = 0x4000000000000000ULL,
2013 /* popcntw and popcntd instructions */
2014 PPC_POPCNTWD = 0x8000000000000000ULL,
2015
2016 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2017 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2018 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2019 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2020 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2021 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2022 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2023 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2024 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2025 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2026 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2027 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2028 | PPC_CACHE | PPC_CACHE_ICBI \
2029 | PPC_CACHE_DCBZ \
2030 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2031 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2032 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2033 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2034 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2035 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2036 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2037 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2038 | PPC_POPCNTWD)
2039
2040 /* extended type values */
2041
2042 /* BookE 2.06 PowerPC specification */
2043 PPC2_BOOKE206 = 0x0000000000000001ULL,
2044 /* VSX (extensions to Altivec / VMX) */
2045 PPC2_VSX = 0x0000000000000002ULL,
2046 /* Decimal Floating Point (DFP) */
2047 PPC2_DFP = 0x0000000000000004ULL,
2048 /* Embedded.Processor Control */
2049 PPC2_PRCNTL = 0x0000000000000008ULL,
2050 /* Byte-reversed, indexed, double-word load and store */
2051 PPC2_DBRX = 0x0000000000000010ULL,
2052 /* Book I 2.05 PowerPC specification */
2053 PPC2_ISA205 = 0x0000000000000020ULL,
2054 /* VSX additions in ISA 2.07 */
2055 PPC2_VSX207 = 0x0000000000000040ULL,
2056 /* ISA 2.06B bpermd */
2057 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2058 /* ISA 2.06B divide extended variants */
2059 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2060 /* ISA 2.06B larx/stcx. instructions */
2061 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2062 /* ISA 2.06B floating point integer conversion */
2063 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2064 /* ISA 2.06B floating point test instructions */
2065 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2066 /* ISA 2.07 bctar instruction */
2067 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2068 /* ISA 2.07 load/store quadword */
2069 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2070 /* ISA 2.07 Altivec */
2071 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2072 /* PowerISA 2.07 Book3s specification */
2073 PPC2_ISA207S = 0x0000000000008000ULL,
2074 /* Double precision floating point conversion for signed integer 64 */
2075 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2076 /* Transactional Memory (ISA 2.07, Book II) */
2077 PPC2_TM = 0x0000000000020000ULL,
2078
2079 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2080 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2081 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2082 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2083 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2084 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2085 PPC2_FP_CVT_S64 | PPC2_TM)
2086 };
2087
2088 /*****************************************************************************/
2089 /* Memory access type :
2090 * may be needed for precise access rights control and precise exceptions.
2091 */
2092 enum {
2093 /* 1 bit to define user level / supervisor access */
2094 ACCESS_USER = 0x00,
2095 ACCESS_SUPER = 0x01,
2096 /* Type of instruction that generated the access */
2097 ACCESS_CODE = 0x10, /* Code fetch access */
2098 ACCESS_INT = 0x20, /* Integer load/store access */
2099 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2100 ACCESS_RES = 0x40, /* load/store with reservation */
2101 ACCESS_EXT = 0x50, /* external access */
2102 ACCESS_CACHE = 0x60, /* Cache manipulation */
2103 };
2104
2105 /* Hardware interruption sources:
2106 * all those exception can be raised simulteaneously
2107 */
2108 /* Input pins definitions */
2109 enum {
2110 /* 6xx bus input pins */
2111 PPC6xx_INPUT_HRESET = 0,
2112 PPC6xx_INPUT_SRESET = 1,
2113 PPC6xx_INPUT_CKSTP_IN = 2,
2114 PPC6xx_INPUT_MCP = 3,
2115 PPC6xx_INPUT_SMI = 4,
2116 PPC6xx_INPUT_INT = 5,
2117 PPC6xx_INPUT_TBEN = 6,
2118 PPC6xx_INPUT_WAKEUP = 7,
2119 PPC6xx_INPUT_NB,
2120 };
2121
2122 enum {
2123 /* Embedded PowerPC input pins */
2124 PPCBookE_INPUT_HRESET = 0,
2125 PPCBookE_INPUT_SRESET = 1,
2126 PPCBookE_INPUT_CKSTP_IN = 2,
2127 PPCBookE_INPUT_MCP = 3,
2128 PPCBookE_INPUT_SMI = 4,
2129 PPCBookE_INPUT_INT = 5,
2130 PPCBookE_INPUT_CINT = 6,
2131 PPCBookE_INPUT_NB,
2132 };
2133
2134 enum {
2135 /* PowerPC E500 input pins */
2136 PPCE500_INPUT_RESET_CORE = 0,
2137 PPCE500_INPUT_MCK = 1,
2138 PPCE500_INPUT_CINT = 3,
2139 PPCE500_INPUT_INT = 4,
2140 PPCE500_INPUT_DEBUG = 6,
2141 PPCE500_INPUT_NB,
2142 };
2143
2144 enum {
2145 /* PowerPC 40x input pins */
2146 PPC40x_INPUT_RESET_CORE = 0,
2147 PPC40x_INPUT_RESET_CHIP = 1,
2148 PPC40x_INPUT_RESET_SYS = 2,
2149 PPC40x_INPUT_CINT = 3,
2150 PPC40x_INPUT_INT = 4,
2151 PPC40x_INPUT_HALT = 5,
2152 PPC40x_INPUT_DEBUG = 6,
2153 PPC40x_INPUT_NB,
2154 };
2155
2156 enum {
2157 /* RCPU input pins */
2158 PPCRCPU_INPUT_PORESET = 0,
2159 PPCRCPU_INPUT_HRESET = 1,
2160 PPCRCPU_INPUT_SRESET = 2,
2161 PPCRCPU_INPUT_IRQ0 = 3,
2162 PPCRCPU_INPUT_IRQ1 = 4,
2163 PPCRCPU_INPUT_IRQ2 = 5,
2164 PPCRCPU_INPUT_IRQ3 = 6,
2165 PPCRCPU_INPUT_IRQ4 = 7,
2166 PPCRCPU_INPUT_IRQ5 = 8,
2167 PPCRCPU_INPUT_IRQ6 = 9,
2168 PPCRCPU_INPUT_IRQ7 = 10,
2169 PPCRCPU_INPUT_NB,
2170 };
2171
2172 #if defined(TARGET_PPC64)
2173 enum {
2174 /* PowerPC 970 input pins */
2175 PPC970_INPUT_HRESET = 0,
2176 PPC970_INPUT_SRESET = 1,
2177 PPC970_INPUT_CKSTP = 2,
2178 PPC970_INPUT_TBEN = 3,
2179 PPC970_INPUT_MCP = 4,
2180 PPC970_INPUT_INT = 5,
2181 PPC970_INPUT_THINT = 6,
2182 PPC970_INPUT_NB,
2183 };
2184
2185 enum {
2186 /* POWER7 input pins */
2187 POWER7_INPUT_INT = 0,
2188 /* POWER7 probably has other inputs, but we don't care about them
2189 * for any existing machine. We can wire these up when we need
2190 * them */
2191 POWER7_INPUT_NB,
2192 };
2193 #endif
2194
2195 /* Hardware exceptions definitions */
2196 enum {
2197 /* External hardware exception sources */
2198 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2199 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2200 PPC_INTERRUPT_MCK, /* Machine check exception */
2201 PPC_INTERRUPT_EXT, /* External interrupt */
2202 PPC_INTERRUPT_SMI, /* System management interrupt */
2203 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2204 PPC_INTERRUPT_DEBUG, /* External debug exception */
2205 PPC_INTERRUPT_THERM, /* Thermal exception */
2206 /* Internal hardware exception sources */
2207 PPC_INTERRUPT_DECR, /* Decrementer exception */
2208 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2209 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2210 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2211 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2212 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2213 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2214 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2215 };
2216
2217 /* Processor Compatibility mask (PCR) */
2218 enum {
2219 PCR_COMPAT_2_05 = 1ull << (63-62),
2220 PCR_COMPAT_2_06 = 1ull << (63-61),
2221 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2222 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2223 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2224 };
2225
2226 /*****************************************************************************/
2227
2228 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2229 {
2230 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2231 }
2232
2233 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2234 {
2235 env->so = (xer >> XER_SO) & 1;
2236 env->ov = (xer >> XER_OV) & 1;
2237 env->ca = (xer >> XER_CA) & 1;
2238 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2239 }
2240
2241 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2242 target_ulong *cs_base, int *flags)
2243 {
2244 *pc = env->nip;
2245 *cs_base = 0;
2246 *flags = env->hflags;
2247 }
2248
2249 #if !defined(CONFIG_USER_ONLY)
2250 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2251 {
2252 uintptr_t tlbml = (uintptr_t)tlbm;
2253 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2254
2255 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2256 }
2257
2258 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2259 {
2260 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2261 int r = tlbncfg & TLBnCFG_N_ENTRY;
2262 return r;
2263 }
2264
2265 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2266 {
2267 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2268 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2269 return r;
2270 }
2271
2272 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2273 {
2274 int id = booke206_tlbm_id(env, tlbm);
2275 int end = 0;
2276 int i;
2277
2278 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2279 end += booke206_tlb_size(env, i);
2280 if (id < end) {
2281 return i;
2282 }
2283 }
2284
2285 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2286 return 0;
2287 }
2288
2289 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2290 {
2291 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2292 int tlbid = booke206_tlbm_id(env, tlb);
2293 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2294 }
2295
2296 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2297 target_ulong ea, int way)
2298 {
2299 int r;
2300 uint32_t ways = booke206_tlb_ways(env, tlbn);
2301 int ways_bits = ctz32(ways);
2302 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2303 int i;
2304
2305 way &= ways - 1;
2306 ea >>= MAS2_EPN_SHIFT;
2307 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2308 r = (ea << ways_bits) | way;
2309
2310 if (r >= booke206_tlb_size(env, tlbn)) {
2311 return NULL;
2312 }
2313
2314 /* bump up to tlbn index */
2315 for (i = 0; i < tlbn; i++) {
2316 r += booke206_tlb_size(env, i);
2317 }
2318
2319 return &env->tlb.tlbm[r];
2320 }
2321
2322 /* returns bitmap of supported page sizes for a given TLB */
2323 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2324 {
2325 bool mav2 = false;
2326 uint32_t ret = 0;
2327
2328 if (mav2) {
2329 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2330 } else {
2331 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2332 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2333 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2334 int i;
2335 for (i = min; i <= max; i++) {
2336 ret |= (1 << (i << 1));
2337 }
2338 }
2339
2340 return ret;
2341 }
2342
2343 #endif
2344
2345 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2346 {
2347 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2348 return msr & (1ULL << MSR_CM);
2349 }
2350
2351 return msr & (1ULL << MSR_SF);
2352 }
2353
2354 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2355
2356 #include "exec/exec-all.h"
2357
2358 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2359
2360 /**
2361 * ppc_get_vcpu_dt_id:
2362 * @cs: a PowerPCCPU struct.
2363 *
2364 * Returns a device-tree ID for a CPU.
2365 */
2366 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2367
2368 /**
2369 * ppc_get_vcpu_by_dt_id:
2370 * @cpu_dt_id: a device tree id
2371 *
2372 * Searches for a CPU by @cpu_dt_id.
2373 *
2374 * Returns: a PowerPCCPU struct
2375 */
2376 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2377
2378 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2379 #endif /* !defined (__CPU_PPC_H__) */
QEmu