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HEAD
qdev/isa: add isa bus support to qdev.
[qemu.git]
/
tests
/
cris
/
check_subm.s
blob
e07ea02dd4c091aeee2a1bfac40a371c15007254
1
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
2
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n
3
4
.include
"testutils.inc"
5
.data
6
x
:
7
.dword -2,1,-0xffff,1,-0x5432f789
8
.word -2,1,1,0x877
9
.byte -2,1,0x77
10
.byte 0x22
11
12
start
13
moveq
-
1
,
r3
14
move.d x
,
r5
15
sub.
d
[
r5+
],
r3
16
test_cc
0 0 0 0
17
checkr3
1
18
19
moveq
2
,
r3
20
sub.
d
[
r5
],
r3
21
test_cc
0 0 0 0
22
addq
4
,
r5
23
checkr3
1
24
25
move.d
0xffff
,
r3
26
sub.
d
[
r5+
],
r3
27
test_cc
0 0 0 1
28
checkr3
1
fffe
29
30
moveq
-
1
,
r3
31
sub.
d
[
r5+
],
r3
32
test_cc
1 0 0 0
33
checkr3 fffffffe
34
35
move.d
0x78134452
,
r3
36
sub.
d
[
r5+
],
r3
37
test_cc
1 0 1 1
38
checkr3 cc463bdb
39
40
moveq
-
1
,
r3
41
sub.
w
[
r5+
],
r3
42
test_cc
0 0 0 0
43
checkr3 ffff0001
44
45
moveq
2
,
r3
46
sub.
w
[
r5+
],
r3
47
test_cc
0 0 0 0
48
checkr3
1
49
50
move.d
0xffff
,
r3
51
sub.
w
[
r5
],
r3
52
test_cc
1 0 0 0
53
checkr3 fffe
54
55
move.d
0xfedaffff
,
r3
56
sub.
w
[
r5+
],
r3
57
test_cc
1 0 0 0
58
checkr3 fedafffe
59
60
move.d
0x78134452
,
r3
61
sub.
w
[
r5+
],
r3
62
test_cc
0 0 0 0
63
checkr3
78133
bdb
64
65
moveq
-
1
,
r3
66
sub.b
[
r5
],
r3
67
test_cc
0 0 0 0
68
addq
1
,
r5
69
checkr3 ffffff01
70
71
moveq
2
,
r3
72
sub.b
[
r5
],
r3
73
test_cc
0 0 0 0
74
checkr3
1
75
76
move.d
0xff
,
r3
77
sub.b
[
r5
],
r3
78
test_cc
1 0 0 0
79
checkr3 fe
80
81
move.d
0xfeda49ff
,
r3
82
sub.b
[
r5+
],
r3
83
test_cc
1 0 0 0
84
checkr3 feda49fe
85
86
move.d
0x78134452
,
r3
87
sub.b
[
r5+
],
r3
88
test_cc
1 0 0 1
89
checkr3
781344
db
90
91
move.d
0x85649222
,
r3
92
sub.b
[
r5
],
r3
93
test_cc
0 1 0 0
94
checkr3
85649200
95
96
quit