target-s390x/mmu_helper.c

   1 /*
   2  * S390x MMU related functions
   3  *
   4  * Copyright (c) 2011 Alexander Graf
   5  * Copyright (c) 2015 Thomas Huth, IBM Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include "cpu.h"
  19
  20 /* #define DEBUG_S390 */
  21 /* #define DEBUG_S390_PTE */
  22 /* #define DEBUG_S390_STDOUT */
  23
  24 #ifdef DEBUG_S390
  25 #ifdef DEBUG_S390_STDOUT
  26 #define DPRINTF(fmt, ...) \
  27     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  28          qemu_log(fmt, ##__VA_ARGS__); } while (0)
  29 #else
  30 #define DPRINTF(fmt, ...) \
  31     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  32 #endif
  33 #else
  34 #define DPRINTF(fmt, ...) \
  35     do { } while (0)
  36 #endif
  37
  38 #ifdef DEBUG_S390_PTE
  39 #define PTE_DPRINTF DPRINTF
  40 #else
  41 #define PTE_DPRINTF(fmt, ...) \
  42     do { } while (0)
  43 #endif
  44
  45 static int trans_bits(CPUS390XState *env, uint64_t mode)
  46 {
  47     S390CPU *cpu = s390_env_get_cpu(env);
  48     int bits = 0;
  49
  50     switch (mode) {
  51     case PSW_ASC_PRIMARY:
  52         bits = 1;
  53         break;
  54     case PSW_ASC_SECONDARY:
  55         bits = 2;
  56         break;
  57     case PSW_ASC_HOME:
  58         bits = 3;
  59         break;
  60     default:
  61         cpu_abort(CPU(cpu), "unknown asc mode\n");
  62         break;
  63     }
  64
  65     return bits;
  66 }
  67
  68 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
  69                                uint64_t mode)
  70 {
  71     CPUState *cs = CPU(s390_env_get_cpu(env));
  72     int ilen = ILEN_LATER_INC;
  73     int bits = trans_bits(env, mode) | 4;
  74
  75     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
  76
  77     stq_phys(cs->as,
  78              env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
  79     trigger_pgm_exception(env, PGM_PROTECTION, ilen);
  80 }
  81
  82 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
  83                                uint32_t type, uint64_t asc, int rw)
  84 {
  85     CPUState *cs = CPU(s390_env_get_cpu(env));
  86     int ilen = ILEN_LATER;
  87     int bits = trans_bits(env, asc);
  88
  89     /* Code accesses have an undefined ilc.  */
  90     if (rw == 2) {
  91         ilen = 2;
  92     }
  93
  94     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
  95
  96     stq_phys(cs->as,
  97              env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
  98     trigger_pgm_exception(env, type, ilen);
  99 }
 100
 101 /**
 102  * Translate real address to absolute (= physical)
 103  * address by taking care of the prefix mapping.
 104  */
 105 static target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
 106 {
 107     if (raddr < 0x2000) {
 108         return raddr + env->psa;    /* Map the lowcore. */
 109     } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
 110         return raddr - env->psa;    /* Map the 0 page. */
 111     }
 112     return raddr;
 113 }
 114
 115 /* Decode page table entry (normal 4KB page) */
 116 static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
 117                              uint64_t asc, uint64_t asce,
 118                              target_ulong *raddr, int *flags, int rw)
 119 {
 120     if (asce & _PAGE_INVALID) {
 121         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, asce);
 122         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
 123         return -1;
 124     }
 125
 126     if (asce & _PAGE_RO) {
 127         *flags &= ~PAGE_WRITE;
 128     }
 129
 130     *raddr = asce & _ASCE_ORIGIN;
 131
 132     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, asce);
 133
 134     return 0;
 135 }
 136
 137 #define VADDR_PX    0xff000         /* Page index bits */
 138
 139 /* Decode segment table entry */
 140 static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
 141                                  uint64_t asc, uint64_t st_entry,
 142                                  target_ulong *raddr, int *flags, int rw)
 143 {
 144     CPUState *cs = CPU(s390_env_get_cpu(env));
 145     uint64_t origin, offs, pt_entry;
 146
 147     if (st_entry & _SEGMENT_ENTRY_RO) {
 148         *flags &= ~PAGE_WRITE;
 149     }
 150
 151     if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
 152         /* Decode EDAT1 segment frame absolute address (1MB page) */
 153         *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
 154         PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);
 155         return 0;
 156     }
 157
 158     /* Look up 4KB page entry */
 159     origin = st_entry & _SEGMENT_ENTRY_ORIGIN;
 160     offs  = (vaddr & VADDR_PX) >> 9;
 161     pt_entry = ldq_phys(cs->as, origin + offs);
 162     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 163                 __func__, origin, offs, pt_entry);
 164     return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw);
 165 }
 166
 167 /* Decode region table entries */
 168 static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
 169                                 uint64_t asc, uint64_t entry, int level,
 170                                 target_ulong *raddr, int *flags, int rw)
 171 {
 172     CPUState *cs = CPU(s390_env_get_cpu(env));
 173     uint64_t origin, offs, new_entry;
 174
 175     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry);
 176
 177     origin = entry & _REGION_ENTRY_ORIGIN;
 178     offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
 179
 180     new_entry = ldq_phys(cs->as, origin + offs);
 181     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 182                 __func__, origin, offs, new_entry);
 183
 184     if ((new_entry & _REGION_ENTRY_INV) != 0) {
 185         /* XXX different regions have different faults */
 186         DPRINTF("%s: invalid region\n", __func__);
 187         trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
 188         return -1;
 189     }
 190
 191     if ((new_entry & _REGION_ENTRY_TYPE_MASK) != level) {
 192         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 193         return -1;
 194     }
 195
 196     /* XXX region protection flags */
 197     /* *flags &= ~PAGE_WRITE */
 198
 199     if (level == _ASCE_TYPE_SEGMENT) {
 200         return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
 201                                      rw);
 202     }
 203
 204     /* yet another region */
 205     return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
 206                                 raddr, flags, rw);
 207 }
 208
 209 static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
 210                              uint64_t asc, target_ulong *raddr, int *flags,
 211                              int rw)
 212 {
 213     uint64_t asce = 0;
 214     int level;
 215     int r;
 216
 217     switch (asc) {
 218     case PSW_ASC_PRIMARY:
 219         PTE_DPRINTF("%s: asc=primary\n", __func__);
 220         asce = env->cregs[1];
 221         break;
 222     case PSW_ASC_SECONDARY:
 223         PTE_DPRINTF("%s: asc=secondary\n", __func__);
 224         asce = env->cregs[7];
 225         break;
 226     case PSW_ASC_HOME:
 227         PTE_DPRINTF("%s: asc=home\n", __func__);
 228         asce = env->cregs[13];
 229         break;
 230     }
 231
 232     if (asce & _ASCE_REAL_SPACE) {
 233         /* direct mapping */
 234         *raddr = vaddr;
 235         return 0;
 236     }
 237
 238     level = asce & _ASCE_TYPE_MASK;
 239     switch (level) {
 240     case _ASCE_TYPE_REGION1:
 241         break;
 242     case _ASCE_TYPE_REGION2:
 243         if (vaddr & 0xffe0000000000000ULL) {
 244             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 245                     " 0xffe0000000000000ULL\n", __func__, vaddr);
 246             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 247             return -1;
 248         }
 249         break;
 250     case _ASCE_TYPE_REGION3:
 251         if (vaddr & 0xfffffc0000000000ULL) {
 252             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 253                     " 0xfffffc0000000000ULL\n", __func__, vaddr);
 254             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 255             return -1;
 256         }
 257         break;
 258     case _ASCE_TYPE_SEGMENT:
 259         if (vaddr & 0xffffffff80000000ULL) {
 260             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 261                     " 0xffffffff80000000ULL\n", __func__, vaddr);
 262             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 263             return -1;
 264         }
 265         break;
 266     }
 267
 268     r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw);
 269     if ((rw == 1) && !(*flags & PAGE_WRITE)) {
 270         trigger_prot_fault(env, vaddr, asc);
 271         return -1;
 272     }
 273
 274     return r;
 275 }
 276
 277 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 278                   target_ulong *raddr, int *flags)
 279 {
 280     int r = -1;
 281     uint8_t *sk;
 282
 283     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 284     vaddr &= TARGET_PAGE_MASK;
 285
 286     if (!(env->psw.mask & PSW_MASK_DAT)) {
 287         *raddr = vaddr;
 288         r = 0;
 289         goto out;
 290     }
 291
 292     switch (asc) {
 293     case PSW_ASC_PRIMARY:
 294     case PSW_ASC_HOME:
 295         r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
 296         break;
 297     case PSW_ASC_SECONDARY:
 298         /*
 299          * Instruction: Primary
 300          * Data: Secondary
 301          */
 302         if (rw == 2) {
 303             r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
 304                                   rw);
 305             *flags &= ~(PAGE_READ | PAGE_WRITE);
 306         } else {
 307             r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
 308                                   rw);
 309             *flags &= ~(PAGE_EXEC);
 310         }
 311         break;
 312     case PSW_ASC_ACCREG:
 313     default:
 314         hw_error("guest switched to unknown asc mode\n");
 315         break;
 316     }
 317
 318  out:
 319     /* Convert real address -> absolute address */
 320     *raddr = mmu_real2abs(env, *raddr);
 321
 322     if (*raddr <= ram_size) {
 323         sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
 324         if (*flags & PAGE_READ) {
 325             *sk |= SK_R;
 326         }
 327
 328         if (*flags & PAGE_WRITE) {
 329             *sk |= SK_C;
 330         }
 331     }
 332
 333     return r;
 334 }