Merge branch 'net-queue'
[qemu.git] / target-sh4 / cpu.h
blobe597f653a7a51361bc42f01ebc9a7c5126ae8def
1 /*
2 * SH4 emulation
4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
20 #ifndef _CPU_SH4_H
21 #define _CPU_SH4_H
23 #include "config.h"
25 #define TARGET_LONG_BITS 32
26 #define TARGET_HAS_ICE 1
28 #define ELF_MACHINE EM_SH
30 /* CPU Subtypes */
31 #define SH_CPU_SH7750 (1 << 0)
32 #define SH_CPU_SH7750S (1 << 1)
33 #define SH_CPU_SH7750R (1 << 2)
34 #define SH_CPU_SH7751 (1 << 3)
35 #define SH_CPU_SH7751R (1 << 4)
36 #define SH_CPU_SH7785 (1 << 5)
37 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
38 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
40 #define CPUState struct CPUSH4State
42 #include "cpu-defs.h"
44 #include "softfloat.h"
46 #define TARGET_PAGE_BITS 12 /* 4k XXXXX */
48 #define SR_MD (1 << 30)
49 #define SR_RB (1 << 29)
50 #define SR_BL (1 << 28)
51 #define SR_FD (1 << 15)
52 #define SR_M (1 << 9)
53 #define SR_Q (1 << 8)
54 #define SR_I3 (1 << 7)
55 #define SR_I2 (1 << 6)
56 #define SR_I1 (1 << 5)
57 #define SR_I0 (1 << 4)
58 #define SR_S (1 << 1)
59 #define SR_T (1 << 0)
61 #define FPSCR_FR (1 << 21)
62 #define FPSCR_SZ (1 << 20)
63 #define FPSCR_PR (1 << 19)
64 #define FPSCR_DN (1 << 18)
65 #define DELAY_SLOT (1 << 0)
66 #define DELAY_SLOT_CONDITIONAL (1 << 1)
67 #define DELAY_SLOT_TRUE (1 << 2)
68 #define DELAY_SLOT_CLEARME (1 << 3)
69 /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
70 * after the delay slot should be taken or not. It is calculated from SR_T.
72 * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
73 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
76 /* XXXXX The structure could be made more compact */
77 typedef struct tlb_t {
78 uint8_t asid; /* address space identifier */
79 uint32_t vpn; /* virtual page number */
80 uint8_t v; /* validity */
81 uint32_t ppn; /* physical page number */
82 uint8_t sz; /* page size */
83 uint32_t size; /* cached page size in bytes */
84 uint8_t sh; /* share status */
85 uint8_t c; /* cacheability */
86 uint8_t pr; /* protection key */
87 uint8_t d; /* dirty */
88 uint8_t wt; /* write through */
89 uint8_t sa; /* space attribute (PCMCIA) */
90 uint8_t tc; /* timing control */
91 } tlb_t;
93 #define UTLB_SIZE 64
94 #define ITLB_SIZE 4
96 #define NB_MMU_MODES 2
98 enum sh_features {
99 SH_FEATURE_SH4A = 1,
100 SH_FEATURE_BCR3_AND_BCR4 = 2,
103 typedef struct memory_content {
104 uint32_t address;
105 uint32_t value;
106 struct memory_content *next;
107 } memory_content;
109 typedef struct CPUSH4State {
110 int id; /* CPU model */
112 uint32_t flags; /* general execution flags */
113 uint32_t gregs[24]; /* general registers */
114 float32 fregs[32]; /* floating point registers */
115 uint32_t sr; /* status register */
116 uint32_t ssr; /* saved status register */
117 uint32_t spc; /* saved program counter */
118 uint32_t gbr; /* global base register */
119 uint32_t vbr; /* vector base register */
120 uint32_t sgr; /* saved global register 15 */
121 uint32_t dbr; /* debug base register */
122 uint32_t pc; /* program counter */
123 uint32_t delayed_pc; /* target of delayed jump */
124 uint32_t mach; /* multiply and accumulate high */
125 uint32_t macl; /* multiply and accumulate low */
126 uint32_t pr; /* procedure register */
127 uint32_t fpscr; /* floating point status/control register */
128 uint32_t fpul; /* floating point communication register */
130 /* float point status register */
131 float_status fp_status;
133 /* The features that we should emulate. See sh_features above. */
134 uint32_t features;
136 /* Those belong to the specific unit (SH7750) but are handled here */
137 uint32_t mmucr; /* MMU control register */
138 uint32_t pteh; /* page table entry high register */
139 uint32_t ptel; /* page table entry low register */
140 uint32_t ptea; /* page table entry assistance register */
141 uint32_t ttb; /* tranlation table base register */
142 uint32_t tea; /* TLB exception address register */
143 uint32_t tra; /* TRAPA exception register */
144 uint32_t expevt; /* exception event register */
145 uint32_t intevt; /* interrupt event register */
147 uint32_t pvr; /* Processor Version Register */
148 uint32_t prr; /* Processor Revision Register */
149 uint32_t cvr; /* Cache Version Register */
151 uint32_t ldst;
153 CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
154 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
155 void *intc_handle;
156 int intr_at_halt; /* SR_BL ignored during sleep */
157 memory_content *movcal_backup;
158 memory_content **movcal_backup_tail;
159 } CPUSH4State;
161 CPUSH4State *cpu_sh4_init(const char *cpu_model);
162 int cpu_sh4_exec(CPUSH4State * s);
163 int cpu_sh4_signal_handler(int host_signum, void *pinfo,
164 void *puc);
165 int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
166 int mmu_idx, int is_softmmu);
167 void do_interrupt(CPUSH4State * env);
169 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
170 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
171 uint32_t mem_value);
173 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
175 static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
177 env->gbr = newtls;
180 void cpu_load_tlb(CPUSH4State * env);
182 #include "softfloat.h"
184 #define cpu_init cpu_sh4_init
185 #define cpu_exec cpu_sh4_exec
186 #define cpu_gen_code cpu_sh4_gen_code
187 #define cpu_signal_handler cpu_sh4_signal_handler
188 #define cpu_list sh4_cpu_list
190 /* MMU modes definitions */
191 #define MMU_MODE0_SUFFIX _kernel
192 #define MMU_MODE1_SUFFIX _user
193 #define MMU_USER_IDX 1
194 static inline int cpu_mmu_index (CPUState *env)
196 return (env->sr & SR_MD) == 0 ? 1 : 0;
199 #if defined(CONFIG_USER_ONLY)
200 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
202 if (newsp)
203 env->gregs[15] = newsp;
204 env->gregs[0] = 0;
206 #endif
208 #include "cpu-all.h"
209 #include "exec-all.h"
211 /* Memory access type */
212 enum {
213 /* Privilege */
214 ACCESS_PRIV = 0x01,
215 /* Direction */
216 ACCESS_WRITE = 0x02,
217 /* Type of instruction */
218 ACCESS_CODE = 0x10,
219 ACCESS_INT = 0x20
222 /* MMU control register */
223 #define MMUCR 0x1F000010
224 #define MMUCR_AT (1<<0)
225 #define MMUCR_SV (1<<8)
226 #define MMUCR_URC_BITS (6)
227 #define MMUCR_URC_OFFSET (10)
228 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
229 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
230 static inline int cpu_mmucr_urc (uint32_t mmucr)
232 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
235 /* PTEH : Page Translation Entry High register */
236 #define PTEH_ASID_BITS (8)
237 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
238 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
239 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
240 #define PTEH_VPN_BITS (22)
241 #define PTEH_VPN_OFFSET (10)
242 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
243 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
244 static inline int cpu_pteh_vpn (uint32_t pteh)
246 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
249 /* PTEL : Page Translation Entry Low register */
250 #define PTEL_V (1 << 8)
251 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
252 #define PTEL_C (1 << 3)
253 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
254 #define PTEL_D (1 << 2)
255 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
256 #define PTEL_SH (1 << 1)
257 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
258 #define PTEL_WT (1 << 0)
259 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
261 #define PTEL_SZ_HIGH_OFFSET (7)
262 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
263 #define PTEL_SZ_LOW_OFFSET (4)
264 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
265 static inline int cpu_ptel_sz (uint32_t ptel)
267 int sz;
268 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
269 sz <<= 1;
270 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
271 return sz;
274 #define PTEL_PPN_BITS (19)
275 #define PTEL_PPN_OFFSET (10)
276 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
277 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
278 static inline int cpu_ptel_ppn (uint32_t ptel)
280 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
283 #define PTEL_PR_BITS (2)
284 #define PTEL_PR_OFFSET (5)
285 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
286 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
287 static inline int cpu_ptel_pr (uint32_t ptel)
289 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
292 /* PTEA : Page Translation Entry Assistance register */
293 #define PTEA_SA_BITS (3)
294 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
295 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
296 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
297 #define PTEA_TC (1 << 3)
298 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
300 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
302 env->pc = tb->pc;
303 env->flags = tb->flags;
306 #define TB_FLAG_PENDING_MOVCA (1 << 4)
308 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
309 target_ulong *cs_base, int *flags)
311 *pc = env->pc;
312 *cs_base = 0;
313 *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
314 | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
315 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
316 | (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */
317 | (env->sr & SR_FD) /* Bit 15 */
318 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
321 #endif /* _CPU_SH4_H */