target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu/sysemu.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "exec/gdbstub.h"
  29 #include "qemu/host-utils.h"
  30 #include "qemu/config-file.h"
  31 #include "hw/pc.h"
  32 #include "hw/apic.h"
  33 #include "exec/ioport.h"
  34 #include "hyperv.h"
  35 #include "hw/pci/pci.h"
  36
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  58     KVM_CAP_INFO(SET_TSS_ADDR),
  59     KVM_CAP_INFO(EXT_CPUID),
  60     KVM_CAP_INFO(MP_STATE),
  61     KVM_CAP_LAST_INFO
  62 };
  63
  64 static bool has_msr_star;
  65 static bool has_msr_hsave_pa;
  66 static bool has_msr_tsc_adjust;
  67 static bool has_msr_tsc_deadline;
  68 static bool has_msr_async_pf_en;
  69 static bool has_msr_pv_eoi_en;
  70 static bool has_msr_misc_enable;
  71 static int lm_capable_kernel;
  72
  73 bool kvm_allows_irq0_override(void)
  74 {
  75     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  76 }
  77
  78 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  79 {
  80     struct kvm_cpuid2 *cpuid;
  81     int r, size;
  82
  83     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  84     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  85     cpuid->nent = max;
  86     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  87     if (r == 0 && cpuid->nent >= max) {
  88         r = -E2BIG;
  89     }
  90     if (r < 0) {
  91         if (r == -E2BIG) {
  92             g_free(cpuid);
  93             return NULL;
  94         } else {
  95             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  96                     strerror(-r));
  97             exit(1);
  98         }
  99     }
 100     return cpuid;
 101 }
 102
 103 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 104  * for all entries.
 105  */
 106 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 107 {
 108     struct kvm_cpuid2 *cpuid;
 109     int max = 1;
 110     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 111         max *= 2;
 112     }
 113     return cpuid;
 114 }
 115
 116 struct kvm_para_features {
 117     int cap;
 118     int feature;
 119 } para_features[] = {
 120     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 121     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 122     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 123     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 124     { -1, -1 }
 125 };
 126
 127 static int get_para_features(KVMState *s)
 128 {
 129     int i, features = 0;
 130
 131     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 132         if (kvm_check_extension(s, para_features[i].cap)) {
 133             features |= (1 << para_features[i].feature);
 134         }
 135     }
 136
 137     return features;
 138 }
 139
 140
 141 /* Returns the value for a specific register on the cpuid entry
 142  */
 143 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 144 {
 145     uint32_t ret = 0;
 146     switch (reg) {
 147     case R_EAX:
 148         ret = entry->eax;
 149         break;
 150     case R_EBX:
 151         ret = entry->ebx;
 152         break;
 153     case R_ECX:
 154         ret = entry->ecx;
 155         break;
 156     case R_EDX:
 157         ret = entry->edx;
 158         break;
 159     }
 160     return ret;
 161 }
 162
 163 /* Find matching entry for function/index on kvm_cpuid2 struct
 164  */
 165 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 166                                                  uint32_t function,
 167                                                  uint32_t index)
 168 {
 169     int i;
 170     for (i = 0; i < cpuid->nent; ++i) {
 171         if (cpuid->entries[i].function == function &&
 172             cpuid->entries[i].index == index) {
 173             return &cpuid->entries[i];
 174         }
 175     }
 176     /* not found: */
 177     return NULL;
 178 }
 179
 180 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 181                                       uint32_t index, int reg)
 182 {
 183     struct kvm_cpuid2 *cpuid;
 184     uint32_t ret = 0;
 185     uint32_t cpuid_1_edx;
 186     bool found = false;
 187
 188     cpuid = get_supported_cpuid(s);
 189
 190     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 191     if (entry) {
 192         found = true;
 193         ret = cpuid_entry_get_reg(entry, reg);
 194     }
 195
 196     /* Fixups for the data returned by KVM, below */
 197
 198     if (function == 1 && reg == R_EDX) {
 199         /* KVM before 2.6.30 misreports the following features */
 200         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 201     } else if (function == 1 && reg == R_ECX) {
 202         /* We can set the hypervisor flag, even if KVM does not return it on
 203          * GET_SUPPORTED_CPUID
 204          */
 205         ret |= CPUID_EXT_HYPERVISOR;
 206         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 207          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 208          * and the irqchip is in the kernel.
 209          */
 210         if (kvm_irqchip_in_kernel() &&
 211                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 212             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 213         }
 214
 215         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 216          * without the in-kernel irqchip
 217          */
 218         if (!kvm_irqchip_in_kernel()) {
 219             ret &= ~CPUID_EXT_X2APIC;
 220         }
 221     } else if (function == 0x80000001 && reg == R_EDX) {
 222         /* On Intel, kvm returns cpuid according to the Intel spec,
 223          * so add missing bits according to the AMD spec:
 224          */
 225         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 226         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 227     }
 228
 229     g_free(cpuid);
 230
 231     /* fallback for older kernels */
 232     if ((function == KVM_CPUID_FEATURES) && !found) {
 233         ret = get_para_features(s);
 234     }
 235
 236     return ret;
 237 }
 238
 239 typedef struct HWPoisonPage {
 240     ram_addr_t ram_addr;
 241     QLIST_ENTRY(HWPoisonPage) list;
 242 } HWPoisonPage;
 243
 244 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 245     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 246
 247 static void kvm_unpoison_all(void *param)
 248 {
 249     HWPoisonPage *page, *next_page;
 250
 251     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 252         QLIST_REMOVE(page, list);
 253         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 254         g_free(page);
 255     }
 256 }
 257
 258 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 259 {
 260     HWPoisonPage *page;
 261
 262     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 263         if (page->ram_addr == ram_addr) {
 264             return;
 265         }
 266     }
 267     page = g_malloc(sizeof(HWPoisonPage));
 268     page->ram_addr = ram_addr;
 269     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 270 }
 271
 272 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 273                                      int *max_banks)
 274 {
 275     int r;
 276
 277     r = kvm_check_extension(s, KVM_CAP_MCE);
 278     if (r > 0) {
 279         *max_banks = r;
 280         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 281     }
 282     return -ENOSYS;
 283 }
 284
 285 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 286 {
 287     CPUX86State *env = &cpu->env;
 288     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 289                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 290     uint64_t mcg_status = MCG_STATUS_MCIP;
 291
 292     if (code == BUS_MCEERR_AR) {
 293         status |= MCI_STATUS_AR | 0x134;
 294         mcg_status |= MCG_STATUS_EIPV;
 295     } else {
 296         status |= 0xc0;
 297         mcg_status |= MCG_STATUS_RIPV;
 298     }
 299     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 300                        (MCM_ADDR_PHYS << 6) | 0xc,
 301                        cpu_x86_support_mca_broadcast(env) ?
 302                        MCE_INJECT_BROADCAST : 0);
 303 }
 304
 305 static void hardware_memory_error(void)
 306 {
 307     fprintf(stderr, "Hardware memory error!\n");
 308     exit(1);
 309 }
 310
 311 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 312 {
 313     X86CPU *cpu = X86_CPU(c);
 314     CPUX86State *env = &cpu->env;
 315     ram_addr_t ram_addr;
 316     hwaddr paddr;
 317
 318     if ((env->mcg_cap & MCG_SER_P) && addr
 319         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 320         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 321             !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 322             fprintf(stderr, "Hardware memory error for memory used by "
 323                     "QEMU itself instead of guest system!\n");
 324             /* Hope we are lucky for AO MCE */
 325             if (code == BUS_MCEERR_AO) {
 326                 return 0;
 327             } else {
 328                 hardware_memory_error();
 329             }
 330         }
 331         kvm_hwpoison_page_add(ram_addr);
 332         kvm_mce_inject(cpu, paddr, code);
 333     } else {
 334         if (code == BUS_MCEERR_AO) {
 335             return 0;
 336         } else if (code == BUS_MCEERR_AR) {
 337             hardware_memory_error();
 338         } else {
 339             return 1;
 340         }
 341     }
 342     return 0;
 343 }
 344
 345 int kvm_arch_on_sigbus(int code, void *addr)
 346 {
 347     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 348         ram_addr_t ram_addr;
 349         hwaddr paddr;
 350
 351         /* Hope we are lucky for AO MCE */
 352         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 353             !kvm_physical_memory_addr_from_host(CPU(first_cpu)->kvm_state,
 354                                                 addr, &paddr)) {
 355             fprintf(stderr, "Hardware memory error for memory used by "
 356                     "QEMU itself instead of guest system!: %p\n", addr);
 357             return 0;
 358         }
 359         kvm_hwpoison_page_add(ram_addr);
 360         kvm_mce_inject(x86_env_get_cpu(first_cpu), paddr, code);
 361     } else {
 362         if (code == BUS_MCEERR_AO) {
 363             return 0;
 364         } else if (code == BUS_MCEERR_AR) {
 365             hardware_memory_error();
 366         } else {
 367             return 1;
 368         }
 369     }
 370     return 0;
 371 }
 372
 373 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 374 {
 375     CPUX86State *env = &cpu->env;
 376
 377     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 378         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 379         struct kvm_x86_mce mce;
 380
 381         env->exception_injected = -1;
 382
 383         /*
 384          * There must be at least one bank in use if an MCE is pending.
 385          * Find it and use its values for the event injection.
 386          */
 387         for (bank = 0; bank < bank_num; bank++) {
 388             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 389                 break;
 390             }
 391         }
 392         assert(bank < bank_num);
 393
 394         mce.bank = bank;
 395         mce.status = env->mce_banks[bank * 4 + 1];
 396         mce.mcg_status = env->mcg_status;
 397         mce.addr = env->mce_banks[bank * 4 + 2];
 398         mce.misc = env->mce_banks[bank * 4 + 3];
 399
 400         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 401     }
 402     return 0;
 403 }
 404
 405 static void cpu_update_state(void *opaque, int running, RunState state)
 406 {
 407     CPUX86State *env = opaque;
 408
 409     if (running) {
 410         env->tsc_valid = false;
 411     }
 412 }
 413
 414 #define KVM_MAX_CPUID_ENTRIES  100
 415 int kvm_arch_init_vcpu(CPUState *cs)
 416 {
 417     struct {
 418         struct kvm_cpuid2 cpuid;
 419         struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
 420     } QEMU_PACKED cpuid_data;
 421     X86CPU *cpu = X86_CPU(cs);
 422     CPUX86State *env = &cpu->env;
 423     uint32_t limit, i, j, cpuid_i;
 424     uint32_t unused;
 425     struct kvm_cpuid_entry2 *c;
 426     uint32_t signature[3];
 427     int r;
 428
 429     cpuid_i = 0;
 430
 431     /* Paravirtualization CPUIDs */
 432     c = &cpuid_data.entries[cpuid_i++];
 433     memset(c, 0, sizeof(*c));
 434     c->function = KVM_CPUID_SIGNATURE;
 435     if (!hyperv_enabled()) {
 436         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 437         c->eax = 0;
 438     } else {
 439         memcpy(signature, "Microsoft Hv", 12);
 440         c->eax = HYPERV_CPUID_MIN;
 441     }
 442     c->ebx = signature[0];
 443     c->ecx = signature[1];
 444     c->edx = signature[2];
 445
 446     c = &cpuid_data.entries[cpuid_i++];
 447     memset(c, 0, sizeof(*c));
 448     c->function = KVM_CPUID_FEATURES;
 449     c->eax = env->cpuid_kvm_features;
 450
 451     if (hyperv_enabled()) {
 452         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 453         c->eax = signature[0];
 454
 455         c = &cpuid_data.entries[cpuid_i++];
 456         memset(c, 0, sizeof(*c));
 457         c->function = HYPERV_CPUID_VERSION;
 458         c->eax = 0x00001bbc;
 459         c->ebx = 0x00060001;
 460
 461         c = &cpuid_data.entries[cpuid_i++];
 462         memset(c, 0, sizeof(*c));
 463         c->function = HYPERV_CPUID_FEATURES;
 464         if (hyperv_relaxed_timing_enabled()) {
 465             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 466         }
 467         if (hyperv_vapic_recommended()) {
 468             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 469             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 470         }
 471
 472         c = &cpuid_data.entries[cpuid_i++];
 473         memset(c, 0, sizeof(*c));
 474         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 475         if (hyperv_relaxed_timing_enabled()) {
 476             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 477         }
 478         if (hyperv_vapic_recommended()) {
 479             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 480         }
 481         c->ebx = hyperv_get_spinlock_retries();
 482
 483         c = &cpuid_data.entries[cpuid_i++];
 484         memset(c, 0, sizeof(*c));
 485         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 486         c->eax = 0x40;
 487         c->ebx = 0x40;
 488
 489         c = &cpuid_data.entries[cpuid_i++];
 490         memset(c, 0, sizeof(*c));
 491         c->function = KVM_CPUID_SIGNATURE_NEXT;
 492         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 493         c->eax = 0;
 494         c->ebx = signature[0];
 495         c->ecx = signature[1];
 496         c->edx = signature[2];
 497     }
 498
 499     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 500
 501     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 502
 503     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 504
 505     for (i = 0; i <= limit; i++) {
 506         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 507             fprintf(stderr, "unsupported level value: 0x%x\n", limit);
 508             abort();
 509         }
 510         c = &cpuid_data.entries[cpuid_i++];
 511
 512         switch (i) {
 513         case 2: {
 514             /* Keep reading function 2 till all the input is received */
 515             int times;
 516
 517             c->function = i;
 518             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 519                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 520             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 521             times = c->eax & 0xff;
 522
 523             for (j = 1; j < times; ++j) {
 524                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 525                     fprintf(stderr, "cpuid_data is full, no space for "
 526                             "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
 527                     abort();
 528                 }
 529                 c = &cpuid_data.entries[cpuid_i++];
 530                 c->function = i;
 531                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 532                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 533             }
 534             break;
 535         }
 536         case 4:
 537         case 0xb:
 538         case 0xd:
 539             for (j = 0; ; j++) {
 540                 if (i == 0xd && j == 64) {
 541                     break;
 542                 }
 543                 c->function = i;
 544                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 545                 c->index = j;
 546                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 547
 548                 if (i == 4 && c->eax == 0) {
 549                     break;
 550                 }
 551                 if (i == 0xb && !(c->ecx & 0xff00)) {
 552                     break;
 553                 }
 554                 if (i == 0xd && c->eax == 0) {
 555                     continue;
 556                 }
 557                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 558                     fprintf(stderr, "cpuid_data is full, no space for "
 559                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
 560                     abort();
 561                 }
 562                 c = &cpuid_data.entries[cpuid_i++];
 563             }
 564             break;
 565         default:
 566             c->function = i;
 567             c->flags = 0;
 568             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 569             break;
 570         }
 571     }
 572     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 573
 574     for (i = 0x80000000; i <= limit; i++) {
 575         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 576             fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
 577             abort();
 578         }
 579         c = &cpuid_data.entries[cpuid_i++];
 580
 581         c->function = i;
 582         c->flags = 0;
 583         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 584     }
 585
 586     /* Call Centaur's CPUID instructions they are supported. */
 587     if (env->cpuid_xlevel2 > 0) {
 588         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 589
 590         for (i = 0xC0000000; i <= limit; i++) {
 591             if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 592                 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
 593                 abort();
 594             }
 595             c = &cpuid_data.entries[cpuid_i++];
 596
 597             c->function = i;
 598             c->flags = 0;
 599             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 600         }
 601     }
 602
 603     cpuid_data.cpuid.nent = cpuid_i;
 604
 605     if (((env->cpuid_version >> 8)&0xF) >= 6
 606         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 607         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
 608         uint64_t mcg_cap;
 609         int banks;
 610         int ret;
 611
 612         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
 613         if (ret < 0) {
 614             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 615             return ret;
 616         }
 617
 618         if (banks > MCE_BANKS_DEF) {
 619             banks = MCE_BANKS_DEF;
 620         }
 621         mcg_cap &= MCE_CAP_DEF;
 622         mcg_cap |= banks;
 623         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
 624         if (ret < 0) {
 625             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 626             return ret;
 627         }
 628
 629         env->mcg_cap = mcg_cap;
 630     }
 631
 632     qemu_add_vm_change_state_handler(cpu_update_state, env);
 633
 634     cpuid_data.cpuid.padding = 0;
 635     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
 636     if (r) {
 637         return r;
 638     }
 639
 640     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
 641     if (r && env->tsc_khz) {
 642         r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
 643         if (r < 0) {
 644             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 645             return r;
 646         }
 647     }
 648
 649     if (kvm_has_xsave()) {
 650         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 651     }
 652
 653     return 0;
 654 }
 655
 656 void kvm_arch_reset_vcpu(CPUState *cs)
 657 {
 658     X86CPU *cpu = X86_CPU(cs);
 659     CPUX86State *env = &cpu->env;
 660
 661     env->exception_injected = -1;
 662     env->interrupt_injected = -1;
 663     env->xcr0 = 1;
 664     if (kvm_irqchip_in_kernel()) {
 665         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 666                                           KVM_MP_STATE_UNINITIALIZED;
 667     } else {
 668         env->mp_state = KVM_MP_STATE_RUNNABLE;
 669     }
 670 }
 671
 672 static int kvm_get_supported_msrs(KVMState *s)
 673 {
 674     static int kvm_supported_msrs;
 675     int ret = 0;
 676
 677     /* first time */
 678     if (kvm_supported_msrs == 0) {
 679         struct kvm_msr_list msr_list, *kvm_msr_list;
 680
 681         kvm_supported_msrs = -1;
 682
 683         /* Obtain MSR list from KVM.  These are the MSRs that we must
 684          * save/restore */
 685         msr_list.nmsrs = 0;
 686         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 687         if (ret < 0 && ret != -E2BIG) {
 688             return ret;
 689         }
 690         /* Old kernel modules had a bug and could write beyond the provided
 691            memory. Allocate at least a safe amount of 1K. */
 692         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 693                                               msr_list.nmsrs *
 694                                               sizeof(msr_list.indices[0])));
 695
 696         kvm_msr_list->nmsrs = msr_list.nmsrs;
 697         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 698         if (ret >= 0) {
 699             int i;
 700
 701             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 702                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 703                     has_msr_star = true;
 704                     continue;
 705                 }
 706                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 707                     has_msr_hsave_pa = true;
 708                     continue;
 709                 }
 710                 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
 711                     has_msr_tsc_adjust = true;
 712                     continue;
 713                 }
 714                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 715                     has_msr_tsc_deadline = true;
 716                     continue;
 717                 }
 718                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 719                     has_msr_misc_enable = true;
 720                     continue;
 721                 }
 722             }
 723         }
 724
 725         g_free(kvm_msr_list);
 726     }
 727
 728     return ret;
 729 }
 730
 731 int kvm_arch_init(KVMState *s)
 732 {
 733     QemuOptsList *list = qemu_find_opts("machine");
 734     uint64_t identity_base = 0xfffbc000;
 735     uint64_t shadow_mem;
 736     int ret;
 737     struct utsname utsname;
 738
 739     ret = kvm_get_supported_msrs(s);
 740     if (ret < 0) {
 741         return ret;
 742     }
 743
 744     uname(&utsname);
 745     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 746
 747     /*
 748      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 749      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 750      * Since these must be part of guest physical memory, we need to allocate
 751      * them, both by setting their start addresses in the kernel and by
 752      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 753      *
 754      * Older KVM versions may not support setting the identity map base. In
 755      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 756      * size.
 757      */
 758     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 759         /* Allows up to 16M BIOSes. */
 760         identity_base = 0xfeffc000;
 761
 762         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 763         if (ret < 0) {
 764             return ret;
 765         }
 766     }
 767
 768     /* Set TSS base one page after EPT identity map. */
 769     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 770     if (ret < 0) {
 771         return ret;
 772     }
 773
 774     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 775     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 776     if (ret < 0) {
 777         fprintf(stderr, "e820_add_entry() table is full\n");
 778         return ret;
 779     }
 780     qemu_register_reset(kvm_unpoison_all, NULL);
 781
 782     if (!QTAILQ_EMPTY(&list->head)) {
 783         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 784                                        "kvm_shadow_mem", -1);
 785         if (shadow_mem != -1) {
 786             shadow_mem /= 4096;
 787             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 788             if (ret < 0) {
 789                 return ret;
 790             }
 791         }
 792     }
 793     return 0;
 794 }
 795
 796 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 797 {
 798     lhs->selector = rhs->selector;
 799     lhs->base = rhs->base;
 800     lhs->limit = rhs->limit;
 801     lhs->type = 3;
 802     lhs->present = 1;
 803     lhs->dpl = 3;
 804     lhs->db = 0;
 805     lhs->s = 1;
 806     lhs->l = 0;
 807     lhs->g = 0;
 808     lhs->avl = 0;
 809     lhs->unusable = 0;
 810 }
 811
 812 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 813 {
 814     unsigned flags = rhs->flags;
 815     lhs->selector = rhs->selector;
 816     lhs->base = rhs->base;
 817     lhs->limit = rhs->limit;
 818     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 819     lhs->present = (flags & DESC_P_MASK) != 0;
 820     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 821     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 822     lhs->s = (flags & DESC_S_MASK) != 0;
 823     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 824     lhs->g = (flags & DESC_G_MASK) != 0;
 825     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 826     lhs->unusable = 0;
 827     lhs->padding = 0;
 828 }
 829
 830 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 831 {
 832     lhs->selector = rhs->selector;
 833     lhs->base = rhs->base;
 834     lhs->limit = rhs->limit;
 835     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 836                  (rhs->present * DESC_P_MASK) |
 837                  (rhs->dpl << DESC_DPL_SHIFT) |
 838                  (rhs->db << DESC_B_SHIFT) |
 839                  (rhs->s * DESC_S_MASK) |
 840                  (rhs->l << DESC_L_SHIFT) |
 841                  (rhs->g * DESC_G_MASK) |
 842                  (rhs->avl * DESC_AVL_MASK);
 843 }
 844
 845 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 846 {
 847     if (set) {
 848         *kvm_reg = *qemu_reg;
 849     } else {
 850         *qemu_reg = *kvm_reg;
 851     }
 852 }
 853
 854 static int kvm_getput_regs(X86CPU *cpu, int set)
 855 {
 856     CPUX86State *env = &cpu->env;
 857     struct kvm_regs regs;
 858     int ret = 0;
 859
 860     if (!set) {
 861         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
 862         if (ret < 0) {
 863             return ret;
 864         }
 865     }
 866
 867     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 868     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 869     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 870     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 871     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 872     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 873     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 874     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 875 #ifdef TARGET_X86_64
 876     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 877     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 878     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 879     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 880     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 881     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 882     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 883     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 884 #endif
 885
 886     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 887     kvm_getput_reg(&regs.rip, &env->eip, set);
 888
 889     if (set) {
 890         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
 891     }
 892
 893     return ret;
 894 }
 895
 896 static int kvm_put_fpu(X86CPU *cpu)
 897 {
 898     CPUX86State *env = &cpu->env;
 899     struct kvm_fpu fpu;
 900     int i;
 901
 902     memset(&fpu, 0, sizeof fpu);
 903     fpu.fsw = env->fpus & ~(7 << 11);
 904     fpu.fsw |= (env->fpstt & 7) << 11;
 905     fpu.fcw = env->fpuc;
 906     fpu.last_opcode = env->fpop;
 907     fpu.last_ip = env->fpip;
 908     fpu.last_dp = env->fpdp;
 909     for (i = 0; i < 8; ++i) {
 910         fpu.ftwx |= (!env->fptags[i]) << i;
 911     }
 912     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 913     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 914     fpu.mxcsr = env->mxcsr;
 915
 916     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
 917 }
 918
 919 #define XSAVE_FCW_FSW     0
 920 #define XSAVE_FTW_FOP     1
 921 #define XSAVE_CWD_RIP     2
 922 #define XSAVE_CWD_RDP     4
 923 #define XSAVE_MXCSR       6
 924 #define XSAVE_ST_SPACE    8
 925 #define XSAVE_XMM_SPACE   40
 926 #define XSAVE_XSTATE_BV   128
 927 #define XSAVE_YMMH_SPACE  144
 928
 929 static int kvm_put_xsave(X86CPU *cpu)
 930 {
 931     CPUX86State *env = &cpu->env;
 932     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 933     uint16_t cwd, swd, twd;
 934     int i, r;
 935
 936     if (!kvm_has_xsave()) {
 937         return kvm_put_fpu(cpu);
 938     }
 939
 940     memset(xsave, 0, sizeof(struct kvm_xsave));
 941     twd = 0;
 942     swd = env->fpus & ~(7 << 11);
 943     swd |= (env->fpstt & 7) << 11;
 944     cwd = env->fpuc;
 945     for (i = 0; i < 8; ++i) {
 946         twd |= (!env->fptags[i]) << i;
 947     }
 948     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 949     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 950     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 951     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 952     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 953             sizeof env->fpregs);
 954     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 955             sizeof env->xmm_regs);
 956     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 957     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 958     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 959             sizeof env->ymmh_regs);
 960     r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
 961     return r;
 962 }
 963
 964 static int kvm_put_xcrs(X86CPU *cpu)
 965 {
 966     CPUX86State *env = &cpu->env;
 967     struct kvm_xcrs xcrs;
 968
 969     if (!kvm_has_xcrs()) {
 970         return 0;
 971     }
 972
 973     xcrs.nr_xcrs = 1;
 974     xcrs.flags = 0;
 975     xcrs.xcrs[0].xcr = 0;
 976     xcrs.xcrs[0].value = env->xcr0;
 977     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
 978 }
 979
 980 static int kvm_put_sregs(X86CPU *cpu)
 981 {
 982     CPUX86State *env = &cpu->env;
 983     struct kvm_sregs sregs;
 984
 985     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 986     if (env->interrupt_injected >= 0) {
 987         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 988                 (uint64_t)1 << (env->interrupt_injected % 64);
 989     }
 990
 991     if ((env->eflags & VM_MASK)) {
 992         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 993         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 994         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 995         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 996         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 997         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 998     } else {
 999         set_seg(&sregs.cs, &env->segs[R_CS]);
1000         set_seg(&sregs.ds, &env->segs[R_DS]);
1001         set_seg(&sregs.es, &env->segs[R_ES]);
1002         set_seg(&sregs.fs, &env->segs[R_FS]);
1003         set_seg(&sregs.gs, &env->segs[R_GS]);
1004         set_seg(&sregs.ss, &env->segs[R_SS]);
1005     }
1006
1007     set_seg(&sregs.tr, &env->tr);
1008     set_seg(&sregs.ldt, &env->ldt);
1009
1010     sregs.idt.limit = env->idt.limit;
1011     sregs.idt.base = env->idt.base;
1012     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1013     sregs.gdt.limit = env->gdt.limit;
1014     sregs.gdt.base = env->gdt.base;
1015     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1016
1017     sregs.cr0 = env->cr[0];
1018     sregs.cr2 = env->cr[2];
1019     sregs.cr3 = env->cr[3];
1020     sregs.cr4 = env->cr[4];
1021
1022     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
1023     sregs.apic_base = cpu_get_apic_base(env->apic_state);
1024
1025     sregs.efer = env->efer;
1026
1027     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1028 }
1029
1030 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1031                               uint32_t index, uint64_t value)
1032 {
1033     entry->index = index;
1034     entry->data = value;
1035 }
1036
1037 static int kvm_put_msrs(X86CPU *cpu, int level)
1038 {
1039     CPUX86State *env = &cpu->env;
1040     struct {
1041         struct kvm_msrs info;
1042         struct kvm_msr_entry entries[100];
1043     } msr_data;
1044     struct kvm_msr_entry *msrs = msr_data.entries;
1045     int n = 0;
1046
1047     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1048     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1049     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1050     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1051     if (has_msr_star) {
1052         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1053     }
1054     if (has_msr_hsave_pa) {
1055         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1056     }
1057     if (has_msr_tsc_adjust) {
1058         kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1059     }
1060     if (has_msr_tsc_deadline) {
1061         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1062     }
1063     if (has_msr_misc_enable) {
1064         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1065                           env->msr_ia32_misc_enable);
1066     }
1067 #ifdef TARGET_X86_64
1068     if (lm_capable_kernel) {
1069         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1070         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1071         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1072         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1073     }
1074 #endif
1075     if (level == KVM_PUT_FULL_STATE) {
1076         /*
1077          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1078          * writeback. Until this is fixed, we only write the offset to SMP
1079          * guests after migration, desynchronizing the VCPUs, but avoiding
1080          * huge jump-backs that would occur without any writeback at all.
1081          */
1082         if (smp_cpus == 1 || env->tsc != 0) {
1083             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1084         }
1085     }
1086     /*
1087      * The following paravirtual MSRs have side effects on the guest or are
1088      * too heavy for normal writeback. Limit them to reset or full state
1089      * updates.
1090      */
1091     if (level >= KVM_PUT_RESET_STATE) {
1092         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1093                           env->system_time_msr);
1094         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1095         if (has_msr_async_pf_en) {
1096             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1097                               env->async_pf_en_msr);
1098         }
1099         if (has_msr_pv_eoi_en) {
1100             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1101                               env->pv_eoi_en_msr);
1102         }
1103         if (hyperv_hypercall_available()) {
1104             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1105             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1106         }
1107         if (hyperv_vapic_recommended()) {
1108             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1109         }
1110     }
1111     if (env->mcg_cap) {
1112         int i;
1113
1114         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1115         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1116         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1117             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1118         }
1119     }
1120
1121     msr_data.info.nmsrs = n;
1122
1123     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1124
1125 }
1126
1127
1128 static int kvm_get_fpu(X86CPU *cpu)
1129 {
1130     CPUX86State *env = &cpu->env;
1131     struct kvm_fpu fpu;
1132     int i, ret;
1133
1134     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1135     if (ret < 0) {
1136         return ret;
1137     }
1138
1139     env->fpstt = (fpu.fsw >> 11) & 7;
1140     env->fpus = fpu.fsw;
1141     env->fpuc = fpu.fcw;
1142     env->fpop = fpu.last_opcode;
1143     env->fpip = fpu.last_ip;
1144     env->fpdp = fpu.last_dp;
1145     for (i = 0; i < 8; ++i) {
1146         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1147     }
1148     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1149     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1150     env->mxcsr = fpu.mxcsr;
1151
1152     return 0;
1153 }
1154
1155 static int kvm_get_xsave(X86CPU *cpu)
1156 {
1157     CPUX86State *env = &cpu->env;
1158     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1159     int ret, i;
1160     uint16_t cwd, swd, twd;
1161
1162     if (!kvm_has_xsave()) {
1163         return kvm_get_fpu(cpu);
1164     }
1165
1166     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1167     if (ret < 0) {
1168         return ret;
1169     }
1170
1171     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1172     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1173     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1174     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1175     env->fpstt = (swd >> 11) & 7;
1176     env->fpus = swd;
1177     env->fpuc = cwd;
1178     for (i = 0; i < 8; ++i) {
1179         env->fptags[i] = !((twd >> i) & 1);
1180     }
1181     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1182     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1183     env->mxcsr = xsave->region[XSAVE_MXCSR];
1184     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1185             sizeof env->fpregs);
1186     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1187             sizeof env->xmm_regs);
1188     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1189     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1190             sizeof env->ymmh_regs);
1191     return 0;
1192 }
1193
1194 static int kvm_get_xcrs(X86CPU *cpu)
1195 {
1196     CPUX86State *env = &cpu->env;
1197     int i, ret;
1198     struct kvm_xcrs xcrs;
1199
1200     if (!kvm_has_xcrs()) {
1201         return 0;
1202     }
1203
1204     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1205     if (ret < 0) {
1206         return ret;
1207     }
1208
1209     for (i = 0; i < xcrs.nr_xcrs; i++) {
1210         /* Only support xcr0 now */
1211         if (xcrs.xcrs[0].xcr == 0) {
1212             env->xcr0 = xcrs.xcrs[0].value;
1213             break;
1214         }
1215     }
1216     return 0;
1217 }
1218
1219 static int kvm_get_sregs(X86CPU *cpu)
1220 {
1221     CPUX86State *env = &cpu->env;
1222     struct kvm_sregs sregs;
1223     uint32_t hflags;
1224     int bit, i, ret;
1225
1226     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1227     if (ret < 0) {
1228         return ret;
1229     }
1230
1231     /* There can only be one pending IRQ set in the bitmap at a time, so try
1232        to find it and save its number instead (-1 for none). */
1233     env->interrupt_injected = -1;
1234     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1235         if (sregs.interrupt_bitmap[i]) {
1236             bit = ctz64(sregs.interrupt_bitmap[i]);
1237             env->interrupt_injected = i * 64 + bit;
1238             break;
1239         }
1240     }
1241
1242     get_seg(&env->segs[R_CS], &sregs.cs);
1243     get_seg(&env->segs[R_DS], &sregs.ds);
1244     get_seg(&env->segs[R_ES], &sregs.es);
1245     get_seg(&env->segs[R_FS], &sregs.fs);
1246     get_seg(&env->segs[R_GS], &sregs.gs);
1247     get_seg(&env->segs[R_SS], &sregs.ss);
1248
1249     get_seg(&env->tr, &sregs.tr);
1250     get_seg(&env->ldt, &sregs.ldt);
1251
1252     env->idt.limit = sregs.idt.limit;
1253     env->idt.base = sregs.idt.base;
1254     env->gdt.limit = sregs.gdt.limit;
1255     env->gdt.base = sregs.gdt.base;
1256
1257     env->cr[0] = sregs.cr0;
1258     env->cr[2] = sregs.cr2;
1259     env->cr[3] = sregs.cr3;
1260     env->cr[4] = sregs.cr4;
1261
1262     env->efer = sregs.efer;
1263
1264     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1265
1266 #define HFLAG_COPY_MASK \
1267     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1268        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1269        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1270        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1271
1272     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1273     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1274     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1275                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1276     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1277     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1278                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1279
1280     if (env->efer & MSR_EFER_LMA) {
1281         hflags |= HF_LMA_MASK;
1282     }
1283
1284     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1285         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1286     } else {
1287         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1288                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1289         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1290                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1291         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1292             !(hflags & HF_CS32_MASK)) {
1293             hflags |= HF_ADDSEG_MASK;
1294         } else {
1295             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1296                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1297         }
1298     }
1299     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1300
1301     return 0;
1302 }
1303
1304 static int kvm_get_msrs(X86CPU *cpu)
1305 {
1306     CPUX86State *env = &cpu->env;
1307     struct {
1308         struct kvm_msrs info;
1309         struct kvm_msr_entry entries[100];
1310     } msr_data;
1311     struct kvm_msr_entry *msrs = msr_data.entries;
1312     int ret, i, n;
1313
1314     n = 0;
1315     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1316     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1317     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1318     msrs[n++].index = MSR_PAT;
1319     if (has_msr_star) {
1320         msrs[n++].index = MSR_STAR;
1321     }
1322     if (has_msr_hsave_pa) {
1323         msrs[n++].index = MSR_VM_HSAVE_PA;
1324     }
1325     if (has_msr_tsc_adjust) {
1326         msrs[n++].index = MSR_TSC_ADJUST;
1327     }
1328     if (has_msr_tsc_deadline) {
1329         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1330     }
1331     if (has_msr_misc_enable) {
1332         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1333     }
1334
1335     if (!env->tsc_valid) {
1336         msrs[n++].index = MSR_IA32_TSC;
1337         env->tsc_valid = !runstate_is_running();
1338     }
1339
1340 #ifdef TARGET_X86_64
1341     if (lm_capable_kernel) {
1342         msrs[n++].index = MSR_CSTAR;
1343         msrs[n++].index = MSR_KERNELGSBASE;
1344         msrs[n++].index = MSR_FMASK;
1345         msrs[n++].index = MSR_LSTAR;
1346     }
1347 #endif
1348     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1349     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1350     if (has_msr_async_pf_en) {
1351         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1352     }
1353     if (has_msr_pv_eoi_en) {
1354         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1355     }
1356
1357     if (env->mcg_cap) {
1358         msrs[n++].index = MSR_MCG_STATUS;
1359         msrs[n++].index = MSR_MCG_CTL;
1360         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1361             msrs[n++].index = MSR_MC0_CTL + i;
1362         }
1363     }
1364
1365     msr_data.info.nmsrs = n;
1366     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1367     if (ret < 0) {
1368         return ret;
1369     }
1370
1371     for (i = 0; i < ret; i++) {
1372         switch (msrs[i].index) {
1373         case MSR_IA32_SYSENTER_CS:
1374             env->sysenter_cs = msrs[i].data;
1375             break;
1376         case MSR_IA32_SYSENTER_ESP:
1377             env->sysenter_esp = msrs[i].data;
1378             break;
1379         case MSR_IA32_SYSENTER_EIP:
1380             env->sysenter_eip = msrs[i].data;
1381             break;
1382         case MSR_PAT:
1383             env->pat = msrs[i].data;
1384             break;
1385         case MSR_STAR:
1386             env->star = msrs[i].data;
1387             break;
1388 #ifdef TARGET_X86_64
1389         case MSR_CSTAR:
1390             env->cstar = msrs[i].data;
1391             break;
1392         case MSR_KERNELGSBASE:
1393             env->kernelgsbase = msrs[i].data;
1394             break;
1395         case MSR_FMASK:
1396             env->fmask = msrs[i].data;
1397             break;
1398         case MSR_LSTAR:
1399             env->lstar = msrs[i].data;
1400             break;
1401 #endif
1402         case MSR_IA32_TSC:
1403             env->tsc = msrs[i].data;
1404             break;
1405         case MSR_TSC_ADJUST:
1406             env->tsc_adjust = msrs[i].data;
1407             break;
1408         case MSR_IA32_TSCDEADLINE:
1409             env->tsc_deadline = msrs[i].data;
1410             break;
1411         case MSR_VM_HSAVE_PA:
1412             env->vm_hsave = msrs[i].data;
1413             break;
1414         case MSR_KVM_SYSTEM_TIME:
1415             env->system_time_msr = msrs[i].data;
1416             break;
1417         case MSR_KVM_WALL_CLOCK:
1418             env->wall_clock_msr = msrs[i].data;
1419             break;
1420         case MSR_MCG_STATUS:
1421             env->mcg_status = msrs[i].data;
1422             break;
1423         case MSR_MCG_CTL:
1424             env->mcg_ctl = msrs[i].data;
1425             break;
1426         case MSR_IA32_MISC_ENABLE:
1427             env->msr_ia32_misc_enable = msrs[i].data;
1428             break;
1429         default:
1430             if (msrs[i].index >= MSR_MC0_CTL &&
1431                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1432                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1433             }
1434             break;
1435         case MSR_KVM_ASYNC_PF_EN:
1436             env->async_pf_en_msr = msrs[i].data;
1437             break;
1438         case MSR_KVM_PV_EOI_EN:
1439             env->pv_eoi_en_msr = msrs[i].data;
1440             break;
1441         }
1442     }
1443
1444     return 0;
1445 }
1446
1447 static int kvm_put_mp_state(X86CPU *cpu)
1448 {
1449     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1450
1451     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1452 }
1453
1454 static int kvm_get_mp_state(X86CPU *cpu)
1455 {
1456     CPUX86State *env = &cpu->env;
1457     struct kvm_mp_state mp_state;
1458     int ret;
1459
1460     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state);
1461     if (ret < 0) {
1462         return ret;
1463     }
1464     env->mp_state = mp_state.mp_state;
1465     if (kvm_irqchip_in_kernel()) {
1466         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1467     }
1468     return 0;
1469 }
1470
1471 static int kvm_get_apic(X86CPU *cpu)
1472 {
1473     CPUX86State *env = &cpu->env;
1474     DeviceState *apic = env->apic_state;
1475     struct kvm_lapic_state kapic;
1476     int ret;
1477
1478     if (apic && kvm_irqchip_in_kernel()) {
1479         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1480         if (ret < 0) {
1481             return ret;
1482         }
1483
1484         kvm_get_apic_state(apic, &kapic);
1485     }
1486     return 0;
1487 }
1488
1489 static int kvm_put_apic(X86CPU *cpu)
1490 {
1491     CPUX86State *env = &cpu->env;
1492     DeviceState *apic = env->apic_state;
1493     struct kvm_lapic_state kapic;
1494
1495     if (apic && kvm_irqchip_in_kernel()) {
1496         kvm_put_apic_state(apic, &kapic);
1497
1498         return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1499     }
1500     return 0;
1501 }
1502
1503 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1504 {
1505     CPUX86State *env = &cpu->env;
1506     struct kvm_vcpu_events events;
1507
1508     if (!kvm_has_vcpu_events()) {
1509         return 0;
1510     }
1511
1512     events.exception.injected = (env->exception_injected >= 0);
1513     events.exception.nr = env->exception_injected;
1514     events.exception.has_error_code = env->has_error_code;
1515     events.exception.error_code = env->error_code;
1516     events.exception.pad = 0;
1517
1518     events.interrupt.injected = (env->interrupt_injected >= 0);
1519     events.interrupt.nr = env->interrupt_injected;
1520     events.interrupt.soft = env->soft_interrupt;
1521
1522     events.nmi.injected = env->nmi_injected;
1523     events.nmi.pending = env->nmi_pending;
1524     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1525     events.nmi.pad = 0;
1526
1527     events.sipi_vector = env->sipi_vector;
1528
1529     events.flags = 0;
1530     if (level >= KVM_PUT_RESET_STATE) {
1531         events.flags |=
1532             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1533     }
1534
1535     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1536 }
1537
1538 static int kvm_get_vcpu_events(X86CPU *cpu)
1539 {
1540     CPUX86State *env = &cpu->env;
1541     struct kvm_vcpu_events events;
1542     int ret;
1543
1544     if (!kvm_has_vcpu_events()) {
1545         return 0;
1546     }
1547
1548     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1549     if (ret < 0) {
1550        return ret;
1551     }
1552     env->exception_injected =
1553        events.exception.injected ? events.exception.nr : -1;
1554     env->has_error_code = events.exception.has_error_code;
1555     env->error_code = events.exception.error_code;
1556
1557     env->interrupt_injected =
1558         events.interrupt.injected ? events.interrupt.nr : -1;
1559     env->soft_interrupt = events.interrupt.soft;
1560
1561     env->nmi_injected = events.nmi.injected;
1562     env->nmi_pending = events.nmi.pending;
1563     if (events.nmi.masked) {
1564         env->hflags2 |= HF2_NMI_MASK;
1565     } else {
1566         env->hflags2 &= ~HF2_NMI_MASK;
1567     }
1568
1569     env->sipi_vector = events.sipi_vector;
1570
1571     return 0;
1572 }
1573
1574 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1575 {
1576     CPUX86State *env = &cpu->env;
1577     int ret = 0;
1578     unsigned long reinject_trap = 0;
1579
1580     if (!kvm_has_vcpu_events()) {
1581         if (env->exception_injected == 1) {
1582             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1583         } else if (env->exception_injected == 3) {
1584             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1585         }
1586         env->exception_injected = -1;
1587     }
1588
1589     /*
1590      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1591      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1592      * by updating the debug state once again if single-stepping is on.
1593      * Another reason to call kvm_update_guest_debug here is a pending debug
1594      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1595      * reinject them via SET_GUEST_DEBUG.
1596      */
1597     if (reinject_trap ||
1598         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1599         ret = kvm_update_guest_debug(env, reinject_trap);
1600     }
1601     return ret;
1602 }
1603
1604 static int kvm_put_debugregs(X86CPU *cpu)
1605 {
1606     CPUX86State *env = &cpu->env;
1607     struct kvm_debugregs dbgregs;
1608     int i;
1609
1610     if (!kvm_has_debugregs()) {
1611         return 0;
1612     }
1613
1614     for (i = 0; i < 4; i++) {
1615         dbgregs.db[i] = env->dr[i];
1616     }
1617     dbgregs.dr6 = env->dr[6];
1618     dbgregs.dr7 = env->dr[7];
1619     dbgregs.flags = 0;
1620
1621     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1622 }
1623
1624 static int kvm_get_debugregs(X86CPU *cpu)
1625 {
1626     CPUX86State *env = &cpu->env;
1627     struct kvm_debugregs dbgregs;
1628     int i, ret;
1629
1630     if (!kvm_has_debugregs()) {
1631         return 0;
1632     }
1633
1634     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1635     if (ret < 0) {
1636         return ret;
1637     }
1638     for (i = 0; i < 4; i++) {
1639         env->dr[i] = dbgregs.db[i];
1640     }
1641     env->dr[4] = env->dr[6] = dbgregs.dr6;
1642     env->dr[5] = env->dr[7] = dbgregs.dr7;
1643
1644     return 0;
1645 }
1646
1647 int kvm_arch_put_registers(CPUState *cpu, int level)
1648 {
1649     X86CPU *x86_cpu = X86_CPU(cpu);
1650     int ret;
1651
1652     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1653
1654     ret = kvm_getput_regs(x86_cpu, 1);
1655     if (ret < 0) {
1656         return ret;
1657     }
1658     ret = kvm_put_xsave(x86_cpu);
1659     if (ret < 0) {
1660         return ret;
1661     }
1662     ret = kvm_put_xcrs(x86_cpu);
1663     if (ret < 0) {
1664         return ret;
1665     }
1666     ret = kvm_put_sregs(x86_cpu);
1667     if (ret < 0) {
1668         return ret;
1669     }
1670     /* must be before kvm_put_msrs */
1671     ret = kvm_inject_mce_oldstyle(x86_cpu);
1672     if (ret < 0) {
1673         return ret;
1674     }
1675     ret = kvm_put_msrs(x86_cpu, level);
1676     if (ret < 0) {
1677         return ret;
1678     }
1679     if (level >= KVM_PUT_RESET_STATE) {
1680         ret = kvm_put_mp_state(x86_cpu);
1681         if (ret < 0) {
1682             return ret;
1683         }
1684         ret = kvm_put_apic(x86_cpu);
1685         if (ret < 0) {
1686             return ret;
1687         }
1688     }
1689     ret = kvm_put_vcpu_events(x86_cpu, level);
1690     if (ret < 0) {
1691         return ret;
1692     }
1693     ret = kvm_put_debugregs(x86_cpu);
1694     if (ret < 0) {
1695         return ret;
1696     }
1697     /* must be last */
1698     ret = kvm_guest_debug_workarounds(x86_cpu);
1699     if (ret < 0) {
1700         return ret;
1701     }
1702     return 0;
1703 }
1704
1705 int kvm_arch_get_registers(CPUState *cs)
1706 {
1707     X86CPU *cpu = X86_CPU(cs);
1708     int ret;
1709
1710     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1711
1712     ret = kvm_getput_regs(cpu, 0);
1713     if (ret < 0) {
1714         return ret;
1715     }
1716     ret = kvm_get_xsave(cpu);
1717     if (ret < 0) {
1718         return ret;
1719     }
1720     ret = kvm_get_xcrs(cpu);
1721     if (ret < 0) {
1722         return ret;
1723     }
1724     ret = kvm_get_sregs(cpu);
1725     if (ret < 0) {
1726         return ret;
1727     }
1728     ret = kvm_get_msrs(cpu);
1729     if (ret < 0) {
1730         return ret;
1731     }
1732     ret = kvm_get_mp_state(cpu);
1733     if (ret < 0) {
1734         return ret;
1735     }
1736     ret = kvm_get_apic(cpu);
1737     if (ret < 0) {
1738         return ret;
1739     }
1740     ret = kvm_get_vcpu_events(cpu);
1741     if (ret < 0) {
1742         return ret;
1743     }
1744     ret = kvm_get_debugregs(cpu);
1745     if (ret < 0) {
1746         return ret;
1747     }
1748     return 0;
1749 }
1750
1751 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1752 {
1753     X86CPU *x86_cpu = X86_CPU(cpu);
1754     CPUX86State *env = &x86_cpu->env;
1755     int ret;
1756
1757     /* Inject NMI */
1758     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1759         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1760         DPRINTF("injected NMI\n");
1761         ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
1762         if (ret < 0) {
1763             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1764                     strerror(-ret));
1765         }
1766     }
1767
1768     if (!kvm_irqchip_in_kernel()) {
1769         /* Force the VCPU out of its inner loop to process any INIT requests
1770          * or pending TPR access reports. */
1771         if (env->interrupt_request &
1772             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1773             env->exit_request = 1;
1774         }
1775
1776         /* Try to inject an interrupt if the guest can accept it */
1777         if (run->ready_for_interrupt_injection &&
1778             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1779             (env->eflags & IF_MASK)) {
1780             int irq;
1781
1782             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1783             irq = cpu_get_pic_interrupt(env);
1784             if (irq >= 0) {
1785                 struct kvm_interrupt intr;
1786
1787                 intr.irq = irq;
1788                 DPRINTF("injected interrupt %d\n", irq);
1789                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
1790                 if (ret < 0) {
1791                     fprintf(stderr,
1792                             "KVM: injection failed, interrupt lost (%s)\n",
1793                             strerror(-ret));
1794                 }
1795             }
1796         }
1797
1798         /* If we have an interrupt but the guest is not ready to receive an
1799          * interrupt, request an interrupt window exit.  This will
1800          * cause a return to userspace as soon as the guest is ready to
1801          * receive interrupts. */
1802         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1803             run->request_interrupt_window = 1;
1804         } else {
1805             run->request_interrupt_window = 0;
1806         }
1807
1808         DPRINTF("setting tpr\n");
1809         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1810     }
1811 }
1812
1813 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
1814 {
1815     X86CPU *x86_cpu = X86_CPU(cpu);
1816     CPUX86State *env = &x86_cpu->env;
1817
1818     if (run->if_flag) {
1819         env->eflags |= IF_MASK;
1820     } else {
1821         env->eflags &= ~IF_MASK;
1822     }
1823     cpu_set_apic_tpr(env->apic_state, run->cr8);
1824     cpu_set_apic_base(env->apic_state, run->apic_base);
1825 }
1826
1827 int kvm_arch_process_async_events(CPUState *cs)
1828 {
1829     X86CPU *cpu = X86_CPU(cs);
1830     CPUX86State *env = &cpu->env;
1831
1832     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1833         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1834         assert(env->mcg_cap);
1835
1836         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1837
1838         kvm_cpu_synchronize_state(env);
1839
1840         if (env->exception_injected == EXCP08_DBLE) {
1841             /* this means triple fault */
1842             qemu_system_reset_request();
1843             env->exit_request = 1;
1844             return 0;
1845         }
1846         env->exception_injected = EXCP12_MCHK;
1847         env->has_error_code = 0;
1848
1849         env->halted = 0;
1850         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1851             env->mp_state = KVM_MP_STATE_RUNNABLE;
1852         }
1853     }
1854
1855     if (kvm_irqchip_in_kernel()) {
1856         return 0;
1857     }
1858
1859     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1860         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1861         apic_poll_irq(env->apic_state);
1862     }
1863     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1864          (env->eflags & IF_MASK)) ||
1865         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1866         env->halted = 0;
1867     }
1868     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1869         kvm_cpu_synchronize_state(env);
1870         do_cpu_init(cpu);
1871     }
1872     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1873         kvm_cpu_synchronize_state(env);
1874         do_cpu_sipi(cpu);
1875     }
1876     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1877         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1878         kvm_cpu_synchronize_state(env);
1879         apic_handle_tpr_access_report(env->apic_state, env->eip,
1880                                       env->tpr_access_type);
1881     }
1882
1883     return env->halted;
1884 }
1885
1886 static int kvm_handle_halt(X86CPU *cpu)
1887 {
1888     CPUX86State *env = &cpu->env;
1889
1890     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1891           (env->eflags & IF_MASK)) &&
1892         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1893         env->halted = 1;
1894         return EXCP_HLT;
1895     }
1896
1897     return 0;
1898 }
1899
1900 static int kvm_handle_tpr_access(X86CPU *cpu)
1901 {
1902     CPUX86State *env = &cpu->env;
1903     CPUState *cs = CPU(cpu);
1904     struct kvm_run *run = cs->kvm_run;
1905
1906     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1907                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1908                                                            : TPR_ACCESS_READ);
1909     return 1;
1910 }
1911
1912 int kvm_arch_insert_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
1913 {
1914     CPUX86State *env = &X86_CPU(cpu)->env;
1915     static const uint8_t int3 = 0xcc;
1916
1917     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1918         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1919         return -EINVAL;
1920     }
1921     return 0;
1922 }
1923
1924 int kvm_arch_remove_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
1925 {
1926     CPUX86State *env = &X86_CPU(cpu)->env;
1927     uint8_t int3;
1928
1929     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1930         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1931         return -EINVAL;
1932     }
1933     return 0;
1934 }
1935
1936 static struct {
1937     target_ulong addr;
1938     int len;
1939     int type;
1940 } hw_breakpoint[4];
1941
1942 static int nb_hw_breakpoint;
1943
1944 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1945 {
1946     int n;
1947
1948     for (n = 0; n < nb_hw_breakpoint; n++) {
1949         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1950             (hw_breakpoint[n].len == len || len == -1)) {
1951             return n;
1952         }
1953     }
1954     return -1;
1955 }
1956
1957 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1958                                   target_ulong len, int type)
1959 {
1960     switch (type) {
1961     case GDB_BREAKPOINT_HW:
1962         len = 1;
1963         break;
1964     case GDB_WATCHPOINT_WRITE:
1965     case GDB_WATCHPOINT_ACCESS:
1966         switch (len) {
1967         case 1:
1968             break;
1969         case 2:
1970         case 4:
1971         case 8:
1972             if (addr & (len - 1)) {
1973                 return -EINVAL;
1974             }
1975             break;
1976         default:
1977             return -EINVAL;
1978         }
1979         break;
1980     default:
1981         return -ENOSYS;
1982     }
1983
1984     if (nb_hw_breakpoint == 4) {
1985         return -ENOBUFS;
1986     }
1987     if (find_hw_breakpoint(addr, len, type) >= 0) {
1988         return -EEXIST;
1989     }
1990     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1991     hw_breakpoint[nb_hw_breakpoint].len = len;
1992     hw_breakpoint[nb_hw_breakpoint].type = type;
1993     nb_hw_breakpoint++;
1994
1995     return 0;
1996 }
1997
1998 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1999                                   target_ulong len, int type)
2000 {
2001     int n;
2002
2003     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2004     if (n < 0) {
2005         return -ENOENT;
2006     }
2007     nb_hw_breakpoint--;
2008     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2009
2010     return 0;
2011 }
2012
2013 void kvm_arch_remove_all_hw_breakpoints(void)
2014 {
2015     nb_hw_breakpoint = 0;
2016 }
2017
2018 static CPUWatchpoint hw_watchpoint;
2019
2020 static int kvm_handle_debug(X86CPU *cpu,
2021                             struct kvm_debug_exit_arch *arch_info)
2022 {
2023     CPUX86State *env = &cpu->env;
2024     int ret = 0;
2025     int n;
2026
2027     if (arch_info->exception == 1) {
2028         if (arch_info->dr6 & (1 << 14)) {
2029             if (env->singlestep_enabled) {
2030                 ret = EXCP_DEBUG;
2031             }
2032         } else {
2033             for (n = 0; n < 4; n++) {
2034                 if (arch_info->dr6 & (1 << n)) {
2035                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2036                     case 0x0:
2037                         ret = EXCP_DEBUG;
2038                         break;
2039                     case 0x1:
2040                         ret = EXCP_DEBUG;
2041                         env->watchpoint_hit = &hw_watchpoint;
2042                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2043                         hw_watchpoint.flags = BP_MEM_WRITE;
2044                         break;
2045                     case 0x3:
2046                         ret = EXCP_DEBUG;
2047                         env->watchpoint_hit = &hw_watchpoint;
2048                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2049                         hw_watchpoint.flags = BP_MEM_ACCESS;
2050                         break;
2051                     }
2052                 }
2053             }
2054         }
2055     } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
2056         ret = EXCP_DEBUG;
2057     }
2058     if (ret == 0) {
2059         cpu_synchronize_state(env);
2060         assert(env->exception_injected == -1);
2061
2062         /* pass to guest */
2063         env->exception_injected = arch_info->exception;
2064         env->has_error_code = 0;
2065     }
2066
2067     return ret;
2068 }
2069
2070 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2071 {
2072     const uint8_t type_code[] = {
2073         [GDB_BREAKPOINT_HW] = 0x0,
2074         [GDB_WATCHPOINT_WRITE] = 0x1,
2075         [GDB_WATCHPOINT_ACCESS] = 0x3
2076     };
2077     const uint8_t len_code[] = {
2078         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2079     };
2080     int n;
2081
2082     if (kvm_sw_breakpoints_active(cpu)) {
2083         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2084     }
2085     if (nb_hw_breakpoint > 0) {
2086         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2087         dbg->arch.debugreg[7] = 0x0600;
2088         for (n = 0; n < nb_hw_breakpoint; n++) {
2089             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2090             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2091                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2092                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2093         }
2094     }
2095 }
2096
2097 static bool host_supports_vmx(void)
2098 {
2099     uint32_t ecx, unused;
2100
2101     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2102     return ecx & CPUID_EXT_VMX;
2103 }
2104
2105 #define VMX_INVALID_GUEST_STATE 0x80000021
2106
2107 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2108 {
2109     X86CPU *cpu = X86_CPU(cs);
2110     uint64_t code;
2111     int ret;
2112
2113     switch (run->exit_reason) {
2114     case KVM_EXIT_HLT:
2115         DPRINTF("handle_hlt\n");
2116         ret = kvm_handle_halt(cpu);
2117         break;
2118     case KVM_EXIT_SET_TPR:
2119         ret = 0;
2120         break;
2121     case KVM_EXIT_TPR_ACCESS:
2122         ret = kvm_handle_tpr_access(cpu);
2123         break;
2124     case KVM_EXIT_FAIL_ENTRY:
2125         code = run->fail_entry.hardware_entry_failure_reason;
2126         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2127                 code);
2128         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2129             fprintf(stderr,
2130                     "\nIf you're running a guest on an Intel machine without "
2131                         "unrestricted mode\n"
2132                     "support, the failure can be most likely due to the guest "
2133                         "entering an invalid\n"
2134                     "state for Intel VT. For example, the guest maybe running "
2135                         "in big real mode\n"
2136                     "which is not supported on less recent Intel processors."
2137                         "\n\n");
2138         }
2139         ret = -1;
2140         break;
2141     case KVM_EXIT_EXCEPTION:
2142         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2143                 run->ex.exception, run->ex.error_code);
2144         ret = -1;
2145         break;
2146     case KVM_EXIT_DEBUG:
2147         DPRINTF("kvm_exit_debug\n");
2148         ret = kvm_handle_debug(cpu, &run->debug.arch);
2149         break;
2150     default:
2151         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2152         ret = -1;
2153         break;
2154     }
2155
2156     return ret;
2157 }
2158
2159 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2160 {
2161     X86CPU *cpu = X86_CPU(cs);
2162     CPUX86State *env = &cpu->env;
2163
2164     kvm_cpu_synchronize_state(env);
2165     return !(env->cr[0] & CR0_PE_MASK) ||
2166            ((env->segs[R_CS].selector  & 3) != 3);
2167 }
2168
2169 void kvm_arch_init_irq_routing(KVMState *s)
2170 {
2171     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2172         /* If kernel can't do irq routing, interrupt source
2173          * override 0->2 cannot be set up as required by HPET.
2174          * So we have to disable it.
2175          */
2176         no_hpet = 1;
2177     }
2178     /* We know at this point that we're using the in-kernel
2179      * irqchip, so we can use irqfds, and on x86 we know
2180      * we can use msi via irqfd and GSI routing.
2181      */
2182     kvm_irqfds_allowed = true;
2183     kvm_msi_via_irqfd_allowed = true;
2184     kvm_gsi_routing_allowed = true;
2185 }
2186
2187 /* Classic KVM device assignment interface. Will remain x86 only. */
2188 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2189                           uint32_t flags, uint32_t *dev_id)
2190 {
2191     struct kvm_assigned_pci_dev dev_data = {
2192         .segnr = dev_addr->domain,
2193         .busnr = dev_addr->bus,
2194         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2195         .flags = flags,
2196     };
2197     int ret;
2198
2199     dev_data.assigned_dev_id =
2200         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2201
2202     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2203     if (ret < 0) {
2204         return ret;
2205     }
2206
2207     *dev_id = dev_data.assigned_dev_id;
2208
2209     return 0;
2210 }
2211
2212 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2213 {
2214     struct kvm_assigned_pci_dev dev_data = {
2215         .assigned_dev_id = dev_id,
2216     };
2217
2218     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2219 }
2220
2221 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2222                                    uint32_t irq_type, uint32_t guest_irq)
2223 {
2224     struct kvm_assigned_irq assigned_irq = {
2225         .assigned_dev_id = dev_id,
2226         .guest_irq = guest_irq,
2227         .flags = irq_type,
2228     };
2229
2230     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2231         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2232     } else {
2233         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2234     }
2235 }
2236
2237 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2238                            uint32_t guest_irq)
2239 {
2240     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2241         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2242
2243     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2244 }
2245
2246 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2247 {
2248     struct kvm_assigned_pci_dev dev_data = {
2249         .assigned_dev_id = dev_id,
2250         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2251     };
2252
2253     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2254 }
2255
2256 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2257                                      uint32_t type)
2258 {
2259     struct kvm_assigned_irq assigned_irq = {
2260         .assigned_dev_id = dev_id,
2261         .flags = type,
2262     };
2263
2264     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2265 }
2266
2267 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2268 {
2269     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2270         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2271 }
2272
2273 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2274 {
2275     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2276                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2277 }
2278
2279 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2280 {
2281     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2282                                                 KVM_DEV_IRQ_HOST_MSI);
2283 }
2284
2285 bool kvm_device_msix_supported(KVMState *s)
2286 {
2287     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2288      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2289     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2290 }
2291
2292 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2293                                  uint32_t nr_vectors)
2294 {
2295     struct kvm_assigned_msix_nr msix_nr = {
2296         .assigned_dev_id = dev_id,
2297         .entry_nr = nr_vectors,
2298     };
2299
2300     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2301 }
2302
2303 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2304                                int virq)
2305 {
2306     struct kvm_assigned_msix_entry msix_entry = {
2307         .assigned_dev_id = dev_id,
2308         .gsi = virq,
2309         .entry = vector,
2310     };
2311
2312     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2313 }
2314
2315 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2316 {
2317     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2318                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2319 }
2320
2321 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2322 {
2323     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2324                                                 KVM_DEV_IRQ_HOST_MSIX);
2325 }