2 * USB UHCI controller emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu-timer.h"
37 //#define DEBUG_DUMP_DATA
39 #define UHCI_CMD_FGR (1 << 4)
40 #define UHCI_CMD_EGSM (1 << 3)
41 #define UHCI_CMD_GRESET (1 << 2)
42 #define UHCI_CMD_HCRESET (1 << 1)
43 #define UHCI_CMD_RS (1 << 0)
45 #define UHCI_STS_HCHALTED (1 << 5)
46 #define UHCI_STS_HCPERR (1 << 4)
47 #define UHCI_STS_HSERR (1 << 3)
48 #define UHCI_STS_RD (1 << 2)
49 #define UHCI_STS_USBERR (1 << 1)
50 #define UHCI_STS_USBINT (1 << 0)
52 #define TD_CTRL_SPD (1 << 29)
53 #define TD_CTRL_ERROR_SHIFT 27
54 #define TD_CTRL_IOS (1 << 25)
55 #define TD_CTRL_IOC (1 << 24)
56 #define TD_CTRL_ACTIVE (1 << 23)
57 #define TD_CTRL_STALL (1 << 22)
58 #define TD_CTRL_BABBLE (1 << 20)
59 #define TD_CTRL_NAK (1 << 19)
60 #define TD_CTRL_TIMEOUT (1 << 18)
62 #define UHCI_PORT_SUSPEND (1 << 12)
63 #define UHCI_PORT_RESET (1 << 9)
64 #define UHCI_PORT_LSDA (1 << 8)
65 #define UHCI_PORT_RD (1 << 6)
66 #define UHCI_PORT_ENC (1 << 3)
67 #define UHCI_PORT_EN (1 << 2)
68 #define UHCI_PORT_CSC (1 << 1)
69 #define UHCI_PORT_CCS (1 << 0)
71 #define UHCI_PORT_READ_ONLY (0x1bb)
72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
74 #define FRAME_TIMER_FREQ 1000
76 #define FRAME_MAX_LOOPS 256
81 #define DPRINTF printf
83 static const char *pid2str(int pid
)
86 case USB_TOKEN_SETUP
: return "SETUP";
87 case USB_TOKEN_IN
: return "IN";
88 case USB_TOKEN_OUT
: return "OUT";
97 typedef struct UHCIState UHCIState
;
98 typedef struct UHCIAsync UHCIAsync
;
99 typedef struct UHCIQueue UHCIQueue
;
102 * Pending async transaction.
103 * 'packet' must be the first field because completion
104 * handler does "(UHCIAsync *) pkt" cast.
111 QTAILQ_ENTRY(UHCIAsync
) next
;
120 QTAILQ_ENTRY(UHCIQueue
) next
;
121 QTAILQ_HEAD(, UHCIAsync
) asyncs
;
125 typedef struct UHCIPort
{
133 USBBus bus
; /* Note unused when we're a companion controller */
134 uint16_t cmd
; /* cmd register */
136 uint16_t intr
; /* interrupt enable register */
137 uint16_t frnum
; /* frame number */
138 uint32_t fl_base_addr
; /* frame list base address */
140 uint8_t status2
; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
142 QEMUTimer
*frame_timer
;
143 UHCIPort ports
[NB_PORTS
];
145 /* Interrupts that should be raised at the end of the current frame. */
146 uint32_t pending_int_mask
;
149 QTAILQ_HEAD(, UHCIQueue
) queues
;
150 uint8_t num_ports_vmstate
;
157 typedef struct UHCI_TD
{
159 uint32_t ctrl
; /* see TD_CTRL_xxx */
164 typedef struct UHCI_QH
{
169 static inline int32_t uhci_queue_token(UHCI_TD
*td
)
171 /* covers ep, dev, pid -> identifies the endpoint */
172 return td
->token
& 0x7ffff;
175 static UHCIQueue
*uhci_queue_get(UHCIState
*s
, UHCI_TD
*td
)
177 uint32_t token
= uhci_queue_token(td
);
180 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
181 if (queue
->token
== token
) {
186 queue
= g_new0(UHCIQueue
, 1);
188 queue
->token
= token
;
189 QTAILQ_INIT(&queue
->asyncs
);
190 QTAILQ_INSERT_HEAD(&s
->queues
, queue
, next
);
194 static void uhci_queue_free(UHCIQueue
*queue
)
196 UHCIState
*s
= queue
->uhci
;
198 QTAILQ_REMOVE(&s
->queues
, queue
, next
);
202 static UHCIAsync
*uhci_async_alloc(UHCIQueue
*queue
)
204 UHCIAsync
*async
= g_new0(UHCIAsync
, 1);
206 async
->queue
= queue
;
207 usb_packet_init(&async
->packet
);
208 pci_dma_sglist_init(&async
->sgl
, &queue
->uhci
->dev
, 1);
213 static void uhci_async_free(UHCIAsync
*async
)
215 usb_packet_cleanup(&async
->packet
);
216 qemu_sglist_destroy(&async
->sgl
);
220 static void uhci_async_link(UHCIAsync
*async
)
222 UHCIQueue
*queue
= async
->queue
;
223 QTAILQ_INSERT_TAIL(&queue
->asyncs
, async
, next
);
226 static void uhci_async_unlink(UHCIAsync
*async
)
228 UHCIQueue
*queue
= async
->queue
;
229 QTAILQ_REMOVE(&queue
->asyncs
, async
, next
);
232 static void uhci_async_cancel(UHCIAsync
*async
)
234 DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n",
235 async
->td
, async
->token
, async
->done
);
238 usb_cancel_packet(&async
->packet
);
239 uhci_async_free(async
);
243 * Mark all outstanding async packets as invalid.
244 * This is used for canceling them when TDs are removed by the HCD.
246 static void uhci_async_validate_begin(UHCIState
*s
)
250 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
256 * Cancel async packets that are no longer valid
258 static void uhci_async_validate_end(UHCIState
*s
)
260 UHCIQueue
*queue
, *n
;
263 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
264 if (queue
->valid
> 0) {
267 while (!QTAILQ_EMPTY(&queue
->asyncs
)) {
268 async
= QTAILQ_FIRST(&queue
->asyncs
);
269 uhci_async_unlink(async
);
270 uhci_async_cancel(async
);
272 uhci_queue_free(queue
);
276 static void uhci_async_cancel_device(UHCIState
*s
, USBDevice
*dev
)
281 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
282 QTAILQ_FOREACH_SAFE(curr
, &queue
->asyncs
, next
, n
) {
283 if (!usb_packet_is_inflight(&curr
->packet
) ||
284 curr
->packet
.ep
->dev
!= dev
) {
287 uhci_async_unlink(curr
);
288 uhci_async_cancel(curr
);
293 static void uhci_async_cancel_all(UHCIState
*s
)
298 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
299 QTAILQ_FOREACH_SAFE(curr
, &queue
->asyncs
, next
, n
) {
300 uhci_async_unlink(curr
);
301 uhci_async_cancel(curr
);
306 static UHCIAsync
*uhci_async_find_td(UHCIState
*s
, uint32_t addr
, UHCI_TD
*td
)
308 uint32_t token
= uhci_queue_token(td
);
312 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
313 if (queue
->token
== token
) {
321 QTAILQ_FOREACH(async
, &queue
->asyncs
, next
) {
322 if (async
->td
== addr
) {
330 static void uhci_update_irq(UHCIState
*s
)
333 if (((s
->status2
& 1) && (s
->intr
& (1 << 2))) ||
334 ((s
->status2
& 2) && (s
->intr
& (1 << 3))) ||
335 ((s
->status
& UHCI_STS_USBERR
) && (s
->intr
& (1 << 0))) ||
336 ((s
->status
& UHCI_STS_RD
) && (s
->intr
& (1 << 1))) ||
337 (s
->status
& UHCI_STS_HSERR
) ||
338 (s
->status
& UHCI_STS_HCPERR
)) {
343 qemu_set_irq(s
->dev
.irq
[3], level
);
346 static void uhci_reset(void *opaque
)
348 UHCIState
*s
= opaque
;
353 DPRINTF("uhci: full reset\n");
355 pci_conf
= s
->dev
.config
;
357 pci_conf
[0x6a] = 0x01; /* usb clock */
358 pci_conf
[0x6b] = 0x00;
366 for(i
= 0; i
< NB_PORTS
; i
++) {
369 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
370 usb_port_reset(&port
->port
);
374 uhci_async_cancel_all(s
);
377 static void uhci_pre_save(void *opaque
)
379 UHCIState
*s
= opaque
;
381 uhci_async_cancel_all(s
);
384 static const VMStateDescription vmstate_uhci_port
= {
387 .minimum_version_id
= 1,
388 .minimum_version_id_old
= 1,
389 .fields
= (VMStateField
[]) {
390 VMSTATE_UINT16(ctrl
, UHCIPort
),
391 VMSTATE_END_OF_LIST()
395 static const VMStateDescription vmstate_uhci
= {
398 .minimum_version_id
= 1,
399 .minimum_version_id_old
= 1,
400 .pre_save
= uhci_pre_save
,
401 .fields
= (VMStateField
[]) {
402 VMSTATE_PCI_DEVICE(dev
, UHCIState
),
403 VMSTATE_UINT8_EQUAL(num_ports_vmstate
, UHCIState
),
404 VMSTATE_STRUCT_ARRAY(ports
, UHCIState
, NB_PORTS
, 1,
405 vmstate_uhci_port
, UHCIPort
),
406 VMSTATE_UINT16(cmd
, UHCIState
),
407 VMSTATE_UINT16(status
, UHCIState
),
408 VMSTATE_UINT16(intr
, UHCIState
),
409 VMSTATE_UINT16(frnum
, UHCIState
),
410 VMSTATE_UINT32(fl_base_addr
, UHCIState
),
411 VMSTATE_UINT8(sof_timing
, UHCIState
),
412 VMSTATE_UINT8(status2
, UHCIState
),
413 VMSTATE_TIMER(frame_timer
, UHCIState
),
414 VMSTATE_INT64_V(expire_time
, UHCIState
, 2),
415 VMSTATE_END_OF_LIST()
419 static void uhci_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
421 UHCIState
*s
= opaque
;
431 static uint32_t uhci_ioport_readb(void *opaque
, uint32_t addr
)
433 UHCIState
*s
= opaque
;
448 static void uhci_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
450 UHCIState
*s
= opaque
;
453 DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr
, val
);
457 if ((val
& UHCI_CMD_RS
) && !(s
->cmd
& UHCI_CMD_RS
)) {
458 /* start frame processing */
459 s
->expire_time
= qemu_get_clock_ns(vm_clock
) +
460 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
461 qemu_mod_timer(s
->frame_timer
, qemu_get_clock_ns(vm_clock
));
462 s
->status
&= ~UHCI_STS_HCHALTED
;
463 } else if (!(val
& UHCI_CMD_RS
)) {
464 s
->status
|= UHCI_STS_HCHALTED
;
466 if (val
& UHCI_CMD_GRESET
) {
470 /* send reset on the USB bus */
471 for(i
= 0; i
< NB_PORTS
; i
++) {
473 usb_device_reset(port
->port
.dev
);
478 if (val
& UHCI_CMD_HCRESET
) {
486 /* XXX: the chip spec is not coherent, so we add a hidden
487 register to distinguish between IOC and SPD */
488 if (val
& UHCI_STS_USBINT
)
497 if (s
->status
& UHCI_STS_HCHALTED
)
498 s
->frnum
= val
& 0x7ff;
510 dev
= port
->port
.dev
;
511 if (dev
&& dev
->attached
) {
513 if ( (val
& UHCI_PORT_RESET
) &&
514 !(port
->ctrl
& UHCI_PORT_RESET
) ) {
515 usb_device_reset(dev
);
518 port
->ctrl
&= UHCI_PORT_READ_ONLY
;
519 port
->ctrl
|= (val
& ~UHCI_PORT_READ_ONLY
);
520 /* some bits are reset when a '1' is written to them */
521 port
->ctrl
&= ~(val
& UHCI_PORT_WRITE_CLEAR
);
527 static uint32_t uhci_ioport_readw(void *opaque
, uint32_t addr
)
529 UHCIState
*s
= opaque
;
559 val
= 0xff7f; /* disabled port */
563 DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr
, val
);
568 static void uhci_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
570 UHCIState
*s
= opaque
;
573 DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr
, val
);
577 s
->fl_base_addr
= val
& ~0xfff;
582 static uint32_t uhci_ioport_readl(void *opaque
, uint32_t addr
)
584 UHCIState
*s
= opaque
;
590 val
= s
->fl_base_addr
;
599 /* signal resume if controller suspended */
600 static void uhci_resume (void *opaque
)
602 UHCIState
*s
= (UHCIState
*)opaque
;
607 if (s
->cmd
& UHCI_CMD_EGSM
) {
608 s
->cmd
|= UHCI_CMD_FGR
;
609 s
->status
|= UHCI_STS_RD
;
614 static void uhci_attach(USBPort
*port1
)
616 UHCIState
*s
= port1
->opaque
;
617 UHCIPort
*port
= &s
->ports
[port1
->index
];
619 /* set connect status */
620 port
->ctrl
|= UHCI_PORT_CCS
| UHCI_PORT_CSC
;
623 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
624 port
->ctrl
|= UHCI_PORT_LSDA
;
626 port
->ctrl
&= ~UHCI_PORT_LSDA
;
632 static void uhci_detach(USBPort
*port1
)
634 UHCIState
*s
= port1
->opaque
;
635 UHCIPort
*port
= &s
->ports
[port1
->index
];
637 uhci_async_cancel_device(s
, port1
->dev
);
639 /* set connect status */
640 if (port
->ctrl
& UHCI_PORT_CCS
) {
641 port
->ctrl
&= ~UHCI_PORT_CCS
;
642 port
->ctrl
|= UHCI_PORT_CSC
;
645 if (port
->ctrl
& UHCI_PORT_EN
) {
646 port
->ctrl
&= ~UHCI_PORT_EN
;
647 port
->ctrl
|= UHCI_PORT_ENC
;
653 static void uhci_child_detach(USBPort
*port1
, USBDevice
*child
)
655 UHCIState
*s
= port1
->opaque
;
657 uhci_async_cancel_device(s
, child
);
660 static void uhci_wakeup(USBPort
*port1
)
662 UHCIState
*s
= port1
->opaque
;
663 UHCIPort
*port
= &s
->ports
[port1
->index
];
665 if (port
->ctrl
& UHCI_PORT_SUSPEND
&& !(port
->ctrl
& UHCI_PORT_RD
)) {
666 port
->ctrl
|= UHCI_PORT_RD
;
671 static USBDevice
*uhci_find_device(UHCIState
*s
, uint8_t addr
)
676 for (i
= 0; i
< NB_PORTS
; i
++) {
677 UHCIPort
*port
= &s
->ports
[i
];
678 if (!(port
->ctrl
& UHCI_PORT_EN
)) {
681 dev
= usb_find_device(&port
->port
, addr
);
689 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
);
690 static void uhci_process_frame(UHCIState
*s
);
692 /* return -1 if fatal error (frame must be stopped)
694 1 if TD unsuccessful or inactive
696 static int uhci_complete_td(UHCIState
*s
, UHCI_TD
*td
, UHCIAsync
*async
, uint32_t *int_mask
)
698 int len
= 0, max_len
, err
, ret
;
701 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
702 pid
= td
->token
& 0xff;
704 ret
= async
->packet
.result
;
706 if (td
->ctrl
& TD_CTRL_IOS
)
707 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
712 len
= async
->packet
.result
;
713 td
->ctrl
= (td
->ctrl
& ~0x7ff) | ((len
- 1) & 0x7ff);
715 /* The NAK bit may have been set by a previous frame, so clear it
716 here. The docs are somewhat unclear, but win2k relies on this
718 td
->ctrl
&= ~(TD_CTRL_ACTIVE
| TD_CTRL_NAK
);
719 if (td
->ctrl
& TD_CTRL_IOC
)
722 if (pid
== USB_TOKEN_IN
) {
724 ret
= USB_RET_BABBLE
;
728 if ((td
->ctrl
& TD_CTRL_SPD
) && len
< max_len
) {
730 /* short packet: do not update QH */
731 DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async
->td
, async
->token
);
742 td
->ctrl
|= TD_CTRL_STALL
;
743 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
744 s
->status
|= UHCI_STS_USBERR
;
745 if (td
->ctrl
& TD_CTRL_IOC
) {
752 td
->ctrl
|= TD_CTRL_BABBLE
| TD_CTRL_STALL
;
753 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
754 s
->status
|= UHCI_STS_USBERR
;
755 if (td
->ctrl
& TD_CTRL_IOC
) {
759 /* frame interrupted */
763 td
->ctrl
|= TD_CTRL_NAK
;
764 if (pid
== USB_TOKEN_SETUP
)
773 /* Retry the TD if error count is not zero */
775 td
->ctrl
|= TD_CTRL_TIMEOUT
;
776 err
= (td
->ctrl
>> TD_CTRL_ERROR_SHIFT
) & 3;
780 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
781 s
->status
|= UHCI_STS_USBERR
;
782 if (td
->ctrl
& TD_CTRL_IOC
)
787 td
->ctrl
= (td
->ctrl
& ~(3 << TD_CTRL_ERROR_SHIFT
)) |
788 (err
<< TD_CTRL_ERROR_SHIFT
);
792 static int uhci_handle_td(UHCIState
*s
, uint32_t addr
, UHCI_TD
*td
, uint32_t *int_mask
)
795 int len
= 0, max_len
;
801 if (!(td
->ctrl
& TD_CTRL_ACTIVE
))
804 async
= uhci_async_find_td(s
, addr
, td
);
806 /* Already submitted */
807 async
->queue
->valid
= 32;
812 uhci_async_unlink(async
);
816 /* Allocate new packet */
817 async
= uhci_async_alloc(uhci_queue_get(s
, td
));
821 /* valid needs to be large enough to handle 10 frame delay
822 * for initial isochronous requests
824 async
->queue
->valid
= 32;
826 async
->isoc
= td
->ctrl
& TD_CTRL_IOS
;
828 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
829 pid
= td
->token
& 0xff;
831 dev
= uhci_find_device(s
, (td
->token
>> 8) & 0x7f);
832 ep
= usb_ep_get(dev
, pid
, (td
->token
>> 15) & 0xf);
833 usb_packet_setup(&async
->packet
, pid
, ep
);
834 qemu_sglist_add(&async
->sgl
, td
->buffer
, max_len
);
835 usb_packet_map(&async
->packet
, &async
->sgl
);
839 case USB_TOKEN_SETUP
:
840 len
= usb_handle_packet(dev
, &async
->packet
);
846 len
= usb_handle_packet(dev
, &async
->packet
);
850 /* invalid pid : frame interrupted */
851 uhci_async_free(async
);
852 s
->status
|= UHCI_STS_HCPERR
;
857 if (len
== USB_RET_ASYNC
) {
858 uhci_async_link(async
);
862 async
->packet
.result
= len
;
865 len
= uhci_complete_td(s
, td
, async
, int_mask
);
866 usb_packet_unmap(&async
->packet
);
867 uhci_async_free(async
);
871 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
)
873 UHCIAsync
*async
= container_of(packet
, UHCIAsync
, packet
);
874 UHCIState
*s
= async
->queue
->uhci
;
876 DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async
->td
, async
->token
);
880 uint32_t link
= async
->td
;
881 uint32_t int_mask
= 0, val
;
883 pci_dma_read(&s
->dev
, link
& ~0xf, &td
, sizeof(td
));
884 le32_to_cpus(&td
.link
);
885 le32_to_cpus(&td
.ctrl
);
886 le32_to_cpus(&td
.token
);
887 le32_to_cpus(&td
.buffer
);
889 uhci_async_unlink(async
);
890 uhci_complete_td(s
, &td
, async
, &int_mask
);
891 s
->pending_int_mask
|= int_mask
;
893 /* update the status bits of the TD */
894 val
= cpu_to_le32(td
.ctrl
);
895 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
896 uhci_async_free(async
);
899 uhci_process_frame(s
);
903 static int is_valid(uint32_t link
)
905 return (link
& 1) == 0;
908 static int is_qh(uint32_t link
)
910 return (link
& 2) != 0;
913 static int depth_first(uint32_t link
)
915 return (link
& 4) != 0;
918 /* QH DB used for detecting QH loops */
919 #define UHCI_MAX_QUEUES 128
921 uint32_t addr
[UHCI_MAX_QUEUES
];
925 static void qhdb_reset(QhDb
*db
)
930 /* Add QH to DB. Returns 1 if already present or DB is full. */
931 static int qhdb_insert(QhDb
*db
, uint32_t addr
)
934 for (i
= 0; i
< db
->count
; i
++)
935 if (db
->addr
[i
] == addr
)
938 if (db
->count
>= UHCI_MAX_QUEUES
)
941 db
->addr
[db
->count
++] = addr
;
945 static void uhci_process_frame(UHCIState
*s
)
947 uint32_t frame_addr
, link
, old_td_ctrl
, val
, int_mask
;
948 uint32_t curr_qh
, td_count
= 0, bytes_count
= 0;
954 frame_addr
= s
->fl_base_addr
+ ((s
->frnum
& 0x3ff) << 2);
956 DPRINTF("uhci: processing frame %d addr 0x%x\n" , s
->frnum
, frame_addr
);
958 pci_dma_read(&s
->dev
, frame_addr
, &link
, 4);
966 for (cnt
= FRAME_MAX_LOOPS
; is_valid(link
) && cnt
; cnt
--) {
970 if (qhdb_insert(&qhdb
, link
)) {
972 * We're going in circles. Which is not a bug because
973 * HCD is allowed to do that as part of the BW management.
975 * Stop processing here if
976 * (a) no transaction has been done since we've been
978 * (b) we've reached the usb 1.1 bandwidth, which is
981 DPRINTF("uhci: detected loop. qh 0x%x\n", link
);
983 DPRINTF("uhci: no transaction last round, stop\n");
985 } else if (bytes_count
>= 1280) {
986 DPRINTF("uhci: bandwidth limit reached, stop\n");
991 qhdb_insert(&qhdb
, link
);
995 pci_dma_read(&s
->dev
, link
& ~0xf, &qh
, sizeof(qh
));
996 le32_to_cpus(&qh
.link
);
997 le32_to_cpus(&qh
.el_link
);
999 DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
1000 link
, qh
.link
, qh
.el_link
);
1002 if (!is_valid(qh
.el_link
)) {
1003 /* QH w/o elements */
1007 /* QH with elements */
1015 pci_dma_read(&s
->dev
, link
& ~0xf, &td
, sizeof(td
));
1016 le32_to_cpus(&td
.link
);
1017 le32_to_cpus(&td
.ctrl
);
1018 le32_to_cpus(&td
.token
);
1019 le32_to_cpus(&td
.buffer
);
1021 DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1022 link
, td
.link
, td
.ctrl
, td
.token
, curr_qh
);
1024 old_td_ctrl
= td
.ctrl
;
1025 ret
= uhci_handle_td(s
, link
, &td
, &int_mask
);
1026 if (old_td_ctrl
!= td
.ctrl
) {
1027 /* update the status bits of the TD */
1028 val
= cpu_to_le32(td
.ctrl
);
1029 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
1033 /* interrupted frame */
1037 if (ret
== 2 || ret
== 1) {
1038 DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1039 link
, ret
== 2 ? "pend" : "skip",
1040 td
.link
, td
.ctrl
, td
.token
, curr_qh
);
1042 link
= curr_qh
? qh
.link
: td
.link
;
1048 DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1049 link
, td
.link
, td
.ctrl
, td
.token
, curr_qh
);
1053 bytes_count
+= (td
.ctrl
& 0x7ff) + 1;
1056 /* update QH element link */
1058 val
= cpu_to_le32(qh
.el_link
);
1059 pci_dma_write(&s
->dev
, (curr_qh
& ~0xf) + 4, &val
, sizeof(val
));
1061 if (!depth_first(link
)) {
1062 /* done with this QH */
1064 DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
1065 curr_qh
, qh
.link
, qh
.el_link
);
1072 /* go to the next entry */
1075 s
->pending_int_mask
|= int_mask
;
1078 static void uhci_frame_timer(void *opaque
)
1080 UHCIState
*s
= opaque
;
1082 /* prepare the timer for the next frame */
1083 s
->expire_time
+= (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
1085 if (!(s
->cmd
& UHCI_CMD_RS
)) {
1087 qemu_del_timer(s
->frame_timer
);
1088 /* set hchalted bit in status - UHCI11D 2.1.2 */
1089 s
->status
|= UHCI_STS_HCHALTED
;
1091 DPRINTF("uhci: halted\n");
1095 /* Complete the previous frame */
1096 if (s
->pending_int_mask
) {
1097 s
->status2
|= s
->pending_int_mask
;
1098 s
->status
|= UHCI_STS_USBINT
;
1101 s
->pending_int_mask
= 0;
1103 /* Start new frame */
1104 s
->frnum
= (s
->frnum
+ 1) & 0x7ff;
1106 DPRINTF("uhci: new frame #%u\n" , s
->frnum
);
1108 uhci_async_validate_begin(s
);
1110 uhci_process_frame(s
);
1112 uhci_async_validate_end(s
);
1114 qemu_mod_timer(s
->frame_timer
, s
->expire_time
);
1117 static const MemoryRegionPortio uhci_portio
[] = {
1118 { 0, 32, 2, .write
= uhci_ioport_writew
, },
1119 { 0, 32, 2, .read
= uhci_ioport_readw
, },
1120 { 0, 32, 4, .write
= uhci_ioport_writel
, },
1121 { 0, 32, 4, .read
= uhci_ioport_readl
, },
1122 { 0, 32, 1, .write
= uhci_ioport_writeb
, },
1123 { 0, 32, 1, .read
= uhci_ioport_readb
, },
1124 PORTIO_END_OF_LIST()
1127 static const MemoryRegionOps uhci_ioport_ops
= {
1128 .old_portio
= uhci_portio
,
1131 static USBPortOps uhci_port_ops
= {
1132 .attach
= uhci_attach
,
1133 .detach
= uhci_detach
,
1134 .child_detach
= uhci_child_detach
,
1135 .wakeup
= uhci_wakeup
,
1136 .complete
= uhci_async_complete
,
1139 static USBBusOps uhci_bus_ops
= {
1142 static int usb_uhci_common_initfn(PCIDevice
*dev
)
1144 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1145 uint8_t *pci_conf
= s
->dev
.config
;
1148 pci_conf
[PCI_CLASS_PROG
] = 0x00;
1149 /* TODO: reset value should be 0. */
1150 pci_conf
[PCI_INTERRUPT_PIN
] = 4; /* interrupt pin D */
1151 pci_conf
[USB_SBRN
] = USB_RELEASE_1
; // release number
1154 USBPort
*ports
[NB_PORTS
];
1155 for(i
= 0; i
< NB_PORTS
; i
++) {
1156 ports
[i
] = &s
->ports
[i
].port
;
1158 if (usb_register_companion(s
->masterbus
, ports
, NB_PORTS
,
1159 s
->firstport
, s
, &uhci_port_ops
,
1160 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
) != 0) {
1164 usb_bus_new(&s
->bus
, &uhci_bus_ops
, &s
->dev
.qdev
);
1165 for (i
= 0; i
< NB_PORTS
; i
++) {
1166 usb_register_port(&s
->bus
, &s
->ports
[i
].port
, s
, i
, &uhci_port_ops
,
1167 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1170 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, uhci_frame_timer
, s
);
1171 s
->num_ports_vmstate
= NB_PORTS
;
1172 QTAILQ_INIT(&s
->queues
);
1174 qemu_register_reset(uhci_reset
, s
);
1176 memory_region_init_io(&s
->io_bar
, &uhci_ioport_ops
, s
, "uhci", 0x20);
1177 /* Use region 4 for consistency with real hardware. BSD guests seem
1179 pci_register_bar(&s
->dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1184 static int usb_uhci_vt82c686b_initfn(PCIDevice
*dev
)
1186 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1187 uint8_t *pci_conf
= s
->dev
.config
;
1189 /* USB misc control 1/2 */
1190 pci_set_long(pci_conf
+ 0x40,0x00001000);
1192 pci_set_long(pci_conf
+ 0x80,0x00020001);
1193 /* USB legacy support */
1194 pci_set_long(pci_conf
+ 0xc0,0x00002000);
1196 return usb_uhci_common_initfn(dev
);
1199 static int usb_uhci_exit(PCIDevice
*dev
)
1201 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1203 memory_region_destroy(&s
->io_bar
);
1207 static Property uhci_properties
[] = {
1208 DEFINE_PROP_STRING("masterbus", UHCIState
, masterbus
),
1209 DEFINE_PROP_UINT32("firstport", UHCIState
, firstport
, 0),
1210 DEFINE_PROP_END_OF_LIST(),
1213 static void piix3_uhci_class_init(ObjectClass
*klass
, void *data
)
1215 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1216 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1218 k
->init
= usb_uhci_common_initfn
;
1219 k
->exit
= usb_uhci_exit
;
1220 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1221 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_2
;
1223 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1224 dc
->vmsd
= &vmstate_uhci
;
1225 dc
->props
= uhci_properties
;
1228 static TypeInfo piix3_uhci_info
= {
1229 .name
= "piix3-usb-uhci",
1230 .parent
= TYPE_PCI_DEVICE
,
1231 .instance_size
= sizeof(UHCIState
),
1232 .class_init
= piix3_uhci_class_init
,
1235 static void piix4_uhci_class_init(ObjectClass
*klass
, void *data
)
1237 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1238 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1240 k
->init
= usb_uhci_common_initfn
;
1241 k
->exit
= usb_uhci_exit
;
1242 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1243 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB_2
;
1245 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1246 dc
->vmsd
= &vmstate_uhci
;
1247 dc
->props
= uhci_properties
;
1250 static TypeInfo piix4_uhci_info
= {
1251 .name
= "piix4-usb-uhci",
1252 .parent
= TYPE_PCI_DEVICE
,
1253 .instance_size
= sizeof(UHCIState
),
1254 .class_init
= piix4_uhci_class_init
,
1257 static void vt82c686b_uhci_class_init(ObjectClass
*klass
, void *data
)
1259 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1260 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1262 k
->init
= usb_uhci_vt82c686b_initfn
;
1263 k
->exit
= usb_uhci_exit
;
1264 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
1265 k
->device_id
= PCI_DEVICE_ID_VIA_UHCI
;
1267 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1268 dc
->vmsd
= &vmstate_uhci
;
1269 dc
->props
= uhci_properties
;
1272 static TypeInfo vt82c686b_uhci_info
= {
1273 .name
= "vt82c686b-usb-uhci",
1274 .parent
= TYPE_PCI_DEVICE
,
1275 .instance_size
= sizeof(UHCIState
),
1276 .class_init
= vt82c686b_uhci_class_init
,
1279 static void ich9_uhci1_class_init(ObjectClass
*klass
, void *data
)
1281 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1282 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1284 k
->init
= usb_uhci_common_initfn
;
1285 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1286 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI1
;
1288 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1289 dc
->vmsd
= &vmstate_uhci
;
1290 dc
->props
= uhci_properties
;
1293 static TypeInfo ich9_uhci1_info
= {
1294 .name
= "ich9-usb-uhci1",
1295 .parent
= TYPE_PCI_DEVICE
,
1296 .instance_size
= sizeof(UHCIState
),
1297 .class_init
= ich9_uhci1_class_init
,
1300 static void ich9_uhci2_class_init(ObjectClass
*klass
, void *data
)
1302 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1303 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1305 k
->init
= usb_uhci_common_initfn
;
1306 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1307 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI2
;
1309 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1310 dc
->vmsd
= &vmstate_uhci
;
1311 dc
->props
= uhci_properties
;
1314 static TypeInfo ich9_uhci2_info
= {
1315 .name
= "ich9-usb-uhci2",
1316 .parent
= TYPE_PCI_DEVICE
,
1317 .instance_size
= sizeof(UHCIState
),
1318 .class_init
= ich9_uhci2_class_init
,
1321 static void ich9_uhci3_class_init(ObjectClass
*klass
, void *data
)
1323 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1324 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1326 k
->init
= usb_uhci_common_initfn
;
1327 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1328 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI3
;
1330 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1331 dc
->vmsd
= &vmstate_uhci
;
1332 dc
->props
= uhci_properties
;
1335 static TypeInfo ich9_uhci3_info
= {
1336 .name
= "ich9-usb-uhci3",
1337 .parent
= TYPE_PCI_DEVICE
,
1338 .instance_size
= sizeof(UHCIState
),
1339 .class_init
= ich9_uhci3_class_init
,
1342 static void uhci_register_types(void)
1344 type_register_static(&piix3_uhci_info
);
1345 type_register_static(&piix4_uhci_info
);
1346 type_register_static(&vt82c686b_uhci_info
);
1347 type_register_static(&ich9_uhci1_info
);
1348 type_register_static(&ich9_uhci2_info
);
1349 type_register_static(&ich9_uhci3_info
);
1352 type_init(uhci_register_types
)
1354 void usb_uhci_piix3_init(PCIBus
*bus
, int devfn
)
1356 pci_create_simple(bus
, devfn
, "piix3-usb-uhci");
1359 void usb_uhci_piix4_init(PCIBus
*bus
, int devfn
)
1361 pci_create_simple(bus
, devfn
, "piix4-usb-uhci");
1364 void usb_uhci_vt82c686b_init(PCIBus
*bus
, int devfn
)
1366 pci_create_simple(bus
, devfn
, "vt82c686b-usb-uhci");