numa: Fix format string for "Invalid node" message
[qemu.git] / hw / acpi / ich9.c
blob5c279bbacac74033c12de7d223538a4e784692ea
1 /*
2 * ACPI implementation
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
7 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 * This is based on acpi.c.
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License version 2 as published by the Free Software Foundation.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>
23 * Contributions after 2012-01-13 are licensed under the terms of the
24 * GNU GPL, version 2 or (at your option) any later version.
26 #include "qemu/osdep.h"
27 #include "hw/hw.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "hw/i386/pc.h"
31 #include "hw/pci/pci.h"
32 #include "qemu/timer.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/acpi/acpi.h"
35 #include "hw/acpi/tco.h"
36 #include "sysemu/kvm.h"
37 #include "exec/address-spaces.h"
39 #include "hw/i386/ich9.h"
40 #include "hw/mem/pc-dimm.h"
42 //#define DEBUG
44 #ifdef DEBUG
45 #define ICH9_DEBUG(fmt, ...) \
46 do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
47 #else
48 #define ICH9_DEBUG(fmt, ...) do { } while (0)
49 #endif
51 static void ich9_pm_update_sci_fn(ACPIREGS *regs)
53 ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
54 acpi_update_sci(&pm->acpi_regs, pm->irq);
57 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
59 ICH9LPCPMRegs *pm = opaque;
60 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
63 static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
64 unsigned width)
66 ICH9LPCPMRegs *pm = opaque;
67 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
68 acpi_update_sci(&pm->acpi_regs, pm->irq);
71 static const MemoryRegionOps ich9_gpe_ops = {
72 .read = ich9_gpe_readb,
73 .write = ich9_gpe_writeb,
74 .valid.min_access_size = 1,
75 .valid.max_access_size = 4,
76 .impl.min_access_size = 1,
77 .impl.max_access_size = 1,
78 .endianness = DEVICE_LITTLE_ENDIAN,
81 static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
83 ICH9LPCPMRegs *pm = opaque;
84 switch (addr) {
85 case 0:
86 return pm->smi_en;
87 case 4:
88 return pm->smi_sts;
89 default:
90 return 0;
94 static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
95 unsigned width)
97 ICH9LPCPMRegs *pm = opaque;
98 TCOIORegs *tr = &pm->tco_regs;
99 uint64_t tco_en;
101 switch (addr) {
102 case 0:
103 tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN;
104 /* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */
105 if (tr->tco.cnt1 & TCO_LOCK) {
106 val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) | tco_en;
108 pm->smi_en &= ~pm->smi_en_wmask;
109 pm->smi_en |= (val & pm->smi_en_wmask);
110 break;
114 static const MemoryRegionOps ich9_smi_ops = {
115 .read = ich9_smi_readl,
116 .write = ich9_smi_writel,
117 .valid.min_access_size = 4,
118 .valid.max_access_size = 4,
119 .endianness = DEVICE_LITTLE_ENDIAN,
122 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
124 ICH9_DEBUG("to 0x%x\n", pm_io_base);
126 assert((pm_io_base & ICH9_PMIO_MASK) == 0);
128 pm->pm_io_base = pm_io_base;
129 memory_region_transaction_begin();
130 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
131 memory_region_set_address(&pm->io, pm->pm_io_base);
132 memory_region_transaction_commit();
135 static int ich9_pm_post_load(void *opaque, int version_id)
137 ICH9LPCPMRegs *pm = opaque;
138 uint32_t pm_io_base = pm->pm_io_base;
139 pm->pm_io_base = 0;
140 ich9_pm_iospace_update(pm, pm_io_base);
141 return 0;
144 #define VMSTATE_GPE_ARRAY(_field, _state) \
146 .name = (stringify(_field)), \
147 .version_id = 0, \
148 .num = ICH9_PMIO_GPE0_LEN, \
149 .info = &vmstate_info_uint8, \
150 .size = sizeof(uint8_t), \
151 .flags = VMS_ARRAY | VMS_POINTER, \
152 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
155 static bool vmstate_test_use_memhp(void *opaque)
157 ICH9LPCPMRegs *s = opaque;
158 return s->acpi_memory_hotplug.is_enabled;
161 static const VMStateDescription vmstate_memhp_state = {
162 .name = "ich9_pm/memhp",
163 .version_id = 1,
164 .minimum_version_id = 1,
165 .minimum_version_id_old = 1,
166 .needed = vmstate_test_use_memhp,
167 .fields = (VMStateField[]) {
168 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs),
169 VMSTATE_END_OF_LIST()
173 static bool vmstate_test_use_tco(void *opaque)
175 ICH9LPCPMRegs *s = opaque;
176 return s->enable_tco;
179 static const VMStateDescription vmstate_tco_io_state = {
180 .name = "ich9_pm/tco",
181 .version_id = 1,
182 .minimum_version_id = 1,
183 .minimum_version_id_old = 1,
184 .needed = vmstate_test_use_tco,
185 .fields = (VMStateField[]) {
186 VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts,
187 TCOIORegs),
188 VMSTATE_END_OF_LIST()
192 static bool vmstate_test_use_cpuhp(void *opaque)
194 ICH9LPCPMRegs *s = opaque;
195 return !s->cpu_hotplug_legacy;
198 static int vmstate_cpuhp_pre_load(void *opaque)
200 ICH9LPCPMRegs *s = opaque;
201 Object *obj = OBJECT(s->gpe_cpu.device);
202 object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort);
203 return 0;
206 static const VMStateDescription vmstate_cpuhp_state = {
207 .name = "ich9_pm/cpuhp",
208 .version_id = 1,
209 .minimum_version_id = 1,
210 .minimum_version_id_old = 1,
211 .needed = vmstate_test_use_cpuhp,
212 .pre_load = vmstate_cpuhp_pre_load,
213 .fields = (VMStateField[]) {
214 VMSTATE_CPU_HOTPLUG(cpuhp_state, ICH9LPCPMRegs),
215 VMSTATE_END_OF_LIST()
219 const VMStateDescription vmstate_ich9_pm = {
220 .name = "ich9_pm",
221 .version_id = 1,
222 .minimum_version_id = 1,
223 .post_load = ich9_pm_post_load,
224 .fields = (VMStateField[]) {
225 VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
226 VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
227 VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
228 VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs),
229 VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
230 VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
231 VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
232 VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
233 VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
234 VMSTATE_END_OF_LIST()
236 .subsections = (const VMStateDescription*[]) {
237 &vmstate_memhp_state,
238 &vmstate_tco_io_state,
239 &vmstate_cpuhp_state,
240 NULL
244 static void pm_reset(void *opaque)
246 ICH9LPCPMRegs *pm = opaque;
247 ich9_pm_iospace_update(pm, 0);
249 acpi_pm1_evt_reset(&pm->acpi_regs);
250 acpi_pm1_cnt_reset(&pm->acpi_regs);
251 acpi_pm_tmr_reset(&pm->acpi_regs);
252 acpi_gpe_reset(&pm->acpi_regs);
254 pm->smi_en = 0;
255 if (!pm->smm_enabled) {
256 /* Mark SMM as already inited to prevent SMM from running. */
257 pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
259 pm->smi_en_wmask = ~0;
261 acpi_update_sci(&pm->acpi_regs, pm->irq);
264 static void pm_powerdown_req(Notifier *n, void *opaque)
266 ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
268 acpi_pm1_evt_power_down(&pm->acpi_regs);
271 void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
272 bool smm_enabled,
273 qemu_irq sci_irq)
275 memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
276 memory_region_set_enabled(&pm->io, false);
277 memory_region_add_subregion(pci_address_space_io(lpc_pci),
278 0, &pm->io);
280 acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
281 acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
282 acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
283 pm->s4_val);
285 acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
286 memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
287 "acpi-gpe0", ICH9_PMIO_GPE0_LEN);
288 memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
290 memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
291 "acpi-smi", 8);
292 memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
294 pm->smm_enabled = smm_enabled;
296 pm->enable_tco = true;
297 acpi_pm_tco_init(&pm->tco_regs, &pm->io);
299 pm->irq = sci_irq;
300 qemu_register_reset(pm_reset, pm);
301 pm->powerdown_notifier.notify = pm_powerdown_req;
302 qemu_register_powerdown_notifier(&pm->powerdown_notifier);
304 legacy_acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci),
305 OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);
307 if (pm->acpi_memory_hotplug.is_enabled) {
308 acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
309 &pm->acpi_memory_hotplug,
310 ACPI_MEMORY_HOTPLUG_BASE);
314 static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, const char *name,
315 void *opaque, Error **errp)
317 ICH9LPCPMRegs *pm = opaque;
318 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
320 visit_type_uint32(v, name, &value, errp);
323 static bool ich9_pm_get_memory_hotplug_support(Object *obj, Error **errp)
325 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
327 return s->pm.acpi_memory_hotplug.is_enabled;
330 static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value,
331 Error **errp)
333 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
335 s->pm.acpi_memory_hotplug.is_enabled = value;
338 static bool ich9_pm_get_cpu_hotplug_legacy(Object *obj, Error **errp)
340 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
342 return s->pm.cpu_hotplug_legacy;
345 static void ich9_pm_set_cpu_hotplug_legacy(Object *obj, bool value,
346 Error **errp)
348 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
350 assert(!value);
351 if (s->pm.cpu_hotplug_legacy && value == false) {
352 acpi_switch_to_modern_cphp(&s->pm.gpe_cpu, &s->pm.cpuhp_state,
353 ICH9_CPU_HOTPLUG_IO_BASE);
355 s->pm.cpu_hotplug_legacy = value;
358 static void ich9_pm_get_disable_s3(Object *obj, Visitor *v, const char *name,
359 void *opaque, Error **errp)
361 ICH9LPCPMRegs *pm = opaque;
362 uint8_t value = pm->disable_s3;
364 visit_type_uint8(v, name, &value, errp);
367 static void ich9_pm_set_disable_s3(Object *obj, Visitor *v, const char *name,
368 void *opaque, Error **errp)
370 ICH9LPCPMRegs *pm = opaque;
371 Error *local_err = NULL;
372 uint8_t value;
374 visit_type_uint8(v, name, &value, &local_err);
375 if (local_err) {
376 goto out;
378 pm->disable_s3 = value;
379 out:
380 error_propagate(errp, local_err);
383 static void ich9_pm_get_disable_s4(Object *obj, Visitor *v, const char *name,
384 void *opaque, Error **errp)
386 ICH9LPCPMRegs *pm = opaque;
387 uint8_t value = pm->disable_s4;
389 visit_type_uint8(v, name, &value, errp);
392 static void ich9_pm_set_disable_s4(Object *obj, Visitor *v, const char *name,
393 void *opaque, Error **errp)
395 ICH9LPCPMRegs *pm = opaque;
396 Error *local_err = NULL;
397 uint8_t value;
399 visit_type_uint8(v, name, &value, &local_err);
400 if (local_err) {
401 goto out;
403 pm->disable_s4 = value;
404 out:
405 error_propagate(errp, local_err);
408 static void ich9_pm_get_s4_val(Object *obj, Visitor *v, const char *name,
409 void *opaque, Error **errp)
411 ICH9LPCPMRegs *pm = opaque;
412 uint8_t value = pm->s4_val;
414 visit_type_uint8(v, name, &value, errp);
417 static void ich9_pm_set_s4_val(Object *obj, Visitor *v, const char *name,
418 void *opaque, Error **errp)
420 ICH9LPCPMRegs *pm = opaque;
421 Error *local_err = NULL;
422 uint8_t value;
424 visit_type_uint8(v, name, &value, &local_err);
425 if (local_err) {
426 goto out;
428 pm->s4_val = value;
429 out:
430 error_propagate(errp, local_err);
433 static bool ich9_pm_get_enable_tco(Object *obj, Error **errp)
435 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
436 return s->pm.enable_tco;
439 static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp)
441 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
442 s->pm.enable_tco = value;
445 void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
447 static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
448 pm->acpi_memory_hotplug.is_enabled = true;
449 pm->cpu_hotplug_legacy = true;
450 pm->disable_s3 = 0;
451 pm->disable_s4 = 0;
452 pm->s4_val = 2;
454 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
455 &pm->pm_io_base, errp);
456 object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
457 ich9_pm_get_gpe0_blk,
458 NULL, NULL, pm, NULL);
459 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
460 &gpe0_len, errp);
461 object_property_add_bool(obj, "memory-hotplug-support",
462 ich9_pm_get_memory_hotplug_support,
463 ich9_pm_set_memory_hotplug_support,
464 NULL);
465 object_property_add_bool(obj, "cpu-hotplug-legacy",
466 ich9_pm_get_cpu_hotplug_legacy,
467 ich9_pm_set_cpu_hotplug_legacy,
468 NULL);
469 object_property_add(obj, ACPI_PM_PROP_S3_DISABLED, "uint8",
470 ich9_pm_get_disable_s3,
471 ich9_pm_set_disable_s3,
472 NULL, pm, NULL);
473 object_property_add(obj, ACPI_PM_PROP_S4_DISABLED, "uint8",
474 ich9_pm_get_disable_s4,
475 ich9_pm_set_disable_s4,
476 NULL, pm, NULL);
477 object_property_add(obj, ACPI_PM_PROP_S4_VAL, "uint8",
478 ich9_pm_get_s4_val,
479 ich9_pm_set_s4_val,
480 NULL, pm, NULL);
481 object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
482 ich9_pm_get_enable_tco,
483 ich9_pm_set_enable_tco,
484 NULL);
487 void ich9_pm_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
488 Error **errp)
490 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
492 if (lpc->pm.acpi_memory_hotplug.is_enabled &&
493 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
494 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
495 nvdimm_acpi_plug_cb(hotplug_dev, dev);
496 } else {
497 acpi_memory_plug_cb(hotplug_dev, &lpc->pm.acpi_memory_hotplug,
498 dev, errp);
500 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
501 if (lpc->pm.cpu_hotplug_legacy) {
502 legacy_acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.gpe_cpu, dev, errp);
503 } else {
504 acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp);
506 } else {
507 error_setg(errp, "acpi: device plug request for not supported device"
508 " type: %s", object_get_typename(OBJECT(dev)));
512 void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev,
513 DeviceState *dev, Error **errp)
515 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
517 if (lpc->pm.acpi_memory_hotplug.is_enabled &&
518 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
519 acpi_memory_unplug_request_cb(hotplug_dev,
520 &lpc->pm.acpi_memory_hotplug, dev,
521 errp);
522 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
523 !lpc->pm.cpu_hotplug_legacy) {
524 acpi_cpu_unplug_request_cb(hotplug_dev, &lpc->pm.cpuhp_state,
525 dev, errp);
526 } else {
527 error_setg(errp, "acpi: device unplug request for not supported device"
528 " type: %s", object_get_typename(OBJECT(dev)));
532 void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
533 Error **errp)
535 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
537 if (lpc->pm.acpi_memory_hotplug.is_enabled &&
538 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
539 acpi_memory_unplug_cb(&lpc->pm.acpi_memory_hotplug, dev, errp);
540 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
541 !lpc->pm.cpu_hotplug_legacy) {
542 acpi_cpu_unplug_cb(&lpc->pm.cpuhp_state, dev, errp);
543 } else {
544 error_setg(errp, "acpi: device unplug for not supported device"
545 " type: %s", object_get_typename(OBJECT(dev)));
549 void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
551 ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
553 acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list);
554 if (!s->pm.cpu_hotplug_legacy) {
555 acpi_cpu_ospm_status(&s->pm.cpuhp_state, list);