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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150727' into staging
[qemu.git] / tcg / sparc / tcg-target.c
blob1a870a81d7fc2a76ba5e4aa1cd2cf61b9fbc83dc
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg-be-null.h"
26
27 #ifndef NDEBUG
28 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
29 "%g0",
30 "%g1",
31 "%g2",
32 "%g3",
33 "%g4",
34 "%g5",
35 "%g6",
36 "%g7",
37 "%o0",
38 "%o1",
39 "%o2",
40 "%o3",
41 "%o4",
42 "%o5",
43 "%o6",
44 "%o7",
45 "%l0",
46 "%l1",
47 "%l2",
48 "%l3",
49 "%l4",
50 "%l5",
51 "%l6",
52 "%l7",
53 "%i0",
54 "%i1",
55 "%i2",
56 "%i3",
57 "%i4",
58 "%i5",
59 "%i6",
60 "%i7",
61 };
62 #endif
63
64 #ifdef __arch64__
65 # define SPARC64 1
66 #else
67 # define SPARC64 0
68 #endif
69
70 /* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
71 registers. These are saved manually by the kernel in full 64-bit
72 slots. The %i and %l registers are saved by the register window
73 mechanism, which only allocates space for 32 bits. Given that this
74 window spill/fill can happen on any signal, we must consider the
75 high bits of the %i and %l registers garbage at all times. */
76 #if SPARC64
77 # define ALL_64 0xffffffffu
78 #else
79 # define ALL_64 0xffffu
80 #endif
81
82 /* Define some temporary registers. T2 is used for constant generation. */
83 #define TCG_REG_T1 TCG_REG_G1
84 #define TCG_REG_T2 TCG_REG_O7
85
86 #ifdef CONFIG_USE_GUEST_BASE
87 # define TCG_GUEST_BASE_REG TCG_REG_I5
88 #else
89 # define TCG_GUEST_BASE_REG TCG_REG_G0
90 #endif
91
92 static const int tcg_target_reg_alloc_order[] = {
93 TCG_REG_L0,
94 TCG_REG_L1,
95 TCG_REG_L2,
96 TCG_REG_L3,
97 TCG_REG_L4,
98 TCG_REG_L5,
99 TCG_REG_L6,
100 TCG_REG_L7,
101
102 TCG_REG_I0,
103 TCG_REG_I1,
104 TCG_REG_I2,
105 TCG_REG_I3,
106 TCG_REG_I4,
107 TCG_REG_I5,
108
109 TCG_REG_G2,
110 TCG_REG_G3,
111 TCG_REG_G4,
112 TCG_REG_G5,
113
114 TCG_REG_O0,
115 TCG_REG_O1,
116 TCG_REG_O2,
117 TCG_REG_O3,
118 TCG_REG_O4,
119 TCG_REG_O5,
120 };
121
122 static const int tcg_target_call_iarg_regs[6] = {
123 TCG_REG_O0,
124 TCG_REG_O1,
125 TCG_REG_O2,
126 TCG_REG_O3,
127 TCG_REG_O4,
128 TCG_REG_O5,
129 };
130
131 static const int tcg_target_call_oarg_regs[] = {
132 TCG_REG_O0,
133 TCG_REG_O1,
134 TCG_REG_O2,
135 TCG_REG_O3,
136 };
137
138 #define INSN_OP(x) ((x) << 30)
139 #define INSN_OP2(x) ((x) << 22)
140 #define INSN_OP3(x) ((x) << 19)
141 #define INSN_OPF(x) ((x) << 5)
142 #define INSN_RD(x) ((x) << 25)
143 #define INSN_RS1(x) ((x) << 14)
144 #define INSN_RS2(x) (x)
145 #define INSN_ASI(x) ((x) << 5)
146
147 #define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff))
148 #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
149 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
150 #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20))
151 #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
152 #define INSN_COND(x) ((x) << 25)
153
154 #define COND_N 0x0
155 #define COND_E 0x1
156 #define COND_LE 0x2
157 #define COND_L 0x3
158 #define COND_LEU 0x4
159 #define COND_CS 0x5
160 #define COND_NEG 0x6
161 #define COND_VS 0x7
162 #define COND_A 0x8
163 #define COND_NE 0x9
164 #define COND_G 0xa
165 #define COND_GE 0xb
166 #define COND_GU 0xc
167 #define COND_CC 0xd
168 #define COND_POS 0xe
169 #define COND_VC 0xf
170 #define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
171
172 #define RCOND_Z 1
173 #define RCOND_LEZ 2
174 #define RCOND_LZ 3
175 #define RCOND_NZ 5
176 #define RCOND_GZ 6
177 #define RCOND_GEZ 7
178
179 #define MOVCC_ICC (1 << 18)
180 #define MOVCC_XCC (1 << 18 | 1 << 12)
181
182 #define BPCC_ICC 0
183 #define BPCC_XCC (2 << 20)
184 #define BPCC_PT (1 << 19)
185 #define BPCC_PN 0
186 #define BPCC_A (1 << 29)
187
188 #define BPR_PT BPCC_PT
189
190 #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
191 #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
192 #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
193 #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
194 #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
195 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
196 #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
197 #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
198 #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
199 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
200 #define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08))
201 #define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c))
202 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
203 #define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b))
204 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
205 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
206 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
207 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
208 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
209 #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
210 #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
211
212 #define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11))
213 #define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16))
214
215 #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
216 #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
217 #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
218
219 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
220 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
221 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
222
223 #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
224 #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
225 #define JMPL (INSN_OP(2) | INSN_OP3(0x38))
226 #define RETURN (INSN_OP(2) | INSN_OP3(0x39))
227 #define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
228 #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
229 #define SETHI (INSN_OP(0) | INSN_OP2(0x4))
230 #define CALL INSN_OP(1)
231 #define LDUB (INSN_OP(3) | INSN_OP3(0x01))
232 #define LDSB (INSN_OP(3) | INSN_OP3(0x09))
233 #define LDUH (INSN_OP(3) | INSN_OP3(0x02))
234 #define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
235 #define LDUW (INSN_OP(3) | INSN_OP3(0x00))
236 #define LDSW (INSN_OP(3) | INSN_OP3(0x08))
237 #define LDX (INSN_OP(3) | INSN_OP3(0x0b))
238 #define STB (INSN_OP(3) | INSN_OP3(0x05))
239 #define STH (INSN_OP(3) | INSN_OP3(0x06))
240 #define STW (INSN_OP(3) | INSN_OP3(0x04))
241 #define STX (INSN_OP(3) | INSN_OP3(0x0e))
242 #define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
243 #define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
244 #define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
245 #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
246 #define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
247 #define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
248 #define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
249 #define STBA (INSN_OP(3) | INSN_OP3(0x15))
250 #define STHA (INSN_OP(3) | INSN_OP3(0x16))
251 #define STWA (INSN_OP(3) | INSN_OP3(0x14))
252 #define STXA (INSN_OP(3) | INSN_OP3(0x1e))
253
254 #ifndef ASI_PRIMARY_LITTLE
255 #define ASI_PRIMARY_LITTLE 0x88
256 #endif
257
258 #define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE))
259 #define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE))
260 #define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE))
261 #define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE))
262 #define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE))
263
264 #define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE))
265 #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
266 #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
267
268 #ifndef use_vis3_instructions
269 bool use_vis3_instructions;
270 #endif
271
272 static inline int check_fit_i64(int64_t val, unsigned int bits)
273 {
274 return val == sextract64(val, 0, bits);
275 }
276
277 static inline int check_fit_i32(int32_t val, unsigned int bits)
278 {
279 return val == sextract32(val, 0, bits);
280 }
281
282 #define check_fit_tl check_fit_i64
283 #if SPARC64
284 # define check_fit_ptr check_fit_i64
285 #else
286 # define check_fit_ptr check_fit_i32
287 #endif
288
289 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
290 intptr_t value, intptr_t addend)
291 {
292 uint32_t insn;
293
294 assert(addend == 0);
295 value = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr);
296
297 switch (type) {
298 case R_SPARC_WDISP16:
299 if (!check_fit_ptr(value >> 2, 16)) {
300 tcg_abort();
301 }
302 insn = *code_ptr;
303 insn &= ~INSN_OFF16(-1);
304 insn |= INSN_OFF16(value);
305 *code_ptr = insn;
306 break;
307 case R_SPARC_WDISP19:
308 if (!check_fit_ptr(value >> 2, 19)) {
309 tcg_abort();
310 }
311 insn = *code_ptr;
312 insn &= ~INSN_OFF19(-1);
313 insn |= INSN_OFF19(value);
314 *code_ptr = insn;
315 break;
316 default:
317 tcg_abort();
318 }
319 }
320
321 /* parse target specific constraints */
322 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
323 {
324 const char *ct_str;
325
326 ct_str = *pct_str;
327 switch (ct_str[0]) {
328 case 'r':
329 ct->ct |= TCG_CT_REG;
330 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
331 break;
332 case 'R':
333 ct->ct |= TCG_CT_REG;
334 tcg_regset_set32(ct->u.regs, 0, ALL_64);
335 break;
336 case 'A': /* qemu_ld/st address constraint */
337 ct->ct |= TCG_CT_REG;
338 tcg_regset_set32(ct->u.regs, 0,
339 TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff);
340 reserve_helpers:
341 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
342 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
343 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
344 break;
345 case 's': /* qemu_st data 32-bit constraint */
346 ct->ct |= TCG_CT_REG;
347 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
348 goto reserve_helpers;
349 case 'S': /* qemu_st data 64-bit constraint */
350 ct->ct |= TCG_CT_REG;
351 tcg_regset_set32(ct->u.regs, 0, ALL_64);
352 goto reserve_helpers;
353 case 'I':
354 ct->ct |= TCG_CT_CONST_S11;
355 break;
356 case 'J':
357 ct->ct |= TCG_CT_CONST_S13;
358 break;
359 case 'Z':
360 ct->ct |= TCG_CT_CONST_ZERO;
361 break;
362 default:
363 return -1;
364 }
365 ct_str++;
366 *pct_str = ct_str;
367 return 0;
368 }
369
370 /* test if a constant matches the constraint */
371 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
372 const TCGArgConstraint *arg_ct)
373 {
374 int ct = arg_ct->ct;
375
376 if (ct & TCG_CT_CONST) {
377 return 1;
378 }
379
380 if (type == TCG_TYPE_I32) {
381 val = (int32_t)val;
382 }
383
384 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
385 return 1;
386 } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
387 return 1;
388 } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) {
389 return 1;
390 } else {
391 return 0;
392 }
393 }
394
395 static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1,
396 TCGReg rs2, int op)
397 {
398 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2));
399 }
400
401 static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1,
402 int32_t offset, int op)
403 {
404 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset));
405 }
406
407 static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1,
408 int32_t val2, int val2const, int op)
409 {
410 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
411 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
412 }
413
414 static inline void tcg_out_mov(TCGContext *s, TCGType type,
415 TCGReg ret, TCGReg arg)
416 {
417 if (ret != arg) {
418 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
419 }
420 }
421
422 static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg)
423 {
424 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
425 }
426
427 static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg)
428 {
429 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
430 }
431
432 static void tcg_out_movi(TCGContext *s, TCGType type,
433 TCGReg ret, tcg_target_long arg)
434 {
435 tcg_target_long hi, lo = (int32_t)arg;
436
437 /* Make sure we test 32-bit constants for imm13 properly. */
438 if (type == TCG_TYPE_I32) {
439 arg = lo;
440 }
441
442 /* A 13-bit constant sign-extended to 64-bits. */
443 if (check_fit_tl(arg, 13)) {
444 tcg_out_movi_imm13(s, ret, arg);
445 return;
446 }
447
448 /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */
449 if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) {
450 tcg_out_sethi(s, ret, arg);
451 if (arg & 0x3ff) {
452 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
453 }
454 return;
455 }
456
457 /* A 32-bit constant sign-extended to 64-bits. */
458 if (arg == lo) {
459 tcg_out_sethi(s, ret, ~arg);
460 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
461 return;
462 }
463
464 /* A 64-bit constant decomposed into 2 32-bit pieces. */
465 if (check_fit_i32(lo, 13)) {
466 hi = (arg - lo) >> 32;
467 tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
468 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
469 tcg_out_arithi(s, ret, ret, lo, ARITH_ADD);
470 } else {
471 hi = arg >> 32;
472 tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
473 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo);
474 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
475 tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR);
476 }
477 }
478
479 static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1,
480 TCGReg a2, int op)
481 {
482 tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2));
483 }
484
485 static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr,
486 intptr_t offset, int op)
487 {
488 if (check_fit_ptr(offset, 13)) {
489 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
490 INSN_IMM13(offset));
491 } else {
492 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset);
493 tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op);
494 }
495 }
496
497 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
498 TCGReg arg1, intptr_t arg2)
499 {
500 tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX));
501 }
502
503 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
504 TCGReg arg1, intptr_t arg2)
505 {
506 tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX));
507 }
508
509 static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg)
510 {
511 tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff);
512 tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff);
513 }
514
515 static inline void tcg_out_sety(TCGContext *s, TCGReg rs)
516 {
517 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
518 }
519
520 static inline void tcg_out_rdy(TCGContext *s, TCGReg rd)
521 {
522 tcg_out32(s, RDY | INSN_RD(rd));
523 }
524
525 static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,
526 int32_t val2, int val2const, int uns)
527 {
528 /* Load Y with the sign/zero extension of RS1 to 64-bits. */
529 if (uns) {
530 tcg_out_sety(s, TCG_REG_G0);
531 } else {
532 tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA);
533 tcg_out_sety(s, TCG_REG_T1);
534 }
535
536 tcg_out_arithc(s, rd, rs1, val2, val2const,
537 uns ? ARITH_UDIV : ARITH_SDIV);
538 }
539
540 static inline void tcg_out_nop(TCGContext *s)
541 {
542 tcg_out_sethi(s, TCG_REG_G0, 0);
543 }
544
545 static const uint8_t tcg_cond_to_bcond[] = {
546 [TCG_COND_EQ] = COND_E,
547 [TCG_COND_NE] = COND_NE,
548 [TCG_COND_LT] = COND_L,
549 [TCG_COND_GE] = COND_GE,
550 [TCG_COND_LE] = COND_LE,
551 [TCG_COND_GT] = COND_G,
552 [TCG_COND_LTU] = COND_CS,
553 [TCG_COND_GEU] = COND_CC,
554 [TCG_COND_LEU] = COND_LEU,
555 [TCG_COND_GTU] = COND_GU,
556 };
557
558 static const uint8_t tcg_cond_to_rcond[] = {
559 [TCG_COND_EQ] = RCOND_Z,
560 [TCG_COND_NE] = RCOND_NZ,
561 [TCG_COND_LT] = RCOND_LZ,
562 [TCG_COND_GT] = RCOND_GZ,
563 [TCG_COND_LE] = RCOND_LEZ,
564 [TCG_COND_GE] = RCOND_GEZ
565 };
566
567 static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19)
568 {
569 tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19);
570 }
571
572 static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l)
573 {
574 int off19;
575
576 if (l->has_value) {
577 off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr));
578 } else {
579 /* Make sure to preserve destinations during retranslation. */
580 off19 = *s->code_ptr & INSN_OFF19(-1);
581 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0);
582 }
583 tcg_out_bpcc0(s, scond, flags, off19);
584 }
585
586 static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const)
587 {
588 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
589 }
590
591 static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1,
592 int32_t arg2, int const_arg2, TCGLabel *l)
593 {
594 tcg_out_cmp(s, arg1, arg2, const_arg2);
595 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l);
596 tcg_out_nop(s);
597 }
598
599 static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret,
600 int32_t v1, int v1const)
601 {
602 tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret)
603 | INSN_RS1(tcg_cond_to_bcond[cond])
604 | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1)));
605 }
606
607 static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
608 TCGReg c1, int32_t c2, int c2const,
609 int32_t v1, int v1const)
610 {
611 tcg_out_cmp(s, c1, c2, c2const);
612 tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const);
613 }
614
615 static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1,
616 int32_t arg2, int const_arg2, TCGLabel *l)
617 {
618 /* For 64-bit signed comparisons vs zero, we can avoid the compare. */
619 if (arg2 == 0 && !is_unsigned_cond(cond)) {
620 int off16;
621
622 if (l->has_value) {
623 off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr));
624 } else {
625 /* Make sure to preserve destinations during retranslation. */
626 off16 = *s->code_ptr & INSN_OFF16(-1);
627 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0);
628 }
629 tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1)
630 | INSN_COND(tcg_cond_to_rcond[cond]) | off16);
631 } else {
632 tcg_out_cmp(s, arg1, arg2, const_arg2);
633 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l);
634 }
635 tcg_out_nop(s);
636 }
637
638 static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1,
639 int32_t v1, int v1const)
640 {
641 tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1)
642 | (tcg_cond_to_rcond[cond] << 10)
643 | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1)));
644 }
645
646 static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
647 TCGReg c1, int32_t c2, int c2const,
648 int32_t v1, int v1const)
649 {
650 /* For 64-bit signed comparisons vs zero, we can avoid the compare.
651 Note that the immediate range is one bit smaller, so we must check
652 for that as well. */
653 if (c2 == 0 && !is_unsigned_cond(cond)
654 && (!v1const || check_fit_i32(v1, 10))) {
655 tcg_out_movr(s, cond, ret, c1, v1, v1const);
656 } else {
657 tcg_out_cmp(s, c1, c2, c2const);
658 tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
659 }
660 }
661
662 static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
663 TCGReg c1, int32_t c2, int c2const)
664 {
665 /* For 32-bit comparisons, we can play games with ADDC/SUBC. */
666 switch (cond) {
667 case TCG_COND_LTU:
668 case TCG_COND_GEU:
669 /* The result of the comparison is in the carry bit. */
670 break;
671
672 case TCG_COND_EQ:
673 case TCG_COND_NE:
674 /* For equality, we can transform to inequality vs zero. */
675 if (c2 != 0) {
676 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR);
677 c2 = TCG_REG_T1;
678 } else {
679 c2 = c1;
680 }
681 c1 = TCG_REG_G0, c2const = 0;
682 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
683 break;
684
685 case TCG_COND_GTU:
686 case TCG_COND_LEU:
687 /* If we don't need to load a constant into a register, we can
688 swap the operands on GTU/LEU. There's no benefit to loading
689 the constant into a temporary register. */
690 if (!c2const || c2 == 0) {
691 TCGReg t = c1;
692 c1 = c2;
693 c2 = t;
694 c2const = 0;
695 cond = tcg_swap_cond(cond);
696 break;
697 }
698 /* FALLTHRU */
699
700 default:
701 tcg_out_cmp(s, c1, c2, c2const);
702 tcg_out_movi_imm13(s, ret, 0);
703 tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1);
704 return;
705 }
706
707 tcg_out_cmp(s, c1, c2, c2const);
708 if (cond == TCG_COND_LTU) {
709 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC);
710 } else {
711 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC);
712 }
713 }
714
715 static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
716 TCGReg c1, int32_t c2, int c2const)
717 {
718 if (use_vis3_instructions) {
719 switch (cond) {
720 case TCG_COND_NE:
721 if (c2 != 0) {
722 break;
723 }
724 c2 = c1, c2const = 0, c1 = TCG_REG_G0;
725 /* FALLTHRU */
726 case TCG_COND_LTU:
727 tcg_out_cmp(s, c1, c2, c2const);
728 tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC);
729 return;
730 default:
731 break;
732 }
733 }
734
735 /* For 64-bit signed comparisons vs zero, we can avoid the compare
736 if the input does not overlap the output. */
737 if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) {
738 tcg_out_movi_imm13(s, ret, 0);
739 tcg_out_movr(s, cond, ret, c1, 1, 1);
740 } else {
741 tcg_out_cmp(s, c1, c2, c2const);
742 tcg_out_movi_imm13(s, ret, 0);
743 tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
744 }
745 }
746
747 static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh,
748 TCGReg al, TCGReg ah, int32_t bl, int blconst,
749 int32_t bh, int bhconst, int opl, int oph)
750 {
751 TCGReg tmp = TCG_REG_T1;
752
753 /* Note that the low parts are fully consumed before tmp is set. */
754 if (rl != ah && (bhconst || rl != bh)) {
755 tmp = rl;
756 }
757
758 tcg_out_arithc(s, tmp, al, bl, blconst, opl);
759 tcg_out_arithc(s, rh, ah, bh, bhconst, oph);
760 tcg_out_mov(s, TCG_TYPE_I32, rl, tmp);
761 }
762
763 static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
764 TCGReg al, TCGReg ah, int32_t bl, int blconst,
765 int32_t bh, int bhconst, bool is_sub)
766 {
767 TCGReg tmp = TCG_REG_T1;
768
769 /* Note that the low parts are fully consumed before tmp is set. */
770 if (rl != ah && (bhconst || rl != bh)) {
771 tmp = rl;
772 }
773
774 tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC);
775
776 if (use_vis3_instructions && !is_sub) {
777 /* Note that ADDXC doesn't accept immediates. */
778 if (bhconst && bh != 0) {
779 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh);
780 bh = TCG_REG_T2;
781 }
782 tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC);
783 } else if (bh == TCG_REG_G0) {
784 /* If we have a zero, we can perform the operation in two insns,
785 with the arithmetic first, and a conditional move into place. */
786 if (rh == ah) {
787 tcg_out_arithi(s, TCG_REG_T2, ah, 1,
788 is_sub ? ARITH_SUB : ARITH_ADD);
789 tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
790 } else {
791 tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD);
792 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
793 }
794 } else {
795 /* Otherwise adjust BH as if there is carry into T2 ... */
796 if (bhconst) {
797 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh + (is_sub ? -1 : 1));
798 } else {
799 tcg_out_arithi(s, TCG_REG_T2, bh, 1,
800 is_sub ? ARITH_SUB : ARITH_ADD);
801 }
802 /* ... smoosh T2 back to original BH if carry is clear ... */
803 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst);
804 /* ... and finally perform the arithmetic with the new operand. */
805 tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD);
806 }
807
808 tcg_out_mov(s, TCG_TYPE_I64, rl, tmp);
809 }
810
811 static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest)
812 {
813 ptrdiff_t disp = tcg_pcrel_diff(s, dest);
814
815 if (disp == (int32_t)disp) {
816 tcg_out32(s, CALL | (uint32_t)disp >> 2);
817 } else {
818 uintptr_t desti = (uintptr_t)dest;
819 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, desti & ~0xfff);
820 tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL);
821 }
822 }
823
824 static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
825 {
826 tcg_out_call_nodelay(s, dest);
827 tcg_out_nop(s);
828 }
829
830 #ifdef CONFIG_SOFTMMU
831 static tcg_insn_unit *qemu_ld_trampoline[16];
832 static tcg_insn_unit *qemu_st_trampoline[16];
833
834 static void build_trampolines(TCGContext *s)
835 {
836 static void * const qemu_ld_helpers[16] = {
837 [MO_UB] = helper_ret_ldub_mmu,
838 [MO_SB] = helper_ret_ldsb_mmu,
839 [MO_LEUW] = helper_le_lduw_mmu,
840 [MO_LESW] = helper_le_ldsw_mmu,
841 [MO_LEUL] = helper_le_ldul_mmu,
842 [MO_LEQ] = helper_le_ldq_mmu,
843 [MO_BEUW] = helper_be_lduw_mmu,
844 [MO_BESW] = helper_be_ldsw_mmu,
845 [MO_BEUL] = helper_be_ldul_mmu,
846 [MO_BEQ] = helper_be_ldq_mmu,
847 };
848 static void * const qemu_st_helpers[16] = {
849 [MO_UB] = helper_ret_stb_mmu,
850 [MO_LEUW] = helper_le_stw_mmu,
851 [MO_LEUL] = helper_le_stl_mmu,
852 [MO_LEQ] = helper_le_stq_mmu,
853 [MO_BEUW] = helper_be_stw_mmu,
854 [MO_BEUL] = helper_be_stl_mmu,
855 [MO_BEQ] = helper_be_stq_mmu,
856 };
857
858 int i;
859 TCGReg ra;
860
861 for (i = 0; i < 16; ++i) {
862 if (qemu_ld_helpers[i] == NULL) {
863 continue;
864 }
865
866 /* May as well align the trampoline. */
867 while ((uintptr_t)s->code_ptr & 15) {
868 tcg_out_nop(s);
869 }
870 qemu_ld_trampoline[i] = s->code_ptr;
871
872 if (SPARC64 || TARGET_LONG_BITS == 32) {
873 ra = TCG_REG_O3;
874 } else {
875 /* Install the high part of the address. */
876 tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX);
877 ra = TCG_REG_O4;
878 }
879
880 /* Set the retaddr operand. */
881 tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
882 /* Set the env operand. */
883 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
884 /* Tail call. */
885 tcg_out_call_nodelay(s, qemu_ld_helpers[i]);
886 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
887 }
888
889 for (i = 0; i < 16; ++i) {
890 if (qemu_st_helpers[i] == NULL) {
891 continue;
892 }
893
894 /* May as well align the trampoline. */
895 while ((uintptr_t)s->code_ptr & 15) {
896 tcg_out_nop(s);
897 }
898 qemu_st_trampoline[i] = s->code_ptr;
899
900 if (SPARC64) {
901 ra = TCG_REG_O4;
902 } else {
903 ra = TCG_REG_O1;
904 if (TARGET_LONG_BITS == 64) {
905 /* Install the high part of the address. */
906 tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
907 ra += 2;
908 } else {
909 ra += 1;
910 }
911 if ((i & MO_SIZE) == MO_64) {
912 /* Install the high part of the data. */
913 tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
914 ra += 2;
915 } else {
916 ra += 1;
917 }
918 /* Skip the oi argument. */
919 ra += 1;
920 }
921
922 /* Set the retaddr operand. */
923 if (ra >= TCG_REG_O6) {
924 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK,
925 TCG_TARGET_CALL_STACK_OFFSET);
926 ra = TCG_REG_G1;
927 }
928 tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
929 /* Set the env operand. */
930 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
931 /* Tail call. */
932 tcg_out_call_nodelay(s, qemu_st_helpers[i]);
933 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
934 }
935 }
936 #endif
937
938 /* Generate global QEMU prologue and epilogue code */
939 static void tcg_target_qemu_prologue(TCGContext *s)
940 {
941 int tmp_buf_size, frame_size;
942
943 /* The TCG temp buffer is at the top of the frame, immediately
944 below the frame pointer. */
945 tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long);
946 tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size,
947 tmp_buf_size);
948
949 /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is
950 otherwise the minimal frame usable by callees. */
951 frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS;
952 frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size;
953 frame_size += TCG_TARGET_STACK_ALIGN - 1;
954 frame_size &= -TCG_TARGET_STACK_ALIGN;
955 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
956 INSN_IMM13(-frame_size));
957
958 #ifdef CONFIG_USE_GUEST_BASE
959 if (GUEST_BASE != 0) {
960 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
961 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
962 }
963 #endif
964
965 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL);
966 /* delay slot */
967 tcg_out_nop(s);
968
969 /* No epilogue required. We issue ret + restore directly in the TB. */
970
971 #ifdef CONFIG_SOFTMMU
972 build_trampolines(s);
973 #endif
974 }
975
976 #if defined(CONFIG_SOFTMMU)
977 /* Perform the TLB load and compare.
978
979 Inputs:
980 ADDRLO and ADDRHI contain the possible two parts of the address.
981
982 MEM_INDEX and S_BITS are the memory context and log2 size of the load.
983
984 WHICH is the offset into the CPUTLBEntry structure of the slot to read.
985 This should be offsetof addr_read or addr_write.
986
987 The result of the TLB comparison is in %[ix]cc. The sanitized address
988 is in the returned register, maybe %o0. The TLB addend is in %o1. */
989
990 static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
991 TCGMemOp s_bits, int which)
992 {
993 const TCGReg r0 = TCG_REG_O0;
994 const TCGReg r1 = TCG_REG_O1;
995 const TCGReg r2 = TCG_REG_O2;
996 int tlb_ofs;
997
998 /* Shift the page number down. */
999 tcg_out_arithi(s, r1, addr, TARGET_PAGE_BITS, SHIFT_SRL);
1000
1001 /* Mask out the page offset, except for the required alignment. */
1002 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_T1,
1003 TARGET_PAGE_MASK | ((1 << s_bits) - 1));
1004
1005 /* Mask the tlb index. */
1006 tcg_out_arithi(s, r1, r1, CPU_TLB_SIZE - 1, ARITH_AND);
1007
1008 /* Mask page, part 2. */
1009 tcg_out_arith(s, r0, addr, TCG_REG_T1, ARITH_AND);
1010
1011 /* Shift the tlb index into place. */
1012 tcg_out_arithi(s, r1, r1, CPU_TLB_ENTRY_BITS, SHIFT_SLL);
1013
1014 /* Relative to the current ENV. */
1015 tcg_out_arith(s, r1, TCG_AREG0, r1, ARITH_ADD);
1016
1017 /* Find a base address that can load both tlb comparator and addend. */
1018 tlb_ofs = offsetof(CPUArchState, tlb_table[mem_index][0]);
1019 if (!check_fit_ptr(tlb_ofs + sizeof(CPUTLBEntry), 13)) {
1020 if (tlb_ofs & ~0x3ff) {
1021 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, tlb_ofs & ~0x3ff);
1022 tcg_out_arith(s, r1, r1, TCG_REG_T1, ARITH_ADD);
1023 }
1024 tlb_ofs &= 0x3ff;
1025 }
1026
1027 /* Load the tlb comparator and the addend. */
1028 tcg_out_ld(s, TCG_TYPE_TL, r2, r1, tlb_ofs + which);
1029 tcg_out_ld(s, TCG_TYPE_PTR, r1, r1, tlb_ofs+offsetof(CPUTLBEntry, addend));
1030
1031 /* subcc arg0, arg2, %g0 */
1032 tcg_out_cmp(s, r0, r2, 0);
1033
1034 /* If the guest address must be zero-extended, do so now. */
1035 if (SPARC64 && TARGET_LONG_BITS == 32) {
1036 tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL);
1037 return r0;
1038 }
1039 return addr;
1040 }
1041 #endif /* CONFIG_SOFTMMU */
1042
1043 static const int qemu_ld_opc[16] = {
1044 [MO_UB] = LDUB,
1045 [MO_SB] = LDSB,
1046
1047 [MO_BEUW] = LDUH,
1048 [MO_BESW] = LDSH,
1049 [MO_BEUL] = LDUW,
1050 [MO_BESL] = LDSW,
1051 [MO_BEQ] = LDX,
1052
1053 [MO_LEUW] = LDUH_LE,
1054 [MO_LESW] = LDSH_LE,
1055 [MO_LEUL] = LDUW_LE,
1056 [MO_LESL] = LDSW_LE,
1057 [MO_LEQ] = LDX_LE,
1058 };
1059
1060 static const int qemu_st_opc[16] = {
1061 [MO_UB] = STB,
1062
1063 [MO_BEUW] = STH,
1064 [MO_BEUL] = STW,
1065 [MO_BEQ] = STX,
1066
1067 [MO_LEUW] = STH_LE,
1068 [MO_LEUL] = STW_LE,
1069 [MO_LEQ] = STX_LE,
1070 };
1071
1072 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
1073 TCGMemOpIdx oi, bool is_64)
1074 {
1075 TCGMemOp memop = get_memop(oi);
1076 #ifdef CONFIG_SOFTMMU
1077 unsigned memi = get_mmuidx(oi);
1078 TCGReg addrz, param;
1079 tcg_insn_unit *func;
1080 tcg_insn_unit *label_ptr;
1081
1082 addrz = tcg_out_tlb_load(s, addr, memi, memop & MO_SIZE,
1083 offsetof(CPUTLBEntry, addr_read));
1084
1085 /* The fast path is exactly one insn. Thus we can perform the
1086 entire TLB Hit in the (annulled) delay slot of the branch
1087 over the TLB Miss case. */
1088
1089 /* beq,a,pt %[xi]cc, label0 */
1090 label_ptr = s->code_ptr;
1091 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
1092 | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
1093 /* delay slot */
1094 tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
1095 qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
1096
1097 /* TLB Miss. */
1098
1099 param = TCG_REG_O1;
1100 if (!SPARC64 && TARGET_LONG_BITS == 64) {
1101 /* Skip the high-part; we'll perform the extract in the trampoline. */
1102 param++;
1103 }
1104 tcg_out_mov(s, TCG_TYPE_REG, param++, addr);
1105
1106 /* We use the helpers to extend SB and SW data, leaving the case
1107 of SL needing explicit extending below. */
1108 if ((memop & MO_SSIZE) == MO_SL) {
1109 func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)];
1110 } else {
1111 func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)];
1112 }
1113 assert(func != NULL);
1114 tcg_out_call_nodelay(s, func);
1115 /* delay slot */
1116 tcg_out_movi(s, TCG_TYPE_I32, param, oi);
1117
1118 /* Recall that all of the helpers return 64-bit results.
1119 Which complicates things for sparcv8plus. */
1120 if (SPARC64) {
1121 /* We let the helper sign-extend SB and SW, but leave SL for here. */
1122 if (is_64 && (memop & MO_SSIZE) == MO_SL) {
1123 tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA);
1124 } else {
1125 tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);
1126 }
1127 } else {
1128 if ((memop & MO_SIZE) == MO_64) {
1129 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX);
1130 tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL);
1131 tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR);
1132 } else if (is_64) {
1133 /* Re-extend from 32-bit rather than reassembling when we
1134 know the high register must be an extension. */
1135 tcg_out_arithi(s, data, TCG_REG_O1, 0,
1136 memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL);
1137 } else {
1138 tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1);
1139 }
1140 }
1141
1142 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1143 #else
1144 if (SPARC64 && TARGET_LONG_BITS == 32) {
1145 tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
1146 addr = TCG_REG_T1;
1147 }
1148 tcg_out_ldst_rr(s, data, addr,
1149 (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
1150 qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
1151 #endif /* CONFIG_SOFTMMU */
1152 }
1153
1154 static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
1155 TCGMemOpIdx oi)
1156 {
1157 TCGMemOp memop = get_memop(oi);
1158 #ifdef CONFIG_SOFTMMU
1159 unsigned memi = get_mmuidx(oi);
1160 TCGReg addrz, param;
1161 tcg_insn_unit *func;
1162 tcg_insn_unit *label_ptr;
1163
1164 addrz = tcg_out_tlb_load(s, addr, memi, memop & MO_SIZE,
1165 offsetof(CPUTLBEntry, addr_write));
1166
1167 /* The fast path is exactly one insn. Thus we can perform the entire
1168 TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */
1169 /* beq,a,pt %[xi]cc, label0 */
1170 label_ptr = s->code_ptr;
1171 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
1172 | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
1173 /* delay slot */
1174 tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
1175 qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
1176
1177 /* TLB Miss. */
1178
1179 param = TCG_REG_O1;
1180 if (!SPARC64 && TARGET_LONG_BITS == 64) {
1181 /* Skip the high-part; we'll perform the extract in the trampoline. */
1182 param++;
1183 }
1184 tcg_out_mov(s, TCG_TYPE_REG, param++, addr);
1185 if (!SPARC64 && (memop & MO_SIZE) == MO_64) {
1186 /* Skip the high-part; we'll perform the extract in the trampoline. */
1187 param++;
1188 }
1189 tcg_out_mov(s, TCG_TYPE_REG, param++, data);
1190
1191 func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)];
1192 assert(func != NULL);
1193 tcg_out_call_nodelay(s, func);
1194 /* delay slot */
1195 tcg_out_movi(s, TCG_TYPE_I32, param, oi);
1196
1197 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1198 #else
1199 if (SPARC64 && TARGET_LONG_BITS == 32) {
1200 tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
1201 addr = TCG_REG_T1;
1202 }
1203 tcg_out_ldst_rr(s, data, addr,
1204 (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
1205 qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
1206 #endif /* CONFIG_SOFTMMU */
1207 }
1208
1209 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1210 const TCGArg args[TCG_MAX_OP_ARGS],
1211 const int const_args[TCG_MAX_OP_ARGS])
1212 {
1213 TCGArg a0, a1, a2;
1214 int c, c2;
1215
1216 /* Hoist the loads of the most common arguments. */
1217 a0 = args[0];
1218 a1 = args[1];
1219 a2 = args[2];
1220 c2 = const_args[2];
1221
1222 switch (opc) {
1223 case INDEX_op_exit_tb:
1224 if (check_fit_ptr(a0, 13)) {
1225 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1226 tcg_out_movi_imm13(s, TCG_REG_O0, a0);
1227 } else {
1228 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff);
1229 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1230 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR);
1231 }
1232 break;
1233 case INDEX_op_goto_tb:
1234 if (s->tb_jmp_offset) {
1235 /* direct jump method */
1236 s->tb_jmp_offset[a0] = tcg_current_code_size(s);
1237 /* Make sure to preserve links during retranslation. */
1238 tcg_out32(s, CALL | (*s->code_ptr & ~INSN_OP(-1)));
1239 } else {
1240 /* indirect jump method */
1241 tcg_out_ld_ptr(s, TCG_REG_T1, (uintptr_t)(s->tb_next + a0));
1242 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, 0, JMPL);
1243 }
1244 tcg_out_nop(s);
1245 s->tb_next_offset[a0] = tcg_current_code_size(s);
1246 break;
1247 case INDEX_op_br:
1248 tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0));
1249 tcg_out_nop(s);
1250 break;
1251
1252 #define OP_32_64(x) \
1253 glue(glue(case INDEX_op_, x), _i32): \
1254 glue(glue(case INDEX_op_, x), _i64)
1255
1256 OP_32_64(ld8u):
1257 tcg_out_ldst(s, a0, a1, a2, LDUB);
1258 break;
1259 OP_32_64(ld8s):
1260 tcg_out_ldst(s, a0, a1, a2, LDSB);
1261 break;
1262 OP_32_64(ld16u):
1263 tcg_out_ldst(s, a0, a1, a2, LDUH);
1264 break;
1265 OP_32_64(ld16s):
1266 tcg_out_ldst(s, a0, a1, a2, LDSH);
1267 break;
1268 case INDEX_op_ld_i32:
1269 case INDEX_op_ld32u_i64:
1270 tcg_out_ldst(s, a0, a1, a2, LDUW);
1271 break;
1272 OP_32_64(st8):
1273 tcg_out_ldst(s, a0, a1, a2, STB);
1274 break;
1275 OP_32_64(st16):
1276 tcg_out_ldst(s, a0, a1, a2, STH);
1277 break;
1278 case INDEX_op_st_i32:
1279 case INDEX_op_st32_i64:
1280 tcg_out_ldst(s, a0, a1, a2, STW);
1281 break;
1282 OP_32_64(add):
1283 c = ARITH_ADD;
1284 goto gen_arith;
1285 OP_32_64(sub):
1286 c = ARITH_SUB;
1287 goto gen_arith;
1288 OP_32_64(and):
1289 c = ARITH_AND;
1290 goto gen_arith;
1291 OP_32_64(andc):
1292 c = ARITH_ANDN;
1293 goto gen_arith;
1294 OP_32_64(or):
1295 c = ARITH_OR;
1296 goto gen_arith;
1297 OP_32_64(orc):
1298 c = ARITH_ORN;
1299 goto gen_arith;
1300 OP_32_64(xor):
1301 c = ARITH_XOR;
1302 goto gen_arith;
1303 case INDEX_op_shl_i32:
1304 c = SHIFT_SLL;
1305 do_shift32:
1306 /* Limit immediate shift count lest we create an illegal insn. */
1307 tcg_out_arithc(s, a0, a1, a2 & 31, c2, c);
1308 break;
1309 case INDEX_op_shr_i32:
1310 c = SHIFT_SRL;
1311 goto do_shift32;
1312 case INDEX_op_sar_i32:
1313 c = SHIFT_SRA;
1314 goto do_shift32;
1315 case INDEX_op_mul_i32:
1316 c = ARITH_UMUL;
1317 goto gen_arith;
1318
1319 OP_32_64(neg):
1320 c = ARITH_SUB;
1321 goto gen_arith1;
1322 OP_32_64(not):
1323 c = ARITH_ORN;
1324 goto gen_arith1;
1325
1326 case INDEX_op_div_i32:
1327 tcg_out_div32(s, a0, a1, a2, c2, 0);
1328 break;
1329 case INDEX_op_divu_i32:
1330 tcg_out_div32(s, a0, a1, a2, c2, 1);
1331 break;
1332
1333 case INDEX_op_brcond_i32:
1334 tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3]));
1335 break;
1336 case INDEX_op_setcond_i32:
1337 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2);
1338 break;
1339 case INDEX_op_movcond_i32:
1340 tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
1341 break;
1342
1343 case INDEX_op_add2_i32:
1344 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
1345 args[4], const_args[4], args[5], const_args[5],
1346 ARITH_ADDCC, ARITH_ADDC);
1347 break;
1348 case INDEX_op_sub2_i32:
1349 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
1350 args[4], const_args[4], args[5], const_args[5],
1351 ARITH_SUBCC, ARITH_SUBC);
1352 break;
1353 case INDEX_op_mulu2_i32:
1354 c = ARITH_UMUL;
1355 goto do_mul2;
1356 case INDEX_op_muls2_i32:
1357 c = ARITH_SMUL;
1358 do_mul2:
1359 /* The 32-bit multiply insns produce a full 64-bit result. If the
1360 destination register can hold it, we can avoid the slower RDY. */
1361 tcg_out_arithc(s, a0, a2, args[3], const_args[3], c);
1362 if (SPARC64 || a0 <= TCG_REG_O7) {
1363 tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
1364 } else {
1365 tcg_out_rdy(s, a1);
1366 }
1367 break;
1368
1369 case INDEX_op_qemu_ld_i32:
1370 tcg_out_qemu_ld(s, a0, a1, a2, false);
1371 break;
1372 case INDEX_op_qemu_ld_i64:
1373 tcg_out_qemu_ld(s, a0, a1, a2, true);
1374 break;
1375 case INDEX_op_qemu_st_i32:
1376 case INDEX_op_qemu_st_i64:
1377 tcg_out_qemu_st(s, a0, a1, a2);
1378 break;
1379
1380 case INDEX_op_ld32s_i64:
1381 tcg_out_ldst(s, a0, a1, a2, LDSW);
1382 break;
1383 case INDEX_op_ld_i64:
1384 tcg_out_ldst(s, a0, a1, a2, LDX);
1385 break;
1386 case INDEX_op_st_i64:
1387 tcg_out_ldst(s, a0, a1, a2, STX);
1388 break;
1389 case INDEX_op_shl_i64:
1390 c = SHIFT_SLLX;
1391 do_shift64:
1392 /* Limit immediate shift count lest we create an illegal insn. */
1393 tcg_out_arithc(s, a0, a1, a2 & 63, c2, c);
1394 break;
1395 case INDEX_op_shr_i64:
1396 c = SHIFT_SRLX;
1397 goto do_shift64;
1398 case INDEX_op_sar_i64:
1399 c = SHIFT_SRAX;
1400 goto do_shift64;
1401 case INDEX_op_mul_i64:
1402 c = ARITH_MULX;
1403 goto gen_arith;
1404 case INDEX_op_div_i64:
1405 c = ARITH_SDIVX;
1406 goto gen_arith;
1407 case INDEX_op_divu_i64:
1408 c = ARITH_UDIVX;
1409 goto gen_arith;
1410 case INDEX_op_ext32s_i64:
1411 tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA);
1412 break;
1413 case INDEX_op_ext32u_i64:
1414 tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL);
1415 break;
1416 case INDEX_op_trunc_shr_i32:
1417 if (a2 == 0) {
1418 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1419 } else {
1420 tcg_out_arithi(s, a0, a1, a2, SHIFT_SRLX);
1421 }
1422 break;
1423
1424 case INDEX_op_brcond_i64:
1425 tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3]));
1426 break;
1427 case INDEX_op_setcond_i64:
1428 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2);
1429 break;
1430 case INDEX_op_movcond_i64:
1431 tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
1432 break;
1433 case INDEX_op_add2_i64:
1434 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
1435 const_args[4], args[5], const_args[5], false);
1436 break;
1437 case INDEX_op_sub2_i64:
1438 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
1439 const_args[4], args[5], const_args[5], true);
1440 break;
1441 case INDEX_op_muluh_i64:
1442 tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI);
1443 break;
1444
1445 gen_arith:
1446 tcg_out_arithc(s, a0, a1, a2, c2, c);
1447 break;
1448
1449 gen_arith1:
1450 tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
1451 break;
1452
1453 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1454 case INDEX_op_mov_i64:
1455 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
1456 case INDEX_op_movi_i64:
1457 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1458 default:
1459 tcg_abort();
1460 }
1461 }
1462
1463 static const TCGTargetOpDef sparc_op_defs[] = {
1464 { INDEX_op_exit_tb, { } },
1465 { INDEX_op_goto_tb, { } },
1466 { INDEX_op_br, { } },
1467
1468 { INDEX_op_ld8u_i32, { "r", "r" } },
1469 { INDEX_op_ld8s_i32, { "r", "r" } },
1470 { INDEX_op_ld16u_i32, { "r", "r" } },
1471 { INDEX_op_ld16s_i32, { "r", "r" } },
1472 { INDEX_op_ld_i32, { "r", "r" } },
1473 { INDEX_op_st8_i32, { "rZ", "r" } },
1474 { INDEX_op_st16_i32, { "rZ", "r" } },
1475 { INDEX_op_st_i32, { "rZ", "r" } },
1476
1477 { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
1478 { INDEX_op_mul_i32, { "r", "rZ", "rJ" } },
1479 { INDEX_op_div_i32, { "r", "rZ", "rJ" } },
1480 { INDEX_op_divu_i32, { "r", "rZ", "rJ" } },
1481 { INDEX_op_sub_i32, { "r", "rZ", "rJ" } },
1482 { INDEX_op_and_i32, { "r", "rZ", "rJ" } },
1483 { INDEX_op_andc_i32, { "r", "rZ", "rJ" } },
1484 { INDEX_op_or_i32, { "r", "rZ", "rJ" } },
1485 { INDEX_op_orc_i32, { "r", "rZ", "rJ" } },
1486 { INDEX_op_xor_i32, { "r", "rZ", "rJ" } },
1487
1488 { INDEX_op_shl_i32, { "r", "rZ", "rJ" } },
1489 { INDEX_op_shr_i32, { "r", "rZ", "rJ" } },
1490 { INDEX_op_sar_i32, { "r", "rZ", "rJ" } },
1491
1492 { INDEX_op_neg_i32, { "r", "rJ" } },
1493 { INDEX_op_not_i32, { "r", "rJ" } },
1494
1495 { INDEX_op_brcond_i32, { "rZ", "rJ" } },
1496 { INDEX_op_setcond_i32, { "r", "rZ", "rJ" } },
1497 { INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } },
1498
1499 { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1500 { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1501 { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } },
1502 { INDEX_op_muls2_i32, { "r", "r", "rZ", "rJ" } },
1503
1504 { INDEX_op_ld8u_i64, { "R", "r" } },
1505 { INDEX_op_ld8s_i64, { "R", "r" } },
1506 { INDEX_op_ld16u_i64, { "R", "r" } },
1507 { INDEX_op_ld16s_i64, { "R", "r" } },
1508 { INDEX_op_ld32u_i64, { "R", "r" } },
1509 { INDEX_op_ld32s_i64, { "R", "r" } },
1510 { INDEX_op_ld_i64, { "R", "r" } },
1511 { INDEX_op_st8_i64, { "RZ", "r" } },
1512 { INDEX_op_st16_i64, { "RZ", "r" } },
1513 { INDEX_op_st32_i64, { "RZ", "r" } },
1514 { INDEX_op_st_i64, { "RZ", "r" } },
1515
1516 { INDEX_op_add_i64, { "R", "RZ", "RJ" } },
1517 { INDEX_op_mul_i64, { "R", "RZ", "RJ" } },
1518 { INDEX_op_div_i64, { "R", "RZ", "RJ" } },
1519 { INDEX_op_divu_i64, { "R", "RZ", "RJ" } },
1520 { INDEX_op_sub_i64, { "R", "RZ", "RJ" } },
1521 { INDEX_op_and_i64, { "R", "RZ", "RJ" } },
1522 { INDEX_op_andc_i64, { "R", "RZ", "RJ" } },
1523 { INDEX_op_or_i64, { "R", "RZ", "RJ" } },
1524 { INDEX_op_orc_i64, { "R", "RZ", "RJ" } },
1525 { INDEX_op_xor_i64, { "R", "RZ", "RJ" } },
1526
1527 { INDEX_op_shl_i64, { "R", "RZ", "RJ" } },
1528 { INDEX_op_shr_i64, { "R", "RZ", "RJ" } },
1529 { INDEX_op_sar_i64, { "R", "RZ", "RJ" } },
1530
1531 { INDEX_op_neg_i64, { "R", "RJ" } },
1532 { INDEX_op_not_i64, { "R", "RJ" } },
1533
1534 { INDEX_op_ext32s_i64, { "R", "r" } },
1535 { INDEX_op_ext32u_i64, { "R", "r" } },
1536 { INDEX_op_trunc_shr_i32, { "r", "R" } },
1537
1538 { INDEX_op_brcond_i64, { "RZ", "RJ" } },
1539 { INDEX_op_setcond_i64, { "R", "RZ", "RJ" } },
1540 { INDEX_op_movcond_i64, { "R", "RZ", "RJ", "RI", "0" } },
1541
1542 { INDEX_op_add2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
1543 { INDEX_op_sub2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
1544 { INDEX_op_muluh_i64, { "R", "RZ", "RZ" } },
1545
1546 { INDEX_op_qemu_ld_i32, { "r", "A" } },
1547 { INDEX_op_qemu_ld_i64, { "R", "A" } },
1548 { INDEX_op_qemu_st_i32, { "sZ", "A" } },
1549 { INDEX_op_qemu_st_i64, { "SZ", "A" } },
1550
1551 { -1 },
1552 };
1553
1554 static void tcg_target_init(TCGContext *s)
1555 {
1556 /* Only probe for the platform and capabilities if we havn't already
1557 determined maximum values at compile time. */
1558 #ifndef use_vis3_instructions
1559 {
1560 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
1561 use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0;
1562 }
1563 #endif
1564
1565 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1566 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64);
1567
1568 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1569 (1 << TCG_REG_G1) |
1570 (1 << TCG_REG_G2) |
1571 (1 << TCG_REG_G3) |
1572 (1 << TCG_REG_G4) |
1573 (1 << TCG_REG_G5) |
1574 (1 << TCG_REG_G6) |
1575 (1 << TCG_REG_G7) |
1576 (1 << TCG_REG_O0) |
1577 (1 << TCG_REG_O1) |
1578 (1 << TCG_REG_O2) |
1579 (1 << TCG_REG_O3) |
1580 (1 << TCG_REG_O4) |
1581 (1 << TCG_REG_O5) |
1582 (1 << TCG_REG_O7));
1583
1584 tcg_regset_clear(s->reserved_regs);
1585 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */
1586 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */
1587 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */
1588 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */
1589 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */
1590 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */
1591 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */
1592 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
1593
1594 tcg_add_target_add_op_defs(sparc_op_defs);
1595 }
1596
1597 #if SPARC64
1598 # define ELF_HOST_MACHINE EM_SPARCV9
1599 #else
1600 # define ELF_HOST_MACHINE EM_SPARC32PLUS
1601 # define ELF_HOST_FLAGS EF_SPARC_32PLUS
1602 #endif
1603
1604 typedef struct {
1605 DebugFrameHeader h;
1606 uint8_t fde_def_cfa[SPARC64 ? 4 : 2];
1607 uint8_t fde_win_save;
1608 uint8_t fde_ret_save[3];
1609 } DebugFrame;
1610
1611 static const DebugFrame debug_frame = {
1612 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
1613 .h.cie.id = -1,
1614 .h.cie.version = 1,
1615 .h.cie.code_align = 1,
1616 .h.cie.data_align = -sizeof(void *) & 0x7f,
1617 .h.cie.return_column = 15, /* o7 */
1618
1619 /* Total FDE size does not include the "len" member. */
1620 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
1621
1622 .fde_def_cfa = {
1623 #if SPARC64
1624 12, 30, /* DW_CFA_def_cfa i6, 2047 */
1625 (2047 & 0x7f) | 0x80, (2047 >> 7)
1626 #else
1627 13, 30 /* DW_CFA_def_cfa_register i6 */
1628 #endif
1629 },
1630 .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */
1631 .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */
1632 };
1633
1634 void tcg_register_jit(void *buf, size_t buf_size)
1635 {
1636 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
1637 }
1638
1639 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
1640 {
1641 uint32_t *ptr = (uint32_t *)jmp_addr;
1642 uintptr_t disp = addr - jmp_addr;
1643
1644 /* We can reach the entire address space for 32-bit. For 64-bit
1645 the code_gen_buffer can't be larger than 2GB. */
1646 assert(disp == (int32_t)disp);
1647
1648 *ptr = CALL | (uint32_t)disp >> 2;
1649 flush_icache_range(jmp_addr, jmp_addr + 4);
1650 }
QEmu