2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
24 #include "qemu/timer.h"
25 #include "qemu/queue.h"
26 #include "monitor/monitor.h"
27 #include "sysemu/sysemu.h"
33 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
34 * such can be changed by the guest, so to avoid a guest trigerrable
35 * abort we just qxl_set_guest_bug and set the return to NULL. Still
36 * it may happen as a result of emulator bug as well.
38 #undef SPICE_RING_PROD_ITEM
39 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
40 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
41 if (prod >= ARRAY_SIZE((r)->items)) { \
42 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
43 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
46 ret = &(r)->items[prod].el; \
50 #undef SPICE_RING_CONS_ITEM
51 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
52 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
53 if (cons >= ARRAY_SIZE((r)->items)) { \
54 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
55 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
58 ret = &(r)->items[cons].el; \
63 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
65 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
67 #define QXL_MODE(_x, _y, _b, _o) \
71 .stride = (_x) * (_b) / 8, \
72 .x_mili = PIXEL_SIZE * (_x), \
73 .y_mili = PIXEL_SIZE * (_y), \
77 #define QXL_MODE_16_32(x_res, y_res, orientation) \
78 QXL_MODE(x_res, y_res, 16, orientation), \
79 QXL_MODE(x_res, y_res, 32, orientation)
81 #define QXL_MODE_EX(x_res, y_res) \
82 QXL_MODE_16_32(x_res, y_res, 0), \
83 QXL_MODE_16_32(y_res, x_res, 1), \
84 QXL_MODE_16_32(x_res, y_res, 2), \
85 QXL_MODE_16_32(y_res, x_res, 3)
87 static QXLMode qxl_modes
[] = {
88 QXL_MODE_EX(640, 480),
89 QXL_MODE_EX(800, 480),
90 QXL_MODE_EX(800, 600),
91 QXL_MODE_EX(832, 624),
92 QXL_MODE_EX(960, 640),
93 QXL_MODE_EX(1024, 600),
94 QXL_MODE_EX(1024, 768),
95 QXL_MODE_EX(1152, 864),
96 QXL_MODE_EX(1152, 870),
97 QXL_MODE_EX(1280, 720),
98 QXL_MODE_EX(1280, 760),
99 QXL_MODE_EX(1280, 768),
100 QXL_MODE_EX(1280, 800),
101 QXL_MODE_EX(1280, 960),
102 QXL_MODE_EX(1280, 1024),
103 QXL_MODE_EX(1360, 768),
104 QXL_MODE_EX(1366, 768),
105 QXL_MODE_EX(1400, 1050),
106 QXL_MODE_EX(1440, 900),
107 QXL_MODE_EX(1600, 900),
108 QXL_MODE_EX(1600, 1200),
109 QXL_MODE_EX(1680, 1050),
110 QXL_MODE_EX(1920, 1080),
111 /* these modes need more than 8 MB video memory */
112 QXL_MODE_EX(1920, 1200),
113 QXL_MODE_EX(1920, 1440),
114 QXL_MODE_EX(2048, 1536),
115 QXL_MODE_EX(2560, 1440),
116 QXL_MODE_EX(2560, 1600),
117 /* these modes need more than 16 MB video memory */
118 QXL_MODE_EX(2560, 2048),
119 QXL_MODE_EX(2800, 2100),
120 QXL_MODE_EX(3200, 2400),
123 static PCIQXLDevice
*qxl0
;
125 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
126 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
127 static void qxl_reset_memslots(PCIQXLDevice
*d
);
128 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
129 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
131 void qxl_set_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
133 trace_qxl_set_guest_bug(qxl
->id
);
134 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
136 if (qxl
->guestdebug
) {
139 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
140 vfprintf(stderr
, msg
, ap
);
141 fprintf(stderr
, "\n");
146 static void qxl_clear_guest_bug(PCIQXLDevice
*qxl
)
151 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
152 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
153 uint32_t num_dirty_rects
,
154 uint32_t clear_dirty_region
,
155 qxl_async_io async
, struct QXLCookie
*cookie
)
157 trace_qxl_spice_update_area(qxl
->id
, surface_id
, area
->left
, area
->right
,
158 area
->top
, area
->bottom
);
159 trace_qxl_spice_update_area_rest(qxl
->id
, num_dirty_rects
,
161 if (async
== QXL_SYNC
) {
162 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
,
163 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
165 assert(cookie
!= NULL
);
166 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
167 clear_dirty_region
, (uintptr_t)cookie
);
171 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
174 trace_qxl_spice_destroy_surface_wait_complete(qxl
->id
, id
);
175 qemu_mutex_lock(&qxl
->track_lock
);
176 qxl
->guest_surfaces
.cmds
[id
] = 0;
177 qxl
->guest_surfaces
.count
--;
178 qemu_mutex_unlock(&qxl
->track_lock
);
181 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
186 trace_qxl_spice_destroy_surface_wait(qxl
->id
, id
, async
);
188 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
189 QXL_IO_DESTROY_SURFACE_ASYNC
);
190 cookie
->u
.surface_id
= id
;
191 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
, (uintptr_t)cookie
);
193 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
194 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
198 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
200 trace_qxl_spice_flush_surfaces_async(qxl
->id
, qxl
->guest_surfaces
.count
,
202 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
,
203 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
204 QXL_IO_FLUSH_SURFACES_ASYNC
));
207 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
210 trace_qxl_spice_loadvm_commands(qxl
->id
, ext
, count
);
211 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
214 void qxl_spice_oom(PCIQXLDevice
*qxl
)
216 trace_qxl_spice_oom(qxl
->id
);
217 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
220 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
222 trace_qxl_spice_reset_memslots(qxl
->id
);
223 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
226 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
228 trace_qxl_spice_destroy_surfaces_complete(qxl
->id
);
229 qemu_mutex_lock(&qxl
->track_lock
);
230 memset(qxl
->guest_surfaces
.cmds
, 0,
231 sizeof(qxl
->guest_surfaces
.cmds
) * qxl
->ssd
.num_surfaces
);
232 qxl
->guest_surfaces
.count
= 0;
233 qemu_mutex_unlock(&qxl
->track_lock
);
236 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
238 trace_qxl_spice_destroy_surfaces(qxl
->id
, async
);
240 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
,
241 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
242 QXL_IO_DESTROY_ALL_SURFACES_ASYNC
));
244 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
245 qxl_spice_destroy_surfaces_complete(qxl
);
249 static void qxl_spice_monitors_config_async(PCIQXLDevice
*qxl
, int replay
)
251 trace_qxl_spice_monitors_config(qxl
->id
);
254 * don't use QXL_COOKIE_TYPE_IO:
255 * - we are not running yet (post_load), we will assert
257 * - this is not a guest io, but a reply, so async_io isn't set.
259 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
260 qxl
->guest_monitors_config
,
262 (uintptr_t)qxl_cookie_new(
263 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
,
266 qxl
->guest_monitors_config
= qxl
->ram
->monitors_config
;
267 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
268 qxl
->ram
->monitors_config
,
270 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
271 QXL_IO_MONITORS_CONFIG_ASYNC
));
275 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
277 trace_qxl_spice_reset_image_cache(qxl
->id
);
278 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
281 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
283 trace_qxl_spice_reset_cursor(qxl
->id
);
284 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
285 qemu_mutex_lock(&qxl
->track_lock
);
286 qxl
->guest_cursor
= 0;
287 qemu_mutex_unlock(&qxl
->track_lock
);
288 if (qxl
->ssd
.cursor
) {
289 cursor_put(qxl
->ssd
.cursor
);
291 qxl
->ssd
.cursor
= cursor_builtin_hidden();
295 static inline uint32_t msb_mask(uint32_t val
)
300 mask
= ~(val
- 1) & val
;
302 } while (mask
< val
);
307 static ram_addr_t
qxl_rom_size(void)
309 uint32_t rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) + sizeof(qxl_modes
);
311 rom_size
= MAX(rom_size
, TARGET_PAGE_SIZE
);
312 rom_size
= msb_mask(rom_size
* 2 - 1);
316 static void init_qxl_rom(PCIQXLDevice
*d
)
318 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
319 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
320 uint32_t ram_header_size
;
321 uint32_t surface0_area_size
;
326 memset(rom
, 0, d
->rom_size
);
328 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
329 rom
->id
= cpu_to_le32(d
->id
);
330 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
331 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
333 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
334 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
335 rom
->slots_start
= 1;
336 rom
->slots_end
= NUM_MEMSLOTS
- 1;
337 rom
->n_surfaces
= cpu_to_le32(d
->ssd
.num_surfaces
);
339 for (i
= 0, n
= 0; i
< ARRAY_SIZE(qxl_modes
); i
++) {
340 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
341 if (fb
> d
->vgamem_size
) {
344 modes
->modes
[n
].id
= cpu_to_le32(i
);
345 modes
->modes
[n
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
346 modes
->modes
[n
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
347 modes
->modes
[n
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
348 modes
->modes
[n
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
349 modes
->modes
[n
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
350 modes
->modes
[n
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
351 modes
->modes
[n
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
354 modes
->n_modes
= cpu_to_le32(n
);
356 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
357 surface0_area_size
= ALIGN(d
->vgamem_size
, 4096);
358 num_pages
= d
->vga
.vram_size
;
359 num_pages
-= ram_header_size
;
360 num_pages
-= surface0_area_size
;
361 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
363 rom
->draw_area_offset
= cpu_to_le32(0);
364 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
365 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
366 rom
->num_pages
= cpu_to_le32(num_pages
);
367 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
369 d
->shadow_rom
= *rom
;
374 static void init_qxl_ram(PCIQXLDevice
*d
)
379 buf
= d
->vga
.vram_ptr
;
380 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
381 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
382 d
->ram
->int_pending
= cpu_to_le32(0);
383 d
->ram
->int_mask
= cpu_to_le32(0);
384 d
->ram
->update_surface
= 0;
385 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
386 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
387 SPICE_RING_INIT(&d
->ram
->release_ring
);
388 SPICE_RING_PROD_ITEM(d
, &d
->ram
->release_ring
, item
);
391 qxl_ring_set_dirty(d
);
394 /* can be called from spice server thread context */
395 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
397 memory_region_set_dirty(mr
, addr
, end
- addr
);
400 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
402 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
405 /* called from spice server thread context only */
406 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
408 void *base
= qxl
->vga
.vram_ptr
;
412 offset
&= ~(TARGET_PAGE_SIZE
-1);
413 assert(offset
< qxl
->vga
.vram_size
);
414 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ TARGET_PAGE_SIZE
);
417 /* can be called from spice server thread context */
418 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
420 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
421 ram_addr_t end
= qxl
->vga
.vram_size
;
422 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
426 * keep track of some command state, for savevm/loadvm.
427 * called from spice server thread context only
429 static int qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
431 switch (le32_to_cpu(ext
->cmd
.type
)) {
432 case QXL_CMD_SURFACE
:
434 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
439 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
441 if (id
>= qxl
->ssd
.num_surfaces
) {
442 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE id %d >= %d", id
,
443 qxl
->ssd
.num_surfaces
);
446 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
&&
447 (cmd
->u
.surface_create
.stride
& 0x03) != 0) {
448 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
449 cmd
->u
.surface_create
.stride
);
452 qemu_mutex_lock(&qxl
->track_lock
);
453 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
454 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
455 qxl
->guest_surfaces
.count
++;
456 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
457 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
459 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
460 qxl
->guest_surfaces
.cmds
[id
] = 0;
461 qxl
->guest_surfaces
.count
--;
463 qemu_mutex_unlock(&qxl
->track_lock
);
468 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
473 if (cmd
->type
== QXL_CURSOR_SET
) {
474 qemu_mutex_lock(&qxl
->track_lock
);
475 qxl
->guest_cursor
= ext
->cmd
.data
;
476 qemu_mutex_unlock(&qxl
->track_lock
);
484 /* spice display interface callbacks */
486 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
488 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
490 trace_qxl_interface_attach_worker(qxl
->id
);
491 qxl
->ssd
.worker
= qxl_worker
;
494 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
496 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
498 trace_qxl_interface_set_compression_level(qxl
->id
, level
);
499 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
500 qxl
->rom
->compression_level
= cpu_to_le32(level
);
501 qxl_rom_set_dirty(qxl
);
504 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
506 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
508 trace_qxl_interface_set_mm_time(qxl
->id
, mm_time
);
509 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
510 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
511 qxl_rom_set_dirty(qxl
);
514 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
516 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
518 trace_qxl_interface_get_init_info(qxl
->id
);
519 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
520 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
521 info
->num_memslots
= NUM_MEMSLOTS
;
522 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
523 info
->internal_groupslot_id
= 0;
524 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
525 info
->n_surfaces
= qxl
->ssd
.num_surfaces
;
528 static const char *qxl_mode_to_string(int mode
)
531 case QXL_MODE_COMPAT
:
533 case QXL_MODE_NATIVE
:
535 case QXL_MODE_UNDEFINED
:
543 static const char *io_port_to_string(uint32_t io_port
)
545 if (io_port
>= QXL_IO_RANGE_SIZE
) {
546 return "out of range";
548 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
549 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
550 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
551 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
552 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
553 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
554 [QXL_IO_RESET
] = "QXL_IO_RESET",
555 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
556 [QXL_IO_LOG
] = "QXL_IO_LOG",
557 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
558 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
559 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
560 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
561 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
562 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
563 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
564 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
565 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
566 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
567 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
568 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
569 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
570 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
571 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
572 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
573 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
574 [QXL_IO_MONITORS_CONFIG_ASYNC
] = "QXL_IO_MONITORS_CONFIG_ASYNC",
576 return io_port_to_string
[io_port
];
579 /* called from spice server thread context only */
580 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
582 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
583 SimpleSpiceUpdate
*update
;
584 QXLCommandRing
*ring
;
588 trace_qxl_ring_command_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
593 qemu_mutex_lock(&qxl
->ssd
.lock
);
594 update
= QTAILQ_FIRST(&qxl
->ssd
.updates
);
595 if (update
!= NULL
) {
596 QTAILQ_REMOVE(&qxl
->ssd
.updates
, update
, next
);
600 qemu_mutex_unlock(&qxl
->ssd
.lock
);
602 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
603 qxl_log_command(qxl
, "vga", ext
);
606 case QXL_MODE_COMPAT
:
607 case QXL_MODE_NATIVE
:
608 case QXL_MODE_UNDEFINED
:
609 ring
= &qxl
->ram
->cmd_ring
;
610 if (qxl
->guest_bug
|| SPICE_RING_IS_EMPTY(ring
)) {
613 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
618 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
619 ext
->flags
= qxl
->cmdflags
;
620 SPICE_RING_POP(ring
, notify
);
621 qxl_ring_set_dirty(qxl
);
623 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
625 qxl
->guest_primary
.commands
++;
626 qxl_track_command(qxl
, ext
);
627 qxl_log_command(qxl
, "cmd", ext
);
628 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
635 /* called from spice server thread context only */
636 static int interface_req_cmd_notification(QXLInstance
*sin
)
638 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
641 trace_qxl_ring_command_req_notification(qxl
->id
);
643 case QXL_MODE_COMPAT
:
644 case QXL_MODE_NATIVE
:
645 case QXL_MODE_UNDEFINED
:
646 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
647 qxl_ring_set_dirty(qxl
);
656 /* called from spice server thread context only */
657 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
659 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
663 #define QXL_FREE_BUNCH_SIZE 32
665 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
666 /* ring full -- can't push */
669 if (!flush
&& d
->oom_running
) {
670 /* collect everything from oom handler before pushing */
673 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
674 /* collect a bit more before pushing */
678 SPICE_RING_PUSH(ring
, notify
);
679 trace_qxl_ring_res_push(d
->id
, qxl_mode_to_string(d
->mode
),
680 d
->guest_surfaces
.count
, d
->num_free_res
,
681 d
->last_release
, notify
? "yes" : "no");
682 trace_qxl_ring_res_push_rest(d
->id
, ring
->prod
- ring
->cons
,
683 ring
->num_items
, ring
->prod
, ring
->cons
);
685 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
687 SPICE_RING_PROD_ITEM(d
, ring
, item
);
693 d
->last_release
= NULL
;
694 qxl_ring_set_dirty(d
);
697 /* called from spice server thread context only */
698 static void interface_release_resource(QXLInstance
*sin
,
699 struct QXLReleaseInfoExt ext
)
701 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
702 QXLReleaseRing
*ring
;
705 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
706 /* host group -> vga mode update request */
707 qemu_spice_destroy_update(&qxl
->ssd
, (void *)(intptr_t)ext
.info
->id
);
712 * ext->info points into guest-visible memory
713 * pci bar 0, $command.release_info
715 ring
= &qxl
->ram
->release_ring
;
716 SPICE_RING_PROD_ITEM(qxl
, ring
, item
);
721 /* stick head into the ring */
724 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
726 qxl_ring_set_dirty(qxl
);
728 /* append item to the list */
729 qxl
->last_release
->next
= ext
.info
->id
;
730 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
732 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
734 qxl
->last_release
= ext
.info
;
736 trace_qxl_ring_res_put(qxl
->id
, qxl
->num_free_res
);
737 qxl_push_free_res(qxl
, 0);
740 /* called from spice server thread context only */
741 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
743 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
748 trace_qxl_ring_cursor_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
751 case QXL_MODE_COMPAT
:
752 case QXL_MODE_NATIVE
:
753 case QXL_MODE_UNDEFINED
:
754 ring
= &qxl
->ram
->cursor_ring
;
755 if (SPICE_RING_IS_EMPTY(ring
)) {
758 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
763 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
764 ext
->flags
= qxl
->cmdflags
;
765 SPICE_RING_POP(ring
, notify
);
766 qxl_ring_set_dirty(qxl
);
768 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
770 qxl
->guest_primary
.commands
++;
771 qxl_track_command(qxl
, ext
);
772 qxl_log_command(qxl
, "csr", ext
);
774 qxl_render_cursor(qxl
, ext
);
776 trace_qxl_ring_cursor_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
783 /* called from spice server thread context only */
784 static int interface_req_cursor_notification(QXLInstance
*sin
)
786 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
789 trace_qxl_ring_cursor_req_notification(qxl
->id
);
791 case QXL_MODE_COMPAT
:
792 case QXL_MODE_NATIVE
:
793 case QXL_MODE_UNDEFINED
:
794 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
795 qxl_ring_set_dirty(qxl
);
804 /* called from spice server thread context */
805 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
808 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
809 * use by xf86-video-qxl and is defined out in the qxl windows driver.
810 * Probably was at some earlier version that is prior to git start (2009),
811 * and is still guest trigerrable.
813 fprintf(stderr
, "%s: deprecated\n", __func__
);
816 /* called from spice server thread context only */
817 static int interface_flush_resources(QXLInstance
*sin
)
819 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
822 ret
= qxl
->num_free_res
;
824 qxl_push_free_res(qxl
, 1);
829 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
831 /* called from spice server thread context only */
832 static void interface_async_complete_io(PCIQXLDevice
*qxl
, QXLCookie
*cookie
)
834 uint32_t current_async
;
836 qemu_mutex_lock(&qxl
->async_lock
);
837 current_async
= qxl
->current_async
;
838 qxl
->current_async
= QXL_UNDEFINED_IO
;
839 qemu_mutex_unlock(&qxl
->async_lock
);
841 trace_qxl_interface_async_complete_io(qxl
->id
, current_async
, cookie
);
843 fprintf(stderr
, "qxl: %s: error, cookie is NULL\n", __func__
);
846 if (cookie
&& current_async
!= cookie
->io
) {
848 "qxl: %s: error: current_async = %d != %"
849 PRId64
" = cookie->io\n", __func__
, current_async
, cookie
->io
);
851 switch (current_async
) {
852 case QXL_IO_MEMSLOT_ADD_ASYNC
:
853 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
854 case QXL_IO_UPDATE_AREA_ASYNC
:
855 case QXL_IO_FLUSH_SURFACES_ASYNC
:
856 case QXL_IO_MONITORS_CONFIG_ASYNC
:
858 case QXL_IO_CREATE_PRIMARY_ASYNC
:
859 qxl_create_guest_primary_complete(qxl
);
861 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
862 qxl_spice_destroy_surfaces_complete(qxl
);
864 case QXL_IO_DESTROY_SURFACE_ASYNC
:
865 qxl_spice_destroy_surface_wait_complete(qxl
, cookie
->u
.surface_id
);
868 fprintf(stderr
, "qxl: %s: unexpected current_async %d\n", __func__
,
871 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
874 /* called from spice server thread context only */
875 static void interface_update_area_complete(QXLInstance
*sin
,
877 QXLRect
*dirty
, uint32_t num_updated_rects
)
879 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
883 qemu_mutex_lock(&qxl
->ssd
.lock
);
884 if (surface_id
!= 0 || !qxl
->render_update_cookie_num
) {
885 qemu_mutex_unlock(&qxl
->ssd
.lock
);
888 trace_qxl_interface_update_area_complete(qxl
->id
, surface_id
, dirty
->left
,
889 dirty
->right
, dirty
->top
, dirty
->bottom
);
890 trace_qxl_interface_update_area_complete_rest(qxl
->id
, num_updated_rects
);
891 if (qxl
->num_dirty_rects
+ num_updated_rects
> QXL_NUM_DIRTY_RECTS
) {
893 * overflow - treat this as a full update. Not expected to be common.
895 trace_qxl_interface_update_area_complete_overflow(qxl
->id
,
896 QXL_NUM_DIRTY_RECTS
);
897 qxl
->guest_primary
.resized
= 1;
899 if (qxl
->guest_primary
.resized
) {
901 * Don't bother copying or scheduling the bh since we will flip
902 * the whole area anyway on completion of the update_area async call
904 qemu_mutex_unlock(&qxl
->ssd
.lock
);
907 qxl_i
= qxl
->num_dirty_rects
;
908 for (i
= 0; i
< num_updated_rects
; i
++) {
909 qxl
->dirty
[qxl_i
++] = dirty
[i
];
911 qxl
->num_dirty_rects
+= num_updated_rects
;
912 trace_qxl_interface_update_area_complete_schedule_bh(qxl
->id
,
913 qxl
->num_dirty_rects
);
914 qemu_bh_schedule(qxl
->update_area_bh
);
915 qemu_mutex_unlock(&qxl
->ssd
.lock
);
918 /* called from spice server thread context only */
919 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie_token
)
921 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
922 QXLCookie
*cookie
= (QXLCookie
*)(uintptr_t)cookie_token
;
924 switch (cookie
->type
) {
925 case QXL_COOKIE_TYPE_IO
:
926 interface_async_complete_io(qxl
, cookie
);
929 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA
:
930 qxl_render_update_area_done(qxl
, cookie
);
932 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
:
935 fprintf(stderr
, "qxl: %s: unexpected cookie type %d\n",
936 __func__
, cookie
->type
);
941 /* called from spice server thread context only */
942 static void interface_set_client_capabilities(QXLInstance
*sin
,
943 uint8_t client_present
,
946 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
948 if (runstate_check(RUN_STATE_INMIGRATE
) ||
949 runstate_check(RUN_STATE_POSTMIGRATE
)) {
953 qxl
->shadow_rom
.client_present
= client_present
;
954 memcpy(qxl
->shadow_rom
.client_capabilities
, caps
,
955 sizeof(qxl
->shadow_rom
.client_capabilities
));
956 qxl
->rom
->client_present
= client_present
;
957 memcpy(qxl
->rom
->client_capabilities
, caps
,
958 sizeof(qxl
->rom
->client_capabilities
));
959 qxl_rom_set_dirty(qxl
);
961 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT
);
964 static uint32_t qxl_crc32(const uint8_t *p
, unsigned len
)
967 * zlib xors the seed with 0xffffffff, and xors the result
968 * again with 0xffffffff; Both are not done with linux's crc32,
969 * which we want to be compatible with, so undo that.
971 return crc32(0xffffffff, p
, len
) ^ 0xffffffff;
974 /* called from main context only */
975 static int interface_client_monitors_config(QXLInstance
*sin
,
976 VDAgentMonitorsConfig
*monitors_config
)
978 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
979 QXLRom
*rom
= memory_region_get_ram_ptr(&qxl
->rom_bar
);
983 * Older windows drivers set int_mask to 0 when their ISR is called,
984 * then later set it to ~0. So it doesn't relate to the actual interrupts
985 * handled. However, they are old, so clearly they don't support this
988 if (qxl
->ram
->int_mask
== 0 || qxl
->ram
->int_mask
== ~0 ||
989 !(qxl
->ram
->int_mask
& QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
)) {
990 trace_qxl_client_monitors_config_unsupported_by_guest(qxl
->id
,
995 if (!monitors_config
) {
998 memset(&rom
->client_monitors_config
, 0,
999 sizeof(rom
->client_monitors_config
));
1000 rom
->client_monitors_config
.count
= monitors_config
->num_of_monitors
;
1001 /* monitors_config->flags ignored */
1002 if (rom
->client_monitors_config
.count
>=
1003 ARRAY_SIZE(rom
->client_monitors_config
.heads
)) {
1004 trace_qxl_client_monitors_config_capped(qxl
->id
,
1005 monitors_config
->num_of_monitors
,
1006 ARRAY_SIZE(rom
->client_monitors_config
.heads
));
1007 rom
->client_monitors_config
.count
=
1008 ARRAY_SIZE(rom
->client_monitors_config
.heads
);
1010 for (i
= 0 ; i
< rom
->client_monitors_config
.count
; ++i
) {
1011 VDAgentMonConfig
*monitor
= &monitors_config
->monitors
[i
];
1012 QXLURect
*rect
= &rom
->client_monitors_config
.heads
[i
];
1013 /* monitor->depth ignored */
1014 rect
->left
= monitor
->x
;
1015 rect
->top
= monitor
->y
;
1016 rect
->right
= monitor
->x
+ monitor
->width
;
1017 rect
->bottom
= monitor
->y
+ monitor
->height
;
1019 rom
->client_monitors_config_crc
= qxl_crc32(
1020 (const uint8_t *)&rom
->client_monitors_config
,
1021 sizeof(rom
->client_monitors_config
));
1022 trace_qxl_client_monitors_config_crc(qxl
->id
,
1023 sizeof(rom
->client_monitors_config
),
1024 rom
->client_monitors_config_crc
);
1026 trace_qxl_interrupt_client_monitors_config(qxl
->id
,
1027 rom
->client_monitors_config
.count
,
1028 rom
->client_monitors_config
.heads
);
1029 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
);
1033 static const QXLInterface qxl_interface
= {
1034 .base
.type
= SPICE_INTERFACE_QXL
,
1035 .base
.description
= "qxl gpu",
1036 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
1037 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
1039 .attache_worker
= interface_attach_worker
,
1040 .set_compression_level
= interface_set_compression_level
,
1041 .set_mm_time
= interface_set_mm_time
,
1042 .get_init_info
= interface_get_init_info
,
1044 /* the callbacks below are called from spice server thread context */
1045 .get_command
= interface_get_command
,
1046 .req_cmd_notification
= interface_req_cmd_notification
,
1047 .release_resource
= interface_release_resource
,
1048 .get_cursor_command
= interface_get_cursor_command
,
1049 .req_cursor_notification
= interface_req_cursor_notification
,
1050 .notify_update
= interface_notify_update
,
1051 .flush_resources
= interface_flush_resources
,
1052 .async_complete
= interface_async_complete
,
1053 .update_area_complete
= interface_update_area_complete
,
1054 .set_client_capabilities
= interface_set_client_capabilities
,
1055 .client_monitors_config
= interface_client_monitors_config
,
1058 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
1060 if (d
->mode
== QXL_MODE_VGA
) {
1063 trace_qxl_enter_vga_mode(d
->id
);
1064 qemu_spice_create_host_primary(&d
->ssd
);
1065 d
->mode
= QXL_MODE_VGA
;
1066 dpy_gfx_resize(d
->ssd
.ds
);
1067 vga_dirty_log_start(&d
->vga
);
1070 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
1072 if (d
->mode
!= QXL_MODE_VGA
) {
1075 trace_qxl_exit_vga_mode(d
->id
);
1076 vga_dirty_log_stop(&d
->vga
);
1077 qxl_destroy_primary(d
, QXL_SYNC
);
1080 static void qxl_update_irq(PCIQXLDevice
*d
)
1082 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
1083 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
1084 int level
= !!(pending
& mask
);
1085 qemu_set_irq(d
->pci
.irq
[0], level
);
1086 qxl_ring_set_dirty(d
);
1089 static void qxl_check_state(PCIQXLDevice
*d
)
1091 QXLRam
*ram
= d
->ram
;
1092 int spice_display_running
= qemu_spice_display_is_running(&d
->ssd
);
1094 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
1095 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
1098 static void qxl_reset_state(PCIQXLDevice
*d
)
1100 QXLRom
*rom
= d
->rom
;
1103 d
->shadow_rom
.update_id
= cpu_to_le32(0);
1104 *rom
= d
->shadow_rom
;
1105 qxl_rom_set_dirty(d
);
1107 d
->num_free_res
= 0;
1108 d
->last_release
= NULL
;
1109 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
1112 static void qxl_soft_reset(PCIQXLDevice
*d
)
1114 trace_qxl_soft_reset(d
->id
);
1116 qxl_clear_guest_bug(d
);
1117 d
->current_async
= QXL_UNDEFINED_IO
;
1120 qxl_enter_vga_mode(d
);
1122 d
->mode
= QXL_MODE_UNDEFINED
;
1126 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
1128 trace_qxl_hard_reset(d
->id
, loadvm
);
1130 qxl_spice_reset_cursor(d
);
1131 qxl_spice_reset_image_cache(d
);
1132 qxl_reset_surfaces(d
);
1133 qxl_reset_memslots(d
);
1135 /* pre loadvm reset must not touch QXLRam. This lives in
1136 * device memory, is migrated together with RAM and thus
1137 * already loaded at this point */
1141 qemu_spice_create_host_memslot(&d
->ssd
);
1145 static void qxl_reset_handler(DeviceState
*dev
)
1147 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
1149 qxl_hard_reset(d
, 0);
1152 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
1154 VGACommonState
*vga
= opaque
;
1155 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
1157 trace_qxl_io_write_vga(qxl
->id
, qxl_mode_to_string(qxl
->mode
), addr
, val
);
1158 if (qxl
->mode
!= QXL_MODE_VGA
) {
1159 qxl_destroy_primary(qxl
, QXL_SYNC
);
1160 qxl_soft_reset(qxl
);
1162 vga_ioport_write(opaque
, addr
, val
);
1165 static const MemoryRegionPortio qxl_vga_portio_list
[] = {
1166 { 0x04, 2, 1, .read
= vga_ioport_read
,
1167 .write
= qxl_vga_ioport_write
}, /* 3b4 */
1168 { 0x0a, 1, 1, .read
= vga_ioport_read
,
1169 .write
= qxl_vga_ioport_write
}, /* 3ba */
1170 { 0x10, 16, 1, .read
= vga_ioport_read
,
1171 .write
= qxl_vga_ioport_write
}, /* 3c0 */
1172 { 0x24, 2, 1, .read
= vga_ioport_read
,
1173 .write
= qxl_vga_ioport_write
}, /* 3d4 */
1174 { 0x2a, 1, 1, .read
= vga_ioport_read
,
1175 .write
= qxl_vga_ioport_write
}, /* 3da */
1176 PORTIO_END_OF_LIST(),
1179 static int qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
1182 static const int regions
[] = {
1183 QXL_RAM_RANGE_INDEX
,
1184 QXL_VRAM_RANGE_INDEX
,
1185 QXL_VRAM64_RANGE_INDEX
,
1187 uint64_t guest_start
;
1192 intptr_t virt_start
;
1193 QXLDevMemSlot memslot
;
1196 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
1197 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
1199 trace_qxl_memslot_add_guest(d
->id
, slot_id
, guest_start
, guest_end
);
1201 if (slot_id
>= NUM_MEMSLOTS
) {
1202 qxl_set_guest_bug(d
, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__
,
1203 slot_id
, NUM_MEMSLOTS
);
1206 if (guest_start
> guest_end
) {
1207 qxl_set_guest_bug(d
, "%s: guest_start > guest_end 0x%" PRIx64
1208 " > 0x%" PRIx64
, __func__
, guest_start
, guest_end
);
1212 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
1213 pci_region
= regions
[i
];
1214 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
1215 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
1217 if (pci_start
== -1) {
1220 /* start address in range ? */
1221 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
1224 /* end address in range ? */
1225 if (guest_end
> pci_end
) {
1231 if (i
== ARRAY_SIZE(regions
)) {
1232 qxl_set_guest_bug(d
, "%s: finished loop without match", __func__
);
1236 switch (pci_region
) {
1237 case QXL_RAM_RANGE_INDEX
:
1238 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vga
.vram
);
1240 case QXL_VRAM_RANGE_INDEX
:
1241 case 4 /* vram 64bit */:
1242 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vram_bar
);
1245 /* should not happen */
1246 qxl_set_guest_bug(d
, "%s: pci_region = %d", __func__
, pci_region
);
1250 memslot
.slot_id
= slot_id
;
1251 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
1252 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
1253 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
1254 memslot
.addr_delta
= memslot
.virt_start
- delta
;
1255 memslot
.generation
= d
->rom
->slot_generation
= 0;
1256 qxl_rom_set_dirty(d
);
1258 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
1259 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
1260 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
1261 d
->guest_slots
[slot_id
].delta
= delta
;
1262 d
->guest_slots
[slot_id
].active
= 1;
1266 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
1268 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
1269 d
->guest_slots
[slot_id
].active
= 0;
1272 static void qxl_reset_memslots(PCIQXLDevice
*d
)
1274 qxl_spice_reset_memslots(d
);
1275 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
1278 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
1280 trace_qxl_reset_surfaces(d
->id
);
1281 d
->mode
= QXL_MODE_UNDEFINED
;
1282 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
1285 /* can be also called from spice server thread context */
1286 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
1288 uint64_t phys
= le64_to_cpu(pqxl
);
1289 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1290 uint64_t offset
= phys
& 0xffffffffffff;
1293 case MEMSLOT_GROUP_HOST
:
1294 return (void *)(intptr_t)offset
;
1295 case MEMSLOT_GROUP_GUEST
:
1296 if (slot
>= NUM_MEMSLOTS
) {
1297 qxl_set_guest_bug(qxl
, "slot too large %d >= %d", slot
,
1301 if (!qxl
->guest_slots
[slot
].active
) {
1302 qxl_set_guest_bug(qxl
, "inactive slot %d\n", slot
);
1305 if (offset
< qxl
->guest_slots
[slot
].delta
) {
1306 qxl_set_guest_bug(qxl
,
1307 "slot %d offset %"PRIu64
" < delta %"PRIu64
"\n",
1308 slot
, offset
, qxl
->guest_slots
[slot
].delta
);
1311 offset
-= qxl
->guest_slots
[slot
].delta
;
1312 if (offset
> qxl
->guest_slots
[slot
].size
) {
1313 qxl_set_guest_bug(qxl
,
1314 "slot %d offset %"PRIu64
" > size %"PRIu64
"\n",
1315 slot
, offset
, qxl
->guest_slots
[slot
].size
);
1318 return qxl
->guest_slots
[slot
].ptr
+ offset
;
1323 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1325 /* for local rendering */
1326 qxl_render_resize(qxl
);
1329 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1332 QXLDevSurfaceCreate surface
;
1333 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1335 int requested_height
= le32_to_cpu(sc
->height
);
1336 int requested_stride
= le32_to_cpu(sc
->stride
);
1338 size
= abs(requested_stride
) * requested_height
;
1339 if (size
> qxl
->vgamem_size
) {
1340 qxl_set_guest_bug(qxl
, "%s: requested primary larger then framebuffer"
1345 if (qxl
->mode
== QXL_MODE_NATIVE
) {
1346 qxl_set_guest_bug(qxl
, "%s: nop since already in QXL_MODE_NATIVE",
1349 qxl_exit_vga_mode(qxl
);
1351 surface
.format
= le32_to_cpu(sc
->format
);
1352 surface
.height
= le32_to_cpu(sc
->height
);
1353 surface
.mem
= le64_to_cpu(sc
->mem
);
1354 surface
.position
= le32_to_cpu(sc
->position
);
1355 surface
.stride
= le32_to_cpu(sc
->stride
);
1356 surface
.width
= le32_to_cpu(sc
->width
);
1357 surface
.type
= le32_to_cpu(sc
->type
);
1358 surface
.flags
= le32_to_cpu(sc
->flags
);
1359 trace_qxl_create_guest_primary(qxl
->id
, sc
->width
, sc
->height
, sc
->mem
,
1360 sc
->format
, sc
->position
);
1361 trace_qxl_create_guest_primary_rest(qxl
->id
, sc
->stride
, sc
->type
,
1364 if ((surface
.stride
& 0x3) != 0) {
1365 qxl_set_guest_bug(qxl
, "primary surface stride = %d %% 4 != 0",
1370 surface
.mouse_mode
= true;
1371 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1373 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1376 qxl
->mode
= QXL_MODE_NATIVE
;
1378 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1380 if (async
== QXL_SYNC
) {
1381 qxl_create_guest_primary_complete(qxl
);
1385 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1386 * done (in QXL_SYNC case), 0 otherwise. */
1387 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1389 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1392 trace_qxl_destroy_primary(d
->id
);
1393 d
->mode
= QXL_MODE_UNDEFINED
;
1394 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1395 qxl_spice_reset_cursor(d
);
1399 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
1401 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1402 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1403 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1404 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1409 QXLSurfaceCreate surface
= {
1410 .width
= mode
->x_res
,
1411 .height
= mode
->y_res
,
1412 .stride
= -mode
->x_res
* 4,
1413 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1414 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1416 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1419 trace_qxl_set_mode(d
->id
, modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
,
1422 qxl_hard_reset(d
, 0);
1425 d
->guest_slots
[0].slot
= slot
;
1426 assert(qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
) == 0);
1428 d
->guest_primary
.surface
= surface
;
1429 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1431 d
->mode
= QXL_MODE_COMPAT
;
1432 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1433 if (mode
->bits
== 16) {
1434 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1436 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1437 d
->rom
->mode
= cpu_to_le32(modenr
);
1438 qxl_rom_set_dirty(d
);
1441 static void ioport_write(void *opaque
, hwaddr addr
,
1442 uint64_t val
, unsigned size
)
1444 PCIQXLDevice
*d
= opaque
;
1445 uint32_t io_port
= addr
;
1446 qxl_async_io async
= QXL_SYNC
;
1447 uint32_t orig_io_port
= io_port
;
1449 if (d
->guest_bug
&& io_port
!= QXL_IO_RESET
) {
1453 if (d
->revision
<= QXL_REVISION_STABLE_V10
&&
1454 io_port
> QXL_IO_FLUSH_RELEASE
) {
1455 qxl_set_guest_bug(d
, "unsupported io %d for revision %d\n",
1456 io_port
, d
->revision
);
1462 case QXL_IO_SET_MODE
:
1463 case QXL_IO_MEMSLOT_ADD
:
1464 case QXL_IO_MEMSLOT_DEL
:
1465 case QXL_IO_CREATE_PRIMARY
:
1466 case QXL_IO_UPDATE_IRQ
:
1468 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1469 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1472 if (d
->mode
!= QXL_MODE_VGA
) {
1475 trace_qxl_io_unexpected_vga_mode(d
->id
,
1476 addr
, val
, io_port_to_string(io_port
));
1477 /* be nice to buggy guest drivers */
1478 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1479 io_port
< QXL_IO_RANGE_SIZE
) {
1480 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1485 /* we change the io_port to avoid ifdeffery in the main switch */
1486 orig_io_port
= io_port
;
1488 case QXL_IO_UPDATE_AREA_ASYNC
:
1489 io_port
= QXL_IO_UPDATE_AREA
;
1491 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1492 io_port
= QXL_IO_MEMSLOT_ADD
;
1494 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1495 io_port
= QXL_IO_CREATE_PRIMARY
;
1497 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1498 io_port
= QXL_IO_DESTROY_PRIMARY
;
1500 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1501 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1503 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1504 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1506 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1507 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1510 qemu_mutex_lock(&d
->async_lock
);
1511 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1512 qxl_set_guest_bug(d
, "%d async started before last (%d) complete",
1513 io_port
, d
->current_async
);
1514 qemu_mutex_unlock(&d
->async_lock
);
1517 d
->current_async
= orig_io_port
;
1518 qemu_mutex_unlock(&d
->async_lock
);
1523 trace_qxl_io_write(d
->id
, qxl_mode_to_string(d
->mode
), addr
, val
, size
,
1527 case QXL_IO_UPDATE_AREA
:
1529 QXLCookie
*cookie
= NULL
;
1530 QXLRect update
= d
->ram
->update_area
;
1532 if (d
->ram
->update_surface
> d
->ssd
.num_surfaces
) {
1533 qxl_set_guest_bug(d
, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1534 d
->ram
->update_surface
);
1537 if (update
.left
>= update
.right
|| update
.top
>= update
.bottom
||
1538 update
.left
< 0 || update
.top
< 0) {
1539 qxl_set_guest_bug(d
,
1540 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1541 update
.left
, update
.top
, update
.right
, update
.bottom
);
1544 if (async
== QXL_ASYNC
) {
1545 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
1546 QXL_IO_UPDATE_AREA_ASYNC
);
1547 cookie
->u
.area
= update
;
1549 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1550 cookie
? &cookie
->u
.area
: &update
,
1551 NULL
, 0, 0, async
, cookie
);
1554 case QXL_IO_NOTIFY_CMD
:
1555 qemu_spice_wakeup(&d
->ssd
);
1557 case QXL_IO_NOTIFY_CURSOR
:
1558 qemu_spice_wakeup(&d
->ssd
);
1560 case QXL_IO_UPDATE_IRQ
:
1563 case QXL_IO_NOTIFY_OOM
:
1564 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1571 case QXL_IO_SET_MODE
:
1572 qxl_set_mode(d
, val
, 0);
1575 trace_qxl_io_log(d
->id
, d
->ram
->log_buf
);
1576 if (d
->guestdebug
) {
1577 fprintf(stderr
, "qxl/guest-%d: %" PRId64
": %s", d
->id
,
1578 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1582 qxl_hard_reset(d
, 0);
1584 case QXL_IO_MEMSLOT_ADD
:
1585 if (val
>= NUM_MEMSLOTS
) {
1586 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1589 if (d
->guest_slots
[val
].active
) {
1590 qxl_set_guest_bug(d
,
1591 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1594 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1595 qxl_add_memslot(d
, val
, 0, async
);
1597 case QXL_IO_MEMSLOT_DEL
:
1598 if (val
>= NUM_MEMSLOTS
) {
1599 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1602 qxl_del_memslot(d
, val
);
1604 case QXL_IO_CREATE_PRIMARY
:
1606 qxl_set_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1610 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1611 qxl_create_guest_primary(d
, 0, async
);
1613 case QXL_IO_DESTROY_PRIMARY
:
1615 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1619 if (!qxl_destroy_primary(d
, async
)) {
1620 trace_qxl_io_destroy_primary_ignored(d
->id
,
1621 qxl_mode_to_string(d
->mode
));
1625 case QXL_IO_DESTROY_SURFACE_WAIT
:
1626 if (val
>= d
->ssd
.num_surfaces
) {
1627 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1628 "%" PRIu64
" >= NUM_SURFACES", async
, val
);
1631 qxl_spice_destroy_surface_wait(d
, val
, async
);
1633 case QXL_IO_FLUSH_RELEASE
: {
1634 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1635 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1637 "ERROR: no flush, full release ring [p%d,%dc]\n",
1638 ring
->prod
, ring
->cons
);
1640 qxl_push_free_res(d
, 1 /* flush */);
1643 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1644 qxl_spice_flush_surfaces_async(d
);
1646 case QXL_IO_DESTROY_ALL_SURFACES
:
1647 d
->mode
= QXL_MODE_UNDEFINED
;
1648 qxl_spice_destroy_surfaces(d
, async
);
1650 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1651 qxl_spice_monitors_config_async(d
, 0);
1654 qxl_set_guest_bug(d
, "%s: unexpected ioport=0x%x\n", __func__
, io_port
);
1659 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1660 qemu_mutex_lock(&d
->async_lock
);
1661 d
->current_async
= QXL_UNDEFINED_IO
;
1662 qemu_mutex_unlock(&d
->async_lock
);
1666 static uint64_t ioport_read(void *opaque
, hwaddr addr
,
1669 PCIQXLDevice
*qxl
= opaque
;
1671 trace_qxl_io_read_unexpected(qxl
->id
);
1675 static const MemoryRegionOps qxl_io_ops
= {
1676 .read
= ioport_read
,
1677 .write
= ioport_write
,
1679 .min_access_size
= 1,
1680 .max_access_size
= 1,
1684 static void pipe_read(void *opaque
)
1686 PCIQXLDevice
*d
= opaque
;
1691 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1692 } while (len
== sizeof(dummy
));
1696 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1698 uint32_t old_pending
;
1699 uint32_t le_events
= cpu_to_le32(events
);
1701 trace_qxl_send_events(d
->id
, events
);
1702 if (!qemu_spice_display_is_running(&d
->ssd
)) {
1703 /* spice-server tracks guest running state and should not do this */
1704 fprintf(stderr
, "%s: spice-server bug: guest stopped, ignoring\n",
1706 trace_qxl_send_events_vm_stopped(d
->id
, events
);
1709 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1710 if ((old_pending
& le_events
) == le_events
) {
1713 if (qemu_thread_is_self(&d
->main
)) {
1716 if (write(d
->pipe
[1], d
, 1) != 1) {
1717 dprint(d
, 1, "%s: write to pipe failed\n", __func__
);
1722 static void init_pipe_signaling(PCIQXLDevice
*d
)
1724 if (pipe(d
->pipe
) < 0) {
1725 fprintf(stderr
, "%s:%s: qxl pipe creation failed\n",
1726 __FILE__
, __func__
);
1729 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1730 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1731 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1733 qemu_thread_get_self(&d
->main
);
1734 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1737 /* graphics console */
1739 static void qxl_hw_update(void *opaque
)
1741 PCIQXLDevice
*qxl
= opaque
;
1742 VGACommonState
*vga
= &qxl
->vga
;
1744 switch (qxl
->mode
) {
1748 case QXL_MODE_COMPAT
:
1749 case QXL_MODE_NATIVE
:
1750 qxl_render_update(qxl
);
1757 static void qxl_hw_invalidate(void *opaque
)
1759 PCIQXLDevice
*qxl
= opaque
;
1760 VGACommonState
*vga
= &qxl
->vga
;
1762 vga
->invalidate(vga
);
1765 static void qxl_hw_screen_dump(void *opaque
, const char *filename
, bool cswitch
,
1768 PCIQXLDevice
*qxl
= opaque
;
1769 VGACommonState
*vga
= &qxl
->vga
;
1771 switch (qxl
->mode
) {
1772 case QXL_MODE_COMPAT
:
1773 case QXL_MODE_NATIVE
:
1774 qxl_render_update(qxl
);
1775 ppm_save(filename
, qxl
->ssd
.ds
->surface
, errp
);
1778 vga
->screen_dump(vga
, filename
, cswitch
, errp
);
1785 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1787 PCIQXLDevice
*qxl
= opaque
;
1788 VGACommonState
*vga
= &qxl
->vga
;
1790 if (qxl
->mode
== QXL_MODE_VGA
) {
1791 vga
->text_update(vga
, chardata
);
1796 static void qxl_dirty_surfaces(PCIQXLDevice
*qxl
)
1798 uintptr_t vram_start
;
1801 if (qxl
->mode
!= QXL_MODE_NATIVE
&& qxl
->mode
!= QXL_MODE_COMPAT
) {
1805 /* dirty the primary surface */
1806 qxl_set_dirty(&qxl
->vga
.vram
, qxl
->shadow_rom
.draw_area_offset
,
1807 qxl
->shadow_rom
.surface0_area_size
);
1809 vram_start
= (uintptr_t)memory_region_get_ram_ptr(&qxl
->vram_bar
);
1811 /* dirty the off-screen surfaces */
1812 for (i
= 0; i
< qxl
->ssd
.num_surfaces
; i
++) {
1814 intptr_t surface_offset
;
1817 if (qxl
->guest_surfaces
.cmds
[i
] == 0) {
1821 cmd
= qxl_phys2virt(qxl
, qxl
->guest_surfaces
.cmds
[i
],
1822 MEMSLOT_GROUP_GUEST
);
1824 assert(cmd
->type
== QXL_SURFACE_CMD_CREATE
);
1825 surface_offset
= (intptr_t)qxl_phys2virt(qxl
,
1826 cmd
->u
.surface_create
.data
,
1827 MEMSLOT_GROUP_GUEST
);
1828 assert(surface_offset
);
1829 surface_offset
-= vram_start
;
1830 surface_size
= cmd
->u
.surface_create
.height
*
1831 abs(cmd
->u
.surface_create
.stride
);
1832 trace_qxl_surfaces_dirty(qxl
->id
, i
, (int)surface_offset
, surface_size
);
1833 qxl_set_dirty(&qxl
->vram_bar
, surface_offset
, surface_size
);
1837 static void qxl_vm_change_state_handler(void *opaque
, int running
,
1840 PCIQXLDevice
*qxl
= opaque
;
1844 * if qxl_send_events was called from spice server context before
1845 * migration ended, qxl_update_irq for these events might not have been
1848 qxl_update_irq(qxl
);
1850 /* make sure surfaces are saved before migration */
1851 qxl_dirty_surfaces(qxl
);
1855 /* display change listener */
1857 static void display_update(struct DisplayState
*ds
, int x
, int y
, int w
, int h
)
1859 if (qxl0
->mode
== QXL_MODE_VGA
) {
1860 qemu_spice_display_update(&qxl0
->ssd
, x
, y
, w
, h
);
1864 static void display_resize(struct DisplayState
*ds
)
1866 if (qxl0
->mode
== QXL_MODE_VGA
) {
1867 qemu_spice_display_resize(&qxl0
->ssd
);
1871 static void display_refresh(struct DisplayState
*ds
)
1873 if (qxl0
->mode
== QXL_MODE_VGA
) {
1874 qemu_spice_display_refresh(&qxl0
->ssd
);
1876 qemu_mutex_lock(&qxl0
->ssd
.lock
);
1877 qemu_spice_cursor_refresh_unlocked(&qxl0
->ssd
);
1878 qemu_mutex_unlock(&qxl0
->ssd
.lock
);
1882 static DisplayChangeListener display_listener
= {
1883 .dpy_gfx_update
= display_update
,
1884 .dpy_gfx_resize
= display_resize
,
1885 .dpy_refresh
= display_refresh
,
1888 static void qxl_init_ramsize(PCIQXLDevice
*qxl
)
1890 /* vga mode framebuffer / primary surface (bar 0, first part) */
1891 if (qxl
->vgamem_size_mb
< 8) {
1892 qxl
->vgamem_size_mb
= 8;
1894 qxl
->vgamem_size
= qxl
->vgamem_size_mb
* 1024 * 1024;
1896 /* vga ram (bar 0, total) */
1897 if (qxl
->ram_size_mb
!= -1) {
1898 qxl
->vga
.vram_size
= qxl
->ram_size_mb
* 1024 * 1024;
1900 if (qxl
->vga
.vram_size
< qxl
->vgamem_size
* 2) {
1901 qxl
->vga
.vram_size
= qxl
->vgamem_size
* 2;
1904 /* vram32 (surfaces, 32bit, bar 1) */
1905 if (qxl
->vram32_size_mb
!= -1) {
1906 qxl
->vram32_size
= qxl
->vram32_size_mb
* 1024 * 1024;
1908 if (qxl
->vram32_size
< 4096) {
1909 qxl
->vram32_size
= 4096;
1912 /* vram (surfaces, 64bit, bar 4+5) */
1913 if (qxl
->vram_size_mb
!= -1) {
1914 qxl
->vram_size
= qxl
->vram_size_mb
* 1024 * 1024;
1916 if (qxl
->vram_size
< qxl
->vram32_size
) {
1917 qxl
->vram_size
= qxl
->vram32_size
;
1920 if (qxl
->revision
== 1) {
1921 qxl
->vram32_size
= 4096;
1922 qxl
->vram_size
= 4096;
1924 qxl
->vgamem_size
= msb_mask(qxl
->vgamem_size
* 2 - 1);
1925 qxl
->vga
.vram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1926 qxl
->vram32_size
= msb_mask(qxl
->vram32_size
* 2 - 1);
1927 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1930 static int qxl_init_common(PCIQXLDevice
*qxl
)
1932 uint8_t* config
= qxl
->pci
.config
;
1933 uint32_t pci_device_rev
;
1936 qxl
->mode
= QXL_MODE_UNDEFINED
;
1937 qxl
->generation
= 1;
1938 qxl
->num_memslots
= NUM_MEMSLOTS
;
1939 qemu_mutex_init(&qxl
->track_lock
);
1940 qemu_mutex_init(&qxl
->async_lock
);
1941 qxl
->current_async
= QXL_UNDEFINED_IO
;
1944 switch (qxl
->revision
) {
1945 case 1: /* spice 0.4 -- qxl-1 */
1946 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1949 case 2: /* spice 0.6 -- qxl-2 */
1950 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1954 pci_device_rev
= QXL_REVISION_STABLE_V10
;
1955 io_size
= 32; /* PCI region size must be pow2 */
1958 pci_device_rev
= QXL_REVISION_STABLE_V12
;
1959 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1962 error_report("Invalid revision %d for qxl device (max %d)",
1963 qxl
->revision
, QXL_DEFAULT_REVISION
);
1967 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1968 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1970 qxl
->rom_size
= qxl_rom_size();
1971 memory_region_init_ram(&qxl
->rom_bar
, "qxl.vrom", qxl
->rom_size
);
1972 vmstate_register_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
);
1976 qxl
->guest_surfaces
.cmds
= g_new0(QXLPHYSICAL
, qxl
->ssd
.num_surfaces
);
1977 memory_region_init_ram(&qxl
->vram_bar
, "qxl.vram", qxl
->vram_size
);
1978 vmstate_register_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
);
1979 memory_region_init_alias(&qxl
->vram32_bar
, "qxl.vram32", &qxl
->vram_bar
,
1980 0, qxl
->vram32_size
);
1982 memory_region_init_io(&qxl
->io_bar
, &qxl_io_ops
, qxl
,
1983 "qxl-ioports", io_size
);
1985 vga_dirty_log_start(&qxl
->vga
);
1987 memory_region_set_flush_coalesced(&qxl
->io_bar
);
1990 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
1991 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
1993 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
1994 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
1996 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
1997 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
1999 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
2000 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram32_bar
);
2002 if (qxl
->vram32_size
< qxl
->vram_size
) {
2004 * Make the 64bit vram bar show up only in case it is
2005 * configured to be larger than the 32bit vram bar.
2007 pci_register_bar(&qxl
->pci
, QXL_VRAM64_RANGE_INDEX
,
2008 PCI_BASE_ADDRESS_SPACE_MEMORY
|
2009 PCI_BASE_ADDRESS_MEM_TYPE_64
|
2010 PCI_BASE_ADDRESS_MEM_PREFETCH
,
2014 /* print pci bar details */
2015 dprint(qxl
, 1, "ram/%s: %d MB [region 0]\n",
2016 qxl
->id
== 0 ? "pri" : "sec",
2017 qxl
->vga
.vram_size
/ (1024*1024));
2018 dprint(qxl
, 1, "vram/32: %d MB [region 1]\n",
2019 qxl
->vram32_size
/ (1024*1024));
2020 dprint(qxl
, 1, "vram/64: %d MB %s\n",
2021 qxl
->vram_size
/ (1024*1024),
2022 qxl
->vram32_size
< qxl
->vram_size
? "[region 4]" : "[unmapped]");
2024 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
2025 qxl
->ssd
.qxl
.id
= qxl
->id
;
2026 if (qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
) != 0) {
2027 error_report("qxl interface %d.%d not supported by spice-server\n",
2028 SPICE_INTERFACE_QXL_MAJOR
, SPICE_INTERFACE_QXL_MINOR
);
2031 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
2033 init_pipe_signaling(qxl
);
2034 qxl_reset_state(qxl
);
2036 qxl
->update_area_bh
= qemu_bh_new(qxl_render_update_area_bh
, qxl
);
2041 static int qxl_init_primary(PCIDevice
*dev
)
2043 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
2044 VGACommonState
*vga
= &qxl
->vga
;
2045 PortioList
*qxl_vga_port_list
= g_new(PortioList
, 1);
2049 qxl_init_ramsize(qxl
);
2050 vga
->vram_size_mb
= qxl
->vga
.vram_size
>> 20;
2051 vga_common_init(vga
);
2052 vga_init(vga
, pci_address_space(dev
), pci_address_space_io(dev
), false);
2053 portio_list_init(qxl_vga_port_list
, qxl_vga_portio_list
, vga
, "vga");
2054 portio_list_add(qxl_vga_port_list
, pci_address_space_io(dev
), 0x3b0);
2056 vga
->ds
= graphic_console_init(qxl_hw_update
, qxl_hw_invalidate
,
2057 qxl_hw_screen_dump
, qxl_hw_text_update
, qxl
);
2058 qemu_spice_display_init_common(&qxl
->ssd
, vga
->ds
);
2062 rc
= qxl_init_common(qxl
);
2067 register_displaychangelistener(vga
->ds
, &display_listener
);
2071 static int qxl_init_secondary(PCIDevice
*dev
)
2073 static int device_id
= 1;
2074 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
2076 qxl
->id
= device_id
++;
2077 qxl_init_ramsize(qxl
);
2078 memory_region_init_ram(&qxl
->vga
.vram
, "qxl.vgavram", qxl
->vga
.vram_size
);
2079 vmstate_register_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
);
2080 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
2082 return qxl_init_common(qxl
);
2085 static void qxl_pre_save(void *opaque
)
2087 PCIQXLDevice
* d
= opaque
;
2088 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2090 trace_qxl_pre_save(d
->id
);
2091 if (d
->last_release
== NULL
) {
2092 d
->last_release_offset
= 0;
2094 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
2096 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2099 static int qxl_pre_load(void *opaque
)
2101 PCIQXLDevice
* d
= opaque
;
2103 trace_qxl_pre_load(d
->id
);
2104 qxl_hard_reset(d
, 1);
2105 qxl_exit_vga_mode(d
);
2109 static void qxl_create_memslots(PCIQXLDevice
*d
)
2113 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
2114 if (!d
->guest_slots
[i
].active
) {
2117 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
2121 static int qxl_post_load(void *opaque
, int version
)
2123 PCIQXLDevice
* d
= opaque
;
2124 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2125 QXLCommandExt
*cmds
;
2126 int in
, out
, newmode
;
2128 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2129 if (d
->last_release_offset
== 0) {
2130 d
->last_release
= NULL
;
2132 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
2135 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
2137 trace_qxl_post_load(d
->id
, qxl_mode_to_string(d
->mode
));
2139 d
->mode
= QXL_MODE_UNDEFINED
;
2142 case QXL_MODE_UNDEFINED
:
2143 qxl_create_memslots(d
);
2146 qxl_create_memslots(d
);
2147 qxl_enter_vga_mode(d
);
2149 case QXL_MODE_NATIVE
:
2150 qxl_create_memslots(d
);
2151 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
2153 /* replay surface-create and cursor-set commands */
2154 cmds
= g_malloc0(sizeof(QXLCommandExt
) * (d
->ssd
.num_surfaces
+ 1));
2155 for (in
= 0, out
= 0; in
< d
->ssd
.num_surfaces
; in
++) {
2156 if (d
->guest_surfaces
.cmds
[in
] == 0) {
2159 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
2160 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
2161 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2164 if (d
->guest_cursor
) {
2165 cmds
[out
].cmd
.data
= d
->guest_cursor
;
2166 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
2167 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2170 qxl_spice_loadvm_commands(d
, cmds
, out
);
2172 if (d
->guest_monitors_config
) {
2173 qxl_spice_monitors_config_async(d
, 1);
2176 case QXL_MODE_COMPAT
:
2177 /* note: no need to call qxl_create_memslots, qxl_set_mode
2178 * creates the mem slot. */
2179 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
2185 #define QXL_SAVE_VERSION 21
2187 static bool qxl_monitors_config_needed(void *opaque
)
2189 PCIQXLDevice
*qxl
= opaque
;
2191 return qxl
->guest_monitors_config
!= 0;
2195 static VMStateDescription qxl_memslot
= {
2196 .name
= "qxl-memslot",
2197 .version_id
= QXL_SAVE_VERSION
,
2198 .minimum_version_id
= QXL_SAVE_VERSION
,
2199 .fields
= (VMStateField
[]) {
2200 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
2201 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
2202 VMSTATE_UINT32(active
, struct guest_slots
),
2203 VMSTATE_END_OF_LIST()
2207 static VMStateDescription qxl_surface
= {
2208 .name
= "qxl-surface",
2209 .version_id
= QXL_SAVE_VERSION
,
2210 .minimum_version_id
= QXL_SAVE_VERSION
,
2211 .fields
= (VMStateField
[]) {
2212 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
2213 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
2214 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
2215 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
2216 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
2217 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
2218 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
2219 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
2220 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
2221 VMSTATE_END_OF_LIST()
2225 static VMStateDescription qxl_vmstate_monitors_config
= {
2226 .name
= "qxl/monitors-config",
2228 .minimum_version_id
= 1,
2229 .fields
= (VMStateField
[]) {
2230 VMSTATE_UINT64(guest_monitors_config
, PCIQXLDevice
),
2231 VMSTATE_END_OF_LIST()
2235 static VMStateDescription qxl_vmstate
= {
2237 .version_id
= QXL_SAVE_VERSION
,
2238 .minimum_version_id
= QXL_SAVE_VERSION
,
2239 .pre_save
= qxl_pre_save
,
2240 .pre_load
= qxl_pre_load
,
2241 .post_load
= qxl_post_load
,
2242 .fields
= (VMStateField
[]) {
2243 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
2244 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
2245 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
2246 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
2247 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
2248 VMSTATE_UINT32(mode
, PCIQXLDevice
),
2249 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
2250 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
2251 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
2252 qxl_memslot
, struct guest_slots
),
2253 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
2254 qxl_surface
, QXLSurfaceCreate
),
2255 VMSTATE_INT32_EQUAL(ssd
.num_surfaces
, PCIQXLDevice
),
2256 VMSTATE_VARRAY_INT32(guest_surfaces
.cmds
, PCIQXLDevice
,
2257 ssd
.num_surfaces
, 0,
2258 vmstate_info_uint64
, uint64_t),
2259 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
2260 VMSTATE_END_OF_LIST()
2262 .subsections
= (VMStateSubsection
[]) {
2264 .vmsd
= &qxl_vmstate_monitors_config
,
2265 .needed
= qxl_monitors_config_needed
,
2272 static Property qxl_properties
[] = {
2273 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
2275 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram32_size
,
2277 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
2278 QXL_DEFAULT_REVISION
),
2279 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
2280 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
2281 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
2282 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice
, ram_size_mb
, -1),
2283 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice
, vram32_size_mb
, -1),
2284 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice
, vram_size_mb
, -1),
2285 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice
, vgamem_size_mb
, 16),
2286 DEFINE_PROP_INT32("surfaces", PCIQXLDevice
, ssd
.num_surfaces
, 1024),
2287 DEFINE_PROP_END_OF_LIST(),
2290 static void qxl_primary_class_init(ObjectClass
*klass
, void *data
)
2292 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2293 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2296 k
->init
= qxl_init_primary
;
2297 k
->romfile
= "vgabios-qxl.bin";
2298 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2299 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2300 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
2301 dc
->desc
= "Spice QXL GPU (primary, vga compatible)";
2302 dc
->reset
= qxl_reset_handler
;
2303 dc
->vmsd
= &qxl_vmstate
;
2304 dc
->props
= qxl_properties
;
2307 static const TypeInfo qxl_primary_info
= {
2309 .parent
= TYPE_PCI_DEVICE
,
2310 .instance_size
= sizeof(PCIQXLDevice
),
2311 .class_init
= qxl_primary_class_init
,
2314 static void qxl_secondary_class_init(ObjectClass
*klass
, void *data
)
2316 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2317 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2319 k
->init
= qxl_init_secondary
;
2320 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2321 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2322 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
2323 dc
->desc
= "Spice QXL GPU (secondary)";
2324 dc
->reset
= qxl_reset_handler
;
2325 dc
->vmsd
= &qxl_vmstate
;
2326 dc
->props
= qxl_properties
;
2329 static const TypeInfo qxl_secondary_info
= {
2331 .parent
= TYPE_PCI_DEVICE
,
2332 .instance_size
= sizeof(PCIQXLDevice
),
2333 .class_init
= qxl_secondary_class_init
,
2336 static void qxl_register_types(void)
2338 type_register_static(&qxl_primary_info
);
2339 type_register_static(&qxl_secondary_info
);
2342 type_init(qxl_register_types
)