hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "prep_pci.h"
  33 #include "usb-ohci.h"
  34 #include "ppc.h"
  35 #include "boards.h"
  36 #include "qemu-log.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "mc146818rtc.h"
  40
  41 //#define HARD_DEBUG_PPC_IO
  42 //#define DEBUG_PPC_IO
  43
  44 /* SMP is not enabled, for now */
  45 #define MAX_CPUS 1
  46
  47 #define MAX_IDE_BUS 2
  48
  49 #define BIOS_SIZE (1024 * 1024)
  50 #define BIOS_FILENAME "ppc_rom.bin"
  51 #define KERNEL_LOAD_ADDR 0x01000000
  52 #define INITRD_LOAD_ADDR 0x01800000
  53
  54 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  55 #define DEBUG_PPC_IO
  56 #endif
  57
  58 #if defined (HARD_DEBUG_PPC_IO)
  59 #define PPC_IO_DPRINTF(fmt, ...)                         \
  60 do {                                                     \
  61     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  62         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  63     } else {                                             \
  64         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  65     }                                                    \
  66 } while (0)
  67 #elif defined (DEBUG_PPC_IO)
  68 #define PPC_IO_DPRINTF(fmt, ...) \
  69 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  70 #else
  71 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  72 #endif
  73
  74 /* Constants for devices init */
  75 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  76 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  77 static const int ide_irq[2] = { 13, 13 };
  78
  79 #define NE2000_NB_MAX 6
  80
  81 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  82 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  83
  84 //static PITState *pit;
  85
  86 /* ISA IO ports bridge */
  87 #define PPC_IO_BASE 0x80000000
  88
  89 #if 0
  90 /* Speaker port 0x61 */
  91 static int speaker_data_on;
  92 static int dummy_refresh_clock;
  93 #endif
  94
  95 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  96 {
  97 #if 0
  98     speaker_data_on = (val >> 1) & 1;
  99     pit_set_gate(pit, 2, val & 1);
 100 #endif
 101 }
 102
 103 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
 104 {
 105 #if 0
 106     int out;
 107     out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
 108     dummy_refresh_clock ^= 1;
 109     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
 110         (dummy_refresh_clock << 4);
 111 #endif
 112     return 0;
 113 }
 114
 115 /* PCI intack register */
 116 /* Read-only register (?) */
 117 static void _PPC_intack_write (void *opaque,
 118                                target_phys_addr_t addr, uint32_t value)
 119 {
 120 #if 0
 121     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 122            value);
 123 #endif
 124 }
 125
 126 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
 127 {
 128     uint32_t retval = 0;
 129
 130     if ((addr & 0xf) == 0)
 131         retval = pic_intack_read(isa_pic);
 132 #if 0
 133     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 134            retval);
 135 #endif
 136
 137     return retval;
 138 }
 139
 140 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 141 {
 142     return _PPC_intack_read(addr);
 143 }
 144
 145 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 146 {
 147 #ifdef TARGET_WORDS_BIGENDIAN
 148     return bswap16(_PPC_intack_read(addr));
 149 #else
 150     return _PPC_intack_read(addr);
 151 #endif
 152 }
 153
 154 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 155 {
 156 #ifdef TARGET_WORDS_BIGENDIAN
 157     return bswap32(_PPC_intack_read(addr));
 158 #else
 159     return _PPC_intack_read(addr);
 160 #endif
 161 }
 162
 163 static CPUWriteMemoryFunc * const PPC_intack_write[] = {
 164     &_PPC_intack_write,
 165     &_PPC_intack_write,
 166     &_PPC_intack_write,
 167 };
 168
 169 static CPUReadMemoryFunc * const PPC_intack_read[] = {
 170     &PPC_intack_readb,
 171     &PPC_intack_readw,
 172     &PPC_intack_readl,
 173 };
 174
 175 /* PowerPC control and status registers */
 176 #if 0 // Not used
 177 static struct {
 178     /* IDs */
 179     uint32_t veni_devi;
 180     uint32_t revi;
 181     /* Control and status */
 182     uint32_t gcsr;
 183     uint32_t xcfr;
 184     uint32_t ct32;
 185     uint32_t mcsr;
 186     /* General purpose registers */
 187     uint32_t gprg[6];
 188     /* Exceptions */
 189     uint32_t feen;
 190     uint32_t fest;
 191     uint32_t fema;
 192     uint32_t fecl;
 193     uint32_t eeen;
 194     uint32_t eest;
 195     uint32_t eecl;
 196     uint32_t eeint;
 197     uint32_t eemck0;
 198     uint32_t eemck1;
 199     /* Error diagnostic */
 200 } XCSR;
 201
 202 static void PPC_XCSR_writeb (void *opaque,
 203                              target_phys_addr_t addr, uint32_t value)
 204 {
 205     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 206            value);
 207 }
 208
 209 static void PPC_XCSR_writew (void *opaque,
 210                              target_phys_addr_t addr, uint32_t value)
 211 {
 212 #ifdef TARGET_WORDS_BIGENDIAN
 213     value = bswap16(value);
 214 #endif
 215     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 216            value);
 217 }
 218
 219 static void PPC_XCSR_writel (void *opaque,
 220                              target_phys_addr_t addr, uint32_t value)
 221 {
 222 #ifdef TARGET_WORDS_BIGENDIAN
 223     value = bswap32(value);
 224 #endif
 225     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 226            value);
 227 }
 228
 229 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 230 {
 231     uint32_t retval = 0;
 232
 233     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 234            retval);
 235
 236     return retval;
 237 }
 238
 239 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 240 {
 241     uint32_t retval = 0;
 242
 243     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 244            retval);
 245 #ifdef TARGET_WORDS_BIGENDIAN
 246     retval = bswap16(retval);
 247 #endif
 248
 249     return retval;
 250 }
 251
 252 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 253 {
 254     uint32_t retval = 0;
 255
 256     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 257            retval);
 258 #ifdef TARGET_WORDS_BIGENDIAN
 259     retval = bswap32(retval);
 260 #endif
 261
 262     return retval;
 263 }
 264
 265 static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
 266     &PPC_XCSR_writeb,
 267     &PPC_XCSR_writew,
 268     &PPC_XCSR_writel,
 269 };
 270
 271 static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
 272     &PPC_XCSR_readb,
 273     &PPC_XCSR_readw,
 274     &PPC_XCSR_readl,
 275 };
 276 #endif
 277
 278 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 279 typedef struct sysctrl_t {
 280     qemu_irq reset_irq;
 281     M48t59State *nvram;
 282     uint8_t state;
 283     uint8_t syscontrol;
 284     uint8_t fake_io[2];
 285     int contiguous_map;
 286     int endian;
 287 } sysctrl_t;
 288
 289 enum {
 290     STATE_HARDFILE = 0x01,
 291 };
 292
 293 static sysctrl_t *sysctrl;
 294
 295 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 296 {
 297     sysctrl_t *sysctrl = opaque;
 298
 299     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 300                    val);
 301     sysctrl->fake_io[addr - 0x0398] = val;
 302 }
 303
 304 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 305 {
 306     sysctrl_t *sysctrl = opaque;
 307
 308     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 309                    sysctrl->fake_io[addr - 0x0398]);
 310     return sysctrl->fake_io[addr - 0x0398];
 311 }
 312
 313 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 314 {
 315     sysctrl_t *sysctrl = opaque;
 316
 317     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 318                    addr - PPC_IO_BASE, val);
 319     switch (addr) {
 320     case 0x0092:
 321         /* Special port 92 */
 322         /* Check soft reset asked */
 323         if (val & 0x01) {
 324             qemu_irq_raise(sysctrl->reset_irq);
 325         } else {
 326             qemu_irq_lower(sysctrl->reset_irq);
 327         }
 328         /* Check LE mode */
 329         if (val & 0x02) {
 330             sysctrl->endian = 1;
 331         } else {
 332             sysctrl->endian = 0;
 333         }
 334         break;
 335     case 0x0800:
 336         /* Motorola CPU configuration register : read-only */
 337         break;
 338     case 0x0802:
 339         /* Motorola base module feature register : read-only */
 340         break;
 341     case 0x0803:
 342         /* Motorola base module status register : read-only */
 343         break;
 344     case 0x0808:
 345         /* Hardfile light register */
 346         if (val & 1)
 347             sysctrl->state |= STATE_HARDFILE;
 348         else
 349             sysctrl->state &= ~STATE_HARDFILE;
 350         break;
 351     case 0x0810:
 352         /* Password protect 1 register */
 353         if (sysctrl->nvram != NULL)
 354             m48t59_toggle_lock(sysctrl->nvram, 1);
 355         break;
 356     case 0x0812:
 357         /* Password protect 2 register */
 358         if (sysctrl->nvram != NULL)
 359             m48t59_toggle_lock(sysctrl->nvram, 2);
 360         break;
 361     case 0x0814:
 362         /* L2 invalidate register */
 363         //        tlb_flush(first_cpu, 1);
 364         break;
 365     case 0x081C:
 366         /* system control register */
 367         sysctrl->syscontrol = val & 0x0F;
 368         break;
 369     case 0x0850:
 370         /* I/O map type register */
 371         sysctrl->contiguous_map = val & 0x01;
 372         break;
 373     default:
 374         printf("ERROR: unaffected IO port write: %04" PRIx32
 375                " => %02" PRIx32"\n", addr, val);
 376         break;
 377     }
 378 }
 379
 380 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 381 {
 382     sysctrl_t *sysctrl = opaque;
 383     uint32_t retval = 0xFF;
 384
 385     switch (addr) {
 386     case 0x0092:
 387         /* Special port 92 */
 388         retval = 0x00;
 389         break;
 390     case 0x0800:
 391         /* Motorola CPU configuration register */
 392         retval = 0xEF; /* MPC750 */
 393         break;
 394     case 0x0802:
 395         /* Motorola Base module feature register */
 396         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 397         break;
 398     case 0x0803:
 399         /* Motorola base module status register */
 400         retval = 0xE0; /* Standard MPC750 */
 401         break;
 402     case 0x080C:
 403         /* Equipment present register:
 404          *  no L2 cache
 405          *  no upgrade processor
 406          *  no cards in PCI slots
 407          *  SCSI fuse is bad
 408          */
 409         retval = 0x3C;
 410         break;
 411     case 0x0810:
 412         /* Motorola base module extended feature register */
 413         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 414         break;
 415     case 0x0814:
 416         /* L2 invalidate: don't care */
 417         break;
 418     case 0x0818:
 419         /* Keylock */
 420         retval = 0x00;
 421         break;
 422     case 0x081C:
 423         /* system control register
 424          * 7 - 6 / 1 - 0: L2 cache enable
 425          */
 426         retval = sysctrl->syscontrol;
 427         break;
 428     case 0x0823:
 429         /* */
 430         retval = 0x03; /* no L2 cache */
 431         break;
 432     case 0x0850:
 433         /* I/O map type register */
 434         retval = sysctrl->contiguous_map;
 435         break;
 436     default:
 437         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 438         break;
 439     }
 440     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 441                    addr - PPC_IO_BASE, retval);
 442
 443     return retval;
 444 }
 445
 446 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 447                                                  target_phys_addr_t addr)
 448 {
 449     if (sysctrl->contiguous_map == 0) {
 450         /* 64 KB contiguous space for IOs */
 451         addr &= 0xFFFF;
 452     } else {
 453         /* 8 MB non-contiguous space for IOs */
 454         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 455     }
 456
 457     return addr;
 458 }
 459
 460 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 461                                 uint32_t value)
 462 {
 463     sysctrl_t *sysctrl = opaque;
 464
 465     addr = prep_IO_address(sysctrl, addr);
 466     cpu_outb(addr, value);
 467 }
 468
 469 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 470 {
 471     sysctrl_t *sysctrl = opaque;
 472     uint32_t ret;
 473
 474     addr = prep_IO_address(sysctrl, addr);
 475     ret = cpu_inb(addr);
 476
 477     return ret;
 478 }
 479
 480 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 481                                 uint32_t value)
 482 {
 483     sysctrl_t *sysctrl = opaque;
 484
 485     addr = prep_IO_address(sysctrl, addr);
 486 #ifdef TARGET_WORDS_BIGENDIAN
 487     value = bswap16(value);
 488 #endif
 489     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 490     cpu_outw(addr, value);
 491 }
 492
 493 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 494 {
 495     sysctrl_t *sysctrl = opaque;
 496     uint32_t ret;
 497
 498     addr = prep_IO_address(sysctrl, addr);
 499     ret = cpu_inw(addr);
 500 #ifdef TARGET_WORDS_BIGENDIAN
 501     ret = bswap16(ret);
 502 #endif
 503     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 504
 505     return ret;
 506 }
 507
 508 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 509                                 uint32_t value)
 510 {
 511     sysctrl_t *sysctrl = opaque;
 512
 513     addr = prep_IO_address(sysctrl, addr);
 514 #ifdef TARGET_WORDS_BIGENDIAN
 515     value = bswap32(value);
 516 #endif
 517     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 518     cpu_outl(addr, value);
 519 }
 520
 521 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 522 {
 523     sysctrl_t *sysctrl = opaque;
 524     uint32_t ret;
 525
 526     addr = prep_IO_address(sysctrl, addr);
 527     ret = cpu_inl(addr);
 528 #ifdef TARGET_WORDS_BIGENDIAN
 529     ret = bswap32(ret);
 530 #endif
 531     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 532
 533     return ret;
 534 }
 535
 536 static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
 537     &PPC_prep_io_writeb,
 538     &PPC_prep_io_writew,
 539     &PPC_prep_io_writel,
 540 };
 541
 542 static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
 543     &PPC_prep_io_readb,
 544     &PPC_prep_io_readw,
 545     &PPC_prep_io_readl,
 546 };
 547
 548 #define NVRAM_SIZE        0x2000
 549
 550 static void cpu_request_exit(void *opaque, int irq, int level)
 551 {
 552     CPUState *env = cpu_single_env;
 553
 554     if (env && level) {
 555         cpu_exit(env);
 556     }
 557 }
 558
 559 /* PowerPC PREP hardware initialisation */
 560 static void ppc_prep_init (ram_addr_t ram_size,
 561                            const char *boot_device,
 562                            const char *kernel_filename,
 563                            const char *kernel_cmdline,
 564                            const char *initrd_filename,
 565                            const char *cpu_model)
 566 {
 567     CPUState *env = NULL, *envs[MAX_CPUS];
 568     char *filename;
 569     nvram_t nvram;
 570     M48t59State *m48t59;
 571     int PPC_io_memory;
 572     int linux_boot, i, nb_nics1, bios_size;
 573     ram_addr_t ram_offset, bios_offset;
 574     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 575     PCIBus *pci_bus;
 576     qemu_irq *i8259;
 577     qemu_irq *cpu_exit_irq;
 578     int ppc_boot_device;
 579     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 580     DriveInfo *fd[MAX_FD];
 581
 582     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 583
 584     linux_boot = (kernel_filename != NULL);
 585
 586     /* init CPUs */
 587     if (cpu_model == NULL)
 588         cpu_model = "602";
 589     for (i = 0; i < smp_cpus; i++) {
 590         env = cpu_init(cpu_model);
 591         if (!env) {
 592             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 593             exit(1);
 594         }
 595         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 596             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 597             cpu_ppc_tb_init(env, 7812500UL);
 598         } else {
 599             /* Set time-base frequency to 100 Mhz */
 600             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 601         }
 602         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 603         envs[i] = env;
 604     }
 605
 606     /* allocate RAM */
 607     ram_offset = qemu_ram_alloc(ram_size);
 608     cpu_register_physical_memory(0, ram_size, ram_offset);
 609
 610     /* allocate and load BIOS */
 611     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 612     if (bios_name == NULL)
 613         bios_name = BIOS_FILENAME;
 614     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 615     if (filename) {
 616         bios_size = get_image_size(filename);
 617     } else {
 618         bios_size = -1;
 619     }
 620     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 621         target_phys_addr_t bios_addr;
 622         bios_size = (bios_size + 0xfff) & ~0xfff;
 623         bios_addr = (uint32_t)(-bios_size);
 624         cpu_register_physical_memory(bios_addr, bios_size,
 625                                      bios_offset | IO_MEM_ROM);
 626         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 627     }
 628     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 629         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 630     }
 631     if (filename) {
 632         qemu_free(filename);
 633     }
 634     if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
 635         hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
 636     }
 637
 638     if (linux_boot) {
 639         kernel_base = KERNEL_LOAD_ADDR;
 640         /* now we can load the kernel */
 641         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 642                                           ram_size - kernel_base);
 643         if (kernel_size < 0) {
 644             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 645             exit(1);
 646         }
 647         /* load initrd */
 648         if (initrd_filename) {
 649             initrd_base = INITRD_LOAD_ADDR;
 650             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 651                                               ram_size - initrd_base);
 652             if (initrd_size < 0) {
 653                 hw_error("qemu: could not load initial ram disk '%s'\n",
 654                           initrd_filename);
 655             }
 656         } else {
 657             initrd_base = 0;
 658             initrd_size = 0;
 659         }
 660         ppc_boot_device = 'm';
 661     } else {
 662         kernel_base = 0;
 663         kernel_size = 0;
 664         initrd_base = 0;
 665         initrd_size = 0;
 666         ppc_boot_device = '\0';
 667         /* For now, OHW cannot boot from the network. */
 668         for (i = 0; boot_device[i] != '\0'; i++) {
 669             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 670                 ppc_boot_device = boot_device[i];
 671                 break;
 672             }
 673         }
 674         if (ppc_boot_device == '\0') {
 675             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 676             exit(1);
 677         }
 678     }
 679
 680     isa_mem_base = 0xc0000000;
 681     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 682         hw_error("Only 6xx bus is supported on PREP machine\n");
 683     }
 684     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 685     pci_bus = pci_prep_init(i8259);
 686     /* Hmm, prep has no pci-isa bridge ??? */
 687     isa_bus_new(NULL);
 688     isa_bus_irqs(i8259);
 689     //    pci_bus = i440fx_init();
 690     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 691     PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
 692                                            PPC_prep_io_write, sysctrl);
 693     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 694
 695     /* init basic PC hardware */
 696     pci_vga_init(pci_bus, 0, 0);
 697     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 698     //    pit = pit_init(0x40, i8259[0]);
 699     rtc_init(2000, NULL);
 700
 701     if (serial_hds[0])
 702         serial_isa_init(0, serial_hds[0]);
 703     nb_nics1 = nb_nics;
 704     if (nb_nics1 > NE2000_NB_MAX)
 705         nb_nics1 = NE2000_NB_MAX;
 706     for(i = 0; i < nb_nics1; i++) {
 707         if (nd_table[i].model == NULL) {
 708             nd_table[i].model = qemu_strdup("ne2k_isa");
 709         }
 710         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 711             isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
 712         } else {
 713             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 714         }
 715     }
 716
 717     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 718         fprintf(stderr, "qemu: too many IDE bus\n");
 719         exit(1);
 720     }
 721
 722     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 723         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 724     }
 725
 726     for(i = 0; i < MAX_IDE_BUS; i++) {
 727         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 728                      hd[2 * i],
 729                      hd[2 * i + 1]);
 730     }
 731     isa_create_simple("i8042");
 732
 733     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 734     DMA_init(1, cpu_exit_irq);
 735
 736     //    SB16_init();
 737
 738     for(i = 0; i < MAX_FD; i++) {
 739         fd[i] = drive_get(IF_FLOPPY, 0, i);
 740     }
 741     fdctrl_init_isa(fd);
 742
 743     /* Register speaker port */
 744     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 745     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 746     /* Register fake IO ports for PREP */
 747     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 748     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 749     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 750     /* System control ports */
 751     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 752     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 753     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 754     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 755     /* PCI intack location */
 756     PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
 757                                            PPC_intack_write, NULL);
 758     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 759     /* PowerPC control and status register group */
 760 #if 0
 761     PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
 762                                            NULL);
 763     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 764 #endif
 765
 766     if (usb_enabled) {
 767         usb_ohci_init_pci(pci_bus, -1);
 768     }
 769
 770     m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 771     if (m48t59 == NULL)
 772         return;
 773     sysctrl->nvram = m48t59;
 774
 775     /* Initialise NVRAM */
 776     nvram.opaque = m48t59;
 777     nvram.read_fn = &m48t59_read;
 778     nvram.write_fn = &m48t59_write;
 779     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 780                          kernel_base, kernel_size,
 781                          kernel_cmdline,
 782                          initrd_base, initrd_size,
 783                          /* XXX: need an option to load a NVRAM image */
 784                          0,
 785                          graphic_width, graphic_height, graphic_depth);
 786
 787     /* Special port to get debug messages from Open-Firmware */
 788     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 789 }
 790
 791 static QEMUMachine prep_machine = {
 792     .name = "prep",
 793     .desc = "PowerPC PREP platform",
 794     .init = ppc_prep_init,
 795     .max_cpus = MAX_CPUS,
 796 };
 797
 798 static void prep_machine_init(void)
 799 {
 800     qemu_register_machine(&prep_machine);
 801 }
 802
 803 machine_init(prep_machine_init);