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qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs
[qemu.git] / tcg / ppc64 / tcg-target.c
blobf2ad9e3d854b872459c4979abe5e8dfc712e5329
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #define TCG_CT_CONST_U32 0x100
26
27 static uint8_t *tb_ret_addr;
28
29 #define FAST_PATH
30
31 #if TARGET_LONG_BITS == 32
32 #define LD_ADDR LWZU
33 #define CMP_L 0
34 #else
35 #define LD_ADDR LDU
36 #define CMP_L (1<<21)
37 #endif
38
39 #ifndef GUEST_BASE
40 #define GUEST_BASE 0
41 #endif
42
43 #ifdef CONFIG_USE_GUEST_BASE
44 #define TCG_GUEST_BASE_REG 30
45 #else
46 #define TCG_GUEST_BASE_REG 0
47 #endif
48
49 #ifndef NDEBUG
50 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
51 "r0",
52 "r1",
53 "r2",
54 "r3",
55 "r4",
56 "r5",
57 "r6",
58 "r7",
59 "r8",
60 "r9",
61 "r10",
62 "r11",
63 "r12",
64 "r13",
65 "r14",
66 "r15",
67 "r16",
68 "r17",
69 "r18",
70 "r19",
71 "r20",
72 "r21",
73 "r22",
74 "r23",
75 "r24",
76 "r25",
77 "r26",
78 "r27",
79 "r28",
80 "r29",
81 "r30",
82 "r31"
83 };
84 #endif
85
86 static const int tcg_target_reg_alloc_order[] = {
87 TCG_REG_R14,
88 TCG_REG_R15,
89 TCG_REG_R16,
90 TCG_REG_R17,
91 TCG_REG_R18,
92 TCG_REG_R19,
93 TCG_REG_R20,
94 TCG_REG_R21,
95 TCG_REG_R22,
96 TCG_REG_R23,
97 TCG_REG_R28,
98 TCG_REG_R29,
99 TCG_REG_R30,
100 TCG_REG_R31,
101 #ifdef __APPLE__
102 TCG_REG_R2,
103 #endif
104 TCG_REG_R3,
105 TCG_REG_R4,
106 TCG_REG_R5,
107 TCG_REG_R6,
108 TCG_REG_R7,
109 TCG_REG_R8,
110 TCG_REG_R9,
111 TCG_REG_R10,
112 #ifndef __APPLE__
113 TCG_REG_R11,
114 #endif
115 TCG_REG_R12,
116 TCG_REG_R24,
117 TCG_REG_R25,
118 TCG_REG_R26,
119 TCG_REG_R27
120 };
121
122 static const int tcg_target_call_iarg_regs[] = {
123 TCG_REG_R3,
124 TCG_REG_R4,
125 TCG_REG_R5,
126 TCG_REG_R6,
127 TCG_REG_R7,
128 TCG_REG_R8,
129 TCG_REG_R9,
130 TCG_REG_R10
131 };
132
133 static const int tcg_target_call_oarg_regs[] = {
134 TCG_REG_R3
135 };
136
137 static const int tcg_target_callee_save_regs[] = {
138 #ifdef __APPLE__
139 TCG_REG_R11,
140 #endif
141 TCG_REG_R14,
142 TCG_REG_R15,
143 TCG_REG_R16,
144 TCG_REG_R17,
145 TCG_REG_R18,
146 TCG_REG_R19,
147 TCG_REG_R20,
148 TCG_REG_R21,
149 TCG_REG_R22,
150 TCG_REG_R23,
151 TCG_REG_R24,
152 TCG_REG_R25,
153 TCG_REG_R26,
154 TCG_REG_R27, /* currently used for the global env */
155 TCG_REG_R28,
156 TCG_REG_R29,
157 TCG_REG_R30,
158 TCG_REG_R31
159 };
160
161 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
162 {
163 tcg_target_long disp;
164
165 disp = target - (tcg_target_long) pc;
166 if ((disp << 38) >> 38 != disp)
167 tcg_abort ();
168
169 return disp & 0x3fffffc;
170 }
171
172 static void reloc_pc24 (void *pc, tcg_target_long target)
173 {
174 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
175 | reloc_pc24_val (pc, target);
176 }
177
178 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
179 {
180 tcg_target_long disp;
181
182 disp = target - (tcg_target_long) pc;
183 if (disp != (int16_t) disp)
184 tcg_abort ();
185
186 return disp & 0xfffc;
187 }
188
189 static void reloc_pc14 (void *pc, tcg_target_long target)
190 {
191 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
192 | reloc_pc14_val (pc, target);
193 }
194
195 static void patch_reloc (uint8_t *code_ptr, int type,
196 tcg_target_long value, tcg_target_long addend)
197 {
198 value += addend;
199 switch (type) {
200 case R_PPC_REL14:
201 reloc_pc14 (code_ptr, value);
202 break;
203 case R_PPC_REL24:
204 reloc_pc24 (code_ptr, value);
205 break;
206 default:
207 tcg_abort ();
208 }
209 }
210
211 /* maximum number of register used for input function arguments */
212 static int tcg_target_get_call_iarg_regs_count (int flags)
213 {
214 return ARRAY_SIZE (tcg_target_call_iarg_regs);
215 }
216
217 /* parse target specific constraints */
218 static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
219 {
220 const char *ct_str;
221
222 ct_str = *pct_str;
223 switch (ct_str[0]) {
224 case 'A': case 'B': case 'C': case 'D':
225 ct->ct |= TCG_CT_REG;
226 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
227 break;
228 case 'r':
229 ct->ct |= TCG_CT_REG;
230 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
231 break;
232 case 'L': /* qemu_ld constraint */
233 ct->ct |= TCG_CT_REG;
234 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
235 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
236 #ifdef CONFIG_SOFTMMU
237 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
238 #endif
239 break;
240 case 'S': /* qemu_st constraint */
241 ct->ct |= TCG_CT_REG;
242 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
243 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
244 #ifdef CONFIG_SOFTMMU
245 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
246 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
247 #endif
248 break;
249 case 'Z':
250 ct->ct |= TCG_CT_CONST_U32;
251 break;
252 default:
253 return -1;
254 }
255 ct_str++;
256 *pct_str = ct_str;
257 return 0;
258 }
259
260 /* test if a constant matches the constraint */
261 static int tcg_target_const_match (tcg_target_long val,
262 const TCGArgConstraint *arg_ct)
263 {
264 int ct;
265
266 ct = arg_ct->ct;
267 if (ct & TCG_CT_CONST)
268 return 1;
269 else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val))
270 return 1;
271 return 0;
272 }
273
274 #define OPCD(opc) ((opc)<<26)
275 #define XO19(opc) (OPCD(19)|((opc)<<1))
276 #define XO30(opc) (OPCD(30)|((opc)<<2))
277 #define XO31(opc) (OPCD(31)|((opc)<<1))
278 #define XO58(opc) (OPCD(58)|(opc))
279 #define XO62(opc) (OPCD(62)|(opc))
280
281 #define B OPCD( 18)
282 #define BC OPCD( 16)
283 #define LBZ OPCD( 34)
284 #define LHZ OPCD( 40)
285 #define LHA OPCD( 42)
286 #define LWZ OPCD( 32)
287 #define STB OPCD( 38)
288 #define STH OPCD( 44)
289 #define STW OPCD( 36)
290
291 #define STD XO62( 0)
292 #define STDU XO62( 1)
293 #define STDX XO31(149)
294
295 #define LD XO58( 0)
296 #define LDX XO31( 21)
297 #define LDU XO58( 1)
298 #define LWA XO58( 2)
299 #define LWAX XO31(341)
300
301 #define ADDIC OPCD( 12)
302 #define ADDI OPCD( 14)
303 #define ADDIS OPCD( 15)
304 #define ORI OPCD( 24)
305 #define ORIS OPCD( 25)
306 #define XORI OPCD( 26)
307 #define XORIS OPCD( 27)
308 #define ANDI OPCD( 28)
309 #define ANDIS OPCD( 29)
310 #define MULLI OPCD( 7)
311 #define CMPLI OPCD( 10)
312 #define CMPI OPCD( 11)
313
314 #define LWZU OPCD( 33)
315 #define STWU OPCD( 37)
316
317 #define RLWINM OPCD( 21)
318
319 #define RLDICL XO30( 0)
320 #define RLDICR XO30( 1)
321 #define RLDIMI XO30( 3)
322
323 #define BCLR XO19( 16)
324 #define BCCTR XO19(528)
325 #define CRAND XO19(257)
326 #define CRANDC XO19(129)
327 #define CRNAND XO19(225)
328 #define CROR XO19(449)
329 #define CRNOR XO19( 33)
330
331 #define EXTSB XO31(954)
332 #define EXTSH XO31(922)
333 #define EXTSW XO31(986)
334 #define ADD XO31(266)
335 #define ADDE XO31(138)
336 #define ADDC XO31( 10)
337 #define AND XO31( 28)
338 #define SUBF XO31( 40)
339 #define SUBFC XO31( 8)
340 #define SUBFE XO31(136)
341 #define OR XO31(444)
342 #define XOR XO31(316)
343 #define MULLW XO31(235)
344 #define MULHWU XO31( 11)
345 #define DIVW XO31(491)
346 #define DIVWU XO31(459)
347 #define CMP XO31( 0)
348 #define CMPL XO31( 32)
349 #define LHBRX XO31(790)
350 #define LWBRX XO31(534)
351 #define STHBRX XO31(918)
352 #define STWBRX XO31(662)
353 #define MFSPR XO31(339)
354 #define MTSPR XO31(467)
355 #define SRAWI XO31(824)
356 #define NEG XO31(104)
357 #define MFCR XO31( 19)
358 #define NOR XO31(124)
359 #define CNTLZW XO31( 26)
360 #define CNTLZD XO31( 58)
361
362 #define MULLD XO31(233)
363 #define MULHD XO31( 73)
364 #define MULHDU XO31( 9)
365 #define DIVD XO31(489)
366 #define DIVDU XO31(457)
367
368 #define LBZX XO31( 87)
369 #define LHZX XO31(279)
370 #define LHAX XO31(343)
371 #define LWZX XO31( 23)
372 #define STBX XO31(215)
373 #define STHX XO31(407)
374 #define STWX XO31(151)
375
376 #define SPR(a,b) ((((a)<<5)|(b))<<11)
377 #define LR SPR(8, 0)
378 #define CTR SPR(9, 0)
379
380 #define SLW XO31( 24)
381 #define SRW XO31(536)
382 #define SRAW XO31(792)
383
384 #define SLD XO31( 27)
385 #define SRD XO31(539)
386 #define SRAD XO31(794)
387 #define SRADI XO31(413<<1)
388
389 #define TW XO31( 4)
390 #define TRAP (TW | TO (31))
391
392 #define RT(r) ((r)<<21)
393 #define RS(r) ((r)<<21)
394 #define RA(r) ((r)<<16)
395 #define RB(r) ((r)<<11)
396 #define TO(t) ((t)<<21)
397 #define SH(s) ((s)<<11)
398 #define MB(b) ((b)<<6)
399 #define ME(e) ((e)<<1)
400 #define BO(o) ((o)<<21)
401 #define MB64(b) ((b)<<5)
402
403 #define LK 1
404
405 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
407
408 #define BF(n) ((n)<<23)
409 #define BI(n, c) (((c)+((n)*4))<<16)
410 #define BT(n, c) (((c)+((n)*4))<<21)
411 #define BA(n, c) (((c)+((n)*4))<<16)
412 #define BB(n, c) (((c)+((n)*4))<<11)
413
414 #define BO_COND_TRUE BO (12)
415 #define BO_COND_FALSE BO ( 4)
416 #define BO_ALWAYS BO (20)
417
418 enum {
419 CR_LT,
420 CR_GT,
421 CR_EQ,
422 CR_SO
423 };
424
425 static const uint32_t tcg_to_bc[10] = {
426 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
427 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
428 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
429 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
430 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
431 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
432 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
433 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
434 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
435 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
436 };
437
438 static void tcg_out_mov (TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
439 {
440 tcg_out32 (s, OR | SAB (arg, ret, arg));
441 }
442
443 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
444 {
445 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
446 mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
448 }
449
450 static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg)
451 {
452 if (arg == (int16_t) arg)
453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
454 else {
455 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
456 if (arg & 0xffff)
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
458 }
459 }
460
461 static void tcg_out_movi (TCGContext *s, TCGType type,
462 TCGReg ret, tcg_target_long arg)
463 {
464 int32_t arg32 = arg;
465 arg = type == TCG_TYPE_I32 ? arg & 0xffffffff : arg;
466
467 if (arg == arg32) {
468 tcg_out_movi32 (s, ret, arg32);
469 }
470 else {
471 if ((uint64_t) arg >> 32) {
472 uint16_t h16 = arg >> 16;
473 uint16_t l16 = arg;
474
475 tcg_out_movi32 (s, ret, arg >> 32);
476 tcg_out_rld (s, RLDICR, ret, ret, 32, 31);
477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
479 }
480 else {
481 tcg_out_movi32 (s, ret, arg32);
482 if (arg32 < 0)
483 tcg_out_rld (s, RLDICL, ret, ret, 0, 32);
484 }
485 }
486 }
487
488 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
489 {
490 tcg_target_long disp;
491
492 disp = target - (tcg_target_long) s->code_ptr;
493 if ((disp << 38) >> 38 == disp)
494 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
495 else {
496 tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
497 tcg_out32 (s, MTSPR | RS (0) | CTR);
498 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
499 }
500 }
501
502 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
503 {
504 #ifdef __APPLE__
505 if (const_arg) {
506 tcg_out_b (s, LK, arg);
507 }
508 else {
509 tcg_out32 (s, MTSPR | RS (arg) | LR);
510 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
511 }
512 #else
513 int reg;
514
515 if (const_arg) {
516 reg = 2;
517 tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
518 }
519 else reg = arg;
520
521 tcg_out32 (s, LD | RT (0) | RA (reg));
522 tcg_out32 (s, MTSPR | RA (0) | CTR);
523 tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
524 tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
525 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
526 #endif
527 }
528
529 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
530 int offset, int op1, int op2)
531 {
532 if (offset == (int16_t) offset)
533 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
534 else {
535 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
536 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
537 }
538 }
539
540 static void tcg_out_ldsta (TCGContext *s, int ret, int addr,
541 int offset, int op1, int op2)
542 {
543 if (offset == (int16_t) (offset & ~3))
544 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
545 else {
546 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
547 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
548 }
549 }
550
551 #if defined (CONFIG_SOFTMMU)
552
553 #include "../../softmmu_defs.h"
554
555 #ifdef CONFIG_TCG_PASS_AREG0
556 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
557 int mmu_idx) */
558 static const void * const qemu_ld_helpers[4] = {
559 helper_ldb_mmu,
560 helper_ldw_mmu,
561 helper_ldl_mmu,
562 helper_ldq_mmu,
563 };
564
565 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
566 uintxx_t val, int mmu_idx) */
567 static const void * const qemu_st_helpers[4] = {
568 helper_stb_mmu,
569 helper_stw_mmu,
570 helper_stl_mmu,
571 helper_stq_mmu,
572 };
573 #else
574 /* legacy helper signature: __ld_mmu(target_ulong addr, int
575 mmu_idx) */
576 static void *qemu_ld_helpers[4] = {
577 __ldb_mmu,
578 __ldw_mmu,
579 __ldl_mmu,
580 __ldq_mmu,
581 };
582
583 /* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
584 int mmu_idx) */
585 static void *qemu_st_helpers[4] = {
586 __stb_mmu,
587 __stw_mmu,
588 __stl_mmu,
589 __stq_mmu,
590 };
591 #endif
592
593 static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
594 int addr_reg, int s_bits, int offset)
595 {
596 #if TARGET_LONG_BITS == 32
597 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
598
599 tcg_out32 (s, (RLWINM
600 | RA (r0)
601 | RS (addr_reg)
602 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
603 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
604 | ME (31 - CPU_TLB_ENTRY_BITS)
605 )
606 );
607 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
608 tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset));
609 tcg_out32 (s, (RLWINM
610 | RA (r2)
611 | RS (addr_reg)
612 | SH (0)
613 | MB ((32 - s_bits) & 31)
614 | ME (31 - TARGET_PAGE_BITS)
615 )
616 );
617 #else
618 tcg_out_rld (s, RLDICL, r0, addr_reg,
619 64 - TARGET_PAGE_BITS,
620 64 - CPU_TLB_BITS);
621 tcg_out_rld (s, RLDICR, r0, r0,
622 CPU_TLB_ENTRY_BITS,
623 63 - CPU_TLB_ENTRY_BITS);
624
625 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
626 tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset);
627
628 if (!s_bits) {
629 tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
630 }
631 else {
632 tcg_out_rld (s, RLDICL, r2, addr_reg,
633 64 - TARGET_PAGE_BITS,
634 TARGET_PAGE_BITS - s_bits);
635 tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
636 }
637 #endif
638 }
639 #endif
640
641 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
642 {
643 int addr_reg, data_reg, r0, r1, rbase, bswap;
644 #ifdef CONFIG_SOFTMMU
645 int r2, mem_index, s_bits;
646 void *label1_ptr, *label2_ptr;
647 #endif
648
649 data_reg = *args++;
650 addr_reg = *args++;
651
652 #ifdef CONFIG_SOFTMMU
653 mem_index = *args;
654 s_bits = opc & 3;
655
656 r0 = 3;
657 r1 = 4;
658 r2 = 0;
659 rbase = 0;
660
661 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
662 offsetof (CPUArchState, tlb_table[mem_index][0].addr_read));
663
664 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
665
666 label1_ptr = s->code_ptr;
667 #ifdef FAST_PATH
668 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
669 #endif
670
671 /* slow path */
672 tcg_out_mov (s, TCG_TYPE_I64, 3, addr_reg);
673 tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
674
675 #ifdef CONFIG_TCG_PASS_AREG0
676 /* XXX/FIXME: suboptimal */
677 tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
678 tcg_target_call_iarg_regs[1]);
679 tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
680 tcg_target_call_iarg_regs[0]);
681 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
682 TCG_AREG0);
683 #endif
684 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
685
686 switch (opc) {
687 case 0|4:
688 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
689 break;
690 case 1|4:
691 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
692 break;
693 case 2|4:
694 tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
695 break;
696 case 0:
697 case 1:
698 case 2:
699 case 3:
700 if (data_reg != 3)
701 tcg_out_mov (s, TCG_TYPE_I64, data_reg, 3);
702 break;
703 }
704 label2_ptr = s->code_ptr;
705 tcg_out32 (s, B);
706
707 /* label1: fast path */
708 #ifdef FAST_PATH
709 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
710 #endif
711
712 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
713 tcg_out32 (s, (LD
714 | RT (r0)
715 | RA (r0)
716 | (offsetof (CPUTLBEntry, addend)
717 - offsetof (CPUTLBEntry, addr_read))
718 ));
719 /* r0 = env->tlb_table[mem_index][index].addend */
720 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
721 /* r0 = env->tlb_table[mem_index][index].addend + addr */
722
723 #else /* !CONFIG_SOFTMMU */
724 #if TARGET_LONG_BITS == 32
725 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
726 #endif
727 r0 = addr_reg;
728 r1 = 3;
729 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
730 #endif
731
732 #ifdef TARGET_WORDS_BIGENDIAN
733 bswap = 0;
734 #else
735 bswap = 1;
736 #endif
737 switch (opc) {
738 default:
739 case 0:
740 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
741 break;
742 case 0|4:
743 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
744 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
745 break;
746 case 1:
747 if (bswap)
748 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
749 else
750 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
751 break;
752 case 1|4:
753 if (bswap) {
754 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
755 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
756 }
757 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
758 break;
759 case 2:
760 if (bswap)
761 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
762 else
763 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
764 break;
765 case 2|4:
766 if (bswap) {
767 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
768 tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
769 }
770 else tcg_out32 (s, LWAX | TAB (data_reg, rbase, r0));
771 break;
772 case 3:
773 #ifdef CONFIG_USE_GUEST_BASE
774 if (bswap) {
775 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
776 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
777 tcg_out32 (s, LWBRX | TAB ( r1, rbase, r1));
778 tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
779 }
780 else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0));
781 #else
782 if (bswap) {
783 tcg_out_movi32 (s, 0, 4);
784 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
785 tcg_out32 (s, LWBRX | RT ( r1) | RA (r0));
786 tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
787 }
788 else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
789 #endif
790 break;
791 }
792
793 #ifdef CONFIG_SOFTMMU
794 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
795 #endif
796 }
797
798 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
799 {
800 int addr_reg, r0, r1, rbase, data_reg, bswap;
801 #ifdef CONFIG_SOFTMMU
802 int r2, mem_index;
803 void *label1_ptr, *label2_ptr;
804 #endif
805
806 data_reg = *args++;
807 addr_reg = *args++;
808
809 #ifdef CONFIG_SOFTMMU
810 mem_index = *args;
811
812 r0 = 3;
813 r1 = 4;
814 r2 = 0;
815 rbase = 0;
816
817 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
818 offsetof (CPUArchState, tlb_table[mem_index][0].addr_write));
819
820 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
821
822 label1_ptr = s->code_ptr;
823 #ifdef FAST_PATH
824 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
825 #endif
826
827 /* slow path */
828 tcg_out_mov (s, TCG_TYPE_I64, 3, addr_reg);
829 tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc)));
830 tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
831
832 #ifdef CONFIG_TCG_PASS_AREG0
833 /* XXX/FIXME: suboptimal */
834 tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
835 tcg_target_call_iarg_regs[2]);
836 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
837 tcg_target_call_iarg_regs[1]);
838 tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
839 tcg_target_call_iarg_regs[0]);
840 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
841 TCG_AREG0);
842 #endif
843 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
844
845 label2_ptr = s->code_ptr;
846 tcg_out32 (s, B);
847
848 /* label1: fast path */
849 #ifdef FAST_PATH
850 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
851 #endif
852
853 tcg_out32 (s, (LD
854 | RT (r0)
855 | RA (r0)
856 | (offsetof (CPUTLBEntry, addend)
857 - offsetof (CPUTLBEntry, addr_write))
858 ));
859 /* r0 = env->tlb_table[mem_index][index].addend */
860 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
861 /* r0 = env->tlb_table[mem_index][index].addend + addr */
862
863 #else /* !CONFIG_SOFTMMU */
864 #if TARGET_LONG_BITS == 32
865 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
866 #endif
867 r1 = 3;
868 r0 = addr_reg;
869 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
870 #endif
871
872 #ifdef TARGET_WORDS_BIGENDIAN
873 bswap = 0;
874 #else
875 bswap = 1;
876 #endif
877 switch (opc) {
878 case 0:
879 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
880 break;
881 case 1:
882 if (bswap)
883 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
884 else
885 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
886 break;
887 case 2:
888 if (bswap)
889 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
890 else
891 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
892 break;
893 case 3:
894 if (bswap) {
895 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
896 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
897 tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0);
898 tcg_out32 (s, STWBRX | SAB (0, rbase, r1));
899 }
900 else tcg_out32 (s, STDX | SAB (data_reg, rbase, r0));
901 break;
902 }
903
904 #ifdef CONFIG_SOFTMMU
905 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
906 #endif
907 }
908
909 static void tcg_target_qemu_prologue (TCGContext *s)
910 {
911 int i, frame_size;
912 #ifndef __APPLE__
913 uint64_t addr;
914 #endif
915
916 frame_size = 0
917 + 8 /* back chain */
918 + 8 /* CR */
919 + 8 /* LR */
920 + 8 /* compiler doubleword */
921 + 8 /* link editor doubleword */
922 + 8 /* TOC save area */
923 + TCG_STATIC_CALL_ARGS_SIZE
924 + ARRAY_SIZE (tcg_target_callee_save_regs) * 8
925 + CPU_TEMP_BUF_NLONGS * sizeof(long)
926 ;
927 frame_size = (frame_size + 15) & ~15;
928
929 tcg_set_frame(s, TCG_REG_CALL_STACK, frame_size
930 - CPU_TEMP_BUF_NLONGS * sizeof(long),
931 CPU_TEMP_BUF_NLONGS * sizeof(long));
932
933 #ifndef __APPLE__
934 /* First emit adhoc function descriptor */
935 addr = (uint64_t) s->code_ptr + 24;
936 tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
937 s->code_ptr += 16; /* skip TOC and environment pointer */
938 #endif
939
940 /* Prologue */
941 tcg_out32 (s, MFSPR | RT (0) | LR);
942 tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
943 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
944 tcg_out32 (s, (STD
945 | RS (tcg_target_callee_save_regs[i])
946 | RA (1)
947 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
948 )
949 );
950 tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16));
951
952 #ifdef CONFIG_USE_GUEST_BASE
953 if (GUEST_BASE) {
954 tcg_out_movi (s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
955 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
956 }
957 #endif
958
959 tcg_out_mov (s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
960 tcg_out32 (s, MTSPR | RS (tcg_target_call_iarg_regs[1]) | CTR);
961 tcg_out32 (s, BCCTR | BO_ALWAYS);
962
963 /* Epilogue */
964 tb_ret_addr = s->code_ptr;
965
966 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
967 tcg_out32 (s, (LD
968 | RT (tcg_target_callee_save_regs[i])
969 | RA (1)
970 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
971 )
972 );
973 tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16));
974 tcg_out32 (s, MTSPR | RS (0) | LR);
975 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
976 tcg_out32 (s, BCLR | BO_ALWAYS);
977 }
978
979 static void tcg_out_ld (TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
980 tcg_target_long arg2)
981 {
982 if (type == TCG_TYPE_I32)
983 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
984 else
985 tcg_out_ldsta (s, ret, arg1, arg2, LD, LDX);
986 }
987
988 static void tcg_out_st (TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
989 tcg_target_long arg2)
990 {
991 if (type == TCG_TYPE_I32)
992 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
993 else
994 tcg_out_ldsta (s, arg, arg1, arg2, STD, STDX);
995 }
996
997 static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si)
998 {
999 if (!si && rt == ra)
1000 return;
1001
1002 if (si == (int16_t) si)
1003 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
1004 else {
1005 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
1006 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
1007 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
1008 }
1009 }
1010
1011 static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si)
1012 {
1013 /* XXX: suboptimal */
1014 if (si == (int16_t) si
1015 || ((((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0))
1016 ppc_addi32 (s, rt, ra, si);
1017 else {
1018 tcg_out_movi (s, TCG_TYPE_I64, 0, si);
1019 tcg_out32 (s, ADD | RT (rt) | RA (ra));
1020 }
1021 }
1022
1023 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1024 int const_arg2, int cr, int arch64)
1025 {
1026 int imm;
1027 uint32_t op;
1028
1029 switch (cond) {
1030 case TCG_COND_EQ:
1031 case TCG_COND_NE:
1032 if (const_arg2) {
1033 if ((int16_t) arg2 == arg2) {
1034 op = CMPI;
1035 imm = 1;
1036 break;
1037 }
1038 else if ((uint16_t) arg2 == arg2) {
1039 op = CMPLI;
1040 imm = 1;
1041 break;
1042 }
1043 }
1044 op = CMPL;
1045 imm = 0;
1046 break;
1047
1048 case TCG_COND_LT:
1049 case TCG_COND_GE:
1050 case TCG_COND_LE:
1051 case TCG_COND_GT:
1052 if (const_arg2) {
1053 if ((int16_t) arg2 == arg2) {
1054 op = CMPI;
1055 imm = 1;
1056 break;
1057 }
1058 }
1059 op = CMP;
1060 imm = 0;
1061 break;
1062
1063 case TCG_COND_LTU:
1064 case TCG_COND_GEU:
1065 case TCG_COND_LEU:
1066 case TCG_COND_GTU:
1067 if (const_arg2) {
1068 if ((uint16_t) arg2 == arg2) {
1069 op = CMPLI;
1070 imm = 1;
1071 break;
1072 }
1073 }
1074 op = CMPL;
1075 imm = 0;
1076 break;
1077
1078 default:
1079 tcg_abort ();
1080 }
1081 op |= BF (cr) | (arch64 << 21);
1082
1083 if (imm)
1084 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1085 else {
1086 if (const_arg2) {
1087 tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
1088 tcg_out32 (s, op | RA (arg1) | RB (0));
1089 }
1090 else
1091 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1092 }
1093
1094 }
1095
1096 static void tcg_out_setcond (TCGContext *s, TCGType type, TCGCond cond,
1097 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1098 int const_arg2)
1099 {
1100 int crop, sh, arg;
1101
1102 switch (cond) {
1103 case TCG_COND_EQ:
1104 if (const_arg2) {
1105 if (!arg2) {
1106 arg = arg1;
1107 }
1108 else {
1109 arg = 0;
1110 if ((uint16_t) arg2 == arg2) {
1111 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1112 }
1113 else {
1114 tcg_out_movi (s, type, 0, arg2);
1115 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1116 }
1117 }
1118 }
1119 else {
1120 arg = 0;
1121 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1122 }
1123
1124 if (type == TCG_TYPE_I64) {
1125 tcg_out32 (s, CNTLZD | RS (arg) | RA (0));
1126 tcg_out_rld (s, RLDICL, arg0, 0, 58, 6);
1127 }
1128 else {
1129 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1130 tcg_out32 (s, (RLWINM
1131 | RA (arg0)
1132 | RS (0)
1133 | SH (27)
1134 | MB (5)
1135 | ME (31)
1136 )
1137 );
1138 }
1139 break;
1140
1141 case TCG_COND_NE:
1142 if (const_arg2) {
1143 if (!arg2) {
1144 arg = arg1;
1145 }
1146 else {
1147 arg = 0;
1148 if ((uint16_t) arg2 == arg2) {
1149 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1150 }
1151 else {
1152 tcg_out_movi (s, type, 0, arg2);
1153 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1154 }
1155 }
1156 }
1157 else {
1158 arg = 0;
1159 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1160 }
1161
1162 if (arg == arg1 && arg1 == arg0) {
1163 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1164 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1165 }
1166 else {
1167 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1168 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1169 }
1170 break;
1171
1172 case TCG_COND_GT:
1173 case TCG_COND_GTU:
1174 sh = 30;
1175 crop = 0;
1176 goto crtest;
1177
1178 case TCG_COND_LT:
1179 case TCG_COND_LTU:
1180 sh = 29;
1181 crop = 0;
1182 goto crtest;
1183
1184 case TCG_COND_GE:
1185 case TCG_COND_GEU:
1186 sh = 31;
1187 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
1188 goto crtest;
1189
1190 case TCG_COND_LE:
1191 case TCG_COND_LEU:
1192 sh = 31;
1193 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
1194 crtest:
1195 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type == TCG_TYPE_I64);
1196 if (crop) tcg_out32 (s, crop);
1197 tcg_out32 (s, MFCR | RT (0));
1198 tcg_out32 (s, (RLWINM
1199 | RA (arg0)
1200 | RS (0)
1201 | SH (sh)
1202 | MB (31)
1203 | ME (31)
1204 )
1205 );
1206 break;
1207
1208 default:
1209 tcg_abort ();
1210 }
1211 }
1212
1213 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1214 {
1215 TCGLabel *l = &s->labels[label_index];
1216
1217 if (l->has_value)
1218 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1219 else {
1220 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1221
1222 /* Thanks to Andrzej Zaborowski */
1223 tcg_out32 (s, bc | (val & 0xfffc));
1224 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1225 }
1226 }
1227
1228 static void tcg_out_brcond (TCGContext *s, TCGCond cond,
1229 TCGArg arg1, TCGArg arg2, int const_arg2,
1230 int label_index, int arch64)
1231 {
1232 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
1233 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1234 }
1235
1236 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1237 {
1238 TCGContext s;
1239 unsigned long patch_size;
1240
1241 s.code_ptr = (uint8_t *) jmp_addr;
1242 tcg_out_b (&s, 0, addr);
1243 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1244 flush_icache_range (jmp_addr, jmp_addr + patch_size);
1245 }
1246
1247 static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
1248 const int *const_args)
1249 {
1250 int c;
1251
1252 switch (opc) {
1253 case INDEX_op_exit_tb:
1254 tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1255 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1256 break;
1257 case INDEX_op_goto_tb:
1258 if (s->tb_jmp_offset) {
1259 /* direct jump method */
1260
1261 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1262 s->code_ptr += 28;
1263 }
1264 else {
1265 tcg_abort ();
1266 }
1267 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1268 break;
1269 case INDEX_op_br:
1270 {
1271 TCGLabel *l = &s->labels[args[0]];
1272
1273 if (l->has_value) {
1274 tcg_out_b (s, 0, l->u.value);
1275 }
1276 else {
1277 uint32_t val = *(uint32_t *) s->code_ptr;
1278
1279 /* Thanks to Andrzej Zaborowski */
1280 tcg_out32 (s, B | (val & 0x3fffffc));
1281 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1282 }
1283 }
1284 break;
1285 case INDEX_op_call:
1286 tcg_out_call (s, args[0], const_args[0]);
1287 break;
1288 case INDEX_op_jmp:
1289 if (const_args[0]) {
1290 tcg_out_b (s, 0, args[0]);
1291 }
1292 else {
1293 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1294 tcg_out32 (s, BCCTR | BO_ALWAYS);
1295 }
1296 break;
1297 case INDEX_op_movi_i32:
1298 tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
1299 break;
1300 case INDEX_op_movi_i64:
1301 tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
1302 break;
1303 case INDEX_op_ld8u_i32:
1304 case INDEX_op_ld8u_i64:
1305 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1306 break;
1307 case INDEX_op_ld8s_i32:
1308 case INDEX_op_ld8s_i64:
1309 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1310 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1311 break;
1312 case INDEX_op_ld16u_i32:
1313 case INDEX_op_ld16u_i64:
1314 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1315 break;
1316 case INDEX_op_ld16s_i32:
1317 case INDEX_op_ld16s_i64:
1318 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1319 break;
1320 case INDEX_op_ld_i32:
1321 case INDEX_op_ld32u_i64:
1322 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1323 break;
1324 case INDEX_op_ld32s_i64:
1325 tcg_out_ldsta (s, args[0], args[1], args[2], LWA, LWAX);
1326 break;
1327 case INDEX_op_ld_i64:
1328 tcg_out_ldsta (s, args[0], args[1], args[2], LD, LDX);
1329 break;
1330 case INDEX_op_st8_i32:
1331 case INDEX_op_st8_i64:
1332 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1333 break;
1334 case INDEX_op_st16_i32:
1335 case INDEX_op_st16_i64:
1336 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1337 break;
1338 case INDEX_op_st_i32:
1339 case INDEX_op_st32_i64:
1340 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1341 break;
1342 case INDEX_op_st_i64:
1343 tcg_out_ldsta (s, args[0], args[1], args[2], STD, STDX);
1344 break;
1345
1346 case INDEX_op_add_i32:
1347 if (const_args[2])
1348 ppc_addi32 (s, args[0], args[1], args[2]);
1349 else
1350 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1351 break;
1352 case INDEX_op_sub_i32:
1353 if (const_args[2])
1354 ppc_addi32 (s, args[0], args[1], -args[2]);
1355 else
1356 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1357 break;
1358
1359 case INDEX_op_and_i64:
1360 case INDEX_op_and_i32:
1361 if (const_args[2]) {
1362 if ((args[2] & 0xffff) == args[2])
1363 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1364 else if ((args[2] & 0xffff0000) == args[2])
1365 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1366 | ((args[2] >> 16) & 0xffff));
1367 else {
1368 tcg_out_movi (s, (opc == INDEX_op_and_i32
1369 ? TCG_TYPE_I32
1370 : TCG_TYPE_I64),
1371 0, args[2]);
1372 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1373 }
1374 }
1375 else
1376 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1377 break;
1378 case INDEX_op_or_i64:
1379 case INDEX_op_or_i32:
1380 if (const_args[2]) {
1381 if (args[2] & 0xffff) {
1382 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1383 | (args[2] & 0xffff));
1384 if (args[2] >> 16)
1385 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1386 | ((args[2] >> 16) & 0xffff));
1387 }
1388 else {
1389 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1390 | ((args[2] >> 16) & 0xffff));
1391 }
1392 }
1393 else
1394 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1395 break;
1396 case INDEX_op_xor_i64:
1397 case INDEX_op_xor_i32:
1398 if (const_args[2]) {
1399 if ((args[2] & 0xffff) == args[2])
1400 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1401 | (args[2] & 0xffff));
1402 else if ((args[2] & 0xffff0000) == args[2])
1403 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1404 | ((args[2] >> 16) & 0xffff));
1405 else {
1406 tcg_out_movi (s, (opc == INDEX_op_and_i32
1407 ? TCG_TYPE_I32
1408 : TCG_TYPE_I64),
1409 0, args[2]);
1410 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1411 }
1412 }
1413 else
1414 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1415 break;
1416
1417 case INDEX_op_mul_i32:
1418 if (const_args[2]) {
1419 if (args[2] == (int16_t) args[2])
1420 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1421 | (args[2] & 0xffff));
1422 else {
1423 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1424 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1425 }
1426 }
1427 else
1428 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1429 break;
1430
1431 case INDEX_op_div_i32:
1432 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1433 break;
1434
1435 case INDEX_op_divu_i32:
1436 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1437 break;
1438
1439 case INDEX_op_rem_i32:
1440 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1441 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1442 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1443 break;
1444
1445 case INDEX_op_remu_i32:
1446 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1447 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1448 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1449 break;
1450
1451 case INDEX_op_shl_i32:
1452 if (const_args[2]) {
1453 tcg_out32 (s, (RLWINM
1454 | RA (args[0])
1455 | RS (args[1])
1456 | SH (args[2])
1457 | MB (0)
1458 | ME (31 - args[2])
1459 )
1460 );
1461 }
1462 else
1463 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1464 break;
1465 case INDEX_op_shr_i32:
1466 if (const_args[2]) {
1467 tcg_out32 (s, (RLWINM
1468 | RA (args[0])
1469 | RS (args[1])
1470 | SH (32 - args[2])
1471 | MB (args[2])
1472 | ME (31)
1473 )
1474 );
1475 }
1476 else
1477 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1478 break;
1479 case INDEX_op_sar_i32:
1480 if (const_args[2])
1481 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1482 else
1483 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1484 break;
1485
1486 case INDEX_op_brcond_i32:
1487 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0);
1488 break;
1489
1490 case INDEX_op_brcond_i64:
1491 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1);
1492 break;
1493
1494 case INDEX_op_neg_i32:
1495 case INDEX_op_neg_i64:
1496 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1497 break;
1498
1499 case INDEX_op_not_i32:
1500 case INDEX_op_not_i64:
1501 tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
1502 break;
1503
1504 case INDEX_op_add_i64:
1505 if (const_args[2])
1506 ppc_addi64 (s, args[0], args[1], args[2]);
1507 else
1508 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1509 break;
1510 case INDEX_op_sub_i64:
1511 if (const_args[2])
1512 ppc_addi64 (s, args[0], args[1], -args[2]);
1513 else
1514 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1515 break;
1516
1517 case INDEX_op_shl_i64:
1518 if (const_args[2])
1519 tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]);
1520 else
1521 tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
1522 break;
1523 case INDEX_op_shr_i64:
1524 if (const_args[2])
1525 tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]);
1526 else
1527 tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
1528 break;
1529 case INDEX_op_sar_i64:
1530 if (const_args[2]) {
1531 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1532 tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh);
1533 }
1534 else
1535 tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
1536 break;
1537
1538 case INDEX_op_mul_i64:
1539 tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
1540 break;
1541 case INDEX_op_div_i64:
1542 tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
1543 break;
1544 case INDEX_op_divu_i64:
1545 tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
1546 break;
1547 case INDEX_op_rem_i64:
1548 tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
1549 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1550 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1551 break;
1552 case INDEX_op_remu_i64:
1553 tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
1554 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1555 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1556 break;
1557
1558 case INDEX_op_qemu_ld8u:
1559 tcg_out_qemu_ld (s, args, 0);
1560 break;
1561 case INDEX_op_qemu_ld8s:
1562 tcg_out_qemu_ld (s, args, 0 | 4);
1563 break;
1564 case INDEX_op_qemu_ld16u:
1565 tcg_out_qemu_ld (s, args, 1);
1566 break;
1567 case INDEX_op_qemu_ld16s:
1568 tcg_out_qemu_ld (s, args, 1 | 4);
1569 break;
1570 case INDEX_op_qemu_ld32:
1571 case INDEX_op_qemu_ld32u:
1572 tcg_out_qemu_ld (s, args, 2);
1573 break;
1574 case INDEX_op_qemu_ld32s:
1575 tcg_out_qemu_ld (s, args, 2 | 4);
1576 break;
1577 case INDEX_op_qemu_ld64:
1578 tcg_out_qemu_ld (s, args, 3);
1579 break;
1580 case INDEX_op_qemu_st8:
1581 tcg_out_qemu_st (s, args, 0);
1582 break;
1583 case INDEX_op_qemu_st16:
1584 tcg_out_qemu_st (s, args, 1);
1585 break;
1586 case INDEX_op_qemu_st32:
1587 tcg_out_qemu_st (s, args, 2);
1588 break;
1589 case INDEX_op_qemu_st64:
1590 tcg_out_qemu_st (s, args, 3);
1591 break;
1592
1593 case INDEX_op_ext8s_i32:
1594 case INDEX_op_ext8s_i64:
1595 c = EXTSB;
1596 goto gen_ext;
1597 case INDEX_op_ext16s_i32:
1598 case INDEX_op_ext16s_i64:
1599 c = EXTSH;
1600 goto gen_ext;
1601 case INDEX_op_ext32s_i64:
1602 c = EXTSW;
1603 goto gen_ext;
1604 gen_ext:
1605 tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
1606 break;
1607
1608 case INDEX_op_ext32u_i64:
1609 tcg_out_rld (s, RLDICL, args[0], args[1], 0, 32);
1610 break;
1611
1612 case INDEX_op_setcond_i32:
1613 tcg_out_setcond (s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1614 const_args[2]);
1615 break;
1616 case INDEX_op_setcond_i64:
1617 tcg_out_setcond (s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1618 const_args[2]);
1619 break;
1620
1621 default:
1622 tcg_dump_ops (s, stderr);
1623 tcg_abort ();
1624 }
1625 }
1626
1627 static const TCGTargetOpDef ppc_op_defs[] = {
1628 { INDEX_op_exit_tb, { } },
1629 { INDEX_op_goto_tb, { } },
1630 { INDEX_op_call, { "ri" } },
1631 { INDEX_op_jmp, { "ri" } },
1632 { INDEX_op_br, { } },
1633
1634 { INDEX_op_mov_i32, { "r", "r" } },
1635 { INDEX_op_mov_i64, { "r", "r" } },
1636 { INDEX_op_movi_i32, { "r" } },
1637 { INDEX_op_movi_i64, { "r" } },
1638
1639 { INDEX_op_ld8u_i32, { "r", "r" } },
1640 { INDEX_op_ld8s_i32, { "r", "r" } },
1641 { INDEX_op_ld16u_i32, { "r", "r" } },
1642 { INDEX_op_ld16s_i32, { "r", "r" } },
1643 { INDEX_op_ld_i32, { "r", "r" } },
1644 { INDEX_op_ld_i64, { "r", "r" } },
1645 { INDEX_op_st8_i32, { "r", "r" } },
1646 { INDEX_op_st8_i64, { "r", "r" } },
1647 { INDEX_op_st16_i32, { "r", "r" } },
1648 { INDEX_op_st16_i64, { "r", "r" } },
1649 { INDEX_op_st_i32, { "r", "r" } },
1650 { INDEX_op_st_i64, { "r", "r" } },
1651 { INDEX_op_st32_i64, { "r", "r" } },
1652
1653 { INDEX_op_ld8u_i64, { "r", "r" } },
1654 { INDEX_op_ld8s_i64, { "r", "r" } },
1655 { INDEX_op_ld16u_i64, { "r", "r" } },
1656 { INDEX_op_ld16s_i64, { "r", "r" } },
1657 { INDEX_op_ld32u_i64, { "r", "r" } },
1658 { INDEX_op_ld32s_i64, { "r", "r" } },
1659
1660 { INDEX_op_add_i32, { "r", "r", "ri" } },
1661 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1662 { INDEX_op_div_i32, { "r", "r", "r" } },
1663 { INDEX_op_divu_i32, { "r", "r", "r" } },
1664 { INDEX_op_rem_i32, { "r", "r", "r" } },
1665 { INDEX_op_remu_i32, { "r", "r", "r" } },
1666 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1667 { INDEX_op_and_i32, { "r", "r", "ri" } },
1668 { INDEX_op_or_i32, { "r", "r", "ri" } },
1669 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1670
1671 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1672 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1673 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1674
1675 { INDEX_op_brcond_i32, { "r", "ri" } },
1676 { INDEX_op_brcond_i64, { "r", "ri" } },
1677
1678 { INDEX_op_neg_i32, { "r", "r" } },
1679 { INDEX_op_not_i32, { "r", "r" } },
1680
1681 { INDEX_op_add_i64, { "r", "r", "ri" } },
1682 { INDEX_op_sub_i64, { "r", "r", "ri" } },
1683 { INDEX_op_and_i64, { "r", "r", "rZ" } },
1684 { INDEX_op_or_i64, { "r", "r", "rZ" } },
1685 { INDEX_op_xor_i64, { "r", "r", "rZ" } },
1686
1687 { INDEX_op_shl_i64, { "r", "r", "ri" } },
1688 { INDEX_op_shr_i64, { "r", "r", "ri" } },
1689 { INDEX_op_sar_i64, { "r", "r", "ri" } },
1690
1691 { INDEX_op_mul_i64, { "r", "r", "r" } },
1692 { INDEX_op_div_i64, { "r", "r", "r" } },
1693 { INDEX_op_divu_i64, { "r", "r", "r" } },
1694 { INDEX_op_rem_i64, { "r", "r", "r" } },
1695 { INDEX_op_remu_i64, { "r", "r", "r" } },
1696
1697 { INDEX_op_neg_i64, { "r", "r" } },
1698 { INDEX_op_not_i64, { "r", "r" } },
1699
1700 { INDEX_op_qemu_ld8u, { "r", "L" } },
1701 { INDEX_op_qemu_ld8s, { "r", "L" } },
1702 { INDEX_op_qemu_ld16u, { "r", "L" } },
1703 { INDEX_op_qemu_ld16s, { "r", "L" } },
1704 { INDEX_op_qemu_ld32, { "r", "L" } },
1705 { INDEX_op_qemu_ld32u, { "r", "L" } },
1706 { INDEX_op_qemu_ld32s, { "r", "L" } },
1707 { INDEX_op_qemu_ld64, { "r", "L" } },
1708
1709 { INDEX_op_qemu_st8, { "S", "S" } },
1710 { INDEX_op_qemu_st16, { "S", "S" } },
1711 { INDEX_op_qemu_st32, { "S", "S" } },
1712 { INDEX_op_qemu_st64, { "S", "S" } },
1713
1714 { INDEX_op_ext8s_i32, { "r", "r" } },
1715 { INDEX_op_ext16s_i32, { "r", "r" } },
1716 { INDEX_op_ext8s_i64, { "r", "r" } },
1717 { INDEX_op_ext16s_i64, { "r", "r" } },
1718 { INDEX_op_ext32s_i64, { "r", "r" } },
1719 { INDEX_op_ext32u_i64, { "r", "r" } },
1720
1721 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1722 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
1723
1724 { -1 },
1725 };
1726
1727 static void tcg_target_init (TCGContext *s)
1728 {
1729 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1730 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1731 tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
1732 (1 << TCG_REG_R0) |
1733 #ifdef __APPLE__
1734 (1 << TCG_REG_R2) |
1735 #endif
1736 (1 << TCG_REG_R3) |
1737 (1 << TCG_REG_R4) |
1738 (1 << TCG_REG_R5) |
1739 (1 << TCG_REG_R6) |
1740 (1 << TCG_REG_R7) |
1741 (1 << TCG_REG_R8) |
1742 (1 << TCG_REG_R9) |
1743 (1 << TCG_REG_R10) |
1744 (1 << TCG_REG_R11) |
1745 (1 << TCG_REG_R12)
1746 );
1747
1748 tcg_regset_clear (s->reserved_regs);
1749 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
1750 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
1751 #ifndef __APPLE__
1752 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
1753 #endif
1754 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
1755
1756 tcg_add_target_add_op_defs (ppc_op_defs);
1757 }
QEmu