hw/spapr.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  * Copyright (c) 2010 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27 #include "sysemu.h"
  28 #include "hw.h"
  29 #include "elf.h"
  30 #include "net.h"
  31 #include "blockdev.h"
  32
  33 #include "hw/boards.h"
  34 #include "hw/ppc.h"
  35 #include "hw/loader.h"
  36
  37 #include "hw/spapr.h"
  38 #include "hw/spapr_vio.h"
  39 #include "hw/xics.h"
  40
  41 #include "kvm.h"
  42 #include "kvm_ppc.h"
  43
  44 #include <libfdt.h>
  45
  46 #define KERNEL_LOAD_ADDR        0x00000000
  47 #define INITRD_LOAD_ADDR        0x02800000
  48 #define FDT_MAX_SIZE            0x10000
  49 #define RTAS_MAX_SIZE           0x10000
  50 #define FW_MAX_SIZE             0x400000
  51 #define FW_FILE_NAME            "slof.bin"
  52
  53 #define MIN_RAM_SLOF            512UL
  54
  55 #define TIMEBASE_FREQ           512000000ULL
  56
  57 #define MAX_CPUS                256
  58 #define XICS_IRQS               1024
  59
  60 #define PHANDLE_XICP            0x00001111
  61
  62 sPAPREnvironment *spapr;
  63
  64 static void *spapr_create_fdt_skel(const char *cpu_model,
  65                                    target_phys_addr_t initrd_base,
  66                                    target_phys_addr_t initrd_size,
  67                                    const char *boot_device,
  68                                    const char *kernel_cmdline,
  69                                    long hash_shift)
  70 {
  71     void *fdt;
  72     CPUState *env;
  73     uint64_t mem_reg_property[] = { 0, cpu_to_be64(ram_size) };
  74     uint32_t start_prop = cpu_to_be32(initrd_base);
  75     uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
  76     uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
  77     char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
  78         "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
  79     uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
  80     int i;
  81     char *modelname;
  82
  83 #define _FDT(exp) \
  84     do { \
  85         int ret = (exp);                                           \
  86         if (ret < 0) {                                             \
  87             fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
  88                     #exp, fdt_strerror(ret));                      \
  89             exit(1);                                               \
  90         }                                                          \
  91     } while (0)
  92
  93     fdt = g_malloc0(FDT_MAX_SIZE);
  94     _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
  95
  96     _FDT((fdt_finish_reservemap(fdt)));
  97
  98     /* Root node */
  99     _FDT((fdt_begin_node(fdt, "")));
 100     _FDT((fdt_property_string(fdt, "device_type", "chrp")));
 101     _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
 102
 103     _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
 104     _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
 105
 106     /* /chosen */
 107     _FDT((fdt_begin_node(fdt, "chosen")));
 108
 109     _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
 110     _FDT((fdt_property(fdt, "linux,initrd-start",
 111                        &start_prop, sizeof(start_prop))));
 112     _FDT((fdt_property(fdt, "linux,initrd-end",
 113                        &end_prop, sizeof(end_prop))));
 114     _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
 115
 116     _FDT((fdt_end_node(fdt)));
 117
 118     /* memory node */
 119     _FDT((fdt_begin_node(fdt, "memory@0")));
 120
 121     _FDT((fdt_property_string(fdt, "device_type", "memory")));
 122     _FDT((fdt_property(fdt, "reg",
 123                        mem_reg_property, sizeof(mem_reg_property))));
 124
 125     _FDT((fdt_end_node(fdt)));
 126
 127     /* cpus */
 128     _FDT((fdt_begin_node(fdt, "cpus")));
 129
 130     _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
 131     _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
 132
 133     modelname = g_strdup(cpu_model);
 134
 135     for (i = 0; i < strlen(modelname); i++) {
 136         modelname[i] = toupper(modelname[i]);
 137     }
 138
 139     for (env = first_cpu; env != NULL; env = env->next_cpu) {
 140         int index = env->cpu_index;
 141         uint32_t gserver_prop[] = {cpu_to_be32(index), 0}; /* HACK! */
 142         char *nodename;
 143         uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
 144                            0xffffffff, 0xffffffff};
 145         uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
 146         uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
 147
 148         if (asprintf(&nodename, "%s@%x", modelname, index) < 0) {
 149             fprintf(stderr, "Allocation failure\n");
 150             exit(1);
 151         }
 152
 153         _FDT((fdt_begin_node(fdt, nodename)));
 154
 155         free(nodename);
 156
 157         _FDT((fdt_property_cell(fdt, "reg", index)));
 158         _FDT((fdt_property_string(fdt, "device_type", "cpu")));
 159
 160         _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
 161         _FDT((fdt_property_cell(fdt, "dcache-block-size",
 162                                 env->dcache_line_size)));
 163         _FDT((fdt_property_cell(fdt, "icache-block-size",
 164                                 env->icache_line_size)));
 165         _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
 166         _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
 167         _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
 168         _FDT((fdt_property(fdt, "ibm,pft-size",
 169                            pft_size_prop, sizeof(pft_size_prop))));
 170         _FDT((fdt_property_string(fdt, "status", "okay")));
 171         _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
 172         _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", index)));
 173         _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
 174                            gserver_prop, sizeof(gserver_prop))));
 175
 176         if (env->mmu_model & POWERPC_MMU_1TSEG) {
 177             _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
 178                                segs, sizeof(segs))));
 179         }
 180
 181         _FDT((fdt_end_node(fdt)));
 182     }
 183
 184     g_free(modelname);
 185
 186     _FDT((fdt_end_node(fdt)));
 187
 188     /* RTAS */
 189     _FDT((fdt_begin_node(fdt, "rtas")));
 190
 191     _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
 192                        sizeof(hypertas_prop))));
 193
 194     _FDT((fdt_end_node(fdt)));
 195
 196     /* interrupt controller */
 197     _FDT((fdt_begin_node(fdt, "interrupt-controller")));
 198
 199     _FDT((fdt_property_string(fdt, "device_type",
 200                               "PowerPC-External-Interrupt-Presentation")));
 201     _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
 202     _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
 203     _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
 204                        interrupt_server_ranges_prop,
 205                        sizeof(interrupt_server_ranges_prop))));
 206     _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
 207     _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
 208     _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
 209
 210     _FDT((fdt_end_node(fdt)));
 211
 212     /* vdevice */
 213     _FDT((fdt_begin_node(fdt, "vdevice")));
 214
 215     _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
 216     _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
 217     _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
 218     _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
 219     _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
 220     _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
 221
 222     _FDT((fdt_end_node(fdt)));
 223
 224     _FDT((fdt_end_node(fdt))); /* close root node */
 225     _FDT((fdt_finish(fdt)));
 226
 227     return fdt;
 228 }
 229
 230 static void spapr_finalize_fdt(sPAPREnvironment *spapr,
 231                                target_phys_addr_t fdt_addr,
 232                                target_phys_addr_t rtas_addr,
 233                                target_phys_addr_t rtas_size)
 234 {
 235     int ret;
 236     void *fdt;
 237
 238     fdt = g_malloc(FDT_MAX_SIZE);
 239
 240     /* open out the base tree into a temp buffer for the final tweaks */
 241     _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
 242
 243     ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
 244     if (ret < 0) {
 245         fprintf(stderr, "couldn't setup vio devices in fdt\n");
 246         exit(1);
 247     }
 248
 249     /* RTAS */
 250     ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
 251     if (ret < 0) {
 252         fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
 253     }
 254
 255     _FDT((fdt_pack(fdt)));
 256
 257     cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
 258
 259     g_free(fdt);
 260 }
 261
 262 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
 263 {
 264     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
 265 }
 266
 267 static void emulate_spapr_hypercall(CPUState *env)
 268 {
 269     env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
 270 }
 271
 272 static void spapr_reset(void *opaque)
 273 {
 274     sPAPREnvironment *spapr = (sPAPREnvironment *)opaque;
 275
 276     fprintf(stderr, "sPAPR reset\n");
 277
 278     /* flush out the hash table */
 279     memset(spapr->htab, 0, spapr->htab_size);
 280
 281     /* Load the fdt */
 282     spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
 283                        spapr->rtas_size);
 284
 285     /* Set up the entry state */
 286     first_cpu->gpr[3] = spapr->fdt_addr;
 287     first_cpu->gpr[5] = 0;
 288     first_cpu->halted = 0;
 289     first_cpu->nip = spapr->entry_point;
 290
 291 }
 292
 293 /* pSeries LPAR / sPAPR hardware init */
 294 static void ppc_spapr_init(ram_addr_t ram_size,
 295                            const char *boot_device,
 296                            const char *kernel_filename,
 297                            const char *kernel_cmdline,
 298                            const char *initrd_filename,
 299                            const char *cpu_model)
 300 {
 301     CPUState *env;
 302     int i;
 303     ram_addr_t ram_offset;
 304     uint32_t initrd_base;
 305     long kernel_size, initrd_size, fw_size;
 306     long pteg_shift = 17;
 307     char *filename;
 308
 309     spapr = g_malloc(sizeof(*spapr));
 310     cpu_ppc_hypercall = emulate_spapr_hypercall;
 311
 312     /* We place the device tree just below either the top of RAM, or
 313      * 2GB, so that it can be processed with 32-bit code if
 314      * necessary */
 315     spapr->fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
 316     spapr->rtas_addr = spapr->fdt_addr - RTAS_MAX_SIZE;
 317
 318     /* init CPUs */
 319     if (cpu_model == NULL) {
 320         cpu_model = "POWER7";
 321     }
 322     for (i = 0; i < smp_cpus; i++) {
 323         env = cpu_init(cpu_model);
 324
 325         if (!env) {
 326             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 327             exit(1);
 328         }
 329         /* Set time-base frequency to 512 MHz */
 330         cpu_ppc_tb_init(env, TIMEBASE_FREQ);
 331         qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
 332
 333         env->hreset_vector = 0x60;
 334         env->hreset_excp_prefix = 0;
 335         env->gpr[3] = env->cpu_index;
 336     }
 337
 338     /* allocate RAM */
 339     spapr->ram_limit = ram_size;
 340     ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", spapr->ram_limit);
 341     cpu_register_physical_memory(0, ram_size, ram_offset);
 342
 343     /* allocate hash page table.  For now we always make this 16mb,
 344      * later we should probably make it scale to the size of guest
 345      * RAM */
 346     spapr->htab_size = 1ULL << (pteg_shift + 7);
 347     spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size);
 348
 349     for (env = first_cpu; env != NULL; env = env->next_cpu) {
 350         env->external_htab = spapr->htab;
 351         env->htab_base = -1;
 352         env->htab_mask = spapr->htab_size - 1;
 353
 354         /* Tell KVM that we're in PAPR mode */
 355         env->spr[SPR_SDR1] = (unsigned long)spapr->htab |
 356                              ((pteg_shift + 7) - 18);
 357         env->spr[SPR_HIOR] = 0;
 358
 359         if (kvm_enabled()) {
 360             kvmppc_set_papr(env);
 361         }
 362     }
 363
 364     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
 365     spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
 366                                            ram_size - spapr->rtas_addr);
 367     if (spapr->rtas_size < 0) {
 368         hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
 369         exit(1);
 370     }
 371     g_free(filename);
 372
 373     /* Set up Interrupt Controller */
 374     spapr->icp = xics_system_init(XICS_IRQS);
 375
 376     /* Set up VIO bus */
 377     spapr->vio_bus = spapr_vio_bus_init();
 378
 379     for (i = 0; i < MAX_SERIAL_PORTS; i++) {
 380         if (serial_hds[i]) {
 381             spapr_vty_create(spapr->vio_bus, SPAPR_VTY_BASE_ADDRESS + i,
 382                              serial_hds[i]);
 383         }
 384     }
 385
 386     for (i = 0; i < nb_nics; i++) {
 387         NICInfo *nd = &nd_table[i];
 388
 389         if (!nd->model) {
 390             nd->model = g_strdup("ibmveth");
 391         }
 392
 393         if (strcmp(nd->model, "ibmveth") == 0) {
 394             spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd);
 395         } else {
 396             fprintf(stderr, "pSeries (sPAPR) platform does not support "
 397                     "NIC model '%s' (only ibmveth is supported)\n",
 398                     nd->model);
 399             exit(1);
 400         }
 401     }
 402
 403     for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
 404         spapr_vscsi_create(spapr->vio_bus, 0x2000 + i);
 405     }
 406
 407     if (kernel_filename) {
 408         uint64_t lowaddr = 0;
 409
 410         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 411                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
 412         if (kernel_size < 0) {
 413             kernel_size = load_image_targphys(kernel_filename,
 414                                               KERNEL_LOAD_ADDR,
 415                                               ram_size - KERNEL_LOAD_ADDR);
 416         }
 417         if (kernel_size < 0) {
 418             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 419                     kernel_filename);
 420             exit(1);
 421         }
 422
 423         /* load initrd */
 424         if (initrd_filename) {
 425             initrd_base = INITRD_LOAD_ADDR;
 426             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 427                                               ram_size - initrd_base);
 428             if (initrd_size < 0) {
 429                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 430                         initrd_filename);
 431                 exit(1);
 432             }
 433         } else {
 434             initrd_base = 0;
 435             initrd_size = 0;
 436         }
 437
 438         spapr->entry_point = KERNEL_LOAD_ADDR;
 439     } else {
 440         if (ram_size < (MIN_RAM_SLOF << 20)) {
 441             fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
 442                     "%ldM guest RAM\n", MIN_RAM_SLOF);
 443             exit(1);
 444         }
 445         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME);
 446         fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
 447         if (fw_size < 0) {
 448             hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
 449             exit(1);
 450         }
 451         g_free(filename);
 452         spapr->entry_point = 0x100;
 453         initrd_base = 0;
 454         initrd_size = 0;
 455
 456         /* SLOF will startup the secondary CPUs using RTAS,
 457            rather than expecting a kexec() style entry */
 458         for (env = first_cpu; env != NULL; env = env->next_cpu) {
 459             env->halted = 1;
 460         }
 461     }
 462
 463     /* Prepare the device tree */
 464     spapr->fdt_skel = spapr_create_fdt_skel(cpu_model,
 465                                             initrd_base, initrd_size,
 466                                             boot_device, kernel_cmdline,
 467                                             pteg_shift + 7);
 468     assert(spapr->fdt_skel != NULL);
 469
 470     qemu_register_reset(spapr_reset, spapr);
 471 }
 472
 473 static QEMUMachine spapr_machine = {
 474     .name = "pseries",
 475     .desc = "pSeries Logical Partition (PAPR compliant)",
 476     .init = ppc_spapr_init,
 477     .max_cpus = MAX_CPUS,
 478     .no_vga = 1,
 479     .no_parallel = 1,
 480     .use_scsi = 1,
 481 };
 482
 483 static void spapr_machine_init(void)
 484 {
 485     qemu_register_machine(&spapr_machine);
 486 }
 487
 488 machine_init(spapr_machine_init);