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dataplane: allow virtio-1 devices
[qemu.git] / target-s390x / translate.c
blobfbffd3066dfab5e2f1b7f6fe5ce7ce6dc3de64f2
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36 #include "exec/cpu_ldst.h"
37
38 /* global register indexes */
39 static TCGv_ptr cpu_env;
40
41 #include "exec/gen-icount.h"
42 #include "exec/helper-proto.h"
43 #include "exec/helper-gen.h"
44
45 #include "trace-tcg.h"
46
47
48 /* Information that (most) every instruction needs to manipulate. */
49 typedef struct DisasContext DisasContext;
50 typedef struct DisasInsn DisasInsn;
51 typedef struct DisasFields DisasFields;
52
53 struct DisasContext {
54 struct TranslationBlock *tb;
55 const DisasInsn *insn;
56 DisasFields *fields;
57 uint64_t pc, next_pc;
58 enum cc_op cc_op;
59 bool singlestep_enabled;
60 };
61
62 /* Information carried about a condition to be evaluated. */
63 typedef struct {
64 TCGCond cond:8;
65 bool is_64;
66 bool g1;
67 bool g2;
68 union {
69 struct { TCGv_i64 a, b; } s64;
70 struct { TCGv_i32 a, b; } s32;
71 } u;
72 } DisasCompare;
73
74 #define DISAS_EXCP 4
75
76 #ifdef DEBUG_INLINE_BRANCHES
77 static uint64_t inline_branch_hit[CC_OP_MAX];
78 static uint64_t inline_branch_miss[CC_OP_MAX];
79 #endif
80
81 static uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
82 {
83 if (!(s->tb->flags & FLAG_MASK_64)) {
84 if (s->tb->flags & FLAG_MASK_32) {
85 return pc | 0x80000000;
86 }
87 }
88 return pc;
89 }
90
91 void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
92 int flags)
93 {
94 S390CPU *cpu = S390_CPU(cs);
95 CPUS390XState *env = &cpu->env;
96 int i;
97
98 if (env->cc_op > 3) {
99 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
100 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
101 } else {
102 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
103 env->psw.mask, env->psw.addr, env->cc_op);
104 }
105
106 for (i = 0; i < 16; i++) {
107 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
108 if ((i % 4) == 3) {
109 cpu_fprintf(f, "\n");
110 } else {
111 cpu_fprintf(f, " ");
112 }
113 }
114
115 for (i = 0; i < 16; i++) {
116 cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll);
117 if ((i % 4) == 3) {
118 cpu_fprintf(f, "\n");
119 } else {
120 cpu_fprintf(f, " ");
121 }
122 }
123
124 for (i = 0; i < 32; i++) {
125 cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i,
126 env->vregs[i][0].ll, env->vregs[i][1].ll);
127 cpu_fprintf(f, (i % 2) ? " " : "\n");
128 }
129
130 #ifndef CONFIG_USER_ONLY
131 for (i = 0; i < 16; i++) {
132 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
133 if ((i % 4) == 3) {
134 cpu_fprintf(f, "\n");
135 } else {
136 cpu_fprintf(f, " ");
137 }
138 }
139 #endif
140
141 #ifdef DEBUG_INLINE_BRANCHES
142 for (i = 0; i < CC_OP_MAX; i++) {
143 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
144 inline_branch_miss[i], inline_branch_hit[i]);
145 }
146 #endif
147
148 cpu_fprintf(f, "\n");
149 }
150
151 static TCGv_i64 psw_addr;
152 static TCGv_i64 psw_mask;
153
154 static TCGv_i32 cc_op;
155 static TCGv_i64 cc_src;
156 static TCGv_i64 cc_dst;
157 static TCGv_i64 cc_vr;
158
159 static char cpu_reg_names[32][4];
160 static TCGv_i64 regs[16];
161 static TCGv_i64 fregs[16];
162
163 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
164
165 void s390x_translate_init(void)
166 {
167 int i;
168
169 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
170 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
171 offsetof(CPUS390XState, psw.addr),
172 "psw_addr");
173 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
174 offsetof(CPUS390XState, psw.mask),
175 "psw_mask");
176
177 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
178 "cc_op");
179 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
180 "cc_src");
181 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
182 "cc_dst");
183 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
184 "cc_vr");
185
186 for (i = 0; i < 16; i++) {
187 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
188 regs[i] = tcg_global_mem_new(TCG_AREG0,
189 offsetof(CPUS390XState, regs[i]),
190 cpu_reg_names[i]);
191 }
192
193 for (i = 0; i < 16; i++) {
194 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
195 fregs[i] = tcg_global_mem_new(TCG_AREG0,
196 offsetof(CPUS390XState, vregs[i][0].d),
197 cpu_reg_names[i + 16]);
198 }
199 }
200
201 static TCGv_i64 load_reg(int reg)
202 {
203 TCGv_i64 r = tcg_temp_new_i64();
204 tcg_gen_mov_i64(r, regs[reg]);
205 return r;
206 }
207
208 static TCGv_i64 load_freg32_i64(int reg)
209 {
210 TCGv_i64 r = tcg_temp_new_i64();
211 tcg_gen_shri_i64(r, fregs[reg], 32);
212 return r;
213 }
214
215 static void store_reg(int reg, TCGv_i64 v)
216 {
217 tcg_gen_mov_i64(regs[reg], v);
218 }
219
220 static void store_freg(int reg, TCGv_i64 v)
221 {
222 tcg_gen_mov_i64(fregs[reg], v);
223 }
224
225 static void store_reg32_i64(int reg, TCGv_i64 v)
226 {
227 /* 32 bit register writes keep the upper half */
228 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
229 }
230
231 static void store_reg32h_i64(int reg, TCGv_i64 v)
232 {
233 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
234 }
235
236 static void store_freg32_i64(int reg, TCGv_i64 v)
237 {
238 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
239 }
240
241 static void return_low128(TCGv_i64 dest)
242 {
243 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
244 }
245
246 static void update_psw_addr(DisasContext *s)
247 {
248 /* psw.addr */
249 tcg_gen_movi_i64(psw_addr, s->pc);
250 }
251
252 static void update_cc_op(DisasContext *s)
253 {
254 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
255 tcg_gen_movi_i32(cc_op, s->cc_op);
256 }
257 }
258
259 static void potential_page_fault(DisasContext *s)
260 {
261 update_psw_addr(s);
262 update_cc_op(s);
263 }
264
265 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
266 {
267 return (uint64_t)cpu_lduw_code(env, pc);
268 }
269
270 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
271 {
272 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
273 }
274
275 static int get_mem_index(DisasContext *s)
276 {
277 switch (s->tb->flags & FLAG_MASK_ASC) {
278 case PSW_ASC_PRIMARY >> 32:
279 return 0;
280 case PSW_ASC_SECONDARY >> 32:
281 return 1;
282 case PSW_ASC_HOME >> 32:
283 return 2;
284 default:
285 tcg_abort();
286 break;
287 }
288 }
289
290 static void gen_exception(int excp)
291 {
292 TCGv_i32 tmp = tcg_const_i32(excp);
293 gen_helper_exception(cpu_env, tmp);
294 tcg_temp_free_i32(tmp);
295 }
296
297 static void gen_program_exception(DisasContext *s, int code)
298 {
299 TCGv_i32 tmp;
300
301 /* Remember what pgm exeption this was. */
302 tmp = tcg_const_i32(code);
303 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
304 tcg_temp_free_i32(tmp);
305
306 tmp = tcg_const_i32(s->next_pc - s->pc);
307 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
308 tcg_temp_free_i32(tmp);
309
310 /* Advance past instruction. */
311 s->pc = s->next_pc;
312 update_psw_addr(s);
313
314 /* Save off cc. */
315 update_cc_op(s);
316
317 /* Trigger exception. */
318 gen_exception(EXCP_PGM);
319 }
320
321 static inline void gen_illegal_opcode(DisasContext *s)
322 {
323 gen_program_exception(s, PGM_SPECIFICATION);
324 }
325
326 #ifndef CONFIG_USER_ONLY
327 static void check_privileged(DisasContext *s)
328 {
329 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
330 gen_program_exception(s, PGM_PRIVILEGED);
331 }
332 }
333 #endif
334
335 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
336 {
337 TCGv_i64 tmp = tcg_temp_new_i64();
338 bool need_31 = !(s->tb->flags & FLAG_MASK_64);
339
340 /* Note that d2 is limited to 20 bits, signed. If we crop negative
341 displacements early we create larger immedate addends. */
342
343 /* Note that addi optimizes the imm==0 case. */
344 if (b2 && x2) {
345 tcg_gen_add_i64(tmp, regs[b2], regs[x2]);
346 tcg_gen_addi_i64(tmp, tmp, d2);
347 } else if (b2) {
348 tcg_gen_addi_i64(tmp, regs[b2], d2);
349 } else if (x2) {
350 tcg_gen_addi_i64(tmp, regs[x2], d2);
351 } else {
352 if (need_31) {
353 d2 &= 0x7fffffff;
354 need_31 = false;
355 }
356 tcg_gen_movi_i64(tmp, d2);
357 }
358 if (need_31) {
359 tcg_gen_andi_i64(tmp, tmp, 0x7fffffff);
360 }
361
362 return tmp;
363 }
364
365 static inline bool live_cc_data(DisasContext *s)
366 {
367 return (s->cc_op != CC_OP_DYNAMIC
368 && s->cc_op != CC_OP_STATIC
369 && s->cc_op > 3);
370 }
371
372 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
373 {
374 if (live_cc_data(s)) {
375 tcg_gen_discard_i64(cc_src);
376 tcg_gen_discard_i64(cc_dst);
377 tcg_gen_discard_i64(cc_vr);
378 }
379 s->cc_op = CC_OP_CONST0 + val;
380 }
381
382 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
383 {
384 if (live_cc_data(s)) {
385 tcg_gen_discard_i64(cc_src);
386 tcg_gen_discard_i64(cc_vr);
387 }
388 tcg_gen_mov_i64(cc_dst, dst);
389 s->cc_op = op;
390 }
391
392 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
393 TCGv_i64 dst)
394 {
395 if (live_cc_data(s)) {
396 tcg_gen_discard_i64(cc_vr);
397 }
398 tcg_gen_mov_i64(cc_src, src);
399 tcg_gen_mov_i64(cc_dst, dst);
400 s->cc_op = op;
401 }
402
403 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
404 TCGv_i64 dst, TCGv_i64 vr)
405 {
406 tcg_gen_mov_i64(cc_src, src);
407 tcg_gen_mov_i64(cc_dst, dst);
408 tcg_gen_mov_i64(cc_vr, vr);
409 s->cc_op = op;
410 }
411
412 static void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
413 {
414 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
415 }
416
417 static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
418 {
419 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
420 }
421
422 static void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
423 {
424 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
425 }
426
427 static void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
428 {
429 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
430 }
431
432 /* CC value is in env->cc_op */
433 static void set_cc_static(DisasContext *s)
434 {
435 if (live_cc_data(s)) {
436 tcg_gen_discard_i64(cc_src);
437 tcg_gen_discard_i64(cc_dst);
438 tcg_gen_discard_i64(cc_vr);
439 }
440 s->cc_op = CC_OP_STATIC;
441 }
442
443 /* calculates cc into cc_op */
444 static void gen_op_calc_cc(DisasContext *s)
445 {
446 TCGv_i32 local_cc_op;
447 TCGv_i64 dummy;
448
449 TCGV_UNUSED_I32(local_cc_op);
450 TCGV_UNUSED_I64(dummy);
451 switch (s->cc_op) {
452 default:
453 dummy = tcg_const_i64(0);
454 /* FALLTHRU */
455 case CC_OP_ADD_64:
456 case CC_OP_ADDU_64:
457 case CC_OP_ADDC_64:
458 case CC_OP_SUB_64:
459 case CC_OP_SUBU_64:
460 case CC_OP_SUBB_64:
461 case CC_OP_ADD_32:
462 case CC_OP_ADDU_32:
463 case CC_OP_ADDC_32:
464 case CC_OP_SUB_32:
465 case CC_OP_SUBU_32:
466 case CC_OP_SUBB_32:
467 local_cc_op = tcg_const_i32(s->cc_op);
468 break;
469 case CC_OP_CONST0:
470 case CC_OP_CONST1:
471 case CC_OP_CONST2:
472 case CC_OP_CONST3:
473 case CC_OP_STATIC:
474 case CC_OP_DYNAMIC:
475 break;
476 }
477
478 switch (s->cc_op) {
479 case CC_OP_CONST0:
480 case CC_OP_CONST1:
481 case CC_OP_CONST2:
482 case CC_OP_CONST3:
483 /* s->cc_op is the cc value */
484 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
485 break;
486 case CC_OP_STATIC:
487 /* env->cc_op already is the cc value */
488 break;
489 case CC_OP_NZ:
490 case CC_OP_ABS_64:
491 case CC_OP_NABS_64:
492 case CC_OP_ABS_32:
493 case CC_OP_NABS_32:
494 case CC_OP_LTGT0_32:
495 case CC_OP_LTGT0_64:
496 case CC_OP_COMP_32:
497 case CC_OP_COMP_64:
498 case CC_OP_NZ_F32:
499 case CC_OP_NZ_F64:
500 case CC_OP_FLOGR:
501 /* 1 argument */
502 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
503 break;
504 case CC_OP_ICM:
505 case CC_OP_LTGT_32:
506 case CC_OP_LTGT_64:
507 case CC_OP_LTUGTU_32:
508 case CC_OP_LTUGTU_64:
509 case CC_OP_TM_32:
510 case CC_OP_TM_64:
511 case CC_OP_SLA_32:
512 case CC_OP_SLA_64:
513 case CC_OP_NZ_F128:
514 /* 2 arguments */
515 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
516 break;
517 case CC_OP_ADD_64:
518 case CC_OP_ADDU_64:
519 case CC_OP_ADDC_64:
520 case CC_OP_SUB_64:
521 case CC_OP_SUBU_64:
522 case CC_OP_SUBB_64:
523 case CC_OP_ADD_32:
524 case CC_OP_ADDU_32:
525 case CC_OP_ADDC_32:
526 case CC_OP_SUB_32:
527 case CC_OP_SUBU_32:
528 case CC_OP_SUBB_32:
529 /* 3 arguments */
530 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
531 break;
532 case CC_OP_DYNAMIC:
533 /* unknown operation - assume 3 arguments and cc_op in env */
534 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
535 break;
536 default:
537 tcg_abort();
538 }
539
540 if (!TCGV_IS_UNUSED_I32(local_cc_op)) {
541 tcg_temp_free_i32(local_cc_op);
542 }
543 if (!TCGV_IS_UNUSED_I64(dummy)) {
544 tcg_temp_free_i64(dummy);
545 }
546
547 /* We now have cc in cc_op as constant */
548 set_cc_static(s);
549 }
550
551 static int use_goto_tb(DisasContext *s, uint64_t dest)
552 {
553 /* NOTE: we handle the case where the TB spans two pages here */
554 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
555 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
556 && !s->singlestep_enabled
557 && !(s->tb->cflags & CF_LAST_IO));
558 }
559
560 static void account_noninline_branch(DisasContext *s, int cc_op)
561 {
562 #ifdef DEBUG_INLINE_BRANCHES
563 inline_branch_miss[cc_op]++;
564 #endif
565 }
566
567 static void account_inline_branch(DisasContext *s, int cc_op)
568 {
569 #ifdef DEBUG_INLINE_BRANCHES
570 inline_branch_hit[cc_op]++;
571 #endif
572 }
573
574 /* Table of mask values to comparison codes, given a comparison as input.
575 For such, CC=3 should not be possible. */
576 static const TCGCond ltgt_cond[16] = {
577 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
578 TCG_COND_GT, TCG_COND_GT, /* | | GT | x */
579 TCG_COND_LT, TCG_COND_LT, /* | LT | | x */
580 TCG_COND_NE, TCG_COND_NE, /* | LT | GT | x */
581 TCG_COND_EQ, TCG_COND_EQ, /* EQ | | | x */
582 TCG_COND_GE, TCG_COND_GE, /* EQ | | GT | x */
583 TCG_COND_LE, TCG_COND_LE, /* EQ | LT | | x */
584 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
585 };
586
587 /* Table of mask values to comparison codes, given a logic op as input.
588 For such, only CC=0 and CC=1 should be possible. */
589 static const TCGCond nz_cond[16] = {
590 TCG_COND_NEVER, TCG_COND_NEVER, /* | | x | x */
591 TCG_COND_NEVER, TCG_COND_NEVER,
592 TCG_COND_NE, TCG_COND_NE, /* | NE | x | x */
593 TCG_COND_NE, TCG_COND_NE,
594 TCG_COND_EQ, TCG_COND_EQ, /* EQ | | x | x */
595 TCG_COND_EQ, TCG_COND_EQ,
596 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | NE | x | x */
597 TCG_COND_ALWAYS, TCG_COND_ALWAYS,
598 };
599
600 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
601 details required to generate a TCG comparison. */
602 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
603 {
604 TCGCond cond;
605 enum cc_op old_cc_op = s->cc_op;
606
607 if (mask == 15 || mask == 0) {
608 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
609 c->u.s32.a = cc_op;
610 c->u.s32.b = cc_op;
611 c->g1 = c->g2 = true;
612 c->is_64 = false;
613 return;
614 }
615
616 /* Find the TCG condition for the mask + cc op. */
617 switch (old_cc_op) {
618 case CC_OP_LTGT0_32:
619 case CC_OP_LTGT0_64:
620 case CC_OP_LTGT_32:
621 case CC_OP_LTGT_64:
622 cond = ltgt_cond[mask];
623 if (cond == TCG_COND_NEVER) {
624 goto do_dynamic;
625 }
626 account_inline_branch(s, old_cc_op);
627 break;
628
629 case CC_OP_LTUGTU_32:
630 case CC_OP_LTUGTU_64:
631 cond = tcg_unsigned_cond(ltgt_cond[mask]);
632 if (cond == TCG_COND_NEVER) {
633 goto do_dynamic;
634 }
635 account_inline_branch(s, old_cc_op);
636 break;
637
638 case CC_OP_NZ:
639 cond = nz_cond[mask];
640 if (cond == TCG_COND_NEVER) {
641 goto do_dynamic;
642 }
643 account_inline_branch(s, old_cc_op);
644 break;
645
646 case CC_OP_TM_32:
647 case CC_OP_TM_64:
648 switch (mask) {
649 case 8:
650 cond = TCG_COND_EQ;
651 break;
652 case 4 | 2 | 1:
653 cond = TCG_COND_NE;
654 break;
655 default:
656 goto do_dynamic;
657 }
658 account_inline_branch(s, old_cc_op);
659 break;
660
661 case CC_OP_ICM:
662 switch (mask) {
663 case 8:
664 cond = TCG_COND_EQ;
665 break;
666 case 4 | 2 | 1:
667 case 4 | 2:
668 cond = TCG_COND_NE;
669 break;
670 default:
671 goto do_dynamic;
672 }
673 account_inline_branch(s, old_cc_op);
674 break;
675
676 case CC_OP_FLOGR:
677 switch (mask & 0xa) {
678 case 8: /* src == 0 -> no one bit found */
679 cond = TCG_COND_EQ;
680 break;
681 case 2: /* src != 0 -> one bit found */
682 cond = TCG_COND_NE;
683 break;
684 default:
685 goto do_dynamic;
686 }
687 account_inline_branch(s, old_cc_op);
688 break;
689
690 case CC_OP_ADDU_32:
691 case CC_OP_ADDU_64:
692 switch (mask) {
693 case 8 | 2: /* vr == 0 */
694 cond = TCG_COND_EQ;
695 break;
696 case 4 | 1: /* vr != 0 */
697 cond = TCG_COND_NE;
698 break;
699 case 8 | 4: /* no carry -> vr >= src */
700 cond = TCG_COND_GEU;
701 break;
702 case 2 | 1: /* carry -> vr < src */
703 cond = TCG_COND_LTU;
704 break;
705 default:
706 goto do_dynamic;
707 }
708 account_inline_branch(s, old_cc_op);
709 break;
710
711 case CC_OP_SUBU_32:
712 case CC_OP_SUBU_64:
713 /* Note that CC=0 is impossible; treat it as dont-care. */
714 switch (mask & 7) {
715 case 2: /* zero -> op1 == op2 */
716 cond = TCG_COND_EQ;
717 break;
718 case 4 | 1: /* !zero -> op1 != op2 */
719 cond = TCG_COND_NE;
720 break;
721 case 4: /* borrow (!carry) -> op1 < op2 */
722 cond = TCG_COND_LTU;
723 break;
724 case 2 | 1: /* !borrow (carry) -> op1 >= op2 */
725 cond = TCG_COND_GEU;
726 break;
727 default:
728 goto do_dynamic;
729 }
730 account_inline_branch(s, old_cc_op);
731 break;
732
733 default:
734 do_dynamic:
735 /* Calculate cc value. */
736 gen_op_calc_cc(s);
737 /* FALLTHRU */
738
739 case CC_OP_STATIC:
740 /* Jump based on CC. We'll load up the real cond below;
741 the assignment here merely avoids a compiler warning. */
742 account_noninline_branch(s, old_cc_op);
743 old_cc_op = CC_OP_STATIC;
744 cond = TCG_COND_NEVER;
745 break;
746 }
747
748 /* Load up the arguments of the comparison. */
749 c->is_64 = true;
750 c->g1 = c->g2 = false;
751 switch (old_cc_op) {
752 case CC_OP_LTGT0_32:
753 c->is_64 = false;
754 c->u.s32.a = tcg_temp_new_i32();
755 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
756 c->u.s32.b = tcg_const_i32(0);
757 break;
758 case CC_OP_LTGT_32:
759 case CC_OP_LTUGTU_32:
760 case CC_OP_SUBU_32:
761 c->is_64 = false;
762 c->u.s32.a = tcg_temp_new_i32();
763 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
764 c->u.s32.b = tcg_temp_new_i32();
765 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
766 break;
767
768 case CC_OP_LTGT0_64:
769 case CC_OP_NZ:
770 case CC_OP_FLOGR:
771 c->u.s64.a = cc_dst;
772 c->u.s64.b = tcg_const_i64(0);
773 c->g1 = true;
774 break;
775 case CC_OP_LTGT_64:
776 case CC_OP_LTUGTU_64:
777 case CC_OP_SUBU_64:
778 c->u.s64.a = cc_src;
779 c->u.s64.b = cc_dst;
780 c->g1 = c->g2 = true;
781 break;
782
783 case CC_OP_TM_32:
784 case CC_OP_TM_64:
785 case CC_OP_ICM:
786 c->u.s64.a = tcg_temp_new_i64();
787 c->u.s64.b = tcg_const_i64(0);
788 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
789 break;
790
791 case CC_OP_ADDU_32:
792 c->is_64 = false;
793 c->u.s32.a = tcg_temp_new_i32();
794 c->u.s32.b = tcg_temp_new_i32();
795 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_vr);
796 if (cond == TCG_COND_EQ || cond == TCG_COND_NE) {
797 tcg_gen_movi_i32(c->u.s32.b, 0);
798 } else {
799 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_src);
800 }
801 break;
802
803 case CC_OP_ADDU_64:
804 c->u.s64.a = cc_vr;
805 c->g1 = true;
806 if (cond == TCG_COND_EQ || cond == TCG_COND_NE) {
807 c->u.s64.b = tcg_const_i64(0);
808 } else {
809 c->u.s64.b = cc_src;
810 c->g2 = true;
811 }
812 break;
813
814 case CC_OP_STATIC:
815 c->is_64 = false;
816 c->u.s32.a = cc_op;
817 c->g1 = true;
818 switch (mask) {
819 case 0x8 | 0x4 | 0x2: /* cc != 3 */
820 cond = TCG_COND_NE;
821 c->u.s32.b = tcg_const_i32(3);
822 break;
823 case 0x8 | 0x4 | 0x1: /* cc != 2 */
824 cond = TCG_COND_NE;
825 c->u.s32.b = tcg_const_i32(2);
826 break;
827 case 0x8 | 0x2 | 0x1: /* cc != 1 */
828 cond = TCG_COND_NE;
829 c->u.s32.b = tcg_const_i32(1);
830 break;
831 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
832 cond = TCG_COND_EQ;
833 c->g1 = false;
834 c->u.s32.a = tcg_temp_new_i32();
835 c->u.s32.b = tcg_const_i32(0);
836 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
837 break;
838 case 0x8 | 0x4: /* cc < 2 */
839 cond = TCG_COND_LTU;
840 c->u.s32.b = tcg_const_i32(2);
841 break;
842 case 0x8: /* cc == 0 */
843 cond = TCG_COND_EQ;
844 c->u.s32.b = tcg_const_i32(0);
845 break;
846 case 0x4 | 0x2 | 0x1: /* cc != 0 */
847 cond = TCG_COND_NE;
848 c->u.s32.b = tcg_const_i32(0);
849 break;
850 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
851 cond = TCG_COND_NE;
852 c->g1 = false;
853 c->u.s32.a = tcg_temp_new_i32();
854 c->u.s32.b = tcg_const_i32(0);
855 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
856 break;
857 case 0x4: /* cc == 1 */
858 cond = TCG_COND_EQ;
859 c->u.s32.b = tcg_const_i32(1);
860 break;
861 case 0x2 | 0x1: /* cc > 1 */
862 cond = TCG_COND_GTU;
863 c->u.s32.b = tcg_const_i32(1);
864 break;
865 case 0x2: /* cc == 2 */
866 cond = TCG_COND_EQ;
867 c->u.s32.b = tcg_const_i32(2);
868 break;
869 case 0x1: /* cc == 3 */
870 cond = TCG_COND_EQ;
871 c->u.s32.b = tcg_const_i32(3);
872 break;
873 default:
874 /* CC is masked by something else: (8 >> cc) & mask. */
875 cond = TCG_COND_NE;
876 c->g1 = false;
877 c->u.s32.a = tcg_const_i32(8);
878 c->u.s32.b = tcg_const_i32(0);
879 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
880 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
881 break;
882 }
883 break;
884
885 default:
886 abort();
887 }
888 c->cond = cond;
889 }
890
891 static void free_compare(DisasCompare *c)
892 {
893 if (!c->g1) {
894 if (c->is_64) {
895 tcg_temp_free_i64(c->u.s64.a);
896 } else {
897 tcg_temp_free_i32(c->u.s32.a);
898 }
899 }
900 if (!c->g2) {
901 if (c->is_64) {
902 tcg_temp_free_i64(c->u.s64.b);
903 } else {
904 tcg_temp_free_i32(c->u.s32.b);
905 }
906 }
907 }
908
909 /* ====================================================================== */
910 /* Define the insn format enumeration. */
911 #define F0(N) FMT_##N,
912 #define F1(N, X1) F0(N)
913 #define F2(N, X1, X2) F0(N)
914 #define F3(N, X1, X2, X3) F0(N)
915 #define F4(N, X1, X2, X3, X4) F0(N)
916 #define F5(N, X1, X2, X3, X4, X5) F0(N)
917
918 typedef enum {
919 #include "insn-format.def"
920 } DisasFormat;
921
922 #undef F0
923 #undef F1
924 #undef F2
925 #undef F3
926 #undef F4
927 #undef F5
928
929 /* Define a structure to hold the decoded fields. We'll store each inside
930 an array indexed by an enum. In order to conserve memory, we'll arrange
931 for fields that do not exist at the same time to overlap, thus the "C"
932 for compact. For checking purposes there is an "O" for original index
933 as well that will be applied to availability bitmaps. */
934
935 enum DisasFieldIndexO {
936 FLD_O_r1,
937 FLD_O_r2,
938 FLD_O_r3,
939 FLD_O_m1,
940 FLD_O_m3,
941 FLD_O_m4,
942 FLD_O_b1,
943 FLD_O_b2,
944 FLD_O_b4,
945 FLD_O_d1,
946 FLD_O_d2,
947 FLD_O_d4,
948 FLD_O_x2,
949 FLD_O_l1,
950 FLD_O_l2,
951 FLD_O_i1,
952 FLD_O_i2,
953 FLD_O_i3,
954 FLD_O_i4,
955 FLD_O_i5
956 };
957
958 enum DisasFieldIndexC {
959 FLD_C_r1 = 0,
960 FLD_C_m1 = 0,
961 FLD_C_b1 = 0,
962 FLD_C_i1 = 0,
963
964 FLD_C_r2 = 1,
965 FLD_C_b2 = 1,
966 FLD_C_i2 = 1,
967
968 FLD_C_r3 = 2,
969 FLD_C_m3 = 2,
970 FLD_C_i3 = 2,
971
972 FLD_C_m4 = 3,
973 FLD_C_b4 = 3,
974 FLD_C_i4 = 3,
975 FLD_C_l1 = 3,
976
977 FLD_C_i5 = 4,
978 FLD_C_d1 = 4,
979
980 FLD_C_d2 = 5,
981
982 FLD_C_d4 = 6,
983 FLD_C_x2 = 6,
984 FLD_C_l2 = 6,
985
986 NUM_C_FIELD = 7
987 };
988
989 struct DisasFields {
990 unsigned op:8;
991 unsigned op2:8;
992 unsigned presentC:16;
993 unsigned int presentO;
994 int c[NUM_C_FIELD];
995 };
996
997 /* This is the way fields are to be accessed out of DisasFields. */
998 #define have_field(S, F) have_field1((S), FLD_O_##F)
999 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1000
1001 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
1002 {
1003 return (f->presentO >> c) & 1;
1004 }
1005
1006 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
1007 enum DisasFieldIndexC c)
1008 {
1009 assert(have_field1(f, o));
1010 return f->c[c];
1011 }
1012
1013 /* Describe the layout of each field in each format. */
1014 typedef struct DisasField {
1015 unsigned int beg:8;
1016 unsigned int size:8;
1017 unsigned int type:2;
1018 unsigned int indexC:6;
1019 enum DisasFieldIndexO indexO:8;
1020 } DisasField;
1021
1022 typedef struct DisasFormatInfo {
1023 DisasField op[NUM_C_FIELD];
1024 } DisasFormatInfo;
1025
1026 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1027 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1028 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1029 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1030 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1031 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1032 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1033 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1034 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1035 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1036 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1037 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1038 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1039 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1040
1041 #define F0(N) { { } },
1042 #define F1(N, X1) { { X1 } },
1043 #define F2(N, X1, X2) { { X1, X2 } },
1044 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1045 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1046 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1047
1048 static const DisasFormatInfo format_info[] = {
1049 #include "insn-format.def"
1050 };
1051
1052 #undef F0
1053 #undef F1
1054 #undef F2
1055 #undef F3
1056 #undef F4
1057 #undef F5
1058 #undef R
1059 #undef M
1060 #undef BD
1061 #undef BXD
1062 #undef BDL
1063 #undef BXDL
1064 #undef I
1065 #undef L
1066
1067 /* Generally, we'll extract operands into this structures, operate upon
1068 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1069 of routines below for more details. */
1070 typedef struct {
1071 bool g_out, g_out2, g_in1, g_in2;
1072 TCGv_i64 out, out2, in1, in2;
1073 TCGv_i64 addr1;
1074 } DisasOps;
1075
1076 /* Instructions can place constraints on their operands, raising specification
1077 exceptions if they are violated. To make this easy to automate, each "in1",
1078 "in2", "prep", "wout" helper will have a SPEC_<name> define that equals one
1079 of the following, or 0. To make this easy to document, we'll put the
1080 SPEC_<name> defines next to <name>. */
1081
1082 #define SPEC_r1_even 1
1083 #define SPEC_r2_even 2
1084 #define SPEC_r3_even 4
1085 #define SPEC_r1_f128 8
1086 #define SPEC_r2_f128 16
1087
1088 /* Return values from translate_one, indicating the state of the TB. */
1089 typedef enum {
1090 /* Continue the TB. */
1091 NO_EXIT,
1092 /* We have emitted one or more goto_tb. No fixup required. */
1093 EXIT_GOTO_TB,
1094 /* We are not using a goto_tb (for whatever reason), but have updated
1095 the PC (for whatever reason), so there's no need to do it again on
1096 exiting the TB. */
1097 EXIT_PC_UPDATED,
1098 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1099 updated the PC for the next instruction to be executed. */
1100 EXIT_PC_STALE,
1101 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1102 No following code will be executed. */
1103 EXIT_NORETURN,
1104 } ExitStatus;
1105
1106 typedef enum DisasFacility {
1107 FAC_Z, /* zarch (default) */
1108 FAC_CASS, /* compare and swap and store */
1109 FAC_CASS2, /* compare and swap and store 2*/
1110 FAC_DFP, /* decimal floating point */
1111 FAC_DFPR, /* decimal floating point rounding */
1112 FAC_DO, /* distinct operands */
1113 FAC_EE, /* execute extensions */
1114 FAC_EI, /* extended immediate */
1115 FAC_FPE, /* floating point extension */
1116 FAC_FPSSH, /* floating point support sign handling */
1117 FAC_FPRGR, /* FPR-GR transfer */
1118 FAC_GIE, /* general instructions extension */
1119 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1120 FAC_HW, /* high-word */
1121 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1122 FAC_LOC, /* load/store on condition */
1123 FAC_LD, /* long displacement */
1124 FAC_PC, /* population count */
1125 FAC_SCF, /* store clock fast */
1126 FAC_SFLE, /* store facility list extended */
1127 FAC_ILA, /* interlocked access facility 1 */
1128 } DisasFacility;
1129
1130 struct DisasInsn {
1131 unsigned opc:16;
1132 DisasFormat fmt:8;
1133 DisasFacility fac:8;
1134 unsigned spec:8;
1135
1136 const char *name;
1137
1138 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1139 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1140 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1141 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1142 void (*help_cout)(DisasContext *, DisasOps *);
1143 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1144
1145 uint64_t data;
1146 };
1147
1148 /* ====================================================================== */
1149 /* Miscellaneous helpers, used by several operations. */
1150
1151 static void help_l2_shift(DisasContext *s, DisasFields *f,
1152 DisasOps *o, int mask)
1153 {
1154 int b2 = get_field(f, b2);
1155 int d2 = get_field(f, d2);
1156
1157 if (b2 == 0) {
1158 o->in2 = tcg_const_i64(d2 & mask);
1159 } else {
1160 o->in2 = get_address(s, 0, b2, d2);
1161 tcg_gen_andi_i64(o->in2, o->in2, mask);
1162 }
1163 }
1164
1165 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1166 {
1167 if (dest == s->next_pc) {
1168 return NO_EXIT;
1169 }
1170 if (use_goto_tb(s, dest)) {
1171 update_cc_op(s);
1172 tcg_gen_goto_tb(0);
1173 tcg_gen_movi_i64(psw_addr, dest);
1174 tcg_gen_exit_tb((uintptr_t)s->tb);
1175 return EXIT_GOTO_TB;
1176 } else {
1177 tcg_gen_movi_i64(psw_addr, dest);
1178 return EXIT_PC_UPDATED;
1179 }
1180 }
1181
1182 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1183 bool is_imm, int imm, TCGv_i64 cdest)
1184 {
1185 ExitStatus ret;
1186 uint64_t dest = s->pc + 2 * imm;
1187 TCGLabel *lab;
1188
1189 /* Take care of the special cases first. */
1190 if (c->cond == TCG_COND_NEVER) {
1191 ret = NO_EXIT;
1192 goto egress;
1193 }
1194 if (is_imm) {
1195 if (dest == s->next_pc) {
1196 /* Branch to next. */
1197 ret = NO_EXIT;
1198 goto egress;
1199 }
1200 if (c->cond == TCG_COND_ALWAYS) {
1201 ret = help_goto_direct(s, dest);
1202 goto egress;
1203 }
1204 } else {
1205 if (TCGV_IS_UNUSED_I64(cdest)) {
1206 /* E.g. bcr %r0 -> no branch. */
1207 ret = NO_EXIT;
1208 goto egress;
1209 }
1210 if (c->cond == TCG_COND_ALWAYS) {
1211 tcg_gen_mov_i64(psw_addr, cdest);
1212 ret = EXIT_PC_UPDATED;
1213 goto egress;
1214 }
1215 }
1216
1217 if (use_goto_tb(s, s->next_pc)) {
1218 if (is_imm && use_goto_tb(s, dest)) {
1219 /* Both exits can use goto_tb. */
1220 update_cc_op(s);
1221
1222 lab = gen_new_label();
1223 if (c->is_64) {
1224 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1225 } else {
1226 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1227 }
1228
1229 /* Branch not taken. */
1230 tcg_gen_goto_tb(0);
1231 tcg_gen_movi_i64(psw_addr, s->next_pc);
1232 tcg_gen_exit_tb((uintptr_t)s->tb + 0);
1233
1234 /* Branch taken. */
1235 gen_set_label(lab);
1236 tcg_gen_goto_tb(1);
1237 tcg_gen_movi_i64(psw_addr, dest);
1238 tcg_gen_exit_tb((uintptr_t)s->tb + 1);
1239
1240 ret = EXIT_GOTO_TB;
1241 } else {
1242 /* Fallthru can use goto_tb, but taken branch cannot. */
1243 /* Store taken branch destination before the brcond. This
1244 avoids having to allocate a new local temp to hold it.
1245 We'll overwrite this in the not taken case anyway. */
1246 if (!is_imm) {
1247 tcg_gen_mov_i64(psw_addr, cdest);
1248 }
1249
1250 lab = gen_new_label();
1251 if (c->is_64) {
1252 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1253 } else {
1254 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1255 }
1256
1257 /* Branch not taken. */
1258 update_cc_op(s);
1259 tcg_gen_goto_tb(0);
1260 tcg_gen_movi_i64(psw_addr, s->next_pc);
1261 tcg_gen_exit_tb((uintptr_t)s->tb + 0);
1262
1263 gen_set_label(lab);
1264 if (is_imm) {
1265 tcg_gen_movi_i64(psw_addr, dest);
1266 }
1267 ret = EXIT_PC_UPDATED;
1268 }
1269 } else {
1270 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1271 Most commonly we're single-stepping or some other condition that
1272 disables all use of goto_tb. Just update the PC and exit. */
1273
1274 TCGv_i64 next = tcg_const_i64(s->next_pc);
1275 if (is_imm) {
1276 cdest = tcg_const_i64(dest);
1277 }
1278
1279 if (c->is_64) {
1280 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1281 cdest, next);
1282 } else {
1283 TCGv_i32 t0 = tcg_temp_new_i32();
1284 TCGv_i64 t1 = tcg_temp_new_i64();
1285 TCGv_i64 z = tcg_const_i64(0);
1286 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1287 tcg_gen_extu_i32_i64(t1, t0);
1288 tcg_temp_free_i32(t0);
1289 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1290 tcg_temp_free_i64(t1);
1291 tcg_temp_free_i64(z);
1292 }
1293
1294 if (is_imm) {
1295 tcg_temp_free_i64(cdest);
1296 }
1297 tcg_temp_free_i64(next);
1298
1299 ret = EXIT_PC_UPDATED;
1300 }
1301
1302 egress:
1303 free_compare(c);
1304 return ret;
1305 }
1306
1307 /* ====================================================================== */
1308 /* The operations. These perform the bulk of the work for any insn,
1309 usually after the operands have been loaded and output initialized. */
1310
1311 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1312 {
1313 gen_helper_abs_i64(o->out, o->in2);
1314 return NO_EXIT;
1315 }
1316
1317 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1318 {
1319 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1320 return NO_EXIT;
1321 }
1322
1323 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1324 {
1325 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1326 return NO_EXIT;
1327 }
1328
1329 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1330 {
1331 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1332 tcg_gen_mov_i64(o->out2, o->in2);
1333 return NO_EXIT;
1334 }
1335
1336 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1337 {
1338 tcg_gen_add_i64(o->out, o->in1, o->in2);
1339 return NO_EXIT;
1340 }
1341
1342 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1343 {
1344 DisasCompare cmp;
1345 TCGv_i64 carry;
1346
1347 tcg_gen_add_i64(o->out, o->in1, o->in2);
1348
1349 /* The carry flag is the msb of CC, therefore the branch mask that would
1350 create that comparison is 3. Feeding the generated comparison to
1351 setcond produces the carry flag that we desire. */
1352 disas_jcc(s, &cmp, 3);
1353 carry = tcg_temp_new_i64();
1354 if (cmp.is_64) {
1355 tcg_gen_setcond_i64(cmp.cond, carry, cmp.u.s64.a, cmp.u.s64.b);
1356 } else {
1357 TCGv_i32 t = tcg_temp_new_i32();
1358 tcg_gen_setcond_i32(cmp.cond, t, cmp.u.s32.a, cmp.u.s32.b);
1359 tcg_gen_extu_i32_i64(carry, t);
1360 tcg_temp_free_i32(t);
1361 }
1362 free_compare(&cmp);
1363
1364 tcg_gen_add_i64(o->out, o->out, carry);
1365 tcg_temp_free_i64(carry);
1366 return NO_EXIT;
1367 }
1368
1369 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1370 {
1371 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1372 return NO_EXIT;
1373 }
1374
1375 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1376 {
1377 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1378 return NO_EXIT;
1379 }
1380
1381 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1382 {
1383 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1384 return_low128(o->out2);
1385 return NO_EXIT;
1386 }
1387
1388 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1389 {
1390 tcg_gen_and_i64(o->out, o->in1, o->in2);
1391 return NO_EXIT;
1392 }
1393
1394 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1395 {
1396 int shift = s->insn->data & 0xff;
1397 int size = s->insn->data >> 8;
1398 uint64_t mask = ((1ull << size) - 1) << shift;
1399
1400 assert(!o->g_in2);
1401 tcg_gen_shli_i64(o->in2, o->in2, shift);
1402 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1403 tcg_gen_and_i64(o->out, o->in1, o->in2);
1404
1405 /* Produce the CC from only the bits manipulated. */
1406 tcg_gen_andi_i64(cc_dst, o->out, mask);
1407 set_cc_nz_u64(s, cc_dst);
1408 return NO_EXIT;
1409 }
1410
1411 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1412 {
1413 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1414 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1415 tcg_gen_mov_i64(psw_addr, o->in2);
1416 return EXIT_PC_UPDATED;
1417 } else {
1418 return NO_EXIT;
1419 }
1420 }
1421
1422 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1423 {
1424 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1425 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1426 }
1427
1428 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1429 {
1430 int m1 = get_field(s->fields, m1);
1431 bool is_imm = have_field(s->fields, i2);
1432 int imm = is_imm ? get_field(s->fields, i2) : 0;
1433 DisasCompare c;
1434
1435 disas_jcc(s, &c, m1);
1436 return help_branch(s, &c, is_imm, imm, o->in2);
1437 }
1438
1439 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1440 {
1441 int r1 = get_field(s->fields, r1);
1442 bool is_imm = have_field(s->fields, i2);
1443 int imm = is_imm ? get_field(s->fields, i2) : 0;
1444 DisasCompare c;
1445 TCGv_i64 t;
1446
1447 c.cond = TCG_COND_NE;
1448 c.is_64 = false;
1449 c.g1 = false;
1450 c.g2 = false;
1451
1452 t = tcg_temp_new_i64();
1453 tcg_gen_subi_i64(t, regs[r1], 1);
1454 store_reg32_i64(r1, t);
1455 c.u.s32.a = tcg_temp_new_i32();
1456 c.u.s32.b = tcg_const_i32(0);
1457 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1458 tcg_temp_free_i64(t);
1459
1460 return help_branch(s, &c, is_imm, imm, o->in2);
1461 }
1462
1463 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1464 {
1465 int r1 = get_field(s->fields, r1);
1466 bool is_imm = have_field(s->fields, i2);
1467 int imm = is_imm ? get_field(s->fields, i2) : 0;
1468 DisasCompare c;
1469
1470 c.cond = TCG_COND_NE;
1471 c.is_64 = true;
1472 c.g1 = true;
1473 c.g2 = false;
1474
1475 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1476 c.u.s64.a = regs[r1];
1477 c.u.s64.b = tcg_const_i64(0);
1478
1479 return help_branch(s, &c, is_imm, imm, o->in2);
1480 }
1481
1482 static ExitStatus op_bx32(DisasContext *s, DisasOps *o)
1483 {
1484 int r1 = get_field(s->fields, r1);
1485 int r3 = get_field(s->fields, r3);
1486 bool is_imm = have_field(s->fields, i2);
1487 int imm = is_imm ? get_field(s->fields, i2) : 0;
1488 DisasCompare c;
1489 TCGv_i64 t;
1490
1491 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1492 c.is_64 = false;
1493 c.g1 = false;
1494 c.g2 = false;
1495
1496 t = tcg_temp_new_i64();
1497 tcg_gen_add_i64(t, regs[r1], regs[r3]);
1498 c.u.s32.a = tcg_temp_new_i32();
1499 c.u.s32.b = tcg_temp_new_i32();
1500 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1501 tcg_gen_trunc_i64_i32(c.u.s32.b, regs[r3 | 1]);
1502 store_reg32_i64(r1, t);
1503 tcg_temp_free_i64(t);
1504
1505 return help_branch(s, &c, is_imm, imm, o->in2);
1506 }
1507
1508 static ExitStatus op_bx64(DisasContext *s, DisasOps *o)
1509 {
1510 int r1 = get_field(s->fields, r1);
1511 int r3 = get_field(s->fields, r3);
1512 bool is_imm = have_field(s->fields, i2);
1513 int imm = is_imm ? get_field(s->fields, i2) : 0;
1514 DisasCompare c;
1515
1516 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1517 c.is_64 = true;
1518
1519 if (r1 == (r3 | 1)) {
1520 c.u.s64.b = load_reg(r3 | 1);
1521 c.g2 = false;
1522 } else {
1523 c.u.s64.b = regs[r3 | 1];
1524 c.g2 = true;
1525 }
1526
1527 tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]);
1528 c.u.s64.a = regs[r1];
1529 c.g1 = true;
1530
1531 return help_branch(s, &c, is_imm, imm, o->in2);
1532 }
1533
1534 static ExitStatus op_cj(DisasContext *s, DisasOps *o)
1535 {
1536 int imm, m3 = get_field(s->fields, m3);
1537 bool is_imm;
1538 DisasCompare c;
1539
1540 c.cond = ltgt_cond[m3];
1541 if (s->insn->data) {
1542 c.cond = tcg_unsigned_cond(c.cond);
1543 }
1544 c.is_64 = c.g1 = c.g2 = true;
1545 c.u.s64.a = o->in1;
1546 c.u.s64.b = o->in2;
1547
1548 is_imm = have_field(s->fields, i4);
1549 if (is_imm) {
1550 imm = get_field(s->fields, i4);
1551 } else {
1552 imm = 0;
1553 o->out = get_address(s, 0, get_field(s->fields, b4),
1554 get_field(s->fields, d4));
1555 }
1556
1557 return help_branch(s, &c, is_imm, imm, o->out);
1558 }
1559
1560 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1561 {
1562 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1563 set_cc_static(s);
1564 return NO_EXIT;
1565 }
1566
1567 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1568 {
1569 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1570 set_cc_static(s);
1571 return NO_EXIT;
1572 }
1573
1574 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1575 {
1576 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1577 set_cc_static(s);
1578 return NO_EXIT;
1579 }
1580
1581 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1582 {
1583 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1584 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1585 tcg_temp_free_i32(m3);
1586 gen_set_cc_nz_f32(s, o->in2);
1587 return NO_EXIT;
1588 }
1589
1590 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1591 {
1592 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1593 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1594 tcg_temp_free_i32(m3);
1595 gen_set_cc_nz_f64(s, o->in2);
1596 return NO_EXIT;
1597 }
1598
1599 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1600 {
1601 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1602 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1603 tcg_temp_free_i32(m3);
1604 gen_set_cc_nz_f128(s, o->in1, o->in2);
1605 return NO_EXIT;
1606 }
1607
1608 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1609 {
1610 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1611 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1612 tcg_temp_free_i32(m3);
1613 gen_set_cc_nz_f32(s, o->in2);
1614 return NO_EXIT;
1615 }
1616
1617 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1618 {
1619 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1620 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1621 tcg_temp_free_i32(m3);
1622 gen_set_cc_nz_f64(s, o->in2);
1623 return NO_EXIT;
1624 }
1625
1626 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1627 {
1628 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1629 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1630 tcg_temp_free_i32(m3);
1631 gen_set_cc_nz_f128(s, o->in1, o->in2);
1632 return NO_EXIT;
1633 }
1634
1635 static ExitStatus op_clfeb(DisasContext *s, DisasOps *o)
1636 {
1637 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1638 gen_helper_clfeb(o->out, cpu_env, o->in2, m3);
1639 tcg_temp_free_i32(m3);
1640 gen_set_cc_nz_f32(s, o->in2);
1641 return NO_EXIT;
1642 }
1643
1644 static ExitStatus op_clfdb(DisasContext *s, DisasOps *o)
1645 {
1646 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1647 gen_helper_clfdb(o->out, cpu_env, o->in2, m3);
1648 tcg_temp_free_i32(m3);
1649 gen_set_cc_nz_f64(s, o->in2);
1650 return NO_EXIT;
1651 }
1652
1653 static ExitStatus op_clfxb(DisasContext *s, DisasOps *o)
1654 {
1655 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1656 gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m3);
1657 tcg_temp_free_i32(m3);
1658 gen_set_cc_nz_f128(s, o->in1, o->in2);
1659 return NO_EXIT;
1660 }
1661
1662 static ExitStatus op_clgeb(DisasContext *s, DisasOps *o)
1663 {
1664 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1665 gen_helper_clgeb(o->out, cpu_env, o->in2, m3);
1666 tcg_temp_free_i32(m3);
1667 gen_set_cc_nz_f32(s, o->in2);
1668 return NO_EXIT;
1669 }
1670
1671 static ExitStatus op_clgdb(DisasContext *s, DisasOps *o)
1672 {
1673 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1674 gen_helper_clgdb(o->out, cpu_env, o->in2, m3);
1675 tcg_temp_free_i32(m3);
1676 gen_set_cc_nz_f64(s, o->in2);
1677 return NO_EXIT;
1678 }
1679
1680 static ExitStatus op_clgxb(DisasContext *s, DisasOps *o)
1681 {
1682 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1683 gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m3);
1684 tcg_temp_free_i32(m3);
1685 gen_set_cc_nz_f128(s, o->in1, o->in2);
1686 return NO_EXIT;
1687 }
1688
1689 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1690 {
1691 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1692 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1693 tcg_temp_free_i32(m3);
1694 return NO_EXIT;
1695 }
1696
1697 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1698 {
1699 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1700 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1701 tcg_temp_free_i32(m3);
1702 return NO_EXIT;
1703 }
1704
1705 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1706 {
1707 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1708 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1709 tcg_temp_free_i32(m3);
1710 return_low128(o->out2);
1711 return NO_EXIT;
1712 }
1713
1714 static ExitStatus op_celgb(DisasContext *s, DisasOps *o)
1715 {
1716 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1717 gen_helper_celgb(o->out, cpu_env, o->in2, m3);
1718 tcg_temp_free_i32(m3);
1719 return NO_EXIT;
1720 }
1721
1722 static ExitStatus op_cdlgb(DisasContext *s, DisasOps *o)
1723 {
1724 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1725 gen_helper_cdlgb(o->out, cpu_env, o->in2, m3);
1726 tcg_temp_free_i32(m3);
1727 return NO_EXIT;
1728 }
1729
1730 static ExitStatus op_cxlgb(DisasContext *s, DisasOps *o)
1731 {
1732 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1733 gen_helper_cxlgb(o->out, cpu_env, o->in2, m3);
1734 tcg_temp_free_i32(m3);
1735 return_low128(o->out2);
1736 return NO_EXIT;
1737 }
1738
1739 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1740 {
1741 int r2 = get_field(s->fields, r2);
1742 TCGv_i64 len = tcg_temp_new_i64();
1743
1744 potential_page_fault(s);
1745 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1746 set_cc_static(s);
1747 return_low128(o->out);
1748
1749 tcg_gen_add_i64(regs[r2], regs[r2], len);
1750 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1751 tcg_temp_free_i64(len);
1752
1753 return NO_EXIT;
1754 }
1755
1756 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
1757 {
1758 int l = get_field(s->fields, l1);
1759 TCGv_i32 vl;
1760
1761 switch (l + 1) {
1762 case 1:
1763 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
1764 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
1765 break;
1766 case 2:
1767 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
1768 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
1769 break;
1770 case 4:
1771 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
1772 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
1773 break;
1774 case 8:
1775 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
1776 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
1777 break;
1778 default:
1779 potential_page_fault(s);
1780 vl = tcg_const_i32(l);
1781 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
1782 tcg_temp_free_i32(vl);
1783 set_cc_static(s);
1784 return NO_EXIT;
1785 }
1786 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
1787 return NO_EXIT;
1788 }
1789
1790 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
1791 {
1792 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1793 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1794 potential_page_fault(s);
1795 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
1796 tcg_temp_free_i32(r1);
1797 tcg_temp_free_i32(r3);
1798 set_cc_static(s);
1799 return NO_EXIT;
1800 }
1801
1802 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
1803 {
1804 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1805 TCGv_i32 t1 = tcg_temp_new_i32();
1806 tcg_gen_trunc_i64_i32(t1, o->in1);
1807 potential_page_fault(s);
1808 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
1809 set_cc_static(s);
1810 tcg_temp_free_i32(t1);
1811 tcg_temp_free_i32(m3);
1812 return NO_EXIT;
1813 }
1814
1815 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
1816 {
1817 potential_page_fault(s);
1818 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
1819 set_cc_static(s);
1820 return_low128(o->in2);
1821 return NO_EXIT;
1822 }
1823
1824 static ExitStatus op_cps(DisasContext *s, DisasOps *o)
1825 {
1826 TCGv_i64 t = tcg_temp_new_i64();
1827 tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull);
1828 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1829 tcg_gen_or_i64(o->out, o->out, t);
1830 tcg_temp_free_i64(t);
1831 return NO_EXIT;
1832 }
1833
1834 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
1835 {
1836 /* FIXME: needs an atomic solution for CONFIG_USER_ONLY. */
1837 int d2 = get_field(s->fields, d2);
1838 int b2 = get_field(s->fields, b2);
1839 int is_64 = s->insn->data;
1840 TCGv_i64 addr, mem, cc, z;
1841
1842 /* Note that in1 = R3 (new value) and
1843 in2 = (zero-extended) R1 (expected value). */
1844
1845 /* Load the memory into the (temporary) output. While the PoO only talks
1846 about moving the memory to R1 on inequality, if we include equality it
1847 means that R1 is equal to the memory in all conditions. */
1848 addr = get_address(s, 0, b2, d2);
1849 if (is_64) {
1850 tcg_gen_qemu_ld64(o->out, addr, get_mem_index(s));
1851 } else {
1852 tcg_gen_qemu_ld32u(o->out, addr, get_mem_index(s));
1853 }
1854
1855 /* Are the memory and expected values (un)equal? Note that this setcond
1856 produces the output CC value, thus the NE sense of the test. */
1857 cc = tcg_temp_new_i64();
1858 tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out);
1859
1860 /* If the memory and expected values are equal (CC==0), copy R3 to MEM.
1861 Recall that we are allowed to unconditionally issue the store (and
1862 thus any possible write trap), so (re-)store the original contents
1863 of MEM in case of inequality. */
1864 z = tcg_const_i64(0);
1865 mem = tcg_temp_new_i64();
1866 tcg_gen_movcond_i64(TCG_COND_EQ, mem, cc, z, o->in1, o->out);
1867 if (is_64) {
1868 tcg_gen_qemu_st64(mem, addr, get_mem_index(s));
1869 } else {
1870 tcg_gen_qemu_st32(mem, addr, get_mem_index(s));
1871 }
1872 tcg_temp_free_i64(z);
1873 tcg_temp_free_i64(mem);
1874 tcg_temp_free_i64(addr);
1875
1876 /* Store CC back to cc_op. Wait until after the store so that any
1877 exception gets the old cc_op value. */
1878 tcg_gen_trunc_i64_i32(cc_op, cc);
1879 tcg_temp_free_i64(cc);
1880 set_cc_static(s);
1881 return NO_EXIT;
1882 }
1883
1884 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
1885 {
1886 /* FIXME: needs an atomic solution for CONFIG_USER_ONLY. */
1887 int r1 = get_field(s->fields, r1);
1888 int r3 = get_field(s->fields, r3);
1889 int d2 = get_field(s->fields, d2);
1890 int b2 = get_field(s->fields, b2);
1891 TCGv_i64 addrh, addrl, memh, meml, outh, outl, cc, z;
1892
1893 /* Note that R1:R1+1 = expected value and R3:R3+1 = new value. */
1894
1895 addrh = get_address(s, 0, b2, d2);
1896 addrl = get_address(s, 0, b2, d2 + 8);
1897 outh = tcg_temp_new_i64();
1898 outl = tcg_temp_new_i64();
1899
1900 tcg_gen_qemu_ld64(outh, addrh, get_mem_index(s));
1901 tcg_gen_qemu_ld64(outl, addrl, get_mem_index(s));
1902
1903 /* Fold the double-word compare with arithmetic. */
1904 cc = tcg_temp_new_i64();
1905 z = tcg_temp_new_i64();
1906 tcg_gen_xor_i64(cc, outh, regs[r1]);
1907 tcg_gen_xor_i64(z, outl, regs[r1 + 1]);
1908 tcg_gen_or_i64(cc, cc, z);
1909 tcg_gen_movi_i64(z, 0);
1910 tcg_gen_setcond_i64(TCG_COND_NE, cc, cc, z);
1911
1912 memh = tcg_temp_new_i64();
1913 meml = tcg_temp_new_i64();
1914 tcg_gen_movcond_i64(TCG_COND_EQ, memh, cc, z, regs[r3], outh);
1915 tcg_gen_movcond_i64(TCG_COND_EQ, meml, cc, z, regs[r3 + 1], outl);
1916 tcg_temp_free_i64(z);
1917
1918 tcg_gen_qemu_st64(memh, addrh, get_mem_index(s));
1919 tcg_gen_qemu_st64(meml, addrl, get_mem_index(s));
1920 tcg_temp_free_i64(memh);
1921 tcg_temp_free_i64(meml);
1922 tcg_temp_free_i64(addrh);
1923 tcg_temp_free_i64(addrl);
1924
1925 /* Save back state now that we've passed all exceptions. */
1926 tcg_gen_mov_i64(regs[r1], outh);
1927 tcg_gen_mov_i64(regs[r1 + 1], outl);
1928 tcg_gen_trunc_i64_i32(cc_op, cc);
1929 tcg_temp_free_i64(outh);
1930 tcg_temp_free_i64(outl);
1931 tcg_temp_free_i64(cc);
1932 set_cc_static(s);
1933 return NO_EXIT;
1934 }
1935
1936 #ifndef CONFIG_USER_ONLY
1937 static ExitStatus op_csp(DisasContext *s, DisasOps *o)
1938 {
1939 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1940 check_privileged(s);
1941 gen_helper_csp(cc_op, cpu_env, r1, o->in2);
1942 tcg_temp_free_i32(r1);
1943 set_cc_static(s);
1944 return NO_EXIT;
1945 }
1946 #endif
1947
1948 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
1949 {
1950 TCGv_i64 t1 = tcg_temp_new_i64();
1951 TCGv_i32 t2 = tcg_temp_new_i32();
1952 tcg_gen_trunc_i64_i32(t2, o->in1);
1953 gen_helper_cvd(t1, t2);
1954 tcg_temp_free_i32(t2);
1955 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
1956 tcg_temp_free_i64(t1);
1957 return NO_EXIT;
1958 }
1959
1960 static ExitStatus op_ct(DisasContext *s, DisasOps *o)
1961 {
1962 int m3 = get_field(s->fields, m3);
1963 TCGLabel *lab = gen_new_label();
1964 TCGv_i32 t;
1965 TCGCond c;
1966
1967 c = tcg_invert_cond(ltgt_cond[m3]);
1968 if (s->insn->data) {
1969 c = tcg_unsigned_cond(c);
1970 }
1971 tcg_gen_brcond_i64(c, o->in1, o->in2, lab);
1972
1973 /* Set DXC to 0xff. */
1974 t = tcg_temp_new_i32();
1975 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1976 tcg_gen_ori_i32(t, t, 0xff00);
1977 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1978 tcg_temp_free_i32(t);
1979
1980 /* Trap. */
1981 gen_program_exception(s, PGM_DATA);
1982
1983 gen_set_label(lab);
1984 return NO_EXIT;
1985 }
1986
1987 #ifndef CONFIG_USER_ONLY
1988 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
1989 {
1990 TCGv_i32 tmp;
1991
1992 check_privileged(s);
1993 potential_page_fault(s);
1994
1995 /* We pretend the format is RX_a so that D2 is the field we want. */
1996 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
1997 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
1998 tcg_temp_free_i32(tmp);
1999 return NO_EXIT;
2000 }
2001 #endif
2002
2003 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2004 {
2005 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2006 return_low128(o->out);
2007 return NO_EXIT;
2008 }
2009
2010 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2011 {
2012 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2013 return_low128(o->out);
2014 return NO_EXIT;
2015 }
2016
2017 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2018 {
2019 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2020 return_low128(o->out);
2021 return NO_EXIT;
2022 }
2023
2024 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2025 {
2026 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2027 return_low128(o->out);
2028 return NO_EXIT;
2029 }
2030
2031 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
2032 {
2033 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
2034 return NO_EXIT;
2035 }
2036
2037 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
2038 {
2039 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
2040 return NO_EXIT;
2041 }
2042
2043 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
2044 {
2045 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2046 return_low128(o->out2);
2047 return NO_EXIT;
2048 }
2049
2050 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
2051 {
2052 int r2 = get_field(s->fields, r2);
2053 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
2054 return NO_EXIT;
2055 }
2056
2057 static ExitStatus op_ecag(DisasContext *s, DisasOps *o)
2058 {
2059 /* No cache information provided. */
2060 tcg_gen_movi_i64(o->out, -1);
2061 return NO_EXIT;
2062 }
2063
2064 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
2065 {
2066 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
2067 return NO_EXIT;
2068 }
2069
2070 static ExitStatus op_epsw(DisasContext *s, DisasOps *o)
2071 {
2072 int r1 = get_field(s->fields, r1);
2073 int r2 = get_field(s->fields, r2);
2074 TCGv_i64 t = tcg_temp_new_i64();
2075
2076 /* Note the "subsequently" in the PoO, which implies a defined result
2077 if r1 == r2. Thus we cannot defer these writes to an output hook. */
2078 tcg_gen_shri_i64(t, psw_mask, 32);
2079 store_reg32_i64(r1, t);
2080 if (r2 != 0) {
2081 store_reg32_i64(r2, psw_mask);
2082 }
2083
2084 tcg_temp_free_i64(t);
2085 return NO_EXIT;
2086 }
2087
2088 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2089 {
2090 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2091 tb->flags, (ab)use the tb->cs_base field as the address of
2092 the template in memory, and grab 8 bits of tb->flags/cflags for
2093 the contents of the register. We would then recognize all this
2094 in gen_intermediate_code_internal, generating code for exactly
2095 one instruction. This new TB then gets executed normally.
2096
2097 On the other hand, this seems to be mostly used for modifying
2098 MVC inside of memcpy, which needs a helper call anyway. So
2099 perhaps this doesn't bear thinking about any further. */
2100
2101 TCGv_i64 tmp;
2102
2103 update_psw_addr(s);
2104 update_cc_op(s);
2105
2106 tmp = tcg_const_i64(s->next_pc);
2107 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2108 tcg_temp_free_i64(tmp);
2109
2110 set_cc_static(s);
2111 return NO_EXIT;
2112 }
2113
2114 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
2115 {
2116 /* We'll use the original input for cc computation, since we get to
2117 compare that against 0, which ought to be better than comparing
2118 the real output against 64. It also lets cc_dst be a convenient
2119 temporary during our computation. */
2120 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
2121
2122 /* R1 = IN ? CLZ(IN) : 64. */
2123 gen_helper_clz(o->out, o->in2);
2124
2125 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2126 value by 64, which is undefined. But since the shift is 64 iff the
2127 input is zero, we still get the correct result after and'ing. */
2128 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
2129 tcg_gen_shr_i64(o->out2, o->out2, o->out);
2130 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
2131 return NO_EXIT;
2132 }
2133
2134 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2135 {
2136 int m3 = get_field(s->fields, m3);
2137 int pos, len, base = s->insn->data;
2138 TCGv_i64 tmp = tcg_temp_new_i64();
2139 uint64_t ccm;
2140
2141 switch (m3) {
2142 case 0xf:
2143 /* Effectively a 32-bit load. */
2144 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2145 len = 32;
2146 goto one_insert;
2147
2148 case 0xc:
2149 case 0x6:
2150 case 0x3:
2151 /* Effectively a 16-bit load. */
2152 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2153 len = 16;
2154 goto one_insert;
2155
2156 case 0x8:
2157 case 0x4:
2158 case 0x2:
2159 case 0x1:
2160 /* Effectively an 8-bit load. */
2161 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2162 len = 8;
2163 goto one_insert;
2164
2165 one_insert:
2166 pos = base + ctz32(m3) * 8;
2167 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2168 ccm = ((1ull << len) - 1) << pos;
2169 break;
2170
2171 default:
2172 /* This is going to be a sequence of loads and inserts. */
2173 pos = base + 32 - 8;
2174 ccm = 0;
2175 while (m3) {
2176 if (m3 & 0x8) {
2177 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2178 tcg_gen_addi_i64(o->in2, o->in2, 1);
2179 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2180 ccm |= 0xff << pos;
2181 }
2182 m3 = (m3 << 1) & 0xf;
2183 pos -= 8;
2184 }
2185 break;
2186 }
2187
2188 tcg_gen_movi_i64(tmp, ccm);
2189 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2190 tcg_temp_free_i64(tmp);
2191 return NO_EXIT;
2192 }
2193
2194 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2195 {
2196 int shift = s->insn->data & 0xff;
2197 int size = s->insn->data >> 8;
2198 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2199 return NO_EXIT;
2200 }
2201
2202 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
2203 {
2204 TCGv_i64 t1;
2205
2206 gen_op_calc_cc(s);
2207 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
2208
2209 t1 = tcg_temp_new_i64();
2210 tcg_gen_shli_i64(t1, psw_mask, 20);
2211 tcg_gen_shri_i64(t1, t1, 36);
2212 tcg_gen_or_i64(o->out, o->out, t1);
2213
2214 tcg_gen_extu_i32_i64(t1, cc_op);
2215 tcg_gen_shli_i64(t1, t1, 28);
2216 tcg_gen_or_i64(o->out, o->out, t1);
2217 tcg_temp_free_i64(t1);
2218 return NO_EXIT;
2219 }
2220
2221 #ifndef CONFIG_USER_ONLY
2222 static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
2223 {
2224 check_privileged(s);
2225 gen_helper_ipte(cpu_env, o->in1, o->in2);
2226 return NO_EXIT;
2227 }
2228
2229 static ExitStatus op_iske(DisasContext *s, DisasOps *o)
2230 {
2231 check_privileged(s);
2232 gen_helper_iske(o->out, cpu_env, o->in2);
2233 return NO_EXIT;
2234 }
2235 #endif
2236
2237 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2238 {
2239 gen_helper_ldeb(o->out, cpu_env, o->in2);
2240 return NO_EXIT;
2241 }
2242
2243 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2244 {
2245 gen_helper_ledb(o->out, cpu_env, o->in2);
2246 return NO_EXIT;
2247 }
2248
2249 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2250 {
2251 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2252 return NO_EXIT;
2253 }
2254
2255 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2256 {
2257 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2258 return NO_EXIT;
2259 }
2260
2261 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2262 {
2263 gen_helper_lxdb(o->out, cpu_env, o->in2);
2264 return_low128(o->out2);
2265 return NO_EXIT;
2266 }
2267
2268 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2269 {
2270 gen_helper_lxeb(o->out, cpu_env, o->in2);
2271 return_low128(o->out2);
2272 return NO_EXIT;
2273 }
2274
2275 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2276 {
2277 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2278 return NO_EXIT;
2279 }
2280
2281 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2282 {
2283 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2284 return NO_EXIT;
2285 }
2286
2287 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2288 {
2289 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2290 return NO_EXIT;
2291 }
2292
2293 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2294 {
2295 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2296 return NO_EXIT;
2297 }
2298
2299 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2300 {
2301 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2302 return NO_EXIT;
2303 }
2304
2305 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2306 {
2307 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2308 return NO_EXIT;
2309 }
2310
2311 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2312 {
2313 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2314 return NO_EXIT;
2315 }
2316
2317 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2318 {
2319 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2320 return NO_EXIT;
2321 }
2322
2323 static ExitStatus op_loc(DisasContext *s, DisasOps *o)
2324 {
2325 DisasCompare c;
2326
2327 disas_jcc(s, &c, get_field(s->fields, m3));
2328
2329 if (c.is_64) {
2330 tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
2331 o->in2, o->in1);
2332 free_compare(&c);
2333 } else {
2334 TCGv_i32 t32 = tcg_temp_new_i32();
2335 TCGv_i64 t, z;
2336
2337 tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b);
2338 free_compare(&c);
2339
2340 t = tcg_temp_new_i64();
2341 tcg_gen_extu_i32_i64(t, t32);
2342 tcg_temp_free_i32(t32);
2343
2344 z = tcg_const_i64(0);
2345 tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1);
2346 tcg_temp_free_i64(t);
2347 tcg_temp_free_i64(z);
2348 }
2349
2350 return NO_EXIT;
2351 }
2352
2353 #ifndef CONFIG_USER_ONLY
2354 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2355 {
2356 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2357 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2358 check_privileged(s);
2359 potential_page_fault(s);
2360 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2361 tcg_temp_free_i32(r1);
2362 tcg_temp_free_i32(r3);
2363 return NO_EXIT;
2364 }
2365
2366 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2367 {
2368 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2369 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2370 check_privileged(s);
2371 potential_page_fault(s);
2372 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2373 tcg_temp_free_i32(r1);
2374 tcg_temp_free_i32(r3);
2375 return NO_EXIT;
2376 }
2377 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2378 {
2379 check_privileged(s);
2380 potential_page_fault(s);
2381 gen_helper_lra(o->out, cpu_env, o->in2);
2382 set_cc_static(s);
2383 return NO_EXIT;
2384 }
2385
2386 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2387 {
2388 TCGv_i64 t1, t2;
2389
2390 check_privileged(s);
2391
2392 t1 = tcg_temp_new_i64();
2393 t2 = tcg_temp_new_i64();
2394 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2395 tcg_gen_addi_i64(o->in2, o->in2, 4);
2396 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2397 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2398 tcg_gen_shli_i64(t1, t1, 32);
2399 gen_helper_load_psw(cpu_env, t1, t2);
2400 tcg_temp_free_i64(t1);
2401 tcg_temp_free_i64(t2);
2402 return EXIT_NORETURN;
2403 }
2404
2405 static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
2406 {
2407 TCGv_i64 t1, t2;
2408
2409 check_privileged(s);
2410
2411 t1 = tcg_temp_new_i64();
2412 t2 = tcg_temp_new_i64();
2413 tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
2414 tcg_gen_addi_i64(o->in2, o->in2, 8);
2415 tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
2416 gen_helper_load_psw(cpu_env, t1, t2);
2417 tcg_temp_free_i64(t1);
2418 tcg_temp_free_i64(t2);
2419 return EXIT_NORETURN;
2420 }
2421 #endif
2422
2423 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2424 {
2425 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2426 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2427 potential_page_fault(s);
2428 gen_helper_lam(cpu_env, r1, o->in2, r3);
2429 tcg_temp_free_i32(r1);
2430 tcg_temp_free_i32(r3);
2431 return NO_EXIT;
2432 }
2433
2434 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2435 {
2436 int r1 = get_field(s->fields, r1);
2437 int r3 = get_field(s->fields, r3);
2438 TCGv_i64 t = tcg_temp_new_i64();
2439 TCGv_i64 t4 = tcg_const_i64(4);
2440
2441 while (1) {
2442 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2443 store_reg32_i64(r1, t);
2444 if (r1 == r3) {
2445 break;
2446 }
2447 tcg_gen_add_i64(o->in2, o->in2, t4);
2448 r1 = (r1 + 1) & 15;
2449 }
2450
2451 tcg_temp_free_i64(t);
2452 tcg_temp_free_i64(t4);
2453 return NO_EXIT;
2454 }
2455
2456 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2457 {
2458 int r1 = get_field(s->fields, r1);
2459 int r3 = get_field(s->fields, r3);
2460 TCGv_i64 t = tcg_temp_new_i64();
2461 TCGv_i64 t4 = tcg_const_i64(4);
2462
2463 while (1) {
2464 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2465 store_reg32h_i64(r1, t);
2466 if (r1 == r3) {
2467 break;
2468 }
2469 tcg_gen_add_i64(o->in2, o->in2, t4);
2470 r1 = (r1 + 1) & 15;
2471 }
2472
2473 tcg_temp_free_i64(t);
2474 tcg_temp_free_i64(t4);
2475 return NO_EXIT;
2476 }
2477
2478 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2479 {
2480 int r1 = get_field(s->fields, r1);
2481 int r3 = get_field(s->fields, r3);
2482 TCGv_i64 t8 = tcg_const_i64(8);
2483
2484 while (1) {
2485 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2486 if (r1 == r3) {
2487 break;
2488 }
2489 tcg_gen_add_i64(o->in2, o->in2, t8);
2490 r1 = (r1 + 1) & 15;
2491 }
2492
2493 tcg_temp_free_i64(t8);
2494 return NO_EXIT;
2495 }
2496
2497 #ifndef CONFIG_USER_ONLY
2498 static ExitStatus op_lura(DisasContext *s, DisasOps *o)
2499 {
2500 check_privileged(s);
2501 potential_page_fault(s);
2502 gen_helper_lura(o->out, cpu_env, o->in2);
2503 return NO_EXIT;
2504 }
2505
2506 static ExitStatus op_lurag(DisasContext *s, DisasOps *o)
2507 {
2508 check_privileged(s);
2509 potential_page_fault(s);
2510 gen_helper_lurag(o->out, cpu_env, o->in2);
2511 return NO_EXIT;
2512 }
2513 #endif
2514
2515 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2516 {
2517 o->out = o->in2;
2518 o->g_out = o->g_in2;
2519 TCGV_UNUSED_I64(o->in2);
2520 o->g_in2 = false;
2521 return NO_EXIT;
2522 }
2523
2524 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2525 {
2526 o->out = o->in1;
2527 o->out2 = o->in2;
2528 o->g_out = o->g_in1;
2529 o->g_out2 = o->g_in2;
2530 TCGV_UNUSED_I64(o->in1);
2531 TCGV_UNUSED_I64(o->in2);
2532 o->g_in1 = o->g_in2 = false;
2533 return NO_EXIT;
2534 }
2535
2536 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2537 {
2538 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2539 potential_page_fault(s);
2540 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2541 tcg_temp_free_i32(l);
2542 return NO_EXIT;
2543 }
2544
2545 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2546 {
2547 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2548 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2549 potential_page_fault(s);
2550 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2551 tcg_temp_free_i32(r1);
2552 tcg_temp_free_i32(r2);
2553 set_cc_static(s);
2554 return NO_EXIT;
2555 }
2556
2557 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2558 {
2559 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2560 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2561 potential_page_fault(s);
2562 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2563 tcg_temp_free_i32(r1);
2564 tcg_temp_free_i32(r3);
2565 set_cc_static(s);
2566 return NO_EXIT;
2567 }
2568
2569 #ifndef CONFIG_USER_ONLY
2570 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2571 {
2572 int r1 = get_field(s->fields, l1);
2573 check_privileged(s);
2574 potential_page_fault(s);
2575 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2576 set_cc_static(s);
2577 return NO_EXIT;
2578 }
2579
2580 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2581 {
2582 int r1 = get_field(s->fields, l1);
2583 check_privileged(s);
2584 potential_page_fault(s);
2585 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2586 set_cc_static(s);
2587 return NO_EXIT;
2588 }
2589 #endif
2590
2591 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2592 {
2593 potential_page_fault(s);
2594 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2595 set_cc_static(s);
2596 return NO_EXIT;
2597 }
2598
2599 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2600 {
2601 potential_page_fault(s);
2602 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2603 set_cc_static(s);
2604 return_low128(o->in2);
2605 return NO_EXIT;
2606 }
2607
2608 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2609 {
2610 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2611 return NO_EXIT;
2612 }
2613
2614 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2615 {
2616 tcg_gen_mulu2_i64(o->out2, o->out, o->in1, o->in2);
2617 return NO_EXIT;
2618 }
2619
2620 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2621 {
2622 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2623 return NO_EXIT;
2624 }
2625
2626 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2627 {
2628 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2629 return NO_EXIT;
2630 }
2631
2632 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2633 {
2634 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2635 return NO_EXIT;
2636 }
2637
2638 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2639 {
2640 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2641 return_low128(o->out2);
2642 return NO_EXIT;
2643 }
2644
2645 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2646 {
2647 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2648 return_low128(o->out2);
2649 return NO_EXIT;
2650 }
2651
2652 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2653 {
2654 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2655 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2656 tcg_temp_free_i64(r3);
2657 return NO_EXIT;
2658 }
2659
2660 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2661 {
2662 int r3 = get_field(s->fields, r3);
2663 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2664 return NO_EXIT;
2665 }
2666
2667 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2668 {
2669 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2670 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2671 tcg_temp_free_i64(r3);
2672 return NO_EXIT;
2673 }
2674
2675 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2676 {
2677 int r3 = get_field(s->fields, r3);
2678 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2679 return NO_EXIT;
2680 }
2681
2682 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2683 {
2684 gen_helper_nabs_i64(o->out, o->in2);
2685 return NO_EXIT;
2686 }
2687
2688 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2689 {
2690 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2691 return NO_EXIT;
2692 }
2693
2694 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2695 {
2696 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2697 return NO_EXIT;
2698 }
2699
2700 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2701 {
2702 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2703 tcg_gen_mov_i64(o->out2, o->in2);
2704 return NO_EXIT;
2705 }
2706
2707 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2708 {
2709 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2710 potential_page_fault(s);
2711 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2712 tcg_temp_free_i32(l);
2713 set_cc_static(s);
2714 return NO_EXIT;
2715 }
2716
2717 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2718 {
2719 tcg_gen_neg_i64(o->out, o->in2);
2720 return NO_EXIT;
2721 }
2722
2723 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2724 {
2725 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2726 return NO_EXIT;
2727 }
2728
2729 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2730 {
2731 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2732 return NO_EXIT;
2733 }
2734
2735 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2736 {
2737 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2738 tcg_gen_mov_i64(o->out2, o->in2);
2739 return NO_EXIT;
2740 }
2741
2742 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2743 {
2744 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2745 potential_page_fault(s);
2746 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2747 tcg_temp_free_i32(l);
2748 set_cc_static(s);
2749 return NO_EXIT;
2750 }
2751
2752 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2753 {
2754 tcg_gen_or_i64(o->out, o->in1, o->in2);
2755 return NO_EXIT;
2756 }
2757
2758 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2759 {
2760 int shift = s->insn->data & 0xff;
2761 int size = s->insn->data >> 8;
2762 uint64_t mask = ((1ull << size) - 1) << shift;
2763
2764 assert(!o->g_in2);
2765 tcg_gen_shli_i64(o->in2, o->in2, shift);
2766 tcg_gen_or_i64(o->out, o->in1, o->in2);
2767
2768 /* Produce the CC from only the bits manipulated. */
2769 tcg_gen_andi_i64(cc_dst, o->out, mask);
2770 set_cc_nz_u64(s, cc_dst);
2771 return NO_EXIT;
2772 }
2773
2774 static ExitStatus op_popcnt(DisasContext *s, DisasOps *o)
2775 {
2776 gen_helper_popcnt(o->out, o->in2);
2777 return NO_EXIT;
2778 }
2779
2780 #ifndef CONFIG_USER_ONLY
2781 static ExitStatus op_ptlb(DisasContext *s, DisasOps *o)
2782 {
2783 check_privileged(s);
2784 gen_helper_ptlb(cpu_env);
2785 return NO_EXIT;
2786 }
2787 #endif
2788
2789 static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
2790 {
2791 int i3 = get_field(s->fields, i3);
2792 int i4 = get_field(s->fields, i4);
2793 int i5 = get_field(s->fields, i5);
2794 int do_zero = i4 & 0x80;
2795 uint64_t mask, imask, pmask;
2796 int pos, len, rot;
2797
2798 /* Adjust the arguments for the specific insn. */
2799 switch (s->fields->op2) {
2800 case 0x55: /* risbg */
2801 i3 &= 63;
2802 i4 &= 63;
2803 pmask = ~0;
2804 break;
2805 case 0x5d: /* risbhg */
2806 i3 &= 31;
2807 i4 &= 31;
2808 pmask = 0xffffffff00000000ull;
2809 break;
2810 case 0x51: /* risblg */
2811 i3 &= 31;
2812 i4 &= 31;
2813 pmask = 0x00000000ffffffffull;
2814 break;
2815 default:
2816 abort();
2817 }
2818
2819 /* MASK is the set of bits to be inserted from R2.
2820 Take care for I3/I4 wraparound. */
2821 mask = pmask >> i3;
2822 if (i3 <= i4) {
2823 mask ^= pmask >> i4 >> 1;
2824 } else {
2825 mask |= ~(pmask >> i4 >> 1);
2826 }
2827 mask &= pmask;
2828
2829 /* IMASK is the set of bits to be kept from R1. In the case of the high/low
2830 insns, we need to keep the other half of the register. */
2831 imask = ~mask | ~pmask;
2832 if (do_zero) {
2833 if (s->fields->op2 == 0x55) {
2834 imask = 0;
2835 } else {
2836 imask = ~pmask;
2837 }
2838 }
2839
2840 /* In some cases we can implement this with deposit, which can be more
2841 efficient on some hosts. */
2842 if (~mask == imask && i3 <= i4) {
2843 if (s->fields->op2 == 0x5d) {
2844 i3 += 32, i4 += 32;
2845 }
2846 /* Note that we rotate the bits to be inserted to the lsb, not to
2847 the position as described in the PoO. */
2848 len = i4 - i3 + 1;
2849 pos = 63 - i4;
2850 rot = (i5 - pos) & 63;
2851 } else {
2852 pos = len = -1;
2853 rot = i5 & 63;
2854 }
2855
2856 /* Rotate the input as necessary. */
2857 tcg_gen_rotli_i64(o->in2, o->in2, rot);
2858
2859 /* Insert the selected bits into the output. */
2860 if (pos >= 0) {
2861 tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len);
2862 } else if (imask == 0) {
2863 tcg_gen_andi_i64(o->out, o->in2, mask);
2864 } else {
2865 tcg_gen_andi_i64(o->in2, o->in2, mask);
2866 tcg_gen_andi_i64(o->out, o->out, imask);
2867 tcg_gen_or_i64(o->out, o->out, o->in2);
2868 }
2869 return NO_EXIT;
2870 }
2871
2872 static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
2873 {
2874 int i3 = get_field(s->fields, i3);
2875 int i4 = get_field(s->fields, i4);
2876 int i5 = get_field(s->fields, i5);
2877 uint64_t mask;
2878
2879 /* If this is a test-only form, arrange to discard the result. */
2880 if (i3 & 0x80) {
2881 o->out = tcg_temp_new_i64();
2882 o->g_out = false;
2883 }
2884
2885 i3 &= 63;
2886 i4 &= 63;
2887 i5 &= 63;
2888
2889 /* MASK is the set of bits to be operated on from R2.
2890 Take care for I3/I4 wraparound. */
2891 mask = ~0ull >> i3;
2892 if (i3 <= i4) {
2893 mask ^= ~0ull >> i4 >> 1;
2894 } else {
2895 mask |= ~(~0ull >> i4 >> 1);
2896 }
2897
2898 /* Rotate the input as necessary. */
2899 tcg_gen_rotli_i64(o->in2, o->in2, i5);
2900
2901 /* Operate. */
2902 switch (s->fields->op2) {
2903 case 0x55: /* AND */
2904 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
2905 tcg_gen_and_i64(o->out, o->out, o->in2);
2906 break;
2907 case 0x56: /* OR */
2908 tcg_gen_andi_i64(o->in2, o->in2, mask);
2909 tcg_gen_or_i64(o->out, o->out, o->in2);
2910 break;
2911 case 0x57: /* XOR */
2912 tcg_gen_andi_i64(o->in2, o->in2, mask);
2913 tcg_gen_xor_i64(o->out, o->out, o->in2);
2914 break;
2915 default:
2916 abort();
2917 }
2918
2919 /* Set the CC. */
2920 tcg_gen_andi_i64(cc_dst, o->out, mask);
2921 set_cc_nz_u64(s, cc_dst);
2922 return NO_EXIT;
2923 }
2924
2925 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2926 {
2927 tcg_gen_bswap16_i64(o->out, o->in2);
2928 return NO_EXIT;
2929 }
2930
2931 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2932 {
2933 tcg_gen_bswap32_i64(o->out, o->in2);
2934 return NO_EXIT;
2935 }
2936
2937 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2938 {
2939 tcg_gen_bswap64_i64(o->out, o->in2);
2940 return NO_EXIT;
2941 }
2942
2943 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2944 {
2945 TCGv_i32 t1 = tcg_temp_new_i32();
2946 TCGv_i32 t2 = tcg_temp_new_i32();
2947 TCGv_i32 to = tcg_temp_new_i32();
2948 tcg_gen_trunc_i64_i32(t1, o->in1);
2949 tcg_gen_trunc_i64_i32(t2, o->in2);
2950 tcg_gen_rotl_i32(to, t1, t2);
2951 tcg_gen_extu_i32_i64(o->out, to);
2952 tcg_temp_free_i32(t1);
2953 tcg_temp_free_i32(t2);
2954 tcg_temp_free_i32(to);
2955 return NO_EXIT;
2956 }
2957
2958 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2959 {
2960 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2961 return NO_EXIT;
2962 }
2963
2964 #ifndef CONFIG_USER_ONLY
2965 static ExitStatus op_rrbe(DisasContext *s, DisasOps *o)
2966 {
2967 check_privileged(s);
2968 gen_helper_rrbe(cc_op, cpu_env, o->in2);
2969 set_cc_static(s);
2970 return NO_EXIT;
2971 }
2972
2973 static ExitStatus op_sacf(DisasContext *s, DisasOps *o)
2974 {
2975 check_privileged(s);
2976 gen_helper_sacf(cpu_env, o->in2);
2977 /* Addressing mode has changed, so end the block. */
2978 return EXIT_PC_STALE;
2979 }
2980 #endif
2981
2982 static ExitStatus op_sam(DisasContext *s, DisasOps *o)
2983 {
2984 int sam = s->insn->data;
2985 TCGv_i64 tsam;
2986 uint64_t mask;
2987
2988 switch (sam) {
2989 case 0:
2990 mask = 0xffffff;
2991 break;
2992 case 1:
2993 mask = 0x7fffffff;
2994 break;
2995 default:
2996 mask = -1;
2997 break;
2998 }
2999
3000 /* Bizarre but true, we check the address of the current insn for the
3001 specification exception, not the next to be executed. Thus the PoO
3002 documents that Bad Things Happen two bytes before the end. */
3003 if (s->pc & ~mask) {
3004 gen_program_exception(s, PGM_SPECIFICATION);
3005 return EXIT_NORETURN;
3006 }
3007 s->next_pc &= mask;
3008
3009 tsam = tcg_const_i64(sam);
3010 tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2);
3011 tcg_temp_free_i64(tsam);
3012
3013 /* Always exit the TB, since we (may have) changed execution mode. */
3014 return EXIT_PC_STALE;
3015 }
3016
3017 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
3018 {
3019 int r1 = get_field(s->fields, r1);
3020 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
3021 return NO_EXIT;
3022 }
3023
3024 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
3025 {
3026 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
3027 return NO_EXIT;
3028 }
3029
3030 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
3031 {
3032 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
3033 return NO_EXIT;
3034 }
3035
3036 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
3037 {
3038 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
3039 return_low128(o->out2);
3040 return NO_EXIT;
3041 }
3042
3043 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
3044 {
3045 gen_helper_sqeb(o->out, cpu_env, o->in2);
3046 return NO_EXIT;
3047 }
3048
3049 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
3050 {
3051 gen_helper_sqdb(o->out, cpu_env, o->in2);
3052 return NO_EXIT;
3053 }
3054
3055 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
3056 {
3057 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
3058 return_low128(o->out2);
3059 return NO_EXIT;
3060 }
3061
3062 #ifndef CONFIG_USER_ONLY
3063 static ExitStatus op_servc(DisasContext *s, DisasOps *o)
3064 {
3065 check_privileged(s);
3066 potential_page_fault(s);
3067 gen_helper_servc(cc_op, cpu_env, o->in2, o->in1);
3068 set_cc_static(s);
3069 return NO_EXIT;
3070 }
3071
3072 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
3073 {
3074 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3075 check_privileged(s);
3076 potential_page_fault(s);
3077 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
3078 tcg_temp_free_i32(r1);
3079 return NO_EXIT;
3080 }
3081 #endif
3082
3083 static ExitStatus op_soc(DisasContext *s, DisasOps *o)
3084 {
3085 DisasCompare c;
3086 TCGv_i64 a;
3087 TCGLabel *lab;
3088 int r1;
3089
3090 disas_jcc(s, &c, get_field(s->fields, m3));
3091
3092 /* We want to store when the condition is fulfilled, so branch
3093 out when it's not */
3094 c.cond = tcg_invert_cond(c.cond);
3095
3096 lab = gen_new_label();
3097 if (c.is_64) {
3098 tcg_gen_brcond_i64(c.cond, c.u.s64.a, c.u.s64.b, lab);
3099 } else {
3100 tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab);
3101 }
3102 free_compare(&c);
3103
3104 r1 = get_field(s->fields, r1);
3105 a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
3106 if (s->insn->data) {
3107 tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
3108 } else {
3109 tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
3110 }
3111 tcg_temp_free_i64(a);
3112
3113 gen_set_label(lab);
3114 return NO_EXIT;
3115 }
3116
3117 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
3118 {
3119 uint64_t sign = 1ull << s->insn->data;
3120 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
3121 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
3122 tcg_gen_shl_i64(o->out, o->in1, o->in2);
3123 /* The arithmetic left shift is curious in that it does not affect
3124 the sign bit. Copy that over from the source unchanged. */
3125 tcg_gen_andi_i64(o->out, o->out, ~sign);
3126 tcg_gen_andi_i64(o->in1, o->in1, sign);
3127 tcg_gen_or_i64(o->out, o->out, o->in1);
3128 return NO_EXIT;
3129 }
3130
3131 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
3132 {
3133 tcg_gen_shl_i64(o->out, o->in1, o->in2);
3134 return NO_EXIT;
3135 }
3136
3137 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
3138 {
3139 tcg_gen_sar_i64(o->out, o->in1, o->in2);
3140 return NO_EXIT;
3141 }
3142
3143 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
3144 {
3145 tcg_gen_shr_i64(o->out, o->in1, o->in2);
3146 return NO_EXIT;
3147 }
3148
3149 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
3150 {
3151 gen_helper_sfpc(cpu_env, o->in2);
3152 return NO_EXIT;
3153 }
3154
3155 static ExitStatus op_sfas(DisasContext *s, DisasOps *o)
3156 {
3157 gen_helper_sfas(cpu_env, o->in2);
3158 return NO_EXIT;
3159 }
3160
3161 static ExitStatus op_srnm(DisasContext *s, DisasOps *o)
3162 {
3163 int b2 = get_field(s->fields, b2);
3164 int d2 = get_field(s->fields, d2);
3165 TCGv_i64 t1 = tcg_temp_new_i64();
3166 TCGv_i64 t2 = tcg_temp_new_i64();
3167 int mask, pos, len;
3168
3169 switch (s->fields->op2) {
3170 case 0x99: /* SRNM */
3171 pos = 0, len = 2;
3172 break;
3173 case 0xb8: /* SRNMB */
3174 pos = 0, len = 3;
3175 break;
3176 case 0xb9: /* SRNMT */
3177 pos = 4, len = 3;
3178 break;
3179 default:
3180 tcg_abort();
3181 }
3182 mask = (1 << len) - 1;
3183
3184 /* Insert the value into the appropriate field of the FPC. */
3185 if (b2 == 0) {
3186 tcg_gen_movi_i64(t1, d2 & mask);
3187 } else {
3188 tcg_gen_addi_i64(t1, regs[b2], d2);
3189 tcg_gen_andi_i64(t1, t1, mask);
3190 }
3191 tcg_gen_ld32u_i64(t2, cpu_env, offsetof(CPUS390XState, fpc));
3192 tcg_gen_deposit_i64(t2, t2, t1, pos, len);
3193 tcg_temp_free_i64(t1);
3194
3195 /* Then install the new FPC to set the rounding mode in fpu_status. */
3196 gen_helper_sfpc(cpu_env, t2);
3197 tcg_temp_free_i64(t2);
3198 return NO_EXIT;
3199 }
3200
3201 #ifndef CONFIG_USER_ONLY
3202 static ExitStatus op_spka(DisasContext *s, DisasOps *o)
3203 {
3204 check_privileged(s);
3205 tcg_gen_shri_i64(o->in2, o->in2, 4);
3206 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
3207 return NO_EXIT;
3208 }
3209
3210 static ExitStatus op_sske(DisasContext *s, DisasOps *o)
3211 {
3212 check_privileged(s);
3213 gen_helper_sske(cpu_env, o->in1, o->in2);
3214 return NO_EXIT;
3215 }
3216
3217 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
3218 {
3219 check_privileged(s);
3220 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
3221 return NO_EXIT;
3222 }
3223
3224 static ExitStatus op_stap(DisasContext *s, DisasOps *o)
3225 {
3226 check_privileged(s);
3227 /* ??? Surely cpu address != cpu number. In any case the previous
3228 version of this stored more than the required half-word, so it
3229 is unlikely this has ever been tested. */
3230 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
3231 return NO_EXIT;
3232 }
3233
3234 static ExitStatus op_stck(DisasContext *s, DisasOps *o)
3235 {
3236 gen_helper_stck(o->out, cpu_env);
3237 /* ??? We don't implement clock states. */
3238 gen_op_movi_cc(s, 0);
3239 return NO_EXIT;
3240 }
3241
3242 static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
3243 {
3244 TCGv_i64 c1 = tcg_temp_new_i64();
3245 TCGv_i64 c2 = tcg_temp_new_i64();
3246 gen_helper_stck(c1, cpu_env);
3247 /* Shift the 64-bit value into its place as a zero-extended
3248 104-bit value. Note that "bit positions 64-103 are always
3249 non-zero so that they compare differently to STCK"; we set
3250 the least significant bit to 1. */
3251 tcg_gen_shli_i64(c2, c1, 56);
3252 tcg_gen_shri_i64(c1, c1, 8);
3253 tcg_gen_ori_i64(c2, c2, 0x10000);
3254 tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
3255 tcg_gen_addi_i64(o->in2, o->in2, 8);
3256 tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
3257 tcg_temp_free_i64(c1);
3258 tcg_temp_free_i64(c2);
3259 /* ??? We don't implement clock states. */
3260 gen_op_movi_cc(s, 0);
3261 return NO_EXIT;
3262 }
3263
3264 static ExitStatus op_sckc(DisasContext *s, DisasOps *o)
3265 {
3266 check_privileged(s);
3267 gen_helper_sckc(cpu_env, o->in2);
3268 return NO_EXIT;
3269 }
3270
3271 static ExitStatus op_stckc(DisasContext *s, DisasOps *o)
3272 {
3273 check_privileged(s);
3274 gen_helper_stckc(o->out, cpu_env);
3275 return NO_EXIT;
3276 }
3277
3278 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
3279 {
3280 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3281 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3282 check_privileged(s);
3283 potential_page_fault(s);
3284 gen_helper_stctg(cpu_env, r1, o->in2, r3);
3285 tcg_temp_free_i32(r1);
3286 tcg_temp_free_i32(r3);
3287 return NO_EXIT;
3288 }
3289
3290 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
3291 {
3292 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3293 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3294 check_privileged(s);
3295 potential_page_fault(s);
3296 gen_helper_stctl(cpu_env, r1, o->in2, r3);
3297 tcg_temp_free_i32(r1);
3298 tcg_temp_free_i32(r3);
3299 return NO_EXIT;
3300 }
3301
3302 static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
3303 {
3304 TCGv_i64 t1 = tcg_temp_new_i64();
3305
3306 check_privileged(s);
3307 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
3308 tcg_gen_ld32u_i64(t1, cpu_env, offsetof(CPUS390XState, machine_type));
3309 tcg_gen_deposit_i64(o->out, o->out, t1, 32, 32);
3310 tcg_temp_free_i64(t1);
3311
3312 return NO_EXIT;
3313 }
3314
3315 static ExitStatus op_spt(DisasContext *s, DisasOps *o)
3316 {
3317 check_privileged(s);
3318 gen_helper_spt(cpu_env, o->in2);
3319 return NO_EXIT;
3320 }
3321
3322 static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
3323 {
3324 TCGv_i64 f, a;
3325 /* We really ought to have more complete indication of facilities
3326 that we implement. Address this when STFLE is implemented. */
3327 check_privileged(s);
3328 f = tcg_const_i64(0xc0000000);
3329 a = tcg_const_i64(200);
3330 tcg_gen_qemu_st32(f, a, get_mem_index(s));
3331 tcg_temp_free_i64(f);
3332 tcg_temp_free_i64(a);
3333 return NO_EXIT;
3334 }
3335
3336 static ExitStatus op_stpt(DisasContext *s, DisasOps *o)
3337 {
3338 check_privileged(s);
3339 gen_helper_stpt(o->out, cpu_env);
3340 return NO_EXIT;
3341 }
3342
3343 static ExitStatus op_stsi(DisasContext *s, DisasOps *o)
3344 {
3345 check_privileged(s);
3346 potential_page_fault(s);
3347 gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
3348 set_cc_static(s);
3349 return NO_EXIT;
3350 }
3351
3352 static ExitStatus op_spx(DisasContext *s, DisasOps *o)
3353 {
3354 check_privileged(s);
3355 gen_helper_spx(cpu_env, o->in2);
3356 return NO_EXIT;
3357 }
3358
3359 static ExitStatus op_subchannel(DisasContext *s, DisasOps *o)
3360 {
3361 check_privileged(s);
3362 /* Not operational. */
3363 gen_op_movi_cc(s, 3);
3364 return NO_EXIT;
3365 }
3366
3367 static ExitStatus op_stpx(DisasContext *s, DisasOps *o)
3368 {
3369 check_privileged(s);
3370 tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
3371 tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
3372 return NO_EXIT;
3373 }
3374
3375 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
3376 {
3377 uint64_t i2 = get_field(s->fields, i2);
3378 TCGv_i64 t;
3379
3380 check_privileged(s);
3381
3382 /* It is important to do what the instruction name says: STORE THEN.
3383 If we let the output hook perform the store then if we fault and
3384 restart, we'll have the wrong SYSTEM MASK in place. */
3385 t = tcg_temp_new_i64();
3386 tcg_gen_shri_i64(t, psw_mask, 56);
3387 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
3388 tcg_temp_free_i64(t);
3389
3390 if (s->fields->op == 0xac) {
3391 tcg_gen_andi_i64(psw_mask, psw_mask,
3392 (i2 << 56) | 0x00ffffffffffffffull);
3393 } else {
3394 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
3395 }
3396 return NO_EXIT;
3397 }
3398
3399 static ExitStatus op_stura(DisasContext *s, DisasOps *o)
3400 {
3401 check_privileged(s);
3402 potential_page_fault(s);
3403 gen_helper_stura(cpu_env, o->in2, o->in1);
3404 return NO_EXIT;
3405 }
3406
3407 static ExitStatus op_sturg(DisasContext *s, DisasOps *o)
3408 {
3409 check_privileged(s);
3410 potential_page_fault(s);
3411 gen_helper_sturg(cpu_env, o->in2, o->in1);
3412 return NO_EXIT;
3413 }
3414 #endif
3415
3416 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
3417 {
3418 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
3419 return NO_EXIT;
3420 }
3421
3422 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3423 {
3424 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3425 return NO_EXIT;
3426 }
3427
3428 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3429 {
3430 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3431 return NO_EXIT;
3432 }
3433
3434 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3435 {
3436 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3437 return NO_EXIT;
3438 }
3439
3440 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3441 {
3442 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3443 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3444 potential_page_fault(s);
3445 gen_helper_stam(cpu_env, r1, o->in2, r3);
3446 tcg_temp_free_i32(r1);
3447 tcg_temp_free_i32(r3);
3448 return NO_EXIT;
3449 }
3450
3451 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3452 {
3453 int m3 = get_field(s->fields, m3);
3454 int pos, base = s->insn->data;
3455 TCGv_i64 tmp = tcg_temp_new_i64();
3456
3457 pos = base + ctz32(m3) * 8;
3458 switch (m3) {
3459 case 0xf:
3460 /* Effectively a 32-bit store. */
3461 tcg_gen_shri_i64(tmp, o->in1, pos);
3462 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3463 break;
3464
3465 case 0xc:
3466 case 0x6:
3467 case 0x3:
3468 /* Effectively a 16-bit store. */
3469 tcg_gen_shri_i64(tmp, o->in1, pos);
3470 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3471 break;
3472
3473 case 0x8:
3474 case 0x4:
3475 case 0x2:
3476 case 0x1:
3477 /* Effectively an 8-bit store. */
3478 tcg_gen_shri_i64(tmp, o->in1, pos);
3479 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3480 break;
3481
3482 default:
3483 /* This is going to be a sequence of shifts and stores. */
3484 pos = base + 32 - 8;
3485 while (m3) {
3486 if (m3 & 0x8) {
3487 tcg_gen_shri_i64(tmp, o->in1, pos);
3488 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3489 tcg_gen_addi_i64(o->in2, o->in2, 1);
3490 }
3491 m3 = (m3 << 1) & 0xf;
3492 pos -= 8;
3493 }
3494 break;
3495 }
3496 tcg_temp_free_i64(tmp);
3497 return NO_EXIT;
3498 }
3499
3500 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3501 {
3502 int r1 = get_field(s->fields, r1);
3503 int r3 = get_field(s->fields, r3);
3504 int size = s->insn->data;
3505 TCGv_i64 tsize = tcg_const_i64(size);
3506
3507 while (1) {
3508 if (size == 8) {
3509 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3510 } else {
3511 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3512 }
3513 if (r1 == r3) {
3514 break;
3515 }
3516 tcg_gen_add_i64(o->in2, o->in2, tsize);
3517 r1 = (r1 + 1) & 15;
3518 }
3519
3520 tcg_temp_free_i64(tsize);
3521 return NO_EXIT;
3522 }
3523
3524 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3525 {
3526 int r1 = get_field(s->fields, r1);
3527 int r3 = get_field(s->fields, r3);
3528 TCGv_i64 t = tcg_temp_new_i64();
3529 TCGv_i64 t4 = tcg_const_i64(4);
3530 TCGv_i64 t32 = tcg_const_i64(32);
3531
3532 while (1) {
3533 tcg_gen_shl_i64(t, regs[r1], t32);
3534 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3535 if (r1 == r3) {
3536 break;
3537 }
3538 tcg_gen_add_i64(o->in2, o->in2, t4);
3539 r1 = (r1 + 1) & 15;
3540 }
3541
3542 tcg_temp_free_i64(t);
3543 tcg_temp_free_i64(t4);
3544 tcg_temp_free_i64(t32);
3545 return NO_EXIT;
3546 }
3547
3548 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3549 {
3550 potential_page_fault(s);
3551 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3552 set_cc_static(s);
3553 return_low128(o->in2);
3554 return NO_EXIT;
3555 }
3556
3557 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3558 {
3559 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3560 return NO_EXIT;
3561 }
3562
3563 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3564 {
3565 DisasCompare cmp;
3566 TCGv_i64 borrow;
3567
3568 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3569
3570 /* The !borrow flag is the msb of CC. Since we want the inverse of
3571 that, we ask for a comparison of CC=0 | CC=1 -> mask of 8 | 4. */
3572 disas_jcc(s, &cmp, 8 | 4);
3573 borrow = tcg_temp_new_i64();
3574 if (cmp.is_64) {
3575 tcg_gen_setcond_i64(cmp.cond, borrow, cmp.u.s64.a, cmp.u.s64.b);
3576 } else {
3577 TCGv_i32 t = tcg_temp_new_i32();
3578 tcg_gen_setcond_i32(cmp.cond, t, cmp.u.s32.a, cmp.u.s32.b);
3579 tcg_gen_extu_i32_i64(borrow, t);
3580 tcg_temp_free_i32(t);
3581 }
3582 free_compare(&cmp);
3583
3584 tcg_gen_sub_i64(o->out, o->out, borrow);
3585 tcg_temp_free_i64(borrow);
3586 return NO_EXIT;
3587 }
3588
3589 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3590 {
3591 TCGv_i32 t;
3592
3593 update_psw_addr(s);
3594 update_cc_op(s);
3595
3596 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3597 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3598 tcg_temp_free_i32(t);
3599
3600 t = tcg_const_i32(s->next_pc - s->pc);
3601 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3602 tcg_temp_free_i32(t);
3603
3604 gen_exception(EXCP_SVC);
3605 return EXIT_NORETURN;
3606 }
3607
3608 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3609 {
3610 gen_helper_tceb(cc_op, o->in1, o->in2);
3611 set_cc_static(s);
3612 return NO_EXIT;
3613 }
3614
3615 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3616 {
3617 gen_helper_tcdb(cc_op, o->in1, o->in2);
3618 set_cc_static(s);
3619 return NO_EXIT;
3620 }
3621
3622 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3623 {
3624 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3625 set_cc_static(s);
3626 return NO_EXIT;
3627 }
3628
3629 #ifndef CONFIG_USER_ONLY
3630 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3631 {
3632 potential_page_fault(s);
3633 gen_helper_tprot(cc_op, o->addr1, o->in2);
3634 set_cc_static(s);
3635 return NO_EXIT;
3636 }
3637 #endif
3638
3639 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3640 {
3641 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3642 potential_page_fault(s);
3643 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3644 tcg_temp_free_i32(l);
3645 set_cc_static(s);
3646 return NO_EXIT;
3647 }
3648
3649 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3650 {
3651 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3652 potential_page_fault(s);
3653 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3654 tcg_temp_free_i32(l);
3655 return NO_EXIT;
3656 }
3657
3658 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3659 {
3660 int d1 = get_field(s->fields, d1);
3661 int d2 = get_field(s->fields, d2);
3662 int b1 = get_field(s->fields, b1);
3663 int b2 = get_field(s->fields, b2);
3664 int l = get_field(s->fields, l1);
3665 TCGv_i32 t32;
3666
3667 o->addr1 = get_address(s, 0, b1, d1);
3668
3669 /* If the addresses are identical, this is a store/memset of zero. */
3670 if (b1 == b2 && d1 == d2 && (l + 1) <= 32) {
3671 o->in2 = tcg_const_i64(0);
3672
3673 l++;
3674 while (l >= 8) {
3675 tcg_gen_qemu_st64(o->in2, o->addr1, get_mem_index(s));
3676 l -= 8;
3677 if (l > 0) {
3678 tcg_gen_addi_i64(o->addr1, o->addr1, 8);
3679 }
3680 }
3681 if (l >= 4) {
3682 tcg_gen_qemu_st32(o->in2, o->addr1, get_mem_index(s));
3683 l -= 4;
3684 if (l > 0) {
3685 tcg_gen_addi_i64(o->addr1, o->addr1, 4);
3686 }
3687 }
3688 if (l >= 2) {
3689 tcg_gen_qemu_st16(o->in2, o->addr1, get_mem_index(s));
3690 l -= 2;
3691 if (l > 0) {
3692 tcg_gen_addi_i64(o->addr1, o->addr1, 2);
3693 }
3694 }
3695 if (l) {
3696 tcg_gen_qemu_st8(o->in2, o->addr1, get_mem_index(s));
3697 }
3698 gen_op_movi_cc(s, 0);
3699 return NO_EXIT;
3700 }
3701
3702 /* But in general we'll defer to a helper. */
3703 o->in2 = get_address(s, 0, b2, d2);
3704 t32 = tcg_const_i32(l);
3705 potential_page_fault(s);
3706 gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2);
3707 tcg_temp_free_i32(t32);
3708 set_cc_static(s);
3709 return NO_EXIT;
3710 }
3711
3712 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3713 {
3714 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3715 return NO_EXIT;
3716 }
3717
3718 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3719 {
3720 int shift = s->insn->data & 0xff;
3721 int size = s->insn->data >> 8;
3722 uint64_t mask = ((1ull << size) - 1) << shift;
3723
3724 assert(!o->g_in2);
3725 tcg_gen_shli_i64(o->in2, o->in2, shift);
3726 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3727
3728 /* Produce the CC from only the bits manipulated. */
3729 tcg_gen_andi_i64(cc_dst, o->out, mask);
3730 set_cc_nz_u64(s, cc_dst);
3731 return NO_EXIT;
3732 }
3733
3734 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3735 {
3736 o->out = tcg_const_i64(0);
3737 return NO_EXIT;
3738 }
3739
3740 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3741 {
3742 o->out = tcg_const_i64(0);
3743 o->out2 = o->out;
3744 o->g_out2 = true;
3745 return NO_EXIT;
3746 }
3747
3748 /* ====================================================================== */
3749 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3750 the original inputs), update the various cc data structures in order to
3751 be able to compute the new condition code. */
3752
3753 static void cout_abs32(DisasContext *s, DisasOps *o)
3754 {
3755 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3756 }
3757
3758 static void cout_abs64(DisasContext *s, DisasOps *o)
3759 {
3760 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3761 }
3762
3763 static void cout_adds32(DisasContext *s, DisasOps *o)
3764 {
3765 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3766 }
3767
3768 static void cout_adds64(DisasContext *s, DisasOps *o)
3769 {
3770 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3771 }
3772
3773 static void cout_addu32(DisasContext *s, DisasOps *o)
3774 {
3775 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3776 }
3777
3778 static void cout_addu64(DisasContext *s, DisasOps *o)
3779 {
3780 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3781 }
3782
3783 static void cout_addc32(DisasContext *s, DisasOps *o)
3784 {
3785 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3786 }
3787
3788 static void cout_addc64(DisasContext *s, DisasOps *o)
3789 {
3790 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3791 }
3792
3793 static void cout_cmps32(DisasContext *s, DisasOps *o)
3794 {
3795 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3796 }
3797
3798 static void cout_cmps64(DisasContext *s, DisasOps *o)
3799 {
3800 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3801 }
3802
3803 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3804 {
3805 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3806 }
3807
3808 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3809 {
3810 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3811 }
3812
3813 static void cout_f32(DisasContext *s, DisasOps *o)
3814 {
3815 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3816 }
3817
3818 static void cout_f64(DisasContext *s, DisasOps *o)
3819 {
3820 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3821 }
3822
3823 static void cout_f128(DisasContext *s, DisasOps *o)
3824 {
3825 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3826 }
3827
3828 static void cout_nabs32(DisasContext *s, DisasOps *o)
3829 {
3830 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3831 }
3832
3833 static void cout_nabs64(DisasContext *s, DisasOps *o)
3834 {
3835 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3836 }
3837
3838 static void cout_neg32(DisasContext *s, DisasOps *o)
3839 {
3840 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3841 }
3842
3843 static void cout_neg64(DisasContext *s, DisasOps *o)
3844 {
3845 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3846 }
3847
3848 static void cout_nz32(DisasContext *s, DisasOps *o)
3849 {
3850 tcg_gen_ext32u_i64(cc_dst, o->out);
3851 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3852 }
3853
3854 static void cout_nz64(DisasContext *s, DisasOps *o)
3855 {
3856 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3857 }
3858
3859 static void cout_s32(DisasContext *s, DisasOps *o)
3860 {
3861 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3862 }
3863
3864 static void cout_s64(DisasContext *s, DisasOps *o)
3865 {
3866 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3867 }
3868
3869 static void cout_subs32(DisasContext *s, DisasOps *o)
3870 {
3871 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3872 }
3873
3874 static void cout_subs64(DisasContext *s, DisasOps *o)
3875 {
3876 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3877 }
3878
3879 static void cout_subu32(DisasContext *s, DisasOps *o)
3880 {
3881 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3882 }
3883
3884 static void cout_subu64(DisasContext *s, DisasOps *o)
3885 {
3886 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3887 }
3888
3889 static void cout_subb32(DisasContext *s, DisasOps *o)
3890 {
3891 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3892 }
3893
3894 static void cout_subb64(DisasContext *s, DisasOps *o)
3895 {
3896 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3897 }
3898
3899 static void cout_tm32(DisasContext *s, DisasOps *o)
3900 {
3901 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3902 }
3903
3904 static void cout_tm64(DisasContext *s, DisasOps *o)
3905 {
3906 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3907 }
3908
3909 /* ====================================================================== */
3910 /* The "PREParation" generators. These initialize the DisasOps.OUT fields
3911 with the TCG register to which we will write. Used in combination with
3912 the "wout" generators, in some cases we need a new temporary, and in
3913 some cases we can write to a TCG global. */
3914
3915 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3916 {
3917 o->out = tcg_temp_new_i64();
3918 }
3919 #define SPEC_prep_new 0
3920
3921 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3922 {
3923 o->out = tcg_temp_new_i64();
3924 o->out2 = tcg_temp_new_i64();
3925 }
3926 #define SPEC_prep_new_P 0
3927
3928 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3929 {
3930 o->out = regs[get_field(f, r1)];
3931 o->g_out = true;
3932 }
3933 #define SPEC_prep_r1 0
3934
3935 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3936 {
3937 int r1 = get_field(f, r1);
3938 o->out = regs[r1];
3939 o->out2 = regs[r1 + 1];
3940 o->g_out = o->g_out2 = true;
3941 }
3942 #define SPEC_prep_r1_P SPEC_r1_even
3943
3944 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3945 {
3946 o->out = fregs[get_field(f, r1)];
3947 o->g_out = true;
3948 }
3949 #define SPEC_prep_f1 0
3950
3951 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3952 {
3953 int r1 = get_field(f, r1);
3954 o->out = fregs[r1];
3955 o->out2 = fregs[r1 + 2];
3956 o->g_out = o->g_out2 = true;
3957 }
3958 #define SPEC_prep_x1 SPEC_r1_f128
3959
3960 /* ====================================================================== */
3961 /* The "Write OUTput" generators. These generally perform some non-trivial
3962 copy of data to TCG globals, or to main memory. The trivial cases are
3963 generally handled by having a "prep" generator install the TCG global
3964 as the destination of the operation. */
3965
3966 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3967 {
3968 store_reg(get_field(f, r1), o->out);
3969 }
3970 #define SPEC_wout_r1 0
3971
3972 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3973 {
3974 int r1 = get_field(f, r1);
3975 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3976 }
3977 #define SPEC_wout_r1_8 0
3978
3979 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3980 {
3981 int r1 = get_field(f, r1);
3982 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3983 }
3984 #define SPEC_wout_r1_16 0
3985
3986 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3987 {
3988 store_reg32_i64(get_field(f, r1), o->out);
3989 }
3990 #define SPEC_wout_r1_32 0
3991
3992 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3993 {
3994 int r1 = get_field(f, r1);
3995 store_reg32_i64(r1, o->out);
3996 store_reg32_i64(r1 + 1, o->out2);
3997 }
3998 #define SPEC_wout_r1_P32 SPEC_r1_even
3999
4000 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
4001 {
4002 int r1 = get_field(f, r1);
4003 store_reg32_i64(r1 + 1, o->out);
4004 tcg_gen_shri_i64(o->out, o->out, 32);
4005 store_reg32_i64(r1, o->out);
4006 }
4007 #define SPEC_wout_r1_D32 SPEC_r1_even
4008
4009 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
4010 {
4011 store_freg32_i64(get_field(f, r1), o->out);
4012 }
4013 #define SPEC_wout_e1 0
4014
4015 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
4016 {
4017 store_freg(get_field(f, r1), o->out);
4018 }
4019 #define SPEC_wout_f1 0
4020
4021 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
4022 {
4023 int f1 = get_field(s->fields, r1);
4024 store_freg(f1, o->out);
4025 store_freg(f1 + 2, o->out2);
4026 }
4027 #define SPEC_wout_x1 SPEC_r1_f128
4028
4029 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
4030 {
4031 if (get_field(f, r1) != get_field(f, r2)) {
4032 store_reg32_i64(get_field(f, r1), o->out);
4033 }
4034 }
4035 #define SPEC_wout_cond_r1r2_32 0
4036
4037 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
4038 {
4039 if (get_field(f, r1) != get_field(f, r2)) {
4040 store_freg32_i64(get_field(f, r1), o->out);
4041 }
4042 }
4043 #define SPEC_wout_cond_e1e2 0
4044
4045 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
4046 {
4047 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
4048 }
4049 #define SPEC_wout_m1_8 0
4050
4051 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
4052 {
4053 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
4054 }
4055 #define SPEC_wout_m1_16 0
4056
4057 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
4058 {
4059 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
4060 }
4061 #define SPEC_wout_m1_32 0
4062
4063 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
4064 {
4065 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
4066 }
4067 #define SPEC_wout_m1_64 0
4068
4069 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
4070 {
4071 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
4072 }
4073 #define SPEC_wout_m2_32 0
4074
4075 static void wout_m2_32_r1_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
4076 {
4077 /* XXX release reservation */
4078 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
4079 store_reg32_i64(get_field(f, r1), o->in2);
4080 }
4081 #define SPEC_wout_m2_32_r1_atomic 0
4082
4083 static void wout_m2_64_r1_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
4084 {
4085 /* XXX release reservation */
4086 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
4087 store_reg(get_field(f, r1), o->in2);
4088 }
4089 #define SPEC_wout_m2_64_r1_atomic 0
4090
4091 /* ====================================================================== */
4092 /* The "INput 1" generators. These load the first operand to an insn. */
4093
4094 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
4095 {
4096 o->in1 = load_reg(get_field(f, r1));
4097 }
4098 #define SPEC_in1_r1 0
4099
4100 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
4101 {
4102 o->in1 = regs[get_field(f, r1)];
4103 o->g_in1 = true;
4104 }
4105 #define SPEC_in1_r1_o 0
4106
4107 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4108 {
4109 o->in1 = tcg_temp_new_i64();
4110 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
4111 }
4112 #define SPEC_in1_r1_32s 0
4113
4114 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4115 {
4116 o->in1 = tcg_temp_new_i64();
4117 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
4118 }
4119 #define SPEC_in1_r1_32u 0
4120
4121 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
4122 {
4123 o->in1 = tcg_temp_new_i64();
4124 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
4125 }
4126 #define SPEC_in1_r1_sr32 0
4127
4128 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
4129 {
4130 o->in1 = load_reg(get_field(f, r1) + 1);
4131 }
4132 #define SPEC_in1_r1p1 SPEC_r1_even
4133
4134 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4135 {
4136 o->in1 = tcg_temp_new_i64();
4137 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1) + 1]);
4138 }
4139 #define SPEC_in1_r1p1_32s SPEC_r1_even
4140
4141 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4142 {
4143 o->in1 = tcg_temp_new_i64();
4144 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1) + 1]);
4145 }
4146 #define SPEC_in1_r1p1_32u SPEC_r1_even
4147
4148 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
4149 {
4150 int r1 = get_field(f, r1);
4151 o->in1 = tcg_temp_new_i64();
4152 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
4153 }
4154 #define SPEC_in1_r1_D32 SPEC_r1_even
4155
4156 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
4157 {
4158 o->in1 = load_reg(get_field(f, r2));
4159 }
4160 #define SPEC_in1_r2 0
4161
4162 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
4163 {
4164 o->in1 = load_reg(get_field(f, r3));
4165 }
4166 #define SPEC_in1_r3 0
4167
4168 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
4169 {
4170 o->in1 = regs[get_field(f, r3)];
4171 o->g_in1 = true;
4172 }
4173 #define SPEC_in1_r3_o 0
4174
4175 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4176 {
4177 o->in1 = tcg_temp_new_i64();
4178 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
4179 }
4180 #define SPEC_in1_r3_32s 0
4181
4182 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4183 {
4184 o->in1 = tcg_temp_new_i64();
4185 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
4186 }
4187 #define SPEC_in1_r3_32u 0
4188
4189 static void in1_r3_D32(DisasContext *s, DisasFields *f, DisasOps *o)
4190 {
4191 int r3 = get_field(f, r3);
4192 o->in1 = tcg_temp_new_i64();
4193 tcg_gen_concat32_i64(o->in1, regs[r3 + 1], regs[r3]);
4194 }
4195 #define SPEC_in1_r3_D32 SPEC_r3_even
4196
4197 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
4198 {
4199 o->in1 = load_freg32_i64(get_field(f, r1));
4200 }
4201 #define SPEC_in1_e1 0
4202
4203 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
4204 {
4205 o->in1 = fregs[get_field(f, r1)];
4206 o->g_in1 = true;
4207 }
4208 #define SPEC_in1_f1_o 0
4209
4210 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
4211 {
4212 int r1 = get_field(f, r1);
4213 o->out = fregs[r1];
4214 o->out2 = fregs[r1 + 2];
4215 o->g_out = o->g_out2 = true;
4216 }
4217 #define SPEC_in1_x1_o SPEC_r1_f128
4218
4219 static void in1_f3_o(DisasContext *s, DisasFields *f, DisasOps *o)
4220 {
4221 o->in1 = fregs[get_field(f, r3)];
4222 o->g_in1 = true;
4223 }
4224 #define SPEC_in1_f3_o 0
4225
4226 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
4227 {
4228 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
4229 }
4230 #define SPEC_in1_la1 0
4231
4232 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
4233 {
4234 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
4235 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
4236 }
4237 #define SPEC_in1_la2 0
4238
4239 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4240 {
4241 in1_la1(s, f, o);
4242 o->in1 = tcg_temp_new_i64();
4243 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
4244 }
4245 #define SPEC_in1_m1_8u 0
4246
4247 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
4248 {
4249 in1_la1(s, f, o);
4250 o->in1 = tcg_temp_new_i64();
4251 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
4252 }
4253 #define SPEC_in1_m1_16s 0
4254
4255 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4256 {
4257 in1_la1(s, f, o);
4258 o->in1 = tcg_temp_new_i64();
4259 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
4260 }
4261 #define SPEC_in1_m1_16u 0
4262
4263 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4264 {
4265 in1_la1(s, f, o);
4266 o->in1 = tcg_temp_new_i64();
4267 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
4268 }
4269 #define SPEC_in1_m1_32s 0
4270
4271 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4272 {
4273 in1_la1(s, f, o);
4274 o->in1 = tcg_temp_new_i64();
4275 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
4276 }
4277 #define SPEC_in1_m1_32u 0
4278
4279 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
4280 {
4281 in1_la1(s, f, o);
4282 o->in1 = tcg_temp_new_i64();
4283 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
4284 }
4285 #define SPEC_in1_m1_64 0
4286
4287 /* ====================================================================== */
4288 /* The "INput 2" generators. These load the second operand to an insn. */
4289
4290 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
4291 {
4292 o->in2 = regs[get_field(f, r1)];
4293 o->g_in2 = true;
4294 }
4295 #define SPEC_in2_r1_o 0
4296
4297 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4298 {
4299 o->in2 = tcg_temp_new_i64();
4300 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
4301 }
4302 #define SPEC_in2_r1_16u 0
4303
4304 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4305 {
4306 o->in2 = tcg_temp_new_i64();
4307 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
4308 }
4309 #define SPEC_in2_r1_32u 0
4310
4311 static void in2_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
4312 {
4313 int r1 = get_field(f, r1);
4314 o->in2 = tcg_temp_new_i64();
4315 tcg_gen_concat32_i64(o->in2, regs[r1 + 1], regs[r1]);
4316 }
4317 #define SPEC_in2_r1_D32 SPEC_r1_even
4318
4319 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
4320 {
4321 o->in2 = load_reg(get_field(f, r2));
4322 }
4323 #define SPEC_in2_r2 0
4324
4325 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
4326 {
4327 o->in2 = regs[get_field(f, r2)];
4328 o->g_in2 = true;
4329 }
4330 #define SPEC_in2_r2_o 0
4331
4332 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
4333 {
4334 int r2 = get_field(f, r2);
4335 if (r2 != 0) {
4336 o->in2 = load_reg(r2);
4337 }
4338 }
4339 #define SPEC_in2_r2_nz 0
4340
4341 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
4342 {
4343 o->in2 = tcg_temp_new_i64();
4344 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
4345 }
4346 #define SPEC_in2_r2_8s 0
4347
4348 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4349 {
4350 o->in2 = tcg_temp_new_i64();
4351 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
4352 }
4353 #define SPEC_in2_r2_8u 0
4354
4355 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
4356 {
4357 o->in2 = tcg_temp_new_i64();
4358 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
4359 }
4360 #define SPEC_in2_r2_16s 0
4361
4362 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4363 {
4364 o->in2 = tcg_temp_new_i64();
4365 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
4366 }
4367 #define SPEC_in2_r2_16u 0
4368
4369 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
4370 {
4371 o->in2 = load_reg(get_field(f, r3));
4372 }
4373 #define SPEC_in2_r3 0
4374
4375 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4376 {
4377 o->in2 = tcg_temp_new_i64();
4378 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
4379 }
4380 #define SPEC_in2_r2_32s 0
4381
4382 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4383 {
4384 o->in2 = tcg_temp_new_i64();
4385 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
4386 }
4387 #define SPEC_in2_r2_32u 0
4388
4389 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
4390 {
4391 o->in2 = load_freg32_i64(get_field(f, r2));
4392 }
4393 #define SPEC_in2_e2 0
4394
4395 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
4396 {
4397 o->in2 = fregs[get_field(f, r2)];
4398 o->g_in2 = true;
4399 }
4400 #define SPEC_in2_f2_o 0
4401
4402 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
4403 {
4404 int r2 = get_field(f, r2);
4405 o->in1 = fregs[r2];
4406 o->in2 = fregs[r2 + 2];
4407 o->g_in1 = o->g_in2 = true;
4408 }
4409 #define SPEC_in2_x2_o SPEC_r2_f128
4410
4411 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
4412 {
4413 o->in2 = get_address(s, 0, get_field(f, r2), 0);
4414 }
4415 #define SPEC_in2_ra2 0
4416
4417 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
4418 {
4419 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
4420 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
4421 }
4422 #define SPEC_in2_a2 0
4423
4424 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
4425 {
4426 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
4427 }
4428 #define SPEC_in2_ri2 0
4429
4430 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
4431 {
4432 help_l2_shift(s, f, o, 31);
4433 }
4434 #define SPEC_in2_sh32 0
4435
4436 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
4437 {
4438 help_l2_shift(s, f, o, 63);
4439 }
4440 #define SPEC_in2_sh64 0
4441
4442 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4443 {
4444 in2_a2(s, f, o);
4445 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
4446 }
4447 #define SPEC_in2_m2_8u 0
4448
4449 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
4450 {
4451 in2_a2(s, f, o);
4452 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
4453 }
4454 #define SPEC_in2_m2_16s 0
4455
4456 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4457 {
4458 in2_a2(s, f, o);
4459 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
4460 }
4461 #define SPEC_in2_m2_16u 0
4462
4463 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4464 {
4465 in2_a2(s, f, o);
4466 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
4467 }
4468 #define SPEC_in2_m2_32s 0
4469
4470 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4471 {
4472 in2_a2(s, f, o);
4473 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
4474 }
4475 #define SPEC_in2_m2_32u 0
4476
4477 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
4478 {
4479 in2_a2(s, f, o);
4480 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
4481 }
4482 #define SPEC_in2_m2_64 0
4483
4484 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4485 {
4486 in2_ri2(s, f, o);
4487 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
4488 }
4489 #define SPEC_in2_mri2_16u 0
4490
4491 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4492 {
4493 in2_ri2(s, f, o);
4494 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
4495 }
4496 #define SPEC_in2_mri2_32s 0
4497
4498 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4499 {
4500 in2_ri2(s, f, o);
4501 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
4502 }
4503 #define SPEC_in2_mri2_32u 0
4504
4505 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
4506 {
4507 in2_ri2(s, f, o);
4508 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
4509 }
4510 #define SPEC_in2_mri2_64 0
4511
4512 static void in2_m2_32s_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
4513 {
4514 /* XXX should reserve the address */
4515 in1_la2(s, f, o);
4516 o->in2 = tcg_temp_new_i64();
4517 tcg_gen_qemu_ld32s(o->in2, o->addr1, get_mem_index(s));
4518 }
4519 #define SPEC_in2_m2_32s_atomic 0
4520
4521 static void in2_m2_64_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
4522 {
4523 /* XXX should reserve the address */
4524 in1_la2(s, f, o);
4525 o->in2 = tcg_temp_new_i64();
4526 tcg_gen_qemu_ld64(o->in2, o->addr1, get_mem_index(s));
4527 }
4528 #define SPEC_in2_m2_64_atomic 0
4529
4530 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
4531 {
4532 o->in2 = tcg_const_i64(get_field(f, i2));
4533 }
4534 #define SPEC_in2_i2 0
4535
4536 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4537 {
4538 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
4539 }
4540 #define SPEC_in2_i2_8u 0
4541
4542 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4543 {
4544 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
4545 }
4546 #define SPEC_in2_i2_16u 0
4547
4548 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4549 {
4550 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
4551 }
4552 #define SPEC_in2_i2_32u 0
4553
4554 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4555 {
4556 uint64_t i2 = (uint16_t)get_field(f, i2);
4557 o->in2 = tcg_const_i64(i2 << s->insn->data);
4558 }
4559 #define SPEC_in2_i2_16u_shl 0
4560
4561 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4562 {
4563 uint64_t i2 = (uint32_t)get_field(f, i2);
4564 o->in2 = tcg_const_i64(i2 << s->insn->data);
4565 }
4566 #define SPEC_in2_i2_32u_shl 0
4567
4568 /* ====================================================================== */
4569
4570 /* Find opc within the table of insns. This is formulated as a switch
4571 statement so that (1) we get compile-time notice of cut-paste errors
4572 for duplicated opcodes, and (2) the compiler generates the binary
4573 search tree, rather than us having to post-process the table. */
4574
4575 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
4576 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
4577
4578 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
4579
4580 enum DisasInsnEnum {
4581 #include "insn-data.def"
4582 };
4583
4584 #undef D
4585 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
4586 .opc = OPC, \
4587 .fmt = FMT_##FT, \
4588 .fac = FAC_##FC, \
4589 .spec = SPEC_in1_##I1 | SPEC_in2_##I2 | SPEC_prep_##P | SPEC_wout_##W, \
4590 .name = #NM, \
4591 .help_in1 = in1_##I1, \
4592 .help_in2 = in2_##I2, \
4593 .help_prep = prep_##P, \
4594 .help_wout = wout_##W, \
4595 .help_cout = cout_##CC, \
4596 .help_op = op_##OP, \
4597 .data = D \
4598 },
4599
4600 /* Allow 0 to be used for NULL in the table below. */
4601 #define in1_0 NULL
4602 #define in2_0 NULL
4603 #define prep_0 NULL
4604 #define wout_0 NULL
4605 #define cout_0 NULL
4606 #define op_0 NULL
4607
4608 #define SPEC_in1_0 0
4609 #define SPEC_in2_0 0
4610 #define SPEC_prep_0 0
4611 #define SPEC_wout_0 0
4612
4613 static const DisasInsn insn_info[] = {
4614 #include "insn-data.def"
4615 };
4616
4617 #undef D
4618 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4619 case OPC: return &insn_info[insn_ ## NM];
4620
4621 static const DisasInsn *lookup_opc(uint16_t opc)
4622 {
4623 switch (opc) {
4624 #include "insn-data.def"
4625 default:
4626 return NULL;
4627 }
4628 }
4629
4630 #undef D
4631 #undef C
4632
4633 /* Extract a field from the insn. The INSN should be left-aligned in
4634 the uint64_t so that we can more easily utilize the big-bit-endian
4635 definitions we extract from the Principals of Operation. */
4636
4637 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4638 {
4639 uint32_t r, m;
4640
4641 if (f->size == 0) {
4642 return;
4643 }
4644
4645 /* Zero extract the field from the insn. */
4646 r = (insn << f->beg) >> (64 - f->size);
4647
4648 /* Sign-extend, or un-swap the field as necessary. */
4649 switch (f->type) {
4650 case 0: /* unsigned */
4651 break;
4652 case 1: /* signed */
4653 assert(f->size <= 32);
4654 m = 1u << (f->size - 1);
4655 r = (r ^ m) - m;
4656 break;
4657 case 2: /* dl+dh split, signed 20 bit. */
4658 r = ((int8_t)r << 12) | (r >> 8);
4659 break;
4660 default:
4661 abort();
4662 }
4663
4664 /* Validate that the "compressed" encoding we selected above is valid.
4665 I.e. we havn't make two different original fields overlap. */
4666 assert(((o->presentC >> f->indexC) & 1) == 0);
4667 o->presentC |= 1 << f->indexC;
4668 o->presentO |= 1 << f->indexO;
4669
4670 o->c[f->indexC] = r;
4671 }
4672
4673 /* Lookup the insn at the current PC, extracting the operands into O and
4674 returning the info struct for the insn. Returns NULL for invalid insn. */
4675
4676 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4677 DisasFields *f)
4678 {
4679 uint64_t insn, pc = s->pc;
4680 int op, op2, ilen;
4681 const DisasInsn *info;
4682
4683 insn = ld_code2(env, pc);
4684 op = (insn >> 8) & 0xff;
4685 ilen = get_ilen(op);
4686 s->next_pc = s->pc + ilen;
4687
4688 switch (ilen) {
4689 case 2:
4690 insn = insn << 48;
4691 break;
4692 case 4:
4693 insn = ld_code4(env, pc) << 32;
4694 break;
4695 case 6:
4696 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4697 break;
4698 default:
4699 abort();
4700 }
4701
4702 /* We can't actually determine the insn format until we've looked up
4703 the full insn opcode. Which we can't do without locating the
4704 secondary opcode. Assume by default that OP2 is at bit 40; for
4705 those smaller insns that don't actually have a secondary opcode
4706 this will correctly result in OP2 = 0. */
4707 switch (op) {
4708 case 0x01: /* E */
4709 case 0x80: /* S */
4710 case 0x82: /* S */
4711 case 0x93: /* S */
4712 case 0xb2: /* S, RRF, RRE */
4713 case 0xb3: /* RRE, RRD, RRF */
4714 case 0xb9: /* RRE, RRF */
4715 case 0xe5: /* SSE, SIL */
4716 op2 = (insn << 8) >> 56;
4717 break;
4718 case 0xa5: /* RI */
4719 case 0xa7: /* RI */
4720 case 0xc0: /* RIL */
4721 case 0xc2: /* RIL */
4722 case 0xc4: /* RIL */
4723 case 0xc6: /* RIL */
4724 case 0xc8: /* SSF */
4725 case 0xcc: /* RIL */
4726 op2 = (insn << 12) >> 60;
4727 break;
4728 case 0xd0 ... 0xdf: /* SS */
4729 case 0xe1: /* SS */
4730 case 0xe2: /* SS */
4731 case 0xe8: /* SS */
4732 case 0xe9: /* SS */
4733 case 0xea: /* SS */
4734 case 0xee ... 0xf3: /* SS */
4735 case 0xf8 ... 0xfd: /* SS */
4736 op2 = 0;
4737 break;
4738 default:
4739 op2 = (insn << 40) >> 56;
4740 break;
4741 }
4742
4743 memset(f, 0, sizeof(*f));
4744 f->op = op;
4745 f->op2 = op2;
4746
4747 /* Lookup the instruction. */
4748 info = lookup_opc(op << 8 | op2);
4749
4750 /* If we found it, extract the operands. */
4751 if (info != NULL) {
4752 DisasFormat fmt = info->fmt;
4753 int i;
4754
4755 for (i = 0; i < NUM_C_FIELD; ++i) {
4756 extract_field(f, &format_info[fmt].op[i], insn);
4757 }
4758 }
4759 return info;
4760 }
4761
4762 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4763 {
4764 const DisasInsn *insn;
4765 ExitStatus ret = NO_EXIT;
4766 DisasFields f;
4767 DisasOps o;
4768
4769 /* Search for the insn in the table. */
4770 insn = extract_insn(env, s, &f);
4771
4772 /* Not found means unimplemented/illegal opcode. */
4773 if (insn == NULL) {
4774 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n",
4775 f.op, f.op2);
4776 gen_illegal_opcode(s);
4777 return EXIT_NORETURN;
4778 }
4779
4780 /* Check for insn specification exceptions. */
4781 if (insn->spec) {
4782 int spec = insn->spec, excp = 0, r;
4783
4784 if (spec & SPEC_r1_even) {
4785 r = get_field(&f, r1);
4786 if (r & 1) {
4787 excp = PGM_SPECIFICATION;
4788 }
4789 }
4790 if (spec & SPEC_r2_even) {
4791 r = get_field(&f, r2);
4792 if (r & 1) {
4793 excp = PGM_SPECIFICATION;
4794 }
4795 }
4796 if (spec & SPEC_r3_even) {
4797 r = get_field(&f, r3);
4798 if (r & 1) {
4799 excp = PGM_SPECIFICATION;
4800 }
4801 }
4802 if (spec & SPEC_r1_f128) {
4803 r = get_field(&f, r1);
4804 if (r > 13) {
4805 excp = PGM_SPECIFICATION;
4806 }
4807 }
4808 if (spec & SPEC_r2_f128) {
4809 r = get_field(&f, r2);
4810 if (r > 13) {
4811 excp = PGM_SPECIFICATION;
4812 }
4813 }
4814 if (excp) {
4815 gen_program_exception(s, excp);
4816 return EXIT_NORETURN;
4817 }
4818 }
4819
4820 /* Set up the strutures we use to communicate with the helpers. */
4821 s->insn = insn;
4822 s->fields = &f;
4823 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4824 TCGV_UNUSED_I64(o.out);
4825 TCGV_UNUSED_I64(o.out2);
4826 TCGV_UNUSED_I64(o.in1);
4827 TCGV_UNUSED_I64(o.in2);
4828 TCGV_UNUSED_I64(o.addr1);
4829
4830 /* Implement the instruction. */
4831 if (insn->help_in1) {
4832 insn->help_in1(s, &f, &o);
4833 }
4834 if (insn->help_in2) {
4835 insn->help_in2(s, &f, &o);
4836 }
4837 if (insn->help_prep) {
4838 insn->help_prep(s, &f, &o);
4839 }
4840 if (insn->help_op) {
4841 ret = insn->help_op(s, &o);
4842 }
4843 if (insn->help_wout) {
4844 insn->help_wout(s, &f, &o);
4845 }
4846 if (insn->help_cout) {
4847 insn->help_cout(s, &o);
4848 }
4849
4850 /* Free any temporaries created by the helpers. */
4851 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4852 tcg_temp_free_i64(o.out);
4853 }
4854 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4855 tcg_temp_free_i64(o.out2);
4856 }
4857 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4858 tcg_temp_free_i64(o.in1);
4859 }
4860 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4861 tcg_temp_free_i64(o.in2);
4862 }
4863 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4864 tcg_temp_free_i64(o.addr1);
4865 }
4866
4867 /* Advance to the next instruction. */
4868 s->pc = s->next_pc;
4869 return ret;
4870 }
4871
4872 static inline void gen_intermediate_code_internal(S390CPU *cpu,
4873 TranslationBlock *tb,
4874 bool search_pc)
4875 {
4876 CPUState *cs = CPU(cpu);
4877 CPUS390XState *env = &cpu->env;
4878 DisasContext dc;
4879 target_ulong pc_start;
4880 uint64_t next_page_start;
4881 int j, lj = -1;
4882 int num_insns, max_insns;
4883 CPUBreakpoint *bp;
4884 ExitStatus status;
4885 bool do_debug;
4886
4887 pc_start = tb->pc;
4888
4889 /* 31-bit mode */
4890 if (!(tb->flags & FLAG_MASK_64)) {
4891 pc_start &= 0x7fffffff;
4892 }
4893
4894 dc.tb = tb;
4895 dc.pc = pc_start;
4896 dc.cc_op = CC_OP_DYNAMIC;
4897 do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
4898
4899 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4900
4901 num_insns = 0;
4902 max_insns = tb->cflags & CF_COUNT_MASK;
4903 if (max_insns == 0) {
4904 max_insns = CF_COUNT_MASK;
4905 }
4906
4907 gen_tb_start(tb);
4908
4909 do {
4910 if (search_pc) {
4911 j = tcg_op_buf_count();
4912 if (lj < j) {
4913 lj++;
4914 while (lj < j) {
4915 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4916 }
4917 }
4918 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4919 gen_opc_cc_op[lj] = dc.cc_op;
4920 tcg_ctx.gen_opc_instr_start[lj] = 1;
4921 tcg_ctx.gen_opc_icount[lj] = num_insns;
4922 }
4923 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4924 gen_io_start();
4925 }
4926
4927 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4928 tcg_gen_debug_insn_start(dc.pc);
4929 }
4930
4931 status = NO_EXIT;
4932 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
4933 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
4934 if (bp->pc == dc.pc) {
4935 status = EXIT_PC_STALE;
4936 do_debug = true;
4937 break;
4938 }
4939 }
4940 }
4941 if (status == NO_EXIT) {
4942 status = translate_one(env, &dc);
4943 }
4944
4945 /* If we reach a page boundary, are single stepping,
4946 or exhaust instruction count, stop generation. */
4947 if (status == NO_EXIT
4948 && (dc.pc >= next_page_start
4949 || tcg_op_buf_full()
4950 || num_insns >= max_insns
4951 || singlestep
4952 || cs->singlestep_enabled)) {
4953 status = EXIT_PC_STALE;
4954 }
4955 } while (status == NO_EXIT);
4956
4957 if (tb->cflags & CF_LAST_IO) {
4958 gen_io_end();
4959 }
4960
4961 switch (status) {
4962 case EXIT_GOTO_TB:
4963 case EXIT_NORETURN:
4964 break;
4965 case EXIT_PC_STALE:
4966 update_psw_addr(&dc);
4967 /* FALLTHRU */
4968 case EXIT_PC_UPDATED:
4969 /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
4970 cc op type is in env */
4971 update_cc_op(&dc);
4972 /* Exit the TB, either by raising a debug exception or by return. */
4973 if (do_debug) {
4974 gen_exception(EXCP_DEBUG);
4975 } else {
4976 tcg_gen_exit_tb(0);
4977 }
4978 break;
4979 default:
4980 abort();
4981 }
4982
4983 gen_tb_end(tb, num_insns);
4984
4985 if (search_pc) {
4986 j = tcg_op_buf_count();
4987 lj++;
4988 while (lj <= j) {
4989 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4990 }
4991 } else {
4992 tb->size = dc.pc - pc_start;
4993 tb->icount = num_insns;
4994 }
4995
4996 #if defined(S390X_DEBUG_DISAS)
4997 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4998 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4999 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
5000 qemu_log("\n");
5001 }
5002 #endif
5003 }
5004
5005 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
5006 {
5007 gen_intermediate_code_internal(s390_env_get_cpu(env), tb, false);
5008 }
5009
5010 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
5011 {
5012 gen_intermediate_code_internal(s390_env_get_cpu(env), tb, true);
5013 }
5014
5015 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
5016 {
5017 int cc_op;
5018 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
5019 cc_op = gen_opc_cc_op[pc_pos];
5020 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
5021 env->cc_op = cc_op;
5022 }
5023 }
QEmu