2 * OpenRISC virtual CPU header.
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef CPU_OPENRISC_H
21 #define CPU_OPENRISC_H
23 #define TARGET_LONG_BITS 32
24 #define ELF_MACHINE EM_OPENRISC
26 #define CPUArchState struct CPUOpenRISCState
28 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
32 #include "qemu-common.h"
33 #include "exec/cpu-defs.h"
34 #include "fpu/softfloat.h"
37 #define TYPE_OPENRISC_CPU "or32-cpu"
39 #define OPENRISC_CPU_CLASS(klass) \
40 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
41 #define OPENRISC_CPU(obj) \
42 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
43 #define OPENRISC_CPU_GET_CLASS(obj) \
44 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
48 * @parent_realize: The parent class' realize handler.
49 * @parent_reset: The parent class' reset handler.
51 * A OpenRISC CPU model.
53 typedef struct OpenRISCCPUClass
{
55 CPUClass parent_class
;
58 DeviceRealize parent_realize
;
59 void (*parent_reset
)(CPUState
*cpu
);
62 #define NB_MMU_MODES 3
66 MMU_SUPERVISOR_IDX
= 1,
70 #define TARGET_PAGE_BITS 13
72 #define TARGET_PHYS_ADDR_SPACE_BITS 32
73 #define TARGET_VIRT_ADDR_SPACE_BITS 32
75 #define SET_FP_CAUSE(reg, v) do {\
76 (reg) = ((reg) & ~(0x3f << 12)) | \
79 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
80 #define UPDATE_FP_FLAGS(reg, v) do {\
81 (reg) |= ((v & 0x1f) << 2);\
84 /* Version Register */
85 #define SPR_VR 0xFFFF003F
87 /* Internal flags, delay slot flag */
93 /* Unit presece register */
106 UPR_CUP
= (255 << 24),
109 /* CPU configure register */
111 CPUCFGR_NSGF
= (15 << 0),
112 CPUCFGR_CGF
= (1 << 4),
113 CPUCFGR_OB32S
= (1 << 5),
114 CPUCFGR_OB64S
= (1 << 6),
115 CPUCFGR_OF32S
= (1 << 7),
116 CPUCFGR_OF64S
= (1 << 8),
117 CPUCFGR_OV64S
= (1 << 9),
120 /* DMMU configure register */
122 DMMUCFGR_NTW
= (3 << 0),
123 DMMUCFGR_NTS
= (7 << 2),
124 DMMUCFGR_NAE
= (7 << 5),
125 DMMUCFGR_CRI
= (1 << 8),
126 DMMUCFGR_PRI
= (1 << 9),
127 DMMUCFGR_TEIRI
= (1 << 10),
128 DMMUCFGR_HTR
= (1 << 11),
131 /* IMMU configure register */
133 IMMUCFGR_NTW
= (3 << 0),
134 IMMUCFGR_NTS
= (7 << 2),
135 IMMUCFGR_NAE
= (7 << 5),
136 IMMUCFGR_CRI
= (1 << 8),
137 IMMUCFGR_PRI
= (1 << 9),
138 IMMUCFGR_TEIRI
= (1 << 10),
139 IMMUCFGR_HTR
= (1 << 11),
142 /* Float point control status register */
146 FPCSR_OVF
= (1 << 3),
147 FPCSR_UNF
= (1 << 4),
148 FPCSR_SNF
= (1 << 5),
149 FPCSR_QNF
= (1 << 6),
151 FPCSR_IXF
= (1 << 8),
152 FPCSR_IVF
= (1 << 9),
153 FPCSR_INF
= (1 << 10),
154 FPCSR_DZF
= (1 << 11),
157 /* Exceptions indices */
176 /* Supervisor register */
194 SR_SUMRA
= (1 << 16),
198 /* OpenRISC Hardware Capabilities */
200 OPENRISC_FEATURE_NSGF
= (15 << 0),
201 OPENRISC_FEATURE_CGF
= (1 << 4),
202 OPENRISC_FEATURE_OB32S
= (1 << 5),
203 OPENRISC_FEATURE_OB64S
= (1 << 6),
204 OPENRISC_FEATURE_OF32S
= (1 << 7),
205 OPENRISC_FEATURE_OF64S
= (1 << 8),
206 OPENRISC_FEATURE_OV64S
= (1 << 9),
209 /* Tick Timer Mode Register */
211 TTMR_TP
= (0xfffffff),
219 TIMER_NONE
= (0 << 30),
220 TIMER_INTR
= (1 << 30),
221 TIMER_SHOT
= (2 << 30),
222 TIMER_CONT
= (3 << 30),
229 DTLB_MASK
= (DTLB_SIZE
-1),
232 ITLB_MASK
= (ITLB_SIZE
-1),
246 /* check if tlb available */
254 typedef struct OpenRISCTLBEntry
{
259 #ifndef CONFIG_USER_ONLY
260 typedef struct CPUOpenRISCTLBContext
{
261 OpenRISCTLBEntry itlb
[ITLB_WAYS
][ITLB_SIZE
];
262 OpenRISCTLBEntry dtlb
[DTLB_WAYS
][DTLB_SIZE
];
264 int (*cpu_openrisc_map_address_code
)(struct OpenRISCCPU
*cpu
,
267 target_ulong address
, int rw
);
268 int (*cpu_openrisc_map_address_data
)(struct OpenRISCCPU
*cpu
,
271 target_ulong address
, int rw
);
272 } CPUOpenRISCTLBContext
;
275 typedef struct CPUOpenRISCState
{
276 target_ulong gpr
[32]; /* General registers */
277 target_ulong pc
; /* Program counter */
278 target_ulong npc
; /* Next PC */
279 target_ulong ppc
; /* Prev PC */
280 target_ulong jmp_pc
; /* Jump PC */
282 target_ulong machi
; /* Multiply register MACHI */
283 target_ulong maclo
; /* Multiply register MACLO */
285 target_ulong fpmaddhi
; /* Multiply and add float register FPMADDHI */
286 target_ulong fpmaddlo
; /* Multiply and add float register FPMADDLO */
288 target_ulong epcr
; /* Exception PC register */
289 target_ulong eear
; /* Exception EA register */
291 uint32_t sr
; /* Supervisor register */
292 uint32_t vr
; /* Version register */
293 uint32_t upr
; /* Unit presence register */
294 uint32_t cpucfgr
; /* CPU configure register */
295 uint32_t dmmucfgr
; /* DMMU configure register */
296 uint32_t immucfgr
; /* IMMU configure register */
297 uint32_t esr
; /* Exception supervisor register */
298 uint32_t fpcsr
; /* Float register */
299 float_status fp_status
;
301 uint32_t flags
; /* cpu_flags, we only use it for exception
303 uint32_t btaken
; /* the SR_F bit */
307 #ifndef CONFIG_USER_ONLY
308 CPUOpenRISCTLBContext
* tlb
;
310 struct QEMUTimer
*timer
;
311 uint32_t ttmr
; /* Timer tick mode register */
312 uint32_t ttcr
; /* Timer tick count register */
314 uint32_t picmr
; /* Interrupt mask register */
315 uint32_t picsr
; /* Interrupt contrl register*/
317 void *irq
[32]; /* Interrupt irq input */
322 * @env: #CPUOpenRISCState
326 typedef struct OpenRISCCPU
{
331 CPUOpenRISCState env
;
333 uint32_t feature
; /* CPU Capabilities */
336 static inline OpenRISCCPU
*openrisc_env_get_cpu(CPUOpenRISCState
*env
)
338 return OPENRISC_CPU(container_of(env
, OpenRISCCPU
, env
));
341 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
343 OpenRISCCPU
*cpu_openrisc_init(const char *cpu_model
);
345 void cpu_openrisc_list(FILE *f
, fprintf_function cpu_fprintf
);
346 int cpu_openrisc_exec(CPUOpenRISCState
*s
);
347 void do_interrupt(CPUOpenRISCState
*env
);
348 void openrisc_translate_init(void);
349 int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState
*env
,
350 target_ulong address
,
351 int rw
, int mmu_idx
);
352 int cpu_openrisc_signal_handler(int host_signum
, void *pinfo
, void *puc
);
354 #define cpu_list cpu_openrisc_list
355 #define cpu_exec cpu_openrisc_exec
356 #define cpu_gen_code cpu_openrisc_gen_code
357 #define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
358 #define cpu_signal_handler cpu_openrisc_signal_handler
360 #ifndef CONFIG_USER_ONLY
361 /* hw/openrisc_pic.c */
362 void cpu_openrisc_pic_init(OpenRISCCPU
*cpu
);
364 /* hw/openrisc_timer.c */
365 void cpu_openrisc_clock_init(OpenRISCCPU
*cpu
);
366 void cpu_openrisc_count_update(OpenRISCCPU
*cpu
);
367 void cpu_openrisc_count_start(OpenRISCCPU
*cpu
);
368 void cpu_openrisc_count_stop(OpenRISCCPU
*cpu
);
370 void cpu_openrisc_mmu_init(OpenRISCCPU
*cpu
);
371 int cpu_openrisc_get_phys_nommu(OpenRISCCPU
*cpu
,
373 int *prot
, target_ulong address
, int rw
);
374 int cpu_openrisc_get_phys_code(OpenRISCCPU
*cpu
,
376 int *prot
, target_ulong address
, int rw
);
377 int cpu_openrisc_get_phys_data(OpenRISCCPU
*cpu
,
379 int *prot
, target_ulong address
, int rw
);
382 static inline CPUOpenRISCState
*cpu_init(const char *cpu_model
)
384 OpenRISCCPU
*cpu
= cpu_openrisc_init(cpu_model
);
391 #if defined(CONFIG_USER_ONLY)
392 static inline void cpu_clone_regs(CPUOpenRISCState
*env
, target_ulong newsp
)
401 #include "exec/cpu-all.h"
403 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState
*env
,
405 target_ulong
*cs_base
, int *flags
)
409 /* D_FLAG -- branch instruction exception */
410 *flags
= (env
->flags
& D_FLAG
);
413 static inline int cpu_mmu_index(CPUOpenRISCState
*env
)
415 if (!(env
->sr
& SR_IME
)) {
416 return MMU_NOMMU_IDX
;
418 return (env
->sr
& SR_SM
) == 0 ? MMU_USER_IDX
: MMU_SUPERVISOR_IDX
;
421 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
422 static inline bool cpu_has_work(CPUState
*cpu
)
424 CPUOpenRISCState
*env
= &OPENRISC_CPU(cpu
)->env
;
426 return env
->interrupt_request
& (CPU_INTERRUPT_HARD
|
427 CPU_INTERRUPT_TIMER
);
430 #include "exec/exec-all.h"
432 static inline target_ulong
cpu_get_pc(CPUOpenRISCState
*env
)
437 static inline void cpu_pc_from_tb(CPUOpenRISCState
*env
, TranslationBlock
*tb
)
442 #endif /* CPU_OPENRISC_H */